Preparation method of distributed photovoltaic module and preparation method of single-sided heterojunction solar cell

Abstract

The invention belongs to the technical field of silicon heterojunction solar cells, and discloses a preparation method of a distributed photovoltaic module and a preparation method of a single-sided heterojunction solar cell. According to the preparation method disclosed by the invention, the back seed layer of the copper gate heterojunction cell is reserved by removing copper through single-side etching, the back reflection of the heterojunction cell is greatly improved through the reservation of the metal seed layer, the utilization rate of sunlight long-wave band light by the cell is increased, the short-circuit current can be effectively improved by 20-50mA, and the efficiency gain of the cell is about more than 0.2%.

Description

Technical Field

[0001] The present invention relates to the technical field of silicon heterojunction solar cells, and in particular to a preparation method of a distributed photovoltaic component and a single-sided heterojunction solar cell. Background Art

[0002] Heterojunction solar cells have attracted widespread attention in the industry due to their excellent performance, such as high efficiency and low attenuation. Currently, there are many methods for preparing heterojunction solar cells, but all of them have some defects.

[0003] The paper "Improvement of the conversion efficiency of polycrystalline silicon thin film solar cell" written by M Taguchi et al. is to perform double-sided texturing on silicon wafers at one time, and then use PECVD and PVD to deposit intrinsic amorphous silicon thin film, doped amorphous silicon / nanocrystalline silicon thin film and TCO thin film on both sides respectively, and finally use screen printing technology to print silver grid lines on both sides to obtain conventional heterojunction solar cells HJT. However, this method has the following disadvantages: (1) HJT uses screen printing technology to prepare electrodes, which is difficult to control the precision of this method. The grid lines are not easy to make narrow, and the shading rate of the cell surface is high, resulting in a low short-circuit current; (2) The consumption of precious metal silver in the printing paste is huge, which greatly increases the mass production cost; (3) HJT components are usually double-sided design, but the back gain of distributed rooftop projects is limited (the roof reflectivity is low), and the advantages cannot be fully utilized.

[0004] Chinese patent CN113972302B relates to a TOPCon cell, its preparation method, and electrical equipment. The preparation method involves texturing a double-sided silicon wafer in one go to form a pyramid textured surface, then diffusing boron on the front side of the silicon wafer to form a P+ layer that forms a PN junction with N-type crystalline silicon. The back side is etched to remove the boron diffusion layer on the back side while retaining the borosilicate glass (BSG) layer on the front side. LPCVD is then used to deposit a tunneling layer and a polycrystalline silicon (Poly) passivation layer on the back side of the cell. The back side Poly is then phosphorus-doped to form an NN+ heterostructure with the crystalline silicon. The front side is then etched to remove the polysilicon and BSG layers on the front side. ALD is then used to deposit an aluminum oxide film on the front side to passivate the boron diffusion surface. PECVD is then used to deposit silicon nitride on both sides of the cell as the cell's anti-reflection layer and passivation layer. Finally, high-temperature sintering screen printing technology is used to print grid lines on both sides to obtain a conventional tunneling oxygen passivated contact heterojunction solar cell TOPCon. This technology also has its drawbacks. For example, (1) TOPCon also uses screen printing technology to prepare electrodes. The precision of this method is difficult to control, the grid lines are not easy to make narrow, and the shading rate of the battery surface is high, resulting in a low short-circuit current; (2) The consumption of precious metal silver in the printing paste on the back of the battery is huge, which greatly increases the mass production cost; (3) The bifaciality of TOPCon can reach 80%-85%, but the back gain of rooftop distributed projects is low (<10%), and its advantages cannot be fully utilized.

[0005] Japanese patent JP2009520369A5 uses photolithography or laser technology, and after a series of special graphics and process designs, transfers the front and back sides of the solar cells involved in the existing technical solutions 1 and 2 to the back side, forming a hybrid back contact heterojunction solar cell HBC or a tunnel oxide back contact solar cell TBC. However, there are still disadvantages, such as (1) BC cells need to form cross-finger p+ and n+ regions on the back side, involving multiple photolithography, doping and masking processes, which are far more than HJT / TOPCon. The mass production yield is generally below 95% (HJT / TOPCon can reach 98%+), resulting in high single-chip costs. (2) BC cells require high printing accuracy on the back side, and the silver paste consumption is large, which is 2 to 3 times that of HJT / TOPCon solar cells; (3) BC cells require laser patterning and precision photolithography equipment (such as ASML photolithography equipment), which has high technical barriers and low domestic production rate. Summary of the Invention

[0006] The purpose of the present invention is to overcome the shortcomings of the above-mentioned background technology and provide a method for preparing a distributed photovoltaic module and a single-sided heterojunction solar cell. The seed layer on the back of the copper-grid heterojunction solar cell is retained by a single-sided etching copper removal method. This cell structure greatly increases the back reflection of the cell and can maximize the utilization of long-wavelength light, thereby improving the short-circuit current and cell efficiency.

[0007] To achieve the purpose of the present invention, the method for preparing a distributed photovoltaic module and a single-sided heterojunction solar cell of the present invention comprises the following steps: (1) The first texturing process is to place the silicon wafer in a mixed solution of KOH or NaOH, isopropyl alcohol additive and ultrapure water to react and form a pyramid structure on the front and back surfaces of the silicon wafer; (2) Preparation of the passivation layer: using PECVD to deposit an intrinsic amorphous silicon layer on the front and back of the battery to passivate the crystalline silicon interface; (3) Emitter preparation: using PECVD to deposit doped amorphous silicon or nanocrystalline silicon layers on the front and back of the battery respectively. Phosphorus-doped amorphous silicon / nanocrystalline silicon is deposited on the front to form a nn+ high-low heterostructure with crystalline silicon. Boron-doped amorphous silicon / nanocrystalline silicon is deposited on the back to form an np heterostructure with crystalline silicon as the back emitter of the battery. (4) Preparation of TCO layer: using PVD or RPD to sputter a highly transparent conductive film on the front and back of the battery to collect carriers; (5) Preparation of electroplating seed layer: Option 1: Use PVD, RPD or evaporation to deposit a seed layer on the front and back of the battery. The seed layer can be made of copper, nickel, aluminum, manganese, molybdenum, copper-nickel alloy, copper-manganese alloy or copper-molybdenum alloy. Alternatively, Option 2: Use PVD, RPD, or vapor deposition to deposit a seed layer on the front of the battery. The seed layer is made of copper, nickel, manganese, molybdenum, copper-nickel alloy, copper-manganese alloy, or copper-molybdenum alloy. Then, use PVD, RPD, or vapor deposition to deposit a seed layer on the back of the battery. The seed layer is made of a corrosion-resistant metal (such as aluminum, nickel-based alloy, or other corrosion-resistant metals). (6) Front and back patterning: Use exposure and development to perform masking in other areas outside the gate line grooves. First, print ink on the front and back of the battery with the electroplating seed layer, then expose, and finally develop, leaving the ink in the mask area to form the gate line grooves; (7) Copper electroplating: using vertical continuous electroplating to electroplate copper gate lines in the gate line grooves, with a front main gate width of 50-80µm, a front sub-gate width of 10-40µm, and a height of 5-20µm; a back main gate width of 50-250µm, a back sub-gate width of 20-80µm, and a height of 5-20µm; (8) Remove the ink mask layer. Immerse the electroplated battery in a solution containing KOH or NaOH to remove the ink mask layer. (9) When Option 1 is used in step (5): Remove the front seed layer, cover the back of the cell with a water film as a protective layer, use a chain etcher, place the cell front side down, cover the front side with dilute sulfuric acid or dilute nitric acid solution, remove the seed layer except for the front copper grid line, then clean it with ultrapure water and dry it, finally retaining the back seed layer, and obtain a single-sided copper grid line heterojunction solar cell; When using option 2 in step (5): Remove the front seed layer, soak the battery in dilute sulfuric acid or dilute nitric acid solution, remove the metal seed layer other than the front copper grid line, then clean it with ultrapure water and dry it. The seed layer on the back is a corrosion-resistant metal, so it can be retained, and finally a single-sided copper grid heterojunction solar cell is obtained.

[0008] Furthermore, in some embodiments of the present invention, the reaction time in step (1) is 200-1800s.

[0009] Furthermore, in some embodiments of the present invention, the size of the pyramid in step (1) is 0.5-4 µm.

[0010] Furthermore, in some embodiments of the present invention, the thickness of the intrinsic amorphous silicon layer in step (2) is 4-10 nm.

[0011] Furthermore, in some embodiments of the present invention, the thickness of the phosphorus-doped amorphous silicon / nanocrystalline silicon deposited on the front side in step (3) is 5-40 nm.

[0012] Furthermore, in some embodiments of the present invention, the thickness of the boron-doped amorphous silicon / nanocrystalline silicon deposited on the back side in step (3) is 5-60 nm.

[0013] Furthermore, in some embodiments of the present invention, the thickness of the seed layer in step (5) is 10-150 nm.

[0014] Preferably, in some embodiments of the present invention, the thickness of the seed layer in step (5) is 60-100 nm.

[0015] The seed layer in step (5) can be made of copper, nickel, aluminum, manganese, molybdenum, copper-nickel alloy, copper-manganese alloy, or copper-molybdenum alloy by using different target materials during the preparation process. The main function of the seed layer is to enhance the bonding strength between the gate line and the TCO, which helps to achieve double-sided electroplating of heterojunction cells. If the copper gate line is directly grown on the silicon surface, the sintering process is reduced, which is likely to cause the gate to delaminate.

[0016] Furthermore, in some embodiments of the present invention, in step (8), the electroplated battery is immersed in a solution containing KOH or NaOH for 30-200 seconds.

[0017] Furthermore, in some embodiments of the present invention, in step (9), the front surface of the battery is covered with a dilute sulfuric acid or dilute nitric acid solution for 30-100 seconds.

[0018] Compared with the existing technology, the advantage of the technical solution of the present invention mainly lies in retaining the back seed layer of the copper grid heterojunction battery. The retention of this metal seed layer greatly improves the back reflection of the heterojunction battery, increases the battery's utilization of long-wavelength sunlight, can effectively increase the short-circuit current by 20~50mA, and the battery efficiency gain is about 0.2% or more; in addition, although this battery structure is a single-sided battery (the bifaciality is very low), it can be fully applied to distributed photovoltaic modules, greatly improving the module power and power generation in this application scenario. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a diagram of the structure of a single-sided heterojunction solar cell of the present invention, wherein 1 is an N-type silicon wafer, 2 is an intrinsic amorphous silicon layer, 3 is an N-type nanocrystalline / amorphous silicon layer, 4 is a P-type nanocrystalline silicon / amorphous silicon layer, 5 is a transparent conductive oxide TCO layer, 6 is a seed layer, and 7 is a copper gate electrode; Figure 2 It is a process flow chart of the single-sided heterojunction solar cell of the present invention. DETAILED DESCRIPTION

[0020] In order to make the objects, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and examples. Additional aspects and advantages of the present invention will be partially given in the following description, partially become apparent from the following description, or be understood through practice of the present invention. It should be understood that the following description is only intended to explain the present invention and is not intended to limit the present invention.

[0021] As used herein, the terms "comprises," "including," "having," "containing" or any other variations thereof, are intended to cover a non-exclusive inclusion. For example, a composition, process, method, article, or apparatus that comprises a listed element is not necessarily limited to only those elements but may include other elements not expressly listed or inherent to such composition, process, method, article, or apparatus.

[0022] When amount, concentration or other value or parameter is represented with range, preferred range or the range that a series of upper preferred value and lower preferred value limit are expressed, this should be understood as specifically disclosing all ranges formed by any pairing of any range upper limit or preferred value and any range lower limit or preferred value, no matter whether this range is disclosed separately.For example, when disclosing scope "1 to 5", described scope should be interpreted as including scope "1 to 4", "1 to 3", "1 to 2", "1 to 2 and 4 to 5", "1 to 3 and 5" etc.When numerical range is described in this article, unless otherwise stated, otherwise this scope is intended to include its end value and all integers and fractions within this range.

[0023] The indefinite articles "a" and "an" before the elements or components of the present invention do not limit the quantity requirement (i.e. the number of times they appear). Therefore, "a" or "an" should be interpreted as including one or at least one, and elements or components in the singular also include plural forms, unless the quantity clearly refers to only the singular form.

[0024] In addition, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples" described below mean that the specific features, structures, materials, or characteristics described in conjunction with that embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the technical features involved in the various embodiments of the present invention may be combined with each other as long as they do not conflict with each other.

[0025] Example 1 Step 1: The first texturing process uses a conventional clean texturing process. The silicon wafer is placed in a mixed solution of NaOH, isopropyl alcohol additive and ultrapure water. The reaction lasts for 800 seconds. A pyramid structure with a size of 3µm is formed on the front and back surfaces of the silicon wafer. Step 2: Preparation of the passivation layer: using PECVD to deposit an intrinsic amorphous silicon layer with a thickness of 4-10nm on the front and back of the cell to passivate the crystalline silicon interface; Step 3: Emitter preparation: Use PECVD to deposit doped amorphous silicon or nanocrystalline silicon layers on the front and back of the battery respectively. Phosphorus-doped nanocrystalline silicon is deposited on the front with a thickness of 25nm to form a nn+ high-low heterostructure with crystalline silicon. Boron-doped nanocrystalline silicon is deposited on the back with a thickness of 40nm to form an np heterostructure with crystalline silicon as the back emitter of the battery. Step 4: Preparation of TCO layer: Use PVD to sputter a highly transparent conductive film on the front and back of the battery to collect carriers. Step 5: Electroplating seed layer preparation: Use PVD to deposit a 60nm copper seed layer on the front and back of the battery. Step 6: Patterning the front and back surfaces, using exposure and development to perform masking in areas other than the gate line trenches. First, ink is printed on the front and back of the cell with the electroplating seed layer, then exposed, and finally developed, leaving the ink in the mask area to form the gate line trenches. Step 7: Copper electroplating: Use vertical continuous electroplating to electroplate copper gate lines in the gate line grooves. The front main gate width is 60µm, the front sub-gate width is 20µm, and the height is 10µm; the back main gate width is 80µm, the back sub-gate width is 30µm, and the height is 10µm. Step 8: Remove the ink mask layer. Immerse the electroplated battery in a solution containing NaOH for 100 seconds to remove the ink mask layer. Step 9: Remove the front seed layer and cover the back of the battery with a water film as a protective layer. Use a chain etcher to place the battery front side down. Cover the front side with dilute sulfuric acid or dilute nitric acid solution for 60 seconds to remove the seed layer except for the copper grid line on the front. Then clean it with ultrapure water and dry it. Finally, the seed layer on the back is retained to obtain a single-sided copper grid heterojunction solar cell.

[0026] Although the single-sided heterojunction solar cell obtained in Example 1 is a single-sided cell, it can be fully applied to distributed photovoltaic modules, greatly improving the module power and power generation in this application scenario, as shown in the following table.

[0027] Example 2 Step 1: The first texturing process uses a conventional clean texturing process. The silicon wafer is placed in a mixed solution of NaOH, isopropyl alcohol additive and ultrapure water. The reaction lasts for 800 seconds. A pyramid structure with a size of 3µm is formed on the front and back surfaces of the silicon wafer. Step 2: Preparation of the passivation layer: using PECVD to deposit an intrinsic amorphous silicon layer with a thickness of 4-10nm on the front and back of the cell to passivate the crystalline silicon interface; Step 3: Emitter preparation: Use PECVD to deposit doped amorphous silicon or nanocrystalline silicon layers on the front and back of the battery respectively. Phosphorus-doped nanocrystalline silicon is deposited on the front with a thickness of 20nm to form a nn+ high-low heterostructure with crystalline silicon. Boron-doped nanocrystalline silicon is deposited on the back with a thickness of 35nm to form an np heterostructure with crystalline silicon as the back emitter of the battery. Step 4: Preparation of TCO layer: Use PVD to sputter a highly transparent conductive film on the front and back of the battery to collect carriers. Step 5: Electroplating seed layer preparation: Use PVD, RPD or evaporation to deposit an 80nm seed layer of nickel on the front and back of the battery. Step 6: Patterning the front and back surfaces, using exposure and development to perform masking in areas other than the gate line trenches. First, ink is printed on the front and back of the cell with the electroplating seed layer, then exposed, and finally developed, leaving the ink in the mask area to form the gate line trenches. Step 7: Copper electroplating: Use vertical continuous electroplating to electroplate copper gate lines in the gate line grooves. The front main gate width is 50µm, the front sub-gate width is 20µm, and the height is 12µm; the back main gate width is 80µm, the back sub-gate width is 30µm, and the height is 12µm. Step 8: Remove the ink mask layer. Immerse the electroplated battery in a solution containing NaOH for 80 seconds to remove the ink mask layer. Step 9: Remove the front seed layer and cover the back of the battery with a water film as a protective layer. Use a chain etcher to place the battery front side down. Cover the front side with dilute sulfuric acid or dilute nitric acid solution for 80 seconds to remove the seed layer except for the copper grid line on the front. Then clean it with ultrapure water and dry it. Finally, the seed layer on the back is retained to obtain a single-sided copper grid heterojunction solar cell.

[0028] Example 3 Step 1: The first texturing process uses a conventional clean texturing process. The silicon wafer is placed in a mixed solution of NaOH, isopropyl alcohol additive and ultrapure water. The reaction lasts for 800 seconds. A pyramid structure with a size of 3µm is formed on the front and back surfaces of the silicon wafer. Step 2: Preparation of the passivation layer: using PECVD to deposit an intrinsic amorphous silicon layer with a thickness of 4-10nm on the front and back of the cell to passivate the crystalline silicon interface; Step 3: Emitter preparation: Use PECVD to deposit doped amorphous silicon or nanocrystalline silicon layers on the front and back of the battery respectively. Phosphorus-doped nanocrystalline silicon is deposited on the front with a thickness of 20nm to form a nn+ high-low heterostructure with crystalline silicon. Boron-doped nanocrystalline silicon is deposited on the back with a thickness of 35nm to form an np heterostructure with crystalline silicon as the back emitter of the battery. Step 4: Preparation of TCO layer: Use PVD to sputter a highly transparent conductive film on the front and back of the battery to collect carriers. Step 5: Electroplating seed layer preparation: Use PVD to deposit a 100nm seed layer on the front and back of the battery. The seed layer is made of copper-nickel alloy. Step 6: Patterning the front and back surfaces, using exposure and development to perform masking in areas other than the gate line trenches. First, ink is printed on the front and back of the cell with the electroplating seed layer, then exposed, and finally developed, leaving the ink in the mask area to form the gate line trenches. Step 7: Copper electroplating: Use vertical continuous electroplating to electroplate copper gate lines in the gate line grooves. The front main gate width is 70µm, the front sub-gate width is 30µm, and the height is 15µm; the back main gate width is 80µm, the back sub-gate width is 30µm, and the height is 12µm. Step 8: Remove the ink mask layer. Immerse the electroplated battery in a solution containing NaOH for 120 seconds to remove the ink mask layer. Step 9: Remove the front seed layer and cover the back of the battery with a water film as a protective layer. Use a chain etcher to place the battery front side down. Cover the front side with dilute sulfuric acid or dilute nitric acid solution for 120 seconds to remove the seed layer except for the copper grid line on the front. Then clean it with ultrapure water and dry it. Finally, the seed layer on the back is retained to obtain a single-sided copper grid heterojunction solar cell.

[0029] Example 4 Step 1: The first texturing process uses a conventional clean texturing process. The silicon wafer is placed in a mixed solution of NaOH, isopropyl alcohol additive and ultrapure water. The reaction lasts for 800 seconds. A pyramid structure with a size of 3µm is formed on the front and back surfaces of the silicon wafer. Step 2: Preparation of the passivation layer: using PECVD to deposit an intrinsic amorphous silicon layer with a thickness of 4-10nm on the front and back of the cell to passivate the crystalline silicon interface; Step 3: Emitter preparation: Use PECVD to deposit doped amorphous silicon or nanocrystalline silicon layers on the front and back of the battery respectively. Phosphorus-doped nanocrystalline silicon is deposited on the front with a thickness of 20nm to form a nn+ high-low heterostructure with crystalline silicon. Boron-doped nanocrystalline silicon is deposited on the back with a thickness of 35nm to form an np heterostructure with crystalline silicon as the back emitter of the battery. Step 4: Preparation of TCO layer: Use PVD to sputter a highly transparent conductive film on the front and back of the battery to collect carriers. Step 5: Electroplating seed layer preparation: Use PVD to deposit a 100nm thick seed layer of copper on the front of the battery; then use PVD to deposit a corrosion-resistant nickel-aluminum alloy layer on the back of the battery. Step 6: Patterning the front and back surfaces, using exposure and development to perform masking in areas other than the gate line trenches. First, ink is printed on the front and back of the cell with the electroplating seed layer, then exposed, and finally developed, leaving the ink in the mask area to form the gate line trenches. Step 7: Copper electroplating: Use vertical continuous electroplating to electroplate copper gate lines in the gate line grooves. The front main gate width is 70µm, the front sub-gate width is 30µm, and the height is 15µm; the back main gate width is 80µm, the back sub-gate width is 30µm, and the height is 12µm. Step 8: Remove the ink mask layer. Immerse the electroplated battery in a solution containing NaOH for 120 seconds to remove the ink mask layer. Step 9: Remove the front seed layer. Soak the battery in dilute sulfuric acid or dilute nitric acid solution for 120 seconds to remove the metal seed layer except the copper grid line on the front. Then clean it with ultrapure water and dry it. The seed layer on the back is a corrosion-resistant nickel-aluminum alloy, so it can be retained, and finally a single-sided copper grid heterojunction solar cell is obtained.

[0030] Similar to Example 1, although the single-sided heterojunction solar cells obtained in Examples 2-4 are single-sided cells, they can be fully applied to distributed photovoltaic modules, greatly improving the module power and power generation in this application scenario.

[0031] It will be easily understood by those skilled in the art that the above description is merely an embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for preparing a distributed photovoltaic module and a single-sided heterojunction solar cell, characterized in that: The preparation method comprises the following steps: (1) The first texturing process is to place the silicon wafer in a mixed solution of KOH or NaOH, isopropyl alcohol additive and ultrapure water to react and form a pyramid structure on the front and back surfaces of the silicon wafer; (2) Preparation of the passivation layer: using PECVD to deposit an intrinsic amorphous silicon layer on the front and back of the battery to passivate the crystalline silicon interface; (3) Emitter preparation: using PECVD to deposit doped amorphous silicon or nanocrystalline silicon layers on the front and back of the battery respectively. Phosphorus-doped amorphous silicon / nanocrystalline silicon is deposited on the front to form a nn+ high-low heterostructure with crystalline silicon. Boron-doped amorphous silicon / nanocrystalline silicon is deposited on the back to form an np heterostructure with crystalline silicon as the back emitter of the battery. (4) Preparation of TCO layer: using PVD or RPD to sputter a highly transparent conductive film on the front and back of the battery to collect carriers; (5) Preparation of electroplating seed layer: Option 1: Use PVD, RPD or evaporation to deposit a seed layer on the front and back of the battery. The seed layer can be made of copper, nickel, aluminum, manganese, molybdenum, copper-nickel alloy, copper-manganese alloy or copper-molybdenum alloy. Alternatively, Option 2: Use PVD, RPD, or evaporation to deposit a seed layer on the front of the battery. The seed layer is made of copper, nickel, manganese, molybdenum, copper-nickel alloy, copper-manganese alloy, or copper-molybdenum alloy. Then, use PVD, RPD, or evaporation to deposit a seed layer on the back of the battery. The seed layer is made of a corrosion-resistant metal. (6) Front and back patterning: Use exposure and development to perform masking in other areas outside the gate line grooves. First, print ink on the front and back of the battery with the electroplating seed layer, then expose, and finally develop, leaving the ink in the mask area to form the gate line grooves; (7) Copper electroplating: using vertical continuous electroplating to electroplate copper gate lines in the gate line grooves, with a front main gate width of 50-80µm, a front sub-gate width of 10-40µm, and a height of 5-20µm; a back main gate width of 50-250µm, a back sub-gate width of 20-80µm, and a height of 5-20µm; (8) Remove the ink mask layer. Immerse the electroplated battery in a solution containing KOH or NaOH to remove the ink mask layer. (9) When Option 1 is used in step (5): Remove the front seed layer, cover the back of the cell with a water film as a protective layer, use a chain etcher, place the cell front side down, cover the front side with dilute sulfuric acid or dilute nitric acid solution, remove the seed layer except for the front copper grid line, then clean it with ultrapure water and dry it, finally retaining the back seed layer, and obtain a single-sided copper grid line heterojunction solar cell; When using option 2 in step (5): Remove the front seed layer, cover the front of the battery with dilute sulfuric acid or dilute nitric acid solution, remove the metal seed layer except the front copper grid line, then clean it with ultrapure water and dry it. The seed layer on the back is a corrosion-resistant metal, so it can be retained, and finally a single-sided copper grid heterojunction solar cell is obtained.

2. The method for preparing a distributed photovoltaic module and a single-sided heterojunction solar cell according to claim 1, characterized in that: The reaction time in step (1) is 200-1800s.

3. The method for preparing a distributed photovoltaic module and a single-sided heterojunction solar cell according to claim 1, characterized in that: The size of the pyramid in step (1) is 0.5-4µm.

4. The method for preparing a distributed photovoltaic module and a single-sided heterojunction solar cell according to claim 1, characterized in that: The thickness of the intrinsic amorphous silicon layer in step (2) is 4-10 nm.

5. The method for preparing a distributed photovoltaic module and a single-sided heterojunction solar cell according to claim 1, characterized in that: The thickness of the phosphorus-doped amorphous silicon / nanocrystalline silicon deposited on the front in step (3) is 5-40 nm.

6. The method for preparing a distributed photovoltaic module and a single-sided heterojunction solar cell according to claim 1, characterized in that: The thickness of the boron-doped amorphous silicon / nanocrystalline silicon deposited on the back in step (3) is 5-60 nm.

7. The method for preparing a distributed photovoltaic module and a single-sided heterojunction solar cell according to claim 1, characterized in that: The thickness of the seed layer in step (5) is 10-150 nm.

8. The method for preparing a distributed photovoltaic module and a single-sided heterojunction solar cell according to claim 1, characterized in that: The thickness of the seed layer in step (5) is 60-100 nm.

9. The method for preparing a distributed photovoltaic module and a single-sided heterojunction solar cell according to claim 1, characterized in that: In the step (8), the electroplated battery is immersed in a solution containing KOH or NaOH for 30-200 seconds.

10. The method for preparing a distributed photovoltaic module and a single-sided heterojunction solar cell according to claim 1, characterized in that: In step (9), the front of the battery is covered with a dilute sulfuric acid or dilute nitric acid solution for 30-100 seconds.

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