Processor instruction fetching control methods, systems and electronic devices

Abstract

This invention provides a processor instruction fetch control method, system, and electronic device, relating to the field of chip instruction control. This solution additionally sets up an instruction buffer between the instruction fetch queue unit and the decoding unit, allowing subsequently hit instruction blocks to be read first and cached at a specific location in the instruction buffer. Before outputting to the decoding unit, the instruction data is rearranged according to the order of the instruction fetch blocks, ensuring that from the external logic perspective, execution is still in sequence. This solves the problem of global blocking caused by instruction fetch failures in existing technologies, and fully leverages the performance advantages of wide-issue CPUs.

Description

Technical Field

[0001] This invention relates to the field of chip instruction control, and in particular to a processor instruction read control method, system, and electronic device. Background Technology

[0002] Modern CPU processors typically include branch prediction, a fetch queue, iCache, iTLB architecture, and pipelined components in their front-end. Processor instructions must flow into the decoding unit strictly in program order. This constraint means that if the front-end instruction fetch stage encounters an iCache or iTLB failure, subsequently hit instructions must wait in the queue until they are filled before the pipeline can continue. Therefore, in wide-issue CPUs, if the front-end is blocked, the back-end issue will not receive enough instructions, significantly impacting throughput. Summary of the Invention

[0003] In view of this, the purpose of this invention is to provide a processor instruction fetch control method, system, and electronic device. This solution additionally sets up an instruction buffer between the instruction fetch queue unit and the decoding unit, allowing subsequently hit instruction blocks to be read first and cached in a specific location within the instruction buffer. Before outputting to the decoding unit, the instruction data is rearranged according to the order of the instruction fetch blocks, ensuring that from the perspective of external logic, execution is still in sequence. This solves the global blocking caused by instruction fetch process failures in existing technologies and fully leverages the performance advantages of wide-issue CPUs.

[0004] In a first aspect, embodiments of the present invention provide a processor instruction fetching control method, the method comprising:

[0005] The instruction buffer corresponding to the instruction fetch unit is constructed based on the instruction fetch queue unit and the decoding unit contained in the processor's instruction fetch unit; wherein, the instruction buffer is located between the instruction fetch queue unit and the decoding unit;

[0006] When the instruction fetch request instruction corresponding to the instruction fetch queue unit fails to respond, the first size parameter of the current instruction fetch block corresponding to the instruction fetch request instruction and the response failure information are obtained. The instruction buffer is controlled to reserve the first address range corresponding to the first size parameter, and the instruction fetch queue unit is controlled to fetch the subsequent instruction fetch blocks of the current instruction fetch block according to the execution order of the instruction fetch request instructions.

[0007] When the response failure information is detected to have disappeared, the control fetch queue unit makes a fetch request for the current fetch block and obtains the backfill data corresponding to the current fetch block.

[0008] The control instruction buffer writes the backfill data into the reserved first address range, and uses the first address range to control the first processor instruction corresponding to the backfill data to be sent to the decoding unit.

[0009] Optionally, the first size parameter of the current fetch block corresponding to the fetch request instruction and the response failure information are obtained, and the instruction buffer is controlled to reserve a first address range corresponding to the first size parameter, including:

[0010] Determine the instruction cache tag array corresponding to the instruction fetch request instruction, and obtain the first size parameter corresponding to the current instruction fetch block;

[0011] The instruction cache tag array is used to determine the response failure information corresponding to the current instruction fetch block, and the first flag bit corresponding to the first address range is set to the first flag; wherein, the response failure information includes at least: no data in the instruction cache and translation failure of the instruction translation detection buffer address;

[0012] According to the address length value corresponding to the first size parameter, the control instruction buffer reserves a first address range consistent with the address length value at a preset starting point.

[0013] Optionally, the instruction fetch queue unit is controlled to fetch instruction requests for subsequent instruction fetch blocks of the current instruction fetch block according to the execution order of the instruction fetch requests, including:

[0014] After the first size parameter is called back to the instruction fetch queue unit, the execution order of the instruction fetch request instruction is determined based on the instruction fetch block number information corresponding to the instruction fetch request instruction.

[0015] Get the current number corresponding to the current fetch block, and determine the adjacent numbers corresponding to the current number based on the execution order;

[0016] The adjacent number is used to determine the subsequent instruction fetch block corresponding to the current instruction fetch block, and the instruction fetch queue unit is controlled to make instruction fetch requests for the subsequent instruction fetch block.

[0017] Optionally, when the response failure information is detected to have disappeared, the control fetch queue unit makes a fetch request for the current fetch block and obtains the backfill data corresponding to the current fetch block, including:

[0018] When the response failure message disappears, a wake-up instruction corresponding to the current fetch block is generated;

[0019] The control fetch queue unit controls the current fetch block to make a fetch request based on the wake-up command, obtains the backfill data corresponding to the current fetch block, and obtains the first size parameter through the fetch queue unit.

[0020] Optionally, the control instruction buffer writes the backfill data into a reserved first address range, and uses the first address range to control the first processor instruction corresponding to the backfill data to be sent to the decoding unit, including:

[0021] After the control instruction buffer writes the backfill data into the reserved first address range according to the first size parameter, it sets the first flag bit corresponding to the first address range to the second flag.

[0022] When the first flag bit is detected as the second flag, the control instruction buffer sends the first processor instruction corresponding to the backfill data to the decoding unit.

[0023] Optionally, after controlling the instruction fetch queue unit to fetch instructions for subsequent instruction fetch blocks of the current instruction fetch block according to the execution order of the instruction fetch requests, the method further includes:

[0024] Determine the subsequent fetch request instruction corresponding to the subsequent fetch block;

[0025] When a successful response is detected to the subsequent fetch request instruction corresponding to the fetch queue unit, the second size parameter and instruction data corresponding to the subsequent fetch block are obtained, and the instruction buffer is controlled to determine the second address range corresponding to the second size parameter; wherein, the second address range is adjacent to the first address range;

[0026] The control instruction buffer writes instruction data into the second address range and sets the corresponding flag bit of the second address range to the second flag.

[0027] Optionally, obtain the second size parameters and instruction data corresponding to the subsequent instruction fetch block, including:

[0028] Determine the instruction cache data array corresponding to the subsequent instruction fetch request instruction, and obtain the second size parameter corresponding to the subsequent instruction fetch block;

[0029] The instruction data corresponding to the subsequent instruction fetch block is obtained by using the instruction cache data array.

[0030] Optionally, after the step of controlling the instruction buffer to write the backfill data into the reserved first address range and using the first address range to control the first processor instruction corresponding to the backfill data to be sent to the decoding unit, the method further includes:

[0031] Obtain the second flag bit corresponding to the second address range;

[0032] When the second flag bit is detected as the second flag, the control instruction buffer sends the second processor instruction corresponding to the instruction data to the decoding unit.

[0033] Secondly, the present invention provides a processor instruction fetching control system, the system comprising:

[0034] The instruction buffer construction module is used to construct the instruction buffer corresponding to the instruction fetch unit based on the instruction fetch queue unit and the decoding unit contained in the processor's instruction fetch unit; wherein, the instruction buffer is set between the instruction fetch queue unit and the decoding unit;

[0035] The instruction fetch request exception handling module is used to obtain the first size parameter of the current instruction fetch block corresponding to the instruction fetch request instruction and the response failure information when the instruction fetch request instruction corresponding to the instruction fetch queue unit is detected to fail. It controls the instruction buffer to reserve the first address range corresponding to the first size parameter and controls the instruction fetch queue unit to perform instruction fetch requests on the subsequent instruction fetch blocks of the current instruction fetch block according to the execution order of the instruction fetch request instructions.

[0036] The normal processing module for fetch requests is used to control the fetch queue unit to make a fetch request for the current fetch block and obtain the backfill data corresponding to the current fetch block when the response failure information is detected to have disappeared.

[0037] The processor instruction control module is used to control the instruction buffer to write backfill data into a reserved first address range, and to use the first address range to control the first processor instruction corresponding to the backfill data to be sent to the decoding unit.

[0038] Thirdly, embodiments of the present invention also provide an electronic device, including a processor and a memory, wherein the memory stores computer-executable instructions that can be executed by the processor, and the processor executes the computer-executable instructions to implement the steps of the processor instruction read control method provided in the first aspect.

[0039] Fourthly, embodiments of the present invention also provide a storage medium storing computer-executable instructions, which, when invoked and executed by a processor, cause the processor to implement the steps of the processor instruction read control method provided in the first aspect.

[0040] This invention provides a processor instruction fetching control method, system, and electronic device. In the process of controlling the fetching of processor instructions using an instruction fetching unit, an instruction buffer corresponding to the instruction fetching unit is first constructed based on the fetch queue unit and decoding unit included in the processor's instruction fetching unit. The instruction buffer is positioned between the fetch queue unit and the decoding unit. When a fetch request instruction corresponding to the fetch queue unit fails to respond, the first size parameter of the current fetch block corresponding to the fetch request instruction and the response failure information are obtained. The instruction buffer is then controlled to reserve a first address range corresponding to the first size parameter, and the fetch queue unit is controlled to fetch subsequent fetch blocks of the current fetch block according to the execution order of the fetch request instructions. When the response failure information disappears, the fetch queue unit is controlled to fetch the current fetch block and obtain the backfill data corresponding to the current fetch block. Finally, the instruction buffer is controlled to write the backfill data into the reserved first address range, and the first processor instruction corresponding to the backfill data is sent to the decoding unit using the first address range. This scheme adds an instruction buffer between the fetch queue unit and the decode unit, allowing subsequently hit instruction blocks to be read first and cached in a specific location within this instruction buffer. Before outputting to the decode unit, the instruction data is rearranged according to the order of the fetch blocks, ensuring that from the external logic perspective, it still appears to be executed in sequence. This solves the global blocking caused by instruction fetch failures in existing technologies and fully leverages the performance advantages of wide-issue CPUs.

[0041] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention are realized and obtained in accordance with the structures particularly pointed out in the description, claims and drawings.

[0042] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0043] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0044] Figure 1 A flowchart of a processor instruction read control method provided in an embodiment of the present invention;

[0045] Figure 2In step S102 of a processor instruction fetch control method provided in an embodiment of the present invention, a flowchart is shown in which the first size parameter of the current fetch block corresponding to the fetch request instruction and the response failure information are obtained, and the instruction buffer is controlled to reserve a first address range corresponding to the first size parameter.

[0046] Figure 3 In step S102 of a processor instruction fetch control method provided in an embodiment of the present invention, there is a flowchart of controlling the fetch queue unit to fetch instructions to subsequent fetch blocks of the current fetch block according to the execution order of the fetch request instructions;

[0047] Figure 4 A flowchart of step S103 in a processor instruction read control method provided in an embodiment of the present invention;

[0048] Figure 5 A flowchart of step S104 in a processor instruction read control method provided in an embodiment of the present invention;

[0049] Figure 6 In step S102 of a processor instruction fetch control method provided in an embodiment of the present invention, a flowchart is shown after controlling the fetch queue unit to fetch the subsequent fetch blocks of the current fetch block according to the execution order of the fetch request instructions.

[0050] Figure 7 In step S602 of a processor instruction fetch control method provided in an embodiment of the present invention, a flowchart is provided for obtaining the second size parameter and instruction data corresponding to the subsequent fetch block;

[0051] Figure 8 This is a flowchart following step S104 in a processor instruction read control method provided in an embodiment of the present invention;

[0052] Figure 9 A flowchart of another processor instruction read control method provided in an embodiment of the present invention;

[0053] Figure 10 This is a schematic diagram of the structure of a processor instruction reading control system provided in an embodiment of the present invention;

[0054] Figure 11 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention.

[0055] icon:

[0056] 1010 - Instruction buffer construction module; 1020 - Instruction fetch request exception handling module; 1030 - Instruction fetch request normal handling module; 1040 - Processor instruction control module;

[0057] 101 - Processor; 102 - Memory; 103 - Bus; 104 - Communication interface. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0059] Modern CPU processors typically include branch prediction, a fetch queue, iCache, iTLB architecture, and pipelines in their front-end. Processor instructions must flow into the decoding unit strictly in program order. This constraint means that if an iCache or iTLB miss occurs during the front-end instruction fetching phase, subsequently hit instructions must wait in the queue until they are filled before the pipeline can continue. Therefore, in wide-issue CPUs, if the front-end is blocked, the back-end will not receive enough instructions, significantly impacting throughput. Specifically, when an iCache Miss or iTLB Miss occurs, subsequent hit instruction blocks cannot be fetched, resulting in wasted front-end bandwidth. Furthermore, when the front-end is blocked due to a Miss and cannot supply instructions to the back-end, the performance of the wide-issue pipeline is limited.

[0060] Based on this, the present invention provides a processor instruction fetch control method, system, and electronic device. This solution additionally sets up an instruction buffer between the instruction fetch queue unit and the decoding unit, allowing subsequently hit instruction blocks to be read first and cached in a specific location within the instruction buffer. Before outputting to the decoding unit, the instruction data is rearranged according to the order of the fetch blocks, ensuring that from the external logic perspective, execution is still in sequence. This solves the problem of global blocking caused by instruction fetch failures in existing technologies, and fully leverages the performance advantages of wide-issue CPUs.

[0061] To facilitate understanding of this embodiment, a processor instruction fetching control method disclosed in this embodiment of the invention will first be described in detail, such as... Figure 1 As shown, the method includes:

[0062] Step S101: Construct an instruction buffer corresponding to the instruction fetch unit based on the instruction fetch queue unit and the decoding unit contained in the processor's instruction fetch unit; wherein, the instruction buffer is set between the instruction fetch queue unit and the decoding unit.

[0063] The core of this step is to build an intermediate data buffer structure for the processor's instruction fetch unit. Specifically, based on the two existing key components in the instruction fetch unit: the instruction fetch queue unit (responsible for initiating instruction read requests and temporarily storing instruction fetch tasks to be processed) and the decoding unit (responsible for parsing and preprocessing the read instructions), a dedicated "instruction buffer" is set up between the two.

[0064] This buffer acts like a "data transfer station." Its design aims to resolve the conflict between temporary blockages that may occur during instruction fetching (such as storage system response delays) and the continuous working requirements of the decoding unit. It ensures that the instruction fetching and decoding processes can work together more flexibly and avoids the decoding unit from "running out of control" due to instruction fetching interruptions.

[0065] Step S102: When the instruction fetch request instruction corresponding to the instruction fetch queue unit fails to respond, the first size parameter of the current instruction fetch block corresponding to the instruction fetch request instruction and the response failure information are obtained. The instruction buffer is controlled to reserve the first address range corresponding to the first size parameter, and the instruction fetch queue unit is controlled to fetch the subsequent instruction fetch blocks of the current instruction fetch block according to the execution order of the instruction fetch request instructions.

[0066] When the fetch queue unit sends a fetch request instruction to the cache or memory, if the request response fails (possibly due to a cache miss, bus conflict, or other reasons that temporarily prevent the instruction data from being obtained), the following operations are performed:

[0067] Obtain key information: Extract the first size parameter of the "current fetch block" corresponding to the current failed fetch request (i.e., the instruction length, storage size, and other characteristic parameters contained in the fetch block), and record the specific information of the failure response (such as the reason for failure, the time of failure, etc.).

[0068] Reserved buffer space: The control instruction buffer reserves a first address range that matches the first size parameter for the current instruction fetch block, ensuring that when the data of the instruction fetch block becomes available later, there is dedicated space for storage and the instruction order will not be disrupted.

[0069] Continue with subsequent instruction fetches: To avoid blocking the entire instruction fetch process due to the failure of the current instruction fetch block, the instruction fetch queue unit is controlled to skip the currently failed instruction fetch block and continue to initiate instruction fetch requests for subsequent instruction fetch blocks according to the original instruction fetch request execution order. This design can maximize the utilization of instruction fetch bandwidth and reduce waiting time.

[0070] Step S103: When the response failure information is detected to have disappeared, the control fetch queue unit makes a fetch request for the current fetch block and obtains the backfill data corresponding to the current fetch block.

[0071] When the failure message that previously caused the instruction fetch failure is detected to have disappeared (i.e., the cache has recovered and can respond to the original instruction fetch request), the current instruction fetch block will be reprocessed immediately. The control instruction fetch queue unit will re-initiate an instruction fetch request for the current instruction fetch block. After the request succeeds, the complete instruction data corresponding to the instruction fetch block will be obtained and used as backfill data. Here, backfilling emphasizes that this data supplements the previously reserved space and is a key operation after the process is restored.

[0072] Step S104: The control instruction buffer writes the backfill data into the reserved first address range, and uses the first address range to control the first processor instruction corresponding to the backfill data to be sent to the decoding unit.

[0073] After acquiring the backfill data for the current instruction fetch block, the final instruction flow is completed. First, the backfill data is written into the reserved first address range. The control instruction buffer accurately writes the backfill data into the reserved first address range in step S102, ensuring that the data storage location is consistent with the previous plan and maintaining the continuity of the instruction sequence. Then, it is sent to the decoding unit in sequence. Using the address information (such as the start address and end address) of the first address range, the control buffer sends the first processor instruction corresponding to the backfill data (i.e., the instruction contained in the current instruction fetch block) to the decoding unit in the correct order, connecting it with the previously fetched subsequent instruction fetch block instructions, ensuring that the decoding unit can process the instructions according to the original instruction flow order.

[0074] In summary, this method effectively improves the processor's ability to handle temporary faults during instruction fetching by introducing mechanisms such as instruction buffers, dynamic space reservation, priority processing of subsequent instruction fetches, and backfilling after failures, and reduces the impact of instruction fetch interrupts on overall instruction execution efficiency.

[0075] Optionally, the first size parameter of the current fetch block corresponding to the fetch request instruction and the response failure information are obtained, and the instruction buffer is controlled to reserve a first address range corresponding to the first size parameter, such as... Figure 2 As shown, it includes:

[0076] Step S201: Determine the instruction cache tag array corresponding to the instruction fetch request instruction, and obtain the first size parameter corresponding to the current instruction fetch block.

[0077] When a fetch request from a fetch queue unit fails to respond, it is necessary to determine the basic information and location criteria for the current fetch block. Specific operations include:

[0078] Locating the instruction cache tag array (iCache Tag Array): The instruction cache tag array is a key metadata structure stored in the instruction cache. It records information such as the index tag, address mapping relationship, and validity identifier of each fetch block in the cache. Based on the target address (such as virtual address or physical address) of the current instruction fetch request, the corresponding instruction cache tag array entry can be located, which serves as the basis for subsequent determination of the instruction fetch status.

[0079] The process of extracting the first size parameter involves parsing the attribute information of the current fetch block (which can be obtained from the instruction cache tag array or the fetch request instruction itself) to determine its first size parameter. This parameter specifically includes: the number of instructions contained in the fetch block, the length of storage bytes occupied, the address span (i.e., the difference between the start address and the end address), etc. This information directly determines the size of the buffer space that needs to be reserved subsequently.

[0080] Step S202: Use the instruction cache tag array to determine the response failure information corresponding to the current instruction fetch block, and set the first flag bit corresponding to the first address range to the first flag; wherein, the response failure information includes at least: no data in the instruction cache and instruction translation detection buffer address translation failure.

[0081] After obtaining the instruction cache tag array and the first size parameter, it is necessary to determine the specific reason for the instruction fetch failure and mark the status of the reserved space. Specifically, during the parsing of the response failure information, the status flags in the instruction cache tag array (such as "valid bit," "hit flag," etc.) can be used to determine the specific reason for the failure of the current instruction fetch block response. According to the description, the failure information includes at least two core scenarios:

[0082] No data in instruction cache (iCache Miss): This means that the instruction cache was not hit (there is no matching valid entry in the tag array). The data of the current instruction fetch block is not cached and needs to be read from a lower level of storage (such as main memory), resulting in temporary unresponsiveness.

[0083] Translation Lookaside Buffer (TLB) Address Translation Failure (iTLBMiss): When an instruction fetch request uses a virtual address, the TLB must translate the virtual address into a physical address. If there is no corresponding translation entry in the TLB (TLB miss) or if a permission error occurs during the translation process, the address will be invalid, and the instruction fetch request will fail.

[0084] At this point, a status flag bit (first flag bit) is set in the instruction buffer for the first address range to be reserved, and its value is set to "not ready". The purpose of this flag is to make it clear to the system that this range has been allocated to the currently failed instruction fetch block, but the data has not yet been filled, and it is temporarily unavailable for use by the decoding unit to avoid subsequent process errors.

[0085] Step S203: According to the address length value corresponding to the first size parameter, the control instruction buffer reserves a first address range consistent with the address length value according to a preset starting point.

[0086] After completing parameter acquisition and status marking, accurate storage space needs to be reserved in the instruction buffer for the current instruction fetch block. First, determine the address length value. Based on the first size parameter obtained in step S201, extract its corresponding "address length value" (i.e., the length of the continuous address space required for the complete storage of the current instruction fetch block, usually in bytes).

[0087] Then, the instruction buffer is allocated according to the preset starting point. The instruction buffer has preset space allocation rules (such as continuous allocation from low address to high address, or fixed starting offset divided by block). According to this rule, a "preset starting point" (i.e. the starting address of the reserved interval) is determined. Then, starting from this starting point, a continuous space that completely matches the "address length value" is divided as the first address interval.

[0088] This operation ensures that the "backfill data" following the current instruction fetch block has dedicated, appropriately sized storage space, and that the location of this interval conforms to the buffer management specifications, providing a foundation for the orderly writing of subsequent data and sending of instructions.

[0089] Optionally, the instruction fetch queue unit is controlled to fetch instruction requests for subsequent instruction fetch blocks according to the execution order of the instruction fetch requests, such as... Figure 3 As shown, it includes:

[0090] Step S301: After the first size parameter is called back to the instruction fetch queue unit, the execution order of the instruction fetch request instruction is determined based on the instruction fetch block number information corresponding to the instruction fetch request instruction.

[0091] If the fetch request for the current fetch block fails to respond, two key operations are performed to ensure that the fetch queue unit can correctly process subsequent fetch blocks:

[0092] First size parameter callback: The first size parameters (such as instruction block length, address span, etc.) of the current instruction fetch block obtained in step S201 are fed back (callback) to the instruction fetch queue unit. The purpose of this operation is to let the instruction fetch queue unit know the "space occupancy characteristics" of the current failed instruction fetch block, so as to provide a basis for calculating the starting address of the subsequent instruction fetch block and avoiding address conflicts.

[0093] The execution order is determined based on instruction numbering information: Each instruction fetch request instruction corresponds to an instruction fetch block containing unique "instruction numbering information" (which can be understood as the logical sequence number of the instruction fetch block, such as consecutive numbers assigned according to the program execution flow, such as Block 0, Block 1, Block 2..., or an index number associated with a physical address). By parsing this instruction numbering information, the original execution order of all instruction fetch blocks is determined, which is usually consistent with the order of the program instruction flow (i.e., arranged in the direction of the program counter PC's increment), ensuring that subsequent instruction fetches do not disrupt the logical execution sequence of instructions.

[0094] Step S302: Obtain the current number corresponding to the current fetch block, and determine the adjacent numbers corresponding to the current number based on the execution order.

[0095] After determining the instruction fetch execution order, it is necessary to locate the specific identifier of the "subsequent instruction fetch block". First, obtain the current number by extracting its corresponding "current number" from the metadata of the currently failed instruction fetch block (for example, if the current instruction fetch block is the 5th instruction fetch block, its number is "5"). This number is the basis for locating the subsequent instruction fetch block.

[0096] Then, the adjacent numbers are determined. Based on the execution order determined in step S301 (such as the ascending order of the numbers), the next number immediately adjacent to the current number in the sequence is found, which is the "adjacent number". For example, if the current number is "5" and the execution order is that the numbers ascend sequentially, then the adjacent number is "6". This adjacent number directly points to the "next fetch block of the current fetch block" and is the target identifier for subsequent fetches.

[0097] Step S303: Use adjacent numbers to determine the subsequent fetch block corresponding to the current fetch block, and control the fetch queue unit to make fetch requests for the subsequent fetch block.

[0098] After locking onto the target by adjacent numbering, the actual control of subsequent instruction fetching is completed. First, the subsequent instruction fetch block is determined, specifically by using adjacent numbers as indexes to locate the corresponding instruction fetch block in the instruction fetch task list of the instruction fetch queue unit, i.e., the "subsequent instruction fetch block of the current instruction fetch block". This instruction fetch block should be the next instruction block immediately following the current instruction fetch block in the original execution order. Its address range can be calculated by combining the size parameters of the preceding instruction fetch block (such as the first size parameter of the current instruction fetch block) (for example, the end address of the current instruction fetch block + 1 is the start address of the subsequent instruction fetch block). Then, the control instruction fetch queue unit initiates a request. The instruction fetch queue unit skips the currently failed instruction fetch block and, according to the original execution order, initiates an instruction fetch request for the located subsequent instruction fetch block. This operation ensures that the instruction fetch process does not stall due to the failure of a single instruction fetch block, but continues forward, maximizing the use of instruction fetch bandwidth, reducing waiting time, and reserving data for the decoding and execution of subsequent instructions.

[0099] Optionally, when the response failure information is detected to have disappeared, the step S103, which involves controlling the instruction fetch queue unit to make an instruction fetch request for the current instruction fetch block and then obtaining the backfill data corresponding to the current instruction fetch block, is as follows: Figure 4 As shown, it includes:

[0100] Step S401: When the response failure information is detected to have disappeared, generate the wake-up instruction corresponding to the current fetch block.

[0101] When a real-time monitoring mechanism (such as storage system status feedback, TLB (Instruction Translation Detection Buffer) update notification, detects that the response failure information that previously caused the instruction fetch failure has disappeared (e.g., the instruction cache has completed loading the data for the current instruction fetch block, the TLB has successfully completed address translation and cached the valid mapping relationship), it means that the instruction fetch conditions for the current instruction fetch block have returned to normal. At this time, the system will perform a critical operation: generating the "wake-up instruction" corresponding to the current instruction fetch block.

[0102] This wake-up instruction is a control signal specifically for the blocked current instruction fetch block, and its core functions include:

[0103] The instruction fetch condition for this instruction fetch block has been met, and the state changes from "waiting" to "executable".

[0104] Carry key identification information of the current instruction fetch block (such as number, original instruction fetch address, etc.) to ensure that the instruction fetch queue unit can accurately locate the corresponding instruction fetch task;

[0105] The instruction fetch queue unit is triggered to prioritize the re-request of the instruction fetch block, so as to avoid it being blocked by subsequent instruction fetch tasks for a long time.

[0106] Step S402: Control the instruction fetch queue unit to control the current instruction fetch block to make an instruction fetch request based on the wake-up instruction, obtain the backfill data corresponding to the current instruction fetch block, and obtain the first size parameter through the instruction fetch queue unit.

[0107] After the wake-up command is generated, it further controls the instruction fetch queue unit to complete the specific instruction fetching operation and data acquisition:

[0108] In response to the wake-up command, the instruction fetch queue unit initiates an instruction fetch request: After receiving the wake-up command, the instruction fetch queue unit locates the original instruction fetch request record for that instruction block in the task queue based on the identification information carried in the command (such as the current instruction fetch block number and address), and then re-initiates the instruction fetch request to the storage system (such as the instruction cache with cached data, or the target storage unit after address translation). Since the obstacle to response failure has been removed at this point, the request usually receives a successful response.

[0109] Retrieving Backfill Data: After a successful instruction fetch request, the complete instruction data corresponding to the current fetch block is received, i.e., "backfill data". This data contains key instruction information that was missing due to the previous instruction fetch failure and needs to be written into the first address range reserved in the instruction buffer to complete the instruction stream.

[0110] Re-acquiring the first size parameter: While acquiring the backfill data, the instruction fetch queue unit will again extract the first size parameter of the current instruction fetch block (consistent with the parameters acquired in step S201, such as instruction block length, address span, etc.). The purpose of this operation is to: verify whether the actual size of the backfill data matches the reserved first address range, ensuring data integrity (avoiding data truncation or redundancy due to storage system anomalies); and to provide accurate size basis for subsequent instruction buffer write operations, ensuring that data can be accurately filled into the reserved range without occupying the space of other instruction fetch blocks.

[0111] Optionally, in step S104, the control instruction buffer writes the backfill data into a reserved first address range, and uses the first address range to control the first processor instruction corresponding to the backfill data to be sent to the decoding unit. Figure 5 As shown, it includes:

[0112] Step S501: After the control instruction buffer writes the backfill data to the reserved first address range according to the first size parameter, the first flag bit corresponding to the first address range is set to the second flag.

[0113] Once the instruction fetch queue unit successfully retrieves the backfill data for the current instruction fetch block, it accurately stores the data into the instruction buffer and updates the space status to indicate that the data is ready.

[0114] Write backfill data by size: The instruction buffer writes the backfill data completely into the first address range reserved in step S203 according to the first size parameters (such as address length value, number of instructions, etc.) obtained in step S201. During the writing process, double verification is performed: verifying whether the actual length of the backfill data matches the first size parameter (to avoid data truncation or redundancy); verifying whether the write address is strictly limited to the first address range (to prevent out-of-bounds writing from interfering with the space of other instruction fetch blocks).

[0115] This operation ensures that the backfilled data is stored correctly in the buffer and in a location that is completely consistent with the initial plan.

[0116] Set the first flag bit to the second flag bit: After the data is written, update the first flag bit (originally in the state of "not ready", i.e., the first flag) corresponding to the first address range to the second flag bit (usually "ready", indicating readiness). This flag bit state switch is a key signal, and its functions include: announcing that the data in the address range is complete and available for subsequent process calls; distinguishing between "ready" and "not ready" instruction fetch block data in the buffer to avoid the decoding unit reading invalid or incomplete instructions; and serving as a trigger condition for instruction sending, providing a basis for judgment for the execution of step S502.

[0117] Step S502: When the first flag bit is detected as the second flag, the control instruction buffer sends the first processor instruction corresponding to the backfill data to the decoding unit.

[0118] Once the first flag is updated to the second flag, this change is detected through a status monitoring mechanism (such as real-time polling or interrupt triggering), and the instruction sending process is initiated.

[0119] Flag status detection: The control logic of the instruction buffer continuously monitors the flag status of each address range. When it detects that the first flag of the first address range is the second flag ("ready"), it confirms that the backfilled data for that range has met the transmission conditions.

[0120] Control instructions are sent to the decoding unit: Based on the address information (such as start address and end address) of the first address range, the "first processor instruction" (i.e. the complete instruction sequence contained in the current instruction fetch block) corresponding to the backfill data in the buffer is read from the buffer and sent to the decoding unit in the original order of the instructions (consistent with the program execution flow).

[0121] The "sequential sending" here is particularly important: since the subsequent instruction fetch blocks of the current instruction fetch block may have been fetched in advance and temporarily stored in the buffer (the result of the operation in step S303), it will ensure that the instructions of the current instruction fetch block are sent before the instructions of the subsequent instruction fetch blocks, so as to maintain the logical continuity of the entire instruction stream and avoid execution errors caused by the decoding unit processing out-of-order instructions.

[0122] Optionally, after the control fetch queue unit fetches instructions for subsequent instruction fetch blocks according to the execution order of the instruction fetch requests, such as... Figure 6 The method further includes:

[0123] Step S601: Determine the subsequent fetch request instruction corresponding to the subsequent fetch block.

[0124] In step S303, the instruction fetch queue unit has initiated instruction fetch requests for subsequent instruction fetch blocks of the current instruction fetch block according to the execution order. The core of this step is to clarify the correspondence between these subsequent instruction fetch blocks and the specific requested instructions:

[0125] By using the fetch task list recorded in the fetch queue unit, and based on the numbering information of subsequent fetch blocks (such as the adjacent numbers determined in step S302 and subsequent incrementing numbers), the "subsequent fetch request instruction" corresponding to each subsequent fetch block is located. These request instructions contain key information such as the target address (virtual address or physical address) and fetch range of the fetch block, which are the basis for subsequent data acquisition and storage.

[0126] The purpose of this operation is to establish a precise mapping between the "fetch block" and the "request instruction" to ensure that subsequent data processing corresponds to the original fetch requirements and avoids address or range confusion.

[0127] Step S602: When the subsequent fetch request instruction corresponding to the fetch queue unit is successfully responded to, the second size parameter and instruction data corresponding to the subsequent fetch block are obtained, and the instruction buffer is controlled to determine the second address range corresponding to the second size parameter; wherein, the second address range is adjacent to the first address range.

[0128] When the fetch queue unit detects that a subsequent fetch request instruction has been successfully responded to (i.e., the memory unit has returned the instruction data for the fetch block normally), the following key operations are performed:

[0129] Obtain the second size parameters and instruction data: Extract the "second size parameters" of the subsequent instruction fetch block, the content of which is similar to the first size parameters, including the number of instructions in the instruction fetch block, the length of storage bytes, the address span, etc., to determine the required buffer space size; Receive the complete "instruction data" of the subsequent instruction fetch block returned by the storage unit, that is, all processor instructions contained in the instruction fetch block.

[0130] Determine the second address interval adjacent to the first address interval: The instruction buffer allocates storage space for subsequent instruction fetch blocks according to the following rules: Based on the first address interval reserved in step S203 (the reserved space of the current instruction fetch block), its end address is used as the starting address of the second address interval (i.e., the "adjacent" rule); Calculate the address length value based on the second size parameter, and divide a continuous space matching the length value from the starting address as the "second address interval".

[0131] The core purpose of this "adjacent allocation" mechanism is to strictly arrange data in the instruction buffer according to the execution order of the instruction fetch blocks, ensuring that the instruction data of the current instruction fetch block (to be backfilled in the future) and the subsequent instruction fetch blocks are physically continuous, laying the foundation for subsequent sequential transmission to the decoding unit.

[0132] Step S603: Control the instruction buffer to write instruction data into the second address range, and set the corresponding flag bit of the second address range to the second flag.

[0133] After determining the second address range, the instruction data for the subsequent instruction fetch block is stored in the buffer and its status is marked:

[0134] Write instruction data to the second address range: The control instruction buffer will completely write the instruction data of the subsequent instruction fetch block obtained in step S602 into the determined second address range. During the writing process, double verification will be performed: verifying whether the actual length of the instruction data matches the second size parameter (ensuring data integrity, without missing or redundant data); verifying whether the write address is strictly limited to the second address range (preventing out-of-bounds writing from interfering with the space of other instruction fetch blocks).

[0135] Set the flag bit of the second address range to the second flag: After the data is written, set the flag bit corresponding to the second address range (initially unallocated or pending) to the second flag (usually "ready"). The purpose of this flag is to: indicate that the instruction data of the subsequent instruction fetch block is ready in the buffer and can be used by the decoding unit at any time; and to compare the status with the flag bit of the first address range (if the first address range is still "not ready", it means that the current instruction fetch block has not been backfilled), providing a basis for judgment for the subsequent "in-order transmission" logic (it is necessary to wait for the previous instruction fetch block to be ready before transmitting the whole block).

[0136] Optionally, obtain the second size parameter and instruction data corresponding to the subsequent instruction fetch block, such as... Figure 7 As shown, it includes:

[0137] Step S701: Determine the instruction cache data array corresponding to the subsequent instruction fetch request instruction, and obtain the second size parameter corresponding to the subsequent instruction fetch block.

[0138] When a subsequent instruction fetch request is successfully responded to (i.e., the memory unit has returned the data for the fetch block normally), the first step is to locate the core structure storing the data in the instruction cache and extract the key size information.

[0139] Locating the instruction cache data array (iCache Data Array): The instruction cache typically consists of two parts: a "tag array" and a "data array." The tag array stores metadata such as address mapping and validity (as mentioned in step S201), while the "instruction cache data array" is the physical area that actually stores the instruction binary data. Based on the target address of the subsequent instruction fetch request (the physical address after address translation or the cache index), the entry in the "instruction cache data array" corresponding to that subsequent instruction fetch block is located in the instruction cache, i.e., the specific location where the instruction data of that fetch block is stored.

[0140] Extracting the second size parameter: Each entry in the instruction cache data array contains not only instruction data but also metadata describing the attributes of that data block (such as metadata stored in the header of the data array or in associated control fields). The system parses this metadata to obtain the "second size parameter" for subsequent instruction fetch blocks. This parameter specifically includes: the total byte length of the instruction fetch block (e.g., 32 bytes, 64 bytes, depending on the cache block size or instruction length); the number of valid instructions contained (e.g., if each instruction is 4 bytes, a 32-byte instruction fetch block may contain 8 instructions); and address boundary information (such as the offsets of the start and end addresses to ensure data integrity).

[0141] Obtaining the second size parameter is crucial for allocating the second address range in the instruction buffer (it must strictly match the range size) and is also the basis for verifying data integrity.

[0142] Step S702: Use the instruction cache data array to obtain the instruction data corresponding to the subsequent instruction fetch block.

[0143] After locating the corresponding instruction cache data array entry and obtaining the second size parameter, the actual instruction data for the subsequent instruction fetch block can be extracted from it.

[0144] Reading the valid data region: In the instruction cache data array, each entry corresponds to a contiguous storage space, of which only a portion stores valid instruction data (the remainder may be padding or invalid data). Based on the "valid length" and "address boundary information" in the second size parameter, the contents of the valid region are precisely read from the data array entry, which is the "instruction data" for the subsequent instruction fetch block. This data is a sequence of binary instructions (such as machine code) that the processor can directly execute.

[0145] Data integrity verification: A verification operation is performed during the reading process to ensure that the length of the read instruction data is exactly consistent with the second size parameter (for example, if the second size parameter is 32 bytes, then the read data must be exactly 32 bytes), to avoid partial data loss due to cached data corruption or address calculation errors.

[0146] Format adaptation processing: If the instruction data stored in the instruction cache data array contains additional auxiliary information such as check bits and flag bits, these non-instruction contents will be stripped after reading, and only the pure instruction sequence will be retained to ensure that the "clean data" that can be directly parsed by the decoding unit is passed to the instruction buffer.

[0147] Optionally, after step S104, where the control instruction buffer writes the backfill data into a reserved first address range and uses the first address range to control the first processor instruction corresponding to the backfill data to be sent to the decoding unit, as follows... Figure 8 As shown, the method also includes:

[0148] Step S801: Obtain the second flag bit corresponding to the second address range.

[0149] In step S104, the backfill data for the current instruction fetch block has been written to the first address range and marked as "ready" (second mark), and its corresponding first processor instruction has been successfully sent to the decoding unit. At this point, it is necessary to monitor the status of subsequent instruction fetch blocks in the instruction buffer. Specifically, the operation is as follows:

[0150] Obtain the current state of the "second flag bit" corresponding to the "second address range". The second address range is the storage space allocated in step S602 for the subsequent instruction fetch block and adjacent to the first address range; the second flag bit is a status indicator used to identify whether the instruction data in the range is ready (as described in step S603, when the instruction data of the subsequent instruction fetch block is written, this flag bit will be set to the second flag "ready").

[0151] There are generally two ways to obtain the flag status:

[0152] Active polling: The control logic of the instruction buffer periodically scans the flag bits of each address range and updates the status information in real time;

[0153] Interruption Trigger: When the second flag changes from "not ready" to "ready", a status notification is automatically triggered without continuous scanning.

[0154] The core purpose of this operation is to determine whether the instruction data for the subsequent instruction fetch block has met the sending conditions, so as to provide a basis for decision-making for the next instruction sending.

[0155] Step S802: When the second flag bit is detected as the second flag, the control instruction buffer sends the second processor instruction corresponding to the instruction data to the decoding unit.

[0156] When the status of the second flag bit is confirmed to be the second flag ("ready") in step S801, it means that the instruction data for the subsequent instruction fetch block is fully ready in the buffer, and the instruction for the current instruction fetch block has been sent to the decoding unit (the result of step S104). At this time, the subsequent instruction sending process can be triggered:

[0157] The control instruction buffer reads the instruction data of the subsequent fetch block stored in the second address range (start address, end address), i.e., the "second processor instruction", and sends it to the decoding unit in the original execution order of the instructions (consistent with the increment direction of the program counter PC).

[0158] This process must strictly follow the "sequential sending" principle: since the second processor instruction is logically a follower instruction of the first processor instruction (corresponding to the next segment of the program execution flow), it must be sent only after the first processor instruction has been sent, in order to ensure that the instruction stream received by the decoding unit is completely consistent with the execution order designed in the program, and to avoid instruction dependency errors caused by out-of-order processing (such as the execution logic confusion of jump instructions and data dependency instructions).

[0159] In addition, a final check is performed before transmission: confirming that the instruction data length of the second address range matches the second size parameter, and that the transmission order does not span other unread fetch blocks (if there are more subsequent fetch blocks), ensuring the continuity and integrity of the entire instruction stream.

[0160] like Figure 9 The flowchart of another processor read control method adds an Instruction Ordering Buffer to the CPU front-end IFU, located after the instruction fetch pipeline and before the Decode unit. The In Order path (orange arrow) indicates accessing the iCache TagArray of the instruction cache, used to determine whether the current fetch block has been hit (tag matching is a sequential operation, ensuring "judgment first, processing later").

[0161] Out of Order (pink arrow) indicates accessing the iCacheData Array, the data array of the instruction cache. If the tag matches (i.e., a hit), the instruction data can be read directly in parallel / out of order (improving efficiency and avoiding unnecessary waiting).

[0162] The Instruction Ordering Buffer is used to receive the "hit data" and "tag matching results (hit / miss signal)" from the instruction cache iCache. It is responsible for temporarily storing instructions, organizing their order, and finally outputting them to the Decode Unit in the logical order of the program.

[0163] When an iCache Miss or iTLB Miss occurs in the fetch block queue, the size of that fetch block is read, space is reserved in the instruction ordering buffer, and the buffer waits to be filled. If the next or subsequent fetch block hits, the pipeline can continue to access the instruction normally, read the instruction data, and write it into the instruction ordering buffer according to the previously reserved space size.

[0164] The instruction ordering buffer allocates space according to the order and size of the fetch blocks. For example, if fetch block 0 is 16 bytes, the reserved range is addresses 0-15. If fetch block 0 misses but fetch block 1 hits, the instruction data for block 1 is placed at address 16 bytes. After fetch block 0 is filled, the data is written to addresses 0-15. When outputting to the decode unit, the instruction buffer outputs fetch block 0 first, then fetch block 1, ensuring that it still appears in-order to the decode unit.

[0165] The workflow is as follows: The Fetch Queue initiates fetch requests sequentially (Fetch Block0, Fetch Block1,...). If Fetch Block0 misses, it is written to the Instruction Ordering Buffer, and Fetch Block0 is set to the not ready state. Simultaneously, the position in the Instruction Ordering Buffer is stored in the Fetch Queue. If Block1 hits, the data is immediately written to the Block1 area and set to the ready state.

[0166] When Fetch Block 0 is backfilled, a wake-up signal is generated. Fetch Block 0 will then rejoin the instruction fetch pipeline, retrieve the backfilled data, and write the instruction to the correct position according to the position information of the Instruction Ordering Buffer stored in the Fetch Queue.

[0167] At the instruction buffer output, the FetchBlock 0 instruction is only allowed to be sent to the Decode unit after the Fetch Block 0 area is ready; then the Block 1 instruction is sent to maintain the logical order.

[0168] The same applies to subsequent Fetch Blocks. If a Miss occurs, it will not block the entire front-end; subsequent hit instruction blocks can be fetched first and temporarily stored in the corresponding position in the Buffer.

[0169] As can be seen from the processor instruction fetch control method in the above embodiments, this method sets up an additional instruction buffer between the instruction fetch queue unit and the decoding unit, allowing subsequently hit instruction blocks to be read first and cached in a specific location in the instruction buffer. Before being output to the decoding unit, the instruction data is rearranged according to the order of the instruction fetch blocks, ensuring that from the perspective of external logic, it is still executed in sequence. This solves the problem of global blocking caused by instruction fetch process failure in the prior art and can fully leverage the performance advantages of wide-issue CPUs.

[0170] Corresponding to the above embodiments of the processor instruction read control method, this embodiment of the invention also provides a processor instruction read control system, such as... Figure 10 As shown, the system includes:

[0171] The instruction buffer construction module 1010 is used to construct the instruction buffer corresponding to the instruction fetch unit based on the instruction fetch queue unit and the decoding unit contained in the processor's instruction fetch unit; wherein, the instruction buffer is set between the instruction fetch queue unit and the decoding unit;

[0172] The instruction fetch request exception handling module 1020 is used to obtain the first size parameter of the current instruction fetch block corresponding to the instruction fetch request instruction and the response failure information when the instruction fetch request instruction corresponding to the instruction fetch queue unit is detected to fail, control the instruction buffer to reserve the first address range corresponding to the first size parameter, and control the instruction fetch queue unit to perform instruction fetch requests on the subsequent instruction fetch blocks of the current instruction fetch block according to the execution order of the instruction fetch request instructions.

[0173] The normal processing module 1030 for fetching requests is used to control the fetching queue unit to make a fetching request for the current fetching block and obtain the backfill data corresponding to the current fetching block when the response failure information is detected to have disappeared.

[0174] The processor instruction control module 1040 is used to control the instruction buffer to write backfill data into a reserved first address range, and to use the first address range to control the first processor instruction corresponding to the backfill data to be sent to the decoding unit.

[0175] As can be seen from the processor instruction fetch control system described above, this system sets up an additional instruction buffer between the instruction fetch queue unit and the decoding unit, allowing subsequently hit instruction blocks to be read first and cached in a specific location within this instruction buffer. Before outputting to the decoding unit, the instruction data is rearranged according to the order of the instruction fetch blocks, ensuring that from the perspective of external logic, it still appears to be executed in sequence. This solves the problem of global blocking caused by instruction fetch process failures in existing technologies and fully leverages the performance advantages of wide-issue CPUs.

[0176] The processor instruction reading control system provided in this embodiment of the invention has the same implementation principle and technical effects as the aforementioned processor instruction reading control method embodiment. For the sake of brevity, any parts not mentioned in the system embodiment can be referred to the corresponding content in the aforementioned processor instruction reading control method embodiment.

[0177] This embodiment also provides an electronic device, the structural schematic diagram of which is shown below. Figure 11 As shown, the device includes a processor 101 and a memory 102; wherein, the memory 102 is used to store one or more computer instructions, which are executed by the processor to implement the steps of the processor instruction read control method described above.

[0178] Figure 11 The electronic device shown also includes a bus 103 and a communication interface 104, with the processor 101, communication interface 104 and memory 102 connected via the bus 103.

[0179] The memory 102 may include high-speed random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage device. The bus 103 may be an ISA bus, PCI bus, or EISA bus, etc. The bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 11 The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus or one type of bus.

[0180] The communication interface 104 is used to connect to at least one user terminal and other network units through a network interface, and to send encapsulated IPv4 packets or IPv4 packets to the user terminal through the network interface.

[0181] Processor 101 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of processor 101 or by instructions in software form. The processor 101 can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this disclosure. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this disclosure can be directly manifested as execution by a hardware decoding processor, or execution by a combination of hardware and software modules in the decoding processor. The software module can reside in a mature storage medium in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. This storage medium is located in memory 102. The processor 101 reads the information in memory 102 and, in conjunction with its hardware, completes the steps of the method described in the foregoing embodiments.

[0182] This invention also provides a storage medium storing a computer program, which, when run by a processor, executes the steps of the processor instruction read control method described in the foregoing embodiments.

[0183] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, devices, and methods can be implemented in other ways. The system embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the coupling or direct coupling or communication connection shown or discussed may be through some communication interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0184] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0185] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0186] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, electronic device, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0187] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A processor instruction fetching control method, characterized in that, The method includes; The instruction buffer corresponding to the instruction fetch unit is constructed based on the instruction fetch queue unit and the decoding unit included in the processor's instruction fetch unit; wherein, the instruction buffer is located between the instruction fetch queue unit and the decoding unit; When the instruction fetch request instruction corresponding to the instruction fetch queue unit fails to respond, the first size parameter of the current instruction fetch block corresponding to the instruction fetch request instruction and the response failure information are obtained. The instruction buffer is controlled to reserve a first address range corresponding to the first size parameter, and the instruction fetch queue unit is controlled to fetch instructions to the subsequent instruction fetch blocks of the current instruction fetch block according to the execution order of the instruction fetch request instruction. When the response failure information is detected to have disappeared, the instruction fetch queue unit is controlled to make an instruction fetch request for the current instruction fetch block and then obtain the backfill data corresponding to the current instruction fetch block. The instruction buffer is controlled to write the backfill data into the reserved first address range, and the first address range is used to control the first processor instruction corresponding to the backfill data to be sent to the decoding unit; Controlling the instruction fetch queue unit to fetch instruction requests for subsequent instruction fetch blocks of the current instruction fetch block according to the execution order of the instruction fetch request instructions includes: After the first size parameter is called back to the instruction fetch queue unit, the execution order of the instruction fetch request instruction is determined based on the number information of the instruction fetch block corresponding to the instruction fetch request instruction; Obtain the current number corresponding to the current instruction fetch block, and determine the adjacent numbers corresponding to the current number based on the execution order; The adjacent number is used to determine the subsequent instruction fetch block corresponding to the current instruction fetch block, and the instruction fetch queue unit is controlled to make an instruction fetch request for the subsequent instruction fetch block.

2. The processor instruction read / control method according to claim 1, characterized in that, Obtaining the first size parameter of the current fetch block corresponding to the fetch request instruction and the response failure information, and controlling the instruction buffer to reserve a first address range corresponding to the first size parameter, including: Determine the instruction cache tag array corresponding to the instruction fetch request instruction, and obtain the first size parameter corresponding to the current instruction fetch block; The response failure information corresponding to the current instruction fetch block is determined using the instruction cache tag array, and the first flag bit corresponding to the first address range is set as the first flag; wherein, the response failure information includes at least: no data in the instruction cache and instruction translation detection buffer address translation failure; According to the address length value corresponding to the first size parameter, the instruction buffer is controlled to reserve the first address range consistent with the address length value at a preset starting point.

3. The processor instruction read / control method according to claim 2, characterized in that, When the response failure information is detected to have disappeared, the instruction fetch queue unit is controlled to make an instruction fetch request for the current instruction fetch block, and the backfill data corresponding to the current instruction fetch block is obtained, including: When the response failure information is detected to have disappeared, a wake-up instruction corresponding to the current fetch block is generated; The instruction fetch queue unit controls the current instruction fetch block to make an instruction fetch request based on the wake-up instruction, obtains the backfill data corresponding to the current instruction fetch block, and obtains the first size parameter through the instruction fetch queue unit.

4. The processor instruction read / control method according to claim 3, characterized in that, Controlling the instruction buffer to write the backfill data into the reserved first address range, and using the first address range to control the first processor instruction corresponding to the backfill data to be sent to the decoding unit, includes: After the instruction buffer writes the backfill data into the reserved first address range according to the first size parameter, the first flag bit corresponding to the first address range is set to the second flag. When the first flag bit is detected to be the second flag, the instruction buffer is controlled to send the first processor instruction corresponding to the backfill data to the decoding unit.

5. The processor instruction read / control method according to claim 4, characterized in that, After controlling the instruction fetch queue unit to fetch instructions for subsequent instruction fetch blocks of the current instruction fetch block according to the execution order of the instruction fetch request instructions, the method further includes: Determine the subsequent fetch request instruction corresponding to the subsequent fetch block; When the subsequent fetch request instruction corresponding to the fetch queue unit is successfully responded to, the second size parameter and instruction data corresponding to the subsequent fetch block are obtained, and the instruction buffer is controlled to determine the second address range corresponding to the second size parameter; wherein, the second address range is adjacent to the first address range; The instruction buffer is controlled to write the instruction data into the second address range, and the flag bit corresponding to the second address range is set to the second flag.

6. The processor instruction read / control method according to claim 5, characterized in that, Obtaining the second size parameter and instruction data corresponding to the subsequent instruction fetch block includes: Determine the instruction cache data array corresponding to the subsequent instruction fetch request instruction, and obtain the second size parameter corresponding to the subsequent instruction fetch block; The instruction data corresponding to the subsequent instruction fetch block is obtained using the instruction cache data array.

7. The processor instruction read / control method according to claim 5, characterized in that, After controlling the instruction buffer to write the backfill data into the reserved first address range, and using the first address range to control the first processor instruction corresponding to the backfill data to be sent to the decoding unit, the method further includes: Obtain the second flag bit corresponding to the second address range; When the second flag bit is detected to be the second flag, the instruction buffer is controlled to send the second processor instruction corresponding to the instruction data to the decoding unit.

8. A processor instruction fetching control system, characterized in that, The system includes: An instruction buffer construction module is used to construct an instruction buffer corresponding to the instruction fetch unit based on the instruction fetch queue unit and the decoding unit contained in the processor's instruction fetch unit; wherein, the instruction buffer is disposed between the instruction fetch queue unit and the decoding unit; The instruction fetch request exception handling module is used to, when it is detected that the instruction fetch request instruction corresponding to the instruction fetch queue unit fails to respond, obtain the first size parameter of the current instruction fetch block corresponding to the instruction fetch request instruction and the response failure information, control the instruction buffer to reserve the first address range corresponding to the first size parameter, and control the instruction fetch queue unit to perform instruction fetch requests on the subsequent instruction fetch blocks of the current instruction fetch block according to the execution order of the instruction fetch request instruction; The normal processing module for fetching requests is used to control the fetching queue unit to make a fetching request for the current fetching block and obtain the backfill data corresponding to the current fetching block when the response failure information is detected to have disappeared. The processor instruction control module is used to control the instruction buffer to write the backfill data into the reserved first address range, and to use the first address range to control the first processor instruction corresponding to the backfill data to be sent to the decoding unit; The instruction fetch request exception handling module, while controlling the instruction fetch queue unit to fetch subsequent instruction fetch blocks of the current instruction fetch block according to the execution order of the instruction fetch request instructions, is further configured to: after the first size parameter is called back to the instruction fetch queue unit, determine the execution order of the instruction fetch request instruction based on the number information of the instruction fetch block corresponding to the instruction fetch request instruction; obtain the current number corresponding to the current instruction fetch block, and determine the adjacent number corresponding to the current number based on the execution order; use the adjacent number to determine the subsequent instruction fetch block corresponding to the current instruction fetch block, and control the instruction fetch queue unit to fetch the instruction fetch block.

9. An electronic device, characterized in that, The method includes a processor and a memory, the memory storing computer-executable instructions that can be executed by the processor, the processor executing the computer-executable instructions to implement the steps of the processor instruction read control method according to any one of claims 1 to 7.

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