Speculative wakeup instruction dependency chain cancellation systems, methods, and related devices

Abstract

The invention discloses a speculative wake-up instruction dependency chain cancelling system and method and related equipment, and the system comprises a memory access miss judgment module which is used for judging whether a front instruction of a to-be-executed instruction can hit memory access or not; the register number comparison module is used for comparing whether the source register number of the instruction to be executed is the same as the destination register number of the operand; and the cancel processing module is used for informing the emission queue module to clear the emission flag bits of the to-be-executed instruction and the instruction having the dependency relationship with the to-be-executed instruction when the to-be-executed instruction is supposed to fail to be awakened. Compared with the prior art, the cancel processing module notifies the transmission queue module to initiate the cancel behavior of clearing the transmission flag bit in different time periods, so that a long instruction dependency chain is decoupled into a plurality of short dependencies, and on the premise that the performance is not influenced, the performance of the system is greatly improved. Two register number comparison circuits are reduced from a time sequence critical path of an instruction when speculative wake-up is cancelled.

Description

Technical Field

[0001] The present invention is applicable to the field of computer technology, and in particular relates to a system and method for canceling a speculatively awakened instruction dependency chain, and related equipment. Background Art

[0002] High-performance superscalar processors typically utilize out-of-order execution technology. This means that instructions are no longer executed one by one in the original order of the computer program. Instead, they are intelligently scheduled based on dependencies between instructions and the availability of execution units, improving instruction execution efficiency. Data dependency between instructions means that when a program is executed, if the result of one instruction is used by a subsequent instruction, then a data dependency exists between the two instructions. For example, if the source operand of an add instruction depends on the destination register of a load instruction, the processor hardware assumes that the input data of the add instruction comes from the result data of the load instruction. Even if the processor supports out-of-order execution, the execution of these two instructions must adhere to the original sequential order of the program, ensuring the correct transfer and use of data between instructions.

[0003] Processor design can generally be divided into several parts based on function and structure, including the front-end responsible for instruction fetching and decoding, the back-end responsible for scheduling and execution, and the memory access system responsible for memory access. Out-of-order execution is mainly implemented in the back-end, which is usually divided into multiple pipeline stages such as renaming, dispatching, issuing, arbitration, reading, and execution. The main module of the issue stage is the issue queue, which is the core component of out-of-order execution scheduling: when an instruction reaches the issue queue after passing through the previous pipeline, it is written into one of the multiple entries in the issue queue. If the instruction depends on a predecessor instruction and the predecessor instruction has not yet completed and obtained a result, it will wait in the issue queue and will not be issued to the next pipeline level. The issue queue will then select instructions from other entries that have no data dependencies for issuance.

[0004] Once the preceding instruction is executed and the result data is calculated, the dependent instructions in the emission queue are notified that their source operands are ready and are eligible to be emitted. This notification behavior is called wake-up. Specifically: when an instruction is executed by the execution unit and the result data is obtained, the result data is used to find all the instructions in the emission queue that depend on this data through the register number comparison circuit, and the status of the instruction in the queue item is updated. The source registers with the same number in these instructions will be set to a valid state, so that these instructions can be selected by the selection arbitration circuit and emitted to the subsequent pipeline. The data of the source register is obtained in the bypass network of the reading stage and then executed, such as Figure 1 As shown, Figure 1 A schematic diagram of a computer processor performing a speculative wakeup process in the related art.

[0005] Speculative wake-up, or predicted wake-up, is an optimization technology in processors and is widely used in high-performance superscalar processors to reduce instruction stalls in the pipeline. Speculative wake-up occurs when there is a dependency between instructions. Although the predecessor instruction has not yet been executed to obtain the result data, it can be predicted that it will be completed in a few cycles based on the instruction type. Therefore, all instructions in the emission queue that depend on and wait for the data are speculatively woken up and emitted. When the predecessor instruction is completed, the awakened instruction arrives at the reading stage before execution and obtains its result data, thereby reducing the waiting cycle of the awakened instruction in the emission queue and improving the execution efficiency of the instruction. Take the common high-performance processor pipeline design in which the predecessor instruction is executed in a single cycle as an example, such as Figure 2 and Figure 3 As shown, Figure 2 A time-space diagram of a computer processor performing a normal wake-up operation in the related art. Figure 3 FIG2 is a time-space diagram of a computer processor in the related art executing a speculative wakeup. It can be seen that the speculative wakeup mechanism reduces the delay of the instruction by two cycles.

[0006] However, since speculative wakeup is speculative, it may fail. For example, the read port of the register file fails to compete, the load instruction of the memory access component misses the cache, etc., resulting in the dependent instruction failing to obtain the source register data in the read phase as expected. Therefore, speculative wakeup is equipped with a cancellation mechanism to avoid the propagation of errors, such as Figure 4 As shown, Figure 4 A time-space diagram of a speculative wakeup cancellation mechanism for a computer processor in the related art. If a preceding instruction fails to compete in the register file read port phase, the continued execution of all dependent instructions is canceled.

[0007] When the designed high-performance processor needs to run at a high frequency such as above 3GHz, the above solution is extremely difficult to meet the timing requirements when dealing with the instruction dependency chain problem, especially the instruction dependency chain with load instructions as the source. Figure 5 As shown, Figure 5 The computer processor of the related art executes a long instruction dependency time-space graph with the load instruction as the source. In the design of high-performance processors, the load instruction usually requires 4 execution cycles, that is, the memory access hit information and result data are generated in the 4th execution stage. If the memory access does not hit, the speculation wake-up is wrong. When the load execution stage 2 speculates that the add instruction 1 that depends on it will wake up so that the add instruction 1 can get the data written back by the load in the subsequent reading stage, a speculation window from T2 to T4 is generated. A long instruction dependency chain will be generated within the window, such as Figure 5The pipeline of four instructions is within the window, forming an instruction dependency chain with load as the source. The correctness of the speculative wake-up behavior during this period is unknown. The wake-up behavior is not confirmed until the memory access unit notifies the memory access hit information at T4.

[0008] When a memory access miss occurs, the load instruction needs to find the add instruction 1 through the register number comparison circuit to prevent it from entering the next pipeline level; similarly, the add instruction 1 also needs to find the add instruction 2 through the register number comparison circuit to make it invalid; and so on, the dependency chain from the load instruction to the add instruction 3 requires three serial comparison circuits. In addition, the judgment circuit of the initial memory access component to judge the memory access miss also requires some circuit logic resources, so the judgment circuit and the three comparison circuits are serially connected into a combinational logic circuit to complete within cycle T4, but this circuit structure is very difficult for the design of a high-frequency processor. Figure 6 As shown, Figure 6 A schematic diagram of a circuit connection for executing an instruction dependency chain cancellation process in a computer processor according to the related art.

[0009] Therefore, there is an urgent need for a new speculative wake-up instruction dependency chain cancellation system, method and related equipment to solve the above technical problems. Summary of the Invention

[0010] The present invention provides a system, method and related equipment for canceling a speculative wakeup instruction dependency chain, aiming to solve the timing problem of a long instruction dependency chain when speculative wakeup fails, thereby improving the cancellation efficiency of speculative wakeup.

[0011] In a first aspect, a speculative wake-up instruction dependency chain cancellation system is provided, the instruction dependency chain cancellation system comprising an issue queue module, a selection arbitration module, a reading module, an execution module, a speculative wake-up module, a pipeline register module, a register number comparison module, a memory miss judgment module, and a cancellation processing module; The transmission queue module is used to store instructions to be executed; The selection arbitration module is used to select instructions to be executed from the transmission queue module in the current cycle and send them to the reading module; The reading module is used to read the operands required by the received instruction to be executed in the preceding instruction, and send the instruction to be executed and the corresponding operands to the execution module; The execution module is used to execute a corresponding operation according to the received operand and the instruction to be executed; The speculative wakeup module is used to perform speculative wakeup on the to-be-executed instruction in the transmit queue module according to the dependency relationship between the to-be-executed instruction and the predecessor instruction in the transmit queue module; The pipeline register module is used to transfer data of the to-be-executed instruction between the transmit queue module, the selection arbitration module, the reading module and the execution module; The memory access miss judgment module is used to judge whether the predecessor instruction of the instruction to be executed in the reading module can hit the memory access; The register number comparison module is used to compare whether the source register number of the instruction to be executed and the destination register number of the operand in the transmit queue module, the selection arbitration module and the reading module are the same; The cancellation processing module is used to notify the transmit queue module to clear the transmit flag bits of the instruction to be executed and the instructions that have a dependency relationship with the instruction to be executed when speculation to wake up the instruction to be executed fails.

[0012] Preferably, the memory access miss judgment module is further configured to send the destination register number of the preceding instruction to the register number comparison module when the preceding instruction of the instruction to be executed fails to hit memory access.

[0013] Preferably, the register number comparison module is also used to send a termination signal to the pipeline register module to prevent the instruction to be executed from entering the execution module when it is determined that the source register number of the instruction to be executed and the number of the destination register of the operand are the same, and send the termination signal to the cancellation processing module.

[0014] Preferably, the cancellation processing module is also used to read the destination register number of the instruction to be executed from the pipeline register module, and when receiving the termination signal sent by the register number comparison module, send the destination register number of the instruction to be executed corresponding to the termination signal to the register number comparison module.

[0015] Preferably, the register number comparison module is further used to compare whether the destination register number of the instruction to be executed is the same as the source register number of the instructions in the transmission queue module and the selection arbitration module. If they are the same, a cancel flag is set for the corresponding instruction in the selection arbitration module and the transmission queue module, and the destination register number of the instruction with the cancel flag will be sent to the cancel processing module in a subsequent cycle.

[0016] Preferably, the cancellation processing module is further configured to notify the transmit queue module to clear the transmit flag of the instruction having the cancel flag.

[0017] Preferably, the register number comparison module includes a transmit queue comparison unit, a selection arbitration comparison unit, and a memory access miss comparison unit; The transmit queue comparison unit is used to compare whether the source register number of the instruction in the transmit queue module is the same as the destination register number of the instruction to be executed, and if so, set a cancel flag bit for the corresponding instruction; The selection arbitration comparison unit is used to compare whether the source register number of the instruction in the selection arbitration module is the same as the destination register number of the instruction to be executed, and if so, set a cancel flag bit for the corresponding instruction; The memory miss comparison unit is used to compare whether the source register number of the instruction to be executed is the same as the destination register number of the operand. If so, the termination signal is issued to prevent the instruction to be executed from entering the execution module, and the termination signal is sent to the cancellation processing module.

[0018] In a second aspect, the present invention further provides a method for canceling a speculatively awakened instruction dependency chain. The method is based on the speculatively awakened instruction dependency chain cancellation system as described in any one of the above embodiments, and the method comprises the following steps: S1. performing speculative wakeup on the instruction to be executed by the speculative wakeup module according to the dependency relationship between the instruction to be executed and the preceding instruction in the transmit queue module; S2. When the memory miss judgment module determines that the memory access of the predecessor instruction of the to-be-executed instruction has missed, the register number comparison module determines whether the source register number of the to-be-executed instruction is the same as the destination register number of the predecessor instruction. If so, the speculative wake-up of the to-be-executed instruction fails, and the cancellation processing module notifies the transmit queue module to clear the transmit flag of the to-be-executed instruction. S3, determining, by the register number comparison module, whether the source register number of an instruction in the transmit queue module and the selection arbitration module is the same as the destination register number of the instruction to be executed; if so, setting a cancel flag bit for the corresponding instruction in the transmit queue module and the selection arbitration module; S4. The cancellation processing module notifies the transmit queue module to clear the transmit flag of the instruction with the cancel flag.

[0019] In a third aspect, the present invention also provides a computer device comprising: a memory, a processor, and a speculative awakening instruction dependency chain cancellation program stored on the memory and executable on the processor, wherein the processor implements the steps of the speculative awakening instruction dependency chain cancellation method as described in the above embodiment when executing the speculative awakening instruction dependency chain cancellation program.

[0020] In a fourth aspect, the present invention also provides a computer-readable storage medium, on which a speculative awakening instruction dependency chain cancellation program is stored. When the speculative awakening instruction dependency chain cancellation program is executed by a processor, the steps in the speculative awakening instruction dependency chain cancellation method as described in any one of the above embodiments are implemented.

[0021] Compared with the prior art, the present invention initiates the cancellation behavior of clearing the transmission flag by notifying the transmission queue module in time periods through the cancellation processing module, thereby decoupling the long instruction dependency chain into multiple short dependency relationships, reducing its logical levels, and achieving the purpose of improving the timing frequency. Without affecting the performance, the timing critical path of the instruction when the wake-up is canceled is reduced by two register number comparison circuits, effectively solving the timing bottleneck problem of the long instruction dependency chain. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The present invention will be described in detail below with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and easier to understand through the detailed description made with reference to the following drawings. In the accompanying drawings: Figure 1 This is a schematic diagram of a wake-up process performed by a computer processor in the related art; Figure 2 is a time-space diagram of a computer processor in the related art performing a normal wake-up; Figure 3 is a spatiotemporal diagram of a computer processor performing speculative wakeup in the related art; Figure 4 A time-space diagram of a cancellation mechanism for speculative wakeup performed by a computer processor in the related art; Figure 5 It is a time-space graph of a computer processor in the related art executing a long instruction dependency chain with a load instruction as the source; Figure 6 This is a circuit connection diagram of a computer processor executing an instruction dependency chain cancellation in the related art; Figure 7 1 is a schematic diagram of the structure of a speculative wake-up instruction dependency chain cancellation system provided by an embodiment of the present invention; Figure 8 1. It is a schematic diagram of a framework of a speculative wakeup instruction dependency chain cancellation system provided by an embodiment of the present invention when speculative wakeup is canceled; Figure 9 A time-space diagram of a speculative wakeup cancellation system for a speculative wakeup instruction dependency chain cancellation system provided by an embodiment of the present invention; Figure 10 This is a flowchart of a method for canceling a speculatively awakened instruction dependency chain provided by an embodiment of the present invention; Figure 11 It is a structural diagram of a computer device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0024] Example 1 Please refer to Figure 7 The present invention provides a speculative wake-up instruction dependency chain cancellation system 100, which includes a speculative wake-up module 01, an issue queue module 02, a selection arbitration module 03, a reading module 04, an execution module 05, a pipeline register module 06, a register number comparison module 07, a memory access miss judgment module 08, and a cancellation processing module 09; The transmission queue module 02 is used to store instructions to be executed; The selection arbitration module 03 is used to select instructions to be executed from the transmission queue module 02 in the current cycle and send them to the reading module 04; The reading module 04 is used to read the operands required by the received instruction to be executed in the preceding instruction, and send the instruction to be executed and the corresponding operands to the execution module 05. The operands are the execution results of the preceding instructions with which there is a dependency. For example, if the instruction to be executed A requires the operation A = A1 + A2, A1 and A2 are the operands required by the instruction to be executed.

[0025] The execution module 05 is used to perform corresponding operations based on the received operands and the instructions to be executed. Specifically, the operand is a field of the assembly language instruction, which can be the operand itself, the operation address or the calculation method of the operation address. The operand is a participant in the execution of the instruction, that is, the object of various operations, including the data that needs to be calculated or processed in the instruction.

[0026] The speculative awakening module 01 is used to perform speculative awakening on the instructions to be executed in the transmit queue module 02 according to the dependency relationship between the instructions to be executed and the predecessor instructions in the transmit queue module 02 .

[0027] The pipeline register module 06 is used to transfer data of the to-be-executed instruction between the transmit queue module 02 , the selection arbitration module 03 , the reading module 04 and the execution module 05 .

[0028] In the embodiment of the present invention, Figure 8As shown, the pipeline register module 06 includes a pipeline register 061 between the transmission queue module 02 and the selection arbitration module 03, a pipeline register 062 between the selection arbitration module 03 and the reading module 04, and a pipeline register 063 between the reading module 04 and the execution module 05, etc., and the temporary storage and transfer of instructions to be executed are realized through multiple pipeline registers.

[0029] The memory access miss judgment module 08 is used to judge whether the predecessor instruction of the instruction to be executed in the reading module 04 can hit the memory access. The memory access miss judgment module 08 obtains the execution result of the predecessor instruction through the execution module 05 and judges whether the memory access is hit according to the calculation result.

[0030] In an embodiment of the present invention, the memory access miss judgment module is further configured to send the destination register number of the preceding instruction to the register number comparison module 07 when the preceding instruction of the instruction to be executed fails to hit memory access.

[0031] The register number comparison module 07 is used to compare whether the source register number of the instruction to be executed is the same as the destination register number of the operand in the emission queue module 02, the selection arbitration module 03 and the reading module 04; the register number comparison module 07 is also used to send a termination signal to the pipeline register module 06 to prevent the instruction to be executed from entering the execution module 05 when it is determined that the source register number of the instruction to be executed is the same as the number of the destination register of the operand (that is, the destination register number of the preceding instruction), and send the termination signal to the cancellation processing module 09.

[0032] In an embodiment of the present invention, the register number comparison module 07 is further configured to compare whether the destination register number of the instruction to be executed is the same as the source register number of the instructions in the transmit queue module 02 and the selection arbitration module 03. If they are the same, a cancel flag is set for the corresponding instructions in the selection arbitration module 03 and the transmit queue module 02. The number of the instruction with the cancel flag is sent to the cancel processing module 09 in a subsequent cycle.

[0033] In the embodiment of the present invention, the register number comparison module 07 includes a transmit queue comparison unit 071, a selection arbitration comparison unit 072, and a memory access miss comparison unit 073; The transmit queue comparison unit 071 is used to compare whether the source register number of the instruction in the transmit queue module 02 is the same as the destination register number of the instruction to be executed, and if so, set a cancel flag bit for the corresponding instruction; The selection arbitration comparison unit 072 is used to compare whether the source register number of the instruction in the selection arbitration module 03 is the same as the destination register number of the instruction to be executed, and if so, set a cancel flag bit for the corresponding instruction; The memory miss comparison unit 073 is used to compare whether the source register number of the instruction to be executed is the same as the destination register number of the operand. If so, a termination signal is issued to prevent the instruction to be executed from entering the execution module 05 and the termination signal is sent to the cancellation processing module 09.

[0034] The cancellation processing module 09 is used to notify the transmission queue module 02 to clear the transmission flag of the instruction to be executed and the instructions that have a dependency relationship with the instruction to be executed when the speculation wake-up fails. Specifically, the transmission flag refers to the flag in the instruction transmission, which is used to mark the instruction that has been transmitted but the final status has not yet been determined. Such an instruction will not continue to be transmitted, but will wait for subsequent control information to pop up and wake up the instruction. This helps to avoid instruction execution errors caused by data hazards. Clearing the transmission flag of the instruction enables it to be retransmitted at a subsequent time.

[0035] In an embodiment of the present invention, the cancellation processing module 09 is further configured to read the destination register number of the pending instruction from the pipeline register module 06, and upon receiving the termination signal sent by the register number comparison module 07, send the destination register number of the pending instruction corresponding to the termination signal to the register number comparison module 07. Specifically, upon receiving the termination signal sent by the memory miss comparison unit 073, the cancellation processing module 09 sends the destination register number of the pending instruction to the issue queue comparison unit 071 and the selection arbitration comparison unit 072, respectively.

[0036] In the embodiment of the present invention, the cancellation processing module 09 is further configured to notify the transmit queue module 02 to clear the transmit flag of the instruction with the cancel flag.

[0037] For details, please refer to Figure 8 and Figure 9In the speculatively awakened instruction dependency chain cancellation system 100, the output of the cancellation processing module 09 is connected to the input of the transmit queue module 02, the input of the transmit queue comparison unit 071, and the input of the selection arbitration comparison unit 072; the output of the transmit queue module 02 is connected to the input of the transmit queue comparison unit 071 and the input of the pipeline register 061; the output of the transmit queue comparison unit 071 is connected to the input of the pipeline register 061; the output of the pipeline register 061 is connected to the input of the selection arbitration module 03; the output of the selection arbitration module 03 is connected to the selection arbitration comparison unit 071. 2 and the input end of the pipeline register 062; the output end of the arbitration comparison unit 072 is connected to the input end of the pipeline register 062; the output end of the pipeline register 062 is connected to the input end of the reading module 04 and the input end of the cancellation processing module 09; the output end of the reading module 04 is connected to the input end of the memory miss comparison unit 073 and the input end of the pipeline register 063; the output end of the memory miss comparison unit 073 is connected to the input end of the pipeline register 063 and the input end of the cancellation processing module 09; the memory miss judgment module 08 is connected to the input end of the memory miss comparison unit 073.

[0038] Taking the longest instruction dependency chain load<- A1<- A2<- A3 as an example (the starting point of the arrow depends on the end it points to, with A representing the pending addition instruction), the instruction flows through Issue Queue Module 02, Selection Arbitration Module 03, and Reader Module 04 are defined as Pipeline 1, Pipeline 2, and Pipeline 3, respectively. When a pending instruction A1 in Issue Queue Module 02 is speculatively awakened by a load instruction in cycle T2, Issue Queue Module 02 sets its issue flag to 1 but does not retire it. Retirement refers to deallocation. When an instruction enters Issue Queue Module 02, it allocates and occupies an entry in Issue Queue Module 02. After Issue Queue Module 02 issues the instruction, it remains in the entry because it may be reissued and is not immediately deallocated (i.e., it is not retired). Instead, it waits until the speculative wakeup is confirmed to be correct and will not be reissued before it can be deallocated, releasing resources. Information about instruction A1 remains in Issue Queue Module 02. Instruction A1 arrives at pipeline 2 in cycle T3 and speculates to wake up instruction A2. Then, instruction A1 arrives at pipeline 3 in cycle T4, instruction A2 arrives at pipeline 2 and speculates to wake up instruction A3 of issue queue module 02.

[0039] At this point, if the memory miss determination module 08 detects a load instruction memory miss, it sends the destination register number of the load instruction (i.e., the predecessor instruction of the to-be-executed instruction A1) to the memory miss comparison unit 073 of the register number comparison module 07 for comparison with the source register of instruction A1 in pipeline 3. If the numbers are the same, a termination signal is issued to prevent the instruction in pipeline 3 from advancing to the next stage. This information is also notified to the cancellation processing module 09, which then locates the recorded information of instruction A1 in the issue queue module 02 and clears its issue flag, allowing instruction A1 to be reissued at a later time. Next, the cancellation processing module 09 also broadcasts the destination register of instruction A1 to pipelines 1 and 2 (i.e., the issue queue module 02 and the selection arbitration module 03). The register number comparison circuits of the issue queue comparison unit 071 and the selection arbitration comparison unit 072 respectively compare the source register numbers of the instructions in pipelines 1 and 2 to see if they are the same. If they are the same, it indicates that the instruction in the pipeline was speculatively activated by instruction A1 and needs to be canceled.

[0040] In the present invention, after finding the instruction to be canceled, unlike the traditional solution, it is canceled immediately in the current cycle. Instead, a cancel flag is added to the instruction, and the cancellation action is not performed immediately. In this example, the cancel flag is set for instruction A2. In the subsequent cycle, the cancellation processing module 09 notifies the transmission queue module 02 to cancel, for example Figure 9 In the next cycle T5, instruction A2 enters pipeline 3 and repeats the cancellation behavior of instruction A1 in pipeline 3 (that is, clearing its emission flag and waiting to be re-emitted at a subsequent moment): First, the register number comparison module 07 is used to find instruction A3 that is currently in pipeline 2 (according to the speculative wake-up principle, if instruction A2 is executed in two cycles, instruction A3 may also be found in pipeline 1) and a cancel flag is set for it; Second, instruction A2 is canceled from entering the next pipeline stage and its issue flag is cleared in the issue queue, allowing it to be reissued later. Similarly, instruction A3 will also be canceled in pipeline 3 at a later time, allowing the previously serial instruction-length dependency chain to be split into pipeline-based decoupling and cancellation. Compared to the prior art, this invention eliminates two register number comparison circuits in the critical path.

[0041] Please refer to Figure 9 , Figure 9 The time-space diagram of the embodiment of the present invention when the wake-up is canceled is provided. The existing technical solution is within the T4 period (refer to Figure 5) requires serially completing all cancellation actions through the combinational logic circuit. However, the present invention can greatly reduce the number of single-cycle serial combinational logic levels by dividing the cancellation action of the instruction into different cycles, greatly reducing the pressure on the timing design of the circuit and providing the possibility of the processor running at a higher frequency. Although the final cancellation action ends at the T6 cycle, Figure 5 Compared with the related technical solution in , it takes two more cycles, but this does not affect the performance of the processor, because after the transmission queue is notified to re-transmit, the instructions canceled in the related technical solution still need more than two cycles to be transmitted due to the waiting memory access component to handle the miss problem.

[0042] Compared with the prior art, the present invention initiates the cancellation behavior of clearing the transmission flag bit by notifying the transmission queue module 02 in time periods through the cancellation processing module 09, thereby decoupling the long instruction dependency chain into multiple short dependency relationships, reducing its logical level, and achieving the purpose of improving the timing frequency. Without affecting the performance, the timing critical path of the instruction when the wake-up is canceled is reduced by two register number comparison circuits, effectively solving the timing bottleneck problem of the long instruction dependency chain.

[0043] Example 2 The embodiment of the present invention further provides a method for canceling a speculatively awakened instruction dependency chain. The method for canceling a speculatively awakened instruction dependency chain is based on the system 100 for canceling a speculatively awakened instruction dependency chain as described in any one of the above embodiments. Figure 10 , Figure 10 : is a flowchart of a method for canceling a speculatively awakened instruction dependency chain provided by an embodiment of the present invention, which includes: The instruction dependency chain cancellation method comprises the following steps: S1, speculatively waking up the to-be-executed instruction through the speculative waking up module 01 according to the dependency relationship between the to-be-executed instruction and the preceding instruction in the transmit queue module 02; S2. When the memory access miss judgment module 08 determines that the memory access of the predecessor instruction of the to-be-executed instruction has missed, the register number comparison module 07 determines whether the source register number of the to-be-executed instruction is the same as the destination register number of the predecessor instruction. If so, the speculative wake-up of the to-be-executed instruction fails, and the cancellation processing module 09 notifies the transmit queue module 02 to clear the transmit flag of the to-be-executed instruction. S3, determining, by the register number comparison module 07, whether the source register number of the instruction in the transmit queue module 02 and the selection arbitration module 03 is the same as the destination register number of the to-be-executed instruction; if so, setting a cancel flag bit for the corresponding instruction in the transmit queue module 02 and the selection arbitration module 03; S4. The cancel processing module 09 notifies the transmit queue module 02 to clear the transmit flag of the instruction with the cancel flag.

[0044] In an embodiment of the present invention, clearing the transmit flag refers to setting a flag indicating the transmit status of an instruction (i.e., the transmit flag) to a specific value, thereby indicating that the corresponding transmit status has changed from transmitted to pending. For example, after instruction A is transmitted, its transmit flag is 1, indicating that instruction A has been transmitted and is still recorded in the transmit queue module 02. If the execution of instruction A is subsequently canceled, the transmit flag is cleared, changing the 1 to 0, indicating that instruction A still needs to be retransmitted. Steps S3 and S4 can be re-performed based on the dependency chain of the pending instructions. For example, take the longest instruction dependency chain load<- A1<- A2<- A3 (the starting end of the arrow depends on the end pointed to by the arrow, with A representing the pending addition instruction). If the load instruction fails to hit the memory access, and the source register number of the pending instruction A1 is the same as the destination register number of the load instruction's operand, then the pending instruction A1 is a speculatively awakened instruction. The cancellation processing module 09 needs to notify the issue queue module 02 to clear the issue flag of instruction A1, so that it can be reissued at a subsequent time. At the same time, the destination register number of instruction A1 is broadcast to the issue queue module 02 and the selection arbitration module 03. The modules then determine whether there is an instruction in the issue queue module 02 and the selection arbitration module 03 with the same source register number as the destination register number of instruction A1 (in this example, the source register number of instruction A2 is the same as the destination register number of instruction A1). The cancellation flag is set for instruction A2, so that the cancellation processing module 09 can notify the issue queue module 02 to clear the issue flag of instruction A2 in subsequent cycles. Similarly, instruction A3 is processed in the subsequent cycles like instruction A2, thereby decoupling the entire long instruction dependency chain and successively canceling instructions A1, A2, and A3 in different cycles.

[0045] The method for canceling the instruction dependency chain of speculative awakening is based on the modules in the system 100 for canceling the instruction dependency chain of speculative awakening in the above embodiment, and can achieve the same technical effects. Please refer to the description in the above embodiment and will not be repeated here.

[0046] Example 3 The embodiment of the present invention also provides a computer device, please refer to Figure 11 , Figure 11 3 is a structural diagram of a computer device provided in an embodiment of the present invention. The computer device 300 includes: a memory 302, a processor 301, and a speculative wake-up instruction dependency chain cancellation program stored in the memory 302 and executable on the processor 301.

[0047] The processor 301 calls the instruction dependency chain cancellation program for speculative awakening stored in the memory 302 and executes the steps of the instruction dependency chain cancellation method for speculative awakening provided by the embodiment of the present invention. Figure 10 , specifically including the following steps: S1, speculatively waking up the to-be-executed instruction through the speculative waking up module 01 according to the dependency relationship between the to-be-executed instruction and the preceding instruction in the transmit queue module 02; S2. When the memory access miss judgment module 08 determines that the memory access of the predecessor instruction of the to-be-executed instruction has missed, the register number comparison module 07 determines whether the source register number of the to-be-executed instruction is the same as the destination register number of the predecessor instruction. If so, the speculative wake-up of the to-be-executed instruction fails, and the cancellation processing module 09 notifies the transmit queue module 02 to clear the transmit flag of the to-be-executed instruction. S3, determining, by the register number comparison module 07, whether the source register number of the instruction in the transmit queue module 02 and the selection arbitration module 03 is the same as the destination register number of the to-be-executed instruction; if so, setting a cancel flag bit for the corresponding instruction in the transmit queue module 02 and the selection arbitration module 03; S4. The cancel processing module 09 notifies the transmit queue module 02 to clear the transmit flag of the instruction with the cancel flag.

[0048] The computer device 300 provided in an embodiment of the present invention includes the modules in the speculative awakening instruction dependency chain cancellation system 100 in the above embodiment, and can achieve the same technical effects. Please refer to the description in the above embodiment and will not be repeated here.

[0049] Example 4 An embodiment of the present invention also provides a computer-readable storage medium, on which a speculative awakening instruction dependency chain cancellation program is stored. When the speculative awakening instruction dependency chain cancellation program is executed by a processor, the steps in the speculative awakening instruction dependency chain cancellation method provided in an embodiment of the present invention are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0050] Those skilled in the art will appreciate that all or part of the processes in the above-described method embodiments can be implemented by instructing the relevant hardware through a computer program. The program can be stored in a computer-readable storage medium, and when executed, the program can include the processes in the above-described method embodiments. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

[0051] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0052] Through the above description of the embodiments, those skilled in the art will clearly understand that the methods of the above embodiments can be implemented using software plus the necessary general-purpose hardware platform. Of course, hardware can also be used, but in many cases the former is the more preferred implementation method. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, or optical disk) and includes a number of instructions for enabling a terminal (such as a mobile phone, computer, server, air conditioner, or network device) to execute the methods described in the various embodiments of the present invention.

[0053] The embodiments of the present invention are described above in conjunction with the accompanying drawings. What is disclosed is only a preferred embodiment of the present invention. However, the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms and equivalent changes without departing from the scope of protection of the purpose of the present invention and the claims, which are all within the protection of the present invention.

Claims

1. A speculative wake-up instruction dependency chain cancellation system, characterized in that: The instruction dependency chain cancellation system includes an emission queue module, a selection arbitration module, a reading module, an execution module, a speculation wake-up module, a pipeline register module, a register number comparison module, a memory access miss judgment module and a cancellation processing module; The transmission queue module is used to store instructions to be executed; The selection arbitration module is used to select instructions to be executed from the transmission queue module in the current cycle and send them to the reading module; The reading module is used to read the operands required by the received instruction to be executed in the preceding instruction, and send the instruction to be executed and the corresponding operands to the execution module; The execution module is used to execute a corresponding operation according to the received operand and the instruction to be executed; The speculative wakeup module is used to perform speculative wakeup on the to-be-executed instruction in the transmit queue module according to the dependency relationship between the to-be-executed instruction and the predecessor instruction in the transmit queue module; The pipeline register module is used to transfer data of the to-be-executed instruction between the transmit queue module, the selection arbitration module, the reading module and the execution module; The memory access miss judgment module is used to judge whether the predecessor instruction of the instruction to be executed in the reading module can hit the memory access; The register number comparison module is used to compare whether the source register number of the instruction to be executed and the destination register number of the operand in the transmit queue module, the selection arbitration module and the reading module are the same; The cancellation processing module is used to notify the transmit queue module to clear the transmit flag bits of the instruction to be executed and the instructions that have a dependency relationship with the instruction to be executed when speculation to wake up the instruction to be executed fails.

2. The speculative wakeup instruction dependency chain cancellation system according to claim 1, wherein: The memory access miss judgment module is further configured to send the destination register number of the preceding instruction to the register number comparison module when the preceding instruction of the instruction to be executed fails to hit the memory access.

3. The speculative wakeup instruction dependency chain cancellation system according to claim 1, wherein: The register number comparison module is also used to send a termination signal to the pipeline register module to prevent the instruction to be executed from entering the execution module when it is determined that the source register number of the instruction to be executed is the same as the destination register number of the operand, and send the termination signal to the cancellation processing module.

4. The speculative wakeup instruction dependency chain cancellation system according to claim 3, wherein: The cancellation processing module is further configured to read the destination register number of the instruction to be executed from the pipeline register module, and upon receiving the termination signal sent by the register number comparison module, send the destination register number of the instruction to be executed corresponding to the termination signal to the register number comparison module.

5. The speculative wakeup instruction dependency chain cancellation system according to claim 4, characterized in that: The register number comparison module is further configured to compare the destination register number of the instruction to be executed with the source register numbers of the instructions in the transmit queue module and the selection arbitration module to determine whether they are the same: if they are the same, a cancel flag is set for the corresponding instruction in the selection arbitration module and the transmit queue module, and the destination register number of the instruction with the cancel flag is sent to the cancel processing module in a subsequent cycle.

6. The speculative wakeup instruction dependency chain cancellation system according to claim 5, characterized in that: The cancellation processing module is further configured to notify the transmit queue module to clear the transmit flag of the instruction having the cancel flag.

7. The speculative wakeup instruction dependency chain cancellation system according to claim 5, characterized in that: The register number comparison module includes a transmit queue comparison unit, a selection arbitration comparison unit, and a memory access miss comparison unit; The transmit queue comparison unit is used to compare whether the source register number of the instruction in the transmit queue module is the same as the destination register number of the instruction to be executed, and if so, set a cancel flag bit for the corresponding instruction; The selection arbitration comparison unit is used to compare whether the source register number of the instruction in the selection arbitration module is the same as the destination register number of the instruction to be executed, and if so, set a cancel flag bit for the corresponding instruction; The memory miss comparison unit is used to compare whether the source register number of the instruction to be executed is the same as the destination register number of the operand. If so, the termination signal is issued to prevent the instruction to be executed from entering the execution module, and the termination signal is sent to the cancellation processing module.

8. A method for canceling a speculatively awakened instruction dependency chain, characterized in that: The instruction dependency chain cancellation method is based on the speculatively awakened instruction dependency chain cancellation system according to any one of claims 1 to 7, and the instruction dependency chain cancellation method includes the following steps: S1. performing speculative wakeup on the instruction to be executed by the speculative wakeup module according to the dependency relationship between the instruction to be executed and the preceding instruction in the transmit queue module; S2. When the memory access miss judgment module determines that the memory access of the predecessor instruction of the to-be-executed instruction misses, the register number comparison module determines whether the source register number of the to-be-executed instruction is the same as the destination register number of the predecessor instruction. If so, the speculative wake-up of the to-be-executed instruction fails, and the cancellation processing module notifies the transmit queue module to clear the transmit flag of the to-be-executed instruction. S3, determining, by the register number comparison module, whether a source register number of an instruction in the transmit queue module and the selection arbitration module is the same as a destination register number of the instruction to be executed; if so, setting a cancel flag bit for the corresponding instruction in the transmit queue module and the selection arbitration module; S4. The cancellation processing module notifies the transmit queue module to clear the transmit flag of the instruction with the cancel flag.

9. A computer device, characterized in that: include: A memory, a processor, and a speculative awakening instruction dependency chain cancellation program stored in the memory and executable on the processor, wherein the processor implements the steps of the speculative awakening instruction dependency chain cancellation method as described in claim 8 when executing the speculative awakening instruction dependency chain cancellation program.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a speculatively awakened instruction dependency chain cancellation program, which, when executed by a processor, implements the steps of the speculatively awakened instruction dependency chain cancellation method as claimed in claim 8.

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