Modular packaging system and method for integrated circuits

Abstract

This invention provides a modular packaging system and method for integrated circuits, belonging to the field of semiconductor device technology. The system includes: a circuit partitioning module for dividing a first integrated circuit into multiple independent and functionally complete sub-circuit modules; a characterization module for obtaining standardized interface features and packaging features based on the partitioning logic of the sub-circuit modules; an acquisition module for obtaining modular packaging steps based on the standardized interface features and packaging features; and a packaging module for packaging a second integrated circuit according to the modular packaging steps. This modular packaging system and method for integrated circuits, by dividing the integrated circuit into multiple independent and functionally complete modules and employing standardized interface and packaging technologies, achieves high integration, flexible configuration, and rapid assembly of the integrated circuit.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a modular packaging system and method for integrated circuits. Background Technology

[0002] An integrated circuit is a miniature electronic device that integrates transistors, resistors, capacitors, inductors, and other components required for a circuit, along with interconnected wiring, onto a small piece or several small pieces of semiconductor wafer or dielectric substrate. These components are then packaged in a housing to form a miniature structure with the required circuit function. All components are structurally integrated into a single unit, representing a significant step forward in miniaturization, low power consumption, intelligence, and high reliability of electronic components.

[0003] The integrated circuit design varies from project to project. Generally, the circuit design of integrated circuits is relatively complex. When engineers package and test each component, the various parts of the circuit are relatively scattered and cannot be quickly configured and assembled according to the circuit connection relationship.

[0004] In view of this, there is an urgent need for a modular packaging system and method for integrated circuits to at least address the above-mentioned shortcomings. Summary of the Invention

[0005] One of the objectives of this invention is to provide a modular packaging system and method for integrated circuits. By dividing the integrated circuit into multiple independent and fully functional modules, using standardized interfaces and packaging technologies to obtain standardized interface features and packaging features, and obtaining and applying modular packaging steps based on the standardized interface features and packaging features, the invention achieves high integration, flexible configuration, and rapid assembly of integrated circuits.

[0006] This invention provides a modular packaging system for integrated circuits, comprising:

[0007] A circuit partitioning module is used to divide the first integrated circuit into multiple independent and fully functional sub-circuit modules;

[0008] The characterization module is used to obtain standardized interface features and encapsulation features based on the partitioning logic of the sub-circuit modules;

[0009] The simulation module is used to perform encapsulation simulation based on standardized interface features and encapsulation features;

[0010] Preferably, the circuit partitioning module is used to divide the first integrated circuit into multiple independent and fully functional sub-circuit modules;

[0011] The characterization module is used to obtain standardized interface features and encapsulation features based on the partitioning logic of the sub-circuit modules;

[0012] The acquisition module is used to obtain modular encapsulation steps based on standardized interface characteristics and encapsulation characteristics.

[0013] A packaging module is used to package a second integrated circuit according to modular packaging steps.

[0014] Preferably, the circuit partitioning module divides the first integrated circuit into multiple independent and functionally complete sub-circuit modules, including:

[0015] Based on a preset complete circuit extraction template and according to the circuit characteristics of the first integrated circuit, multiple complete circuits are extracted.

[0016] Extract the first circuit connection relationship in the first integrated circuit of the complete circuit;

[0017] Based on the first circuit connection relationship, a complete circuit group that can just form the first integrated circuit is determined;

[0018] Each complete circuit in the complete circuit group is taken as a sub-circuit module of the partitioning logic corresponding to the complete circuit group.

[0019] Preferably, the circuit partitioning module divides the first integrated circuit into multiple independent and functionally complete sub-circuit modules, and further includes:

[0020] If it is impossible to determine the complete circuit group that can form the first integrated circuit, map the complete circuit into the three-dimensional template of the first integrated circuit, and determine the target template that meets the mapping criteria and has the widest coverage of the three-dimensional template.

[0021] Based on the target connection relationship between the mapped complete circuit and the unmapped circuit part in the target template, determine the condition constraints when performing modular packaging design on the unmapped circuit part;

[0022] Based on the modular packaging design model, and considering the constraints and partial circuit characteristics of the unmapped circuit portion, a modular packaging design scheme for the unmapped circuit portion is determined.

[0023] Based on the modular packaging design scheme of the mapped complete circuit and the unmapped circuit parts in the target template, the sub-circuit modules are determined.

[0024] Preferably, the characterization module obtains standardized interface features and encapsulation features based on the sub-circuit module partitioning logic, including:

[0025] Obtain the second circuit connection relationship of complete circuit groups with different partitioning logics;

[0026] Based on the second circuit connection relationship, extract standardized interface features and encapsulation features.

[0027] Preferably, the acquisition module obtains modular encapsulation steps based on standardized interface features and encapsulation features, including:

[0028] Based on the encapsulation difficulty quantification library, the encapsulation difficulty of logic is quantified according to standardized interface characteristics and encapsulation characteristics;

[0029] Input the encapsulation difficulty of the target partitioning logic with the lowest encapsulation difficulty into the encapsulation difficulty comparator;

[0030] Depending on the comparison result of the encapsulation difficulty comparator, the standardized interface features and encapsulation features are input into the corresponding processing path. The processing path where the encapsulation difficulty is less than the comparison value of the encapsulation difficulty comparator is the encapsulation step parsing model processing path, and the processing path where the encapsulation difficulty is greater than or equal to the comparison value of the encapsulation difficulty comparator is the encapsulation expert node processing path.

[0031] Modular encapsulation steps for obtaining the output of the processing path.

[0032] Preferably, the modular encapsulation step for obtaining the processing path output includes:

[0033] When the processing path is the model processing path of the encapsulation step, the model parsing result is directly used as the modular encapsulation step;

[0034] When the processing path is the encapsulation expert node processing path, obtain the node discussion flow of the encapsulation expert node;

[0035] Parse the node discussion flow, obtain the discussion word sequence, and perform word matching between the discussion words in the discussion word sequence and the standard encapsulation step description words in the standard encapsulation step description lexicon.

[0036] If word matching fails, continue word matching;

[0037] If the word match is successful, the corresponding discussion word will be used as the target discussion word, and the standard encapsulation step corresponding to the target discussion word will be used as the target standard encapsulation step.

[0038] After obtaining the target discussion term, a sub-discussion term sequence is formed by a preset number of discussion terms. The discussion terms in the sub-discussion term sequence are matched with the target standard encapsulation step correction terms in the target standard encapsulation step correction term library in turn.

[0039] If the word match is successful, correct the word according to the target standard encapsulation steps and the target standard encapsulation steps, and determine the output steps;

[0040] If word matching fails, the target standard encapsulation step is directly used as the output step.

[0041] The sequential output steps are treated as modular encapsulation steps.

[0042] This invention provides a modular packaging method for integrated circuits, comprising:

[0043] Step 1: Divide the first integrated circuit into multiple independent and fully functional sub-circuit modules;

[0044] Step 2: Based on the partitioning logic of the sub-circuit modules, obtain the standardized interface features and encapsulation features;

[0045] Step 3: Obtain the modular encapsulation steps based on standardized interface features and encapsulation features;

[0046] Step 4: Package the second integrated circuit according to the modular packaging steps.

[0047] Preferably, step 1: the first integrated circuit is divided into multiple independent and functionally complete sub-circuit modules, including:

[0048] Based on a preset complete circuit extraction template and according to the circuit characteristics of the first integrated circuit, multiple complete circuits are extracted.

[0049] Extract the first circuit connection relationship in the first integrated circuit of the complete circuit;

[0050] Based on the first circuit connection relationship, a complete circuit group that can just form the first integrated circuit is determined;

[0051] Each complete circuit in the complete circuit group is taken as a sub-circuit module of the partitioning logic corresponding to the complete circuit group.

[0052] Preferably, step 2: Based on the sub-circuit module partitioning logic, obtain standardized interface features and encapsulation features, including:

[0053] Obtain the second circuit connection relationship of complete circuit groups with different partitioning logics;

[0054] Based on the second circuit connection relationship, extract standardized interface features and encapsulation features.

[0055] Preferably, step 3: obtaining modular encapsulation steps based on standardized interface features and encapsulation features, including:

[0056] Based on the encapsulation difficulty quantification library, the encapsulation difficulty of logic is quantified according to standardized interface characteristics and encapsulation characteristics;

[0057] Input the encapsulation difficulty of the target partitioning logic with the lowest encapsulation difficulty into the encapsulation difficulty comparator;

[0058] Depending on the comparison result of the encapsulation difficulty comparator, the standardized interface features and encapsulation features are input into the corresponding processing path. The processing path where the encapsulation difficulty is less than the comparison value of the encapsulation difficulty comparator is the encapsulation step parsing model processing path, and the processing path where the encapsulation difficulty is greater than or equal to the comparison value of the encapsulation difficulty comparator is the encapsulation expert node processing path.

[0059] Modular encapsulation steps for obtaining the output of the processing path.

[0060] Preferably, the modular encapsulation step for obtaining the processing path output includes:

[0061] When the processing path is the model processing path of the encapsulation step, the model parsing result is directly used as the modular encapsulation step;

[0062] When the processing path is the encapsulation expert node processing path, obtain the node discussion flow of the encapsulation expert node;

[0063] Parse the node discussion flow, obtain the discussion word sequence, and perform word matching between the discussion words in the discussion word sequence and the standard encapsulation step description words in the standard encapsulation step description lexicon.

[0064] If word matching fails, continue word matching;

[0065] If the word match is successful, the corresponding discussion word will be used as the target discussion word, and the standard encapsulation step corresponding to the target discussion word will be used as the target standard encapsulation step.

[0066] After obtaining the target discussion term, a sub-discussion term sequence is formed by a preset number of discussion terms. The discussion terms in the sub-discussion term sequence are matched with the target standard encapsulation step correction terms in the target standard encapsulation step correction term library in turn.

[0067] If the word match is successful, correct the word according to the target standard encapsulation steps and the target standard encapsulation steps, and determine the output steps;

[0068] If word matching fails, the target standard encapsulation step is directly used as the output step.

[0069] The sequential output steps are treated as modular encapsulation steps.

[0070] The beneficial effects of this invention are as follows:

[0071] This invention achieves high integration, flexible configuration, and rapid assembly of integrated circuits by dividing the integrated circuit into multiple independent and fully functional modules, using standardized interface and packaging technologies to obtain standardized interface and packaging features, and obtaining and applying modular packaging steps based on the standardized interface and packaging features.

[0072] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in this application.

[0073] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0074] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0075] Figure 1 This is a schematic diagram of a modular packaging system for an integrated circuit according to an embodiment of the present invention;

[0076] Figure 2 This is a schematic diagram of a modular packaging method for an integrated circuit according to an embodiment of the present invention. Detailed Implementation

[0077] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0078] This invention provides a modular packaging system for integrated circuits, such as... Figure 1 As shown, it includes:

[0079] Circuit partitioning module 1 is used to divide the first integrated circuit into multiple independent and fully functional sub-circuit modules;

[0080] The circuit partitioning module divides the first integrated circuit into multiple independent and fully functional sub-circuit modules, including:

[0081] Based on a preset complete circuit extraction template and according to the circuit characteristics of the first integrated circuit, multiple complete circuits are extracted.

[0082] Extract the first circuit connection relationship in the first integrated circuit of the complete circuit;

[0083] Based on the first circuit connection relationship, a complete circuit group that can just form the first integrated circuit is determined;

[0084] Each complete circuit in the complete circuit group is taken as a sub-circuit module of the partitioning logic corresponding to the complete circuit group;

[0085] Characterization module 2 is used to obtain standardized interface features and encapsulation features based on the partitioning logic of the sub-circuit modules;

[0086] The characterization module, based on the sub-circuit module partitioning logic, obtains standardized interface features and encapsulation features, including:

[0087] Obtain the second circuit connection relationship of complete circuit groups with different partitioning logics;

[0088] Based on the second circuit connection relationship, extract standardized interface features and encapsulation features;

[0089] Module 3 is used to obtain modular encapsulation steps based on standardized interface features and encapsulation features;

[0090] The acquisition module obtains modular encapsulation steps based on standardized interface features and encapsulation features, including:

[0091] Based on the encapsulation difficulty quantification library, the encapsulation difficulty of logic is quantified according to standardized interface characteristics and encapsulation characteristics;

[0092] Input the encapsulation difficulty of the target partitioning logic with the lowest encapsulation difficulty into the encapsulation difficulty comparator;

[0093] Depending on the comparison result of the encapsulation difficulty comparator, the standardized interface features and encapsulation features are input into the corresponding processing path. The processing path where the encapsulation difficulty is less than the comparison value of the encapsulation difficulty comparator is the encapsulation step parsing model processing path, and the processing path where the encapsulation difficulty is greater than or equal to the comparison value of the encapsulation difficulty comparator is the encapsulation expert node processing path.

[0094] Modular encapsulation steps for obtaining the output of the processing path;

[0095] Packaging module 4 is used to package the second integrated circuit according to the modular packaging steps.

[0096] The working principle and beneficial effects of the above technical solution are as follows:

[0097] The first integrated circuit is an integrated circuit that requires modular packaging design. Circuit features are characteristic representations of the circuit topology, such as component types and connection methods. A pre-defined complete circuit extraction template includes a one-to-one complete circuit topology and its corresponding circuit feature description. By referring to the circuit features, the complete circuit extraction template can extract independent and functionally complete sub-integrated circuits from the first integrated circuit. The complete circuit is a circuit that has historically been designed using modular packaging. The first circuit connection relationship is a characteristic representation of the overall complete circuit and the circuit topology of the first integrated circuit. The partitioning logic is a partitioning scheme for complete circuits in different complete circuit groups, with each partitioning scheme corresponding to a sub-circuit module. The second circuit connection relationship is the circuit connection relationship between complete circuits belonging to the same complete circuit group. Standardized interface features are the physical and electrical characteristics of interfaces conforming to the connection standards between complete circuits, such as pin count, signal type, and voltage level. Packaging features are the physical characteristics conforming to the external physical packaging standards of the complete circuit, such as packaging process, packaging structure, and packaging materials. The packaging difficulty quantification library stores multiple interfaces that meet standardized interface features and packaging characteristics. The difficulty value corresponding to the feature is the sum of the difficulty values ​​corresponding to all standardized interface features and packaging features. The target partitioning logic is the partitioning logic with the lowest packaging difficulty. The packaging difficulty comparator is used to compare the input packaging difficulty with the packaging difficulty threshold (comparison value). Based on the different comparison results, the standardized interface features and packaging features are processed separately. The processing path of the packaging step parsing model is: input the standardized interface features and packaging features into the processing path of the packaging step parsing model. The packaging step parsing model is an AI model that automatically outputs packaging steps that conform to the input standardized interface features and packaging features. It is obtained through training by manually modular packaging records. During training, the standardized interface features and packaging features extracted from the records are used as input to the neural network model, and the packaging steps in the records are used as output to train the model until the model training converges. The processing path of the packaging expert node is: submit the standardized interface features and packaging features to the integrated circuit expert node and obtain the modular packaging steps replied by the integrated circuit expert. The second integrated circuit is a local complete circuit in the first integrated circuit corresponding to the modular packaging steps.

[0098] This application achieves high integration, flexible configuration, and rapid assembly of integrated circuits by dividing the integrated circuit into multiple independent and fully functional modules, using standardized interface and packaging technologies to obtain standardized interface and packaging features, and obtaining and applying modular packaging steps based on the standardized interface and packaging features.

[0099] In one embodiment, the circuit partitioning module divides the first integrated circuit into multiple independent and fully functional sub-circuit modules, and further includes:

[0100] If it is impossible to determine a complete circuit group that can exactly form the first integrated circuit, the complete circuit is mapped onto the three-dimensional template of the first integrated circuit. The target template that meets the mapping criteria and has the widest coverage of the three-dimensional template is determined. Here, "it is impossible to determine a complete circuit group that can exactly form the first integrated circuit" means that it is impossible to find a complete circuit group whose complete circuit combinations can be connected to form the first integrated circuit. The three-dimensional template of the first integrated circuit is a template whose constraint mapping content (circuit elements and element connection relationships) conforms to the circuit elements and element connection relationships in the first integrated circuit. The mapping criteria are: the mapping content does not overlap and does not exceed the range of the three-dimensional template; the widest coverage of the three-dimensional template means that the covered complete circuit occupies the largest area of ​​the three-dimensional template.

[0101] Based on the target connection relationship between the mapped complete circuit and the unmapped circuit portion in the target template, the condition constraints for modular packaging design of the unmapped circuit portion are determined; wherein, the unmapped circuit portion is: the unmapped template portion in the target template corresponds to the local circuit portion of the first integrated circuit; the target connection relationship is: the correspondence between the connected circuit elements of the mapped complete circuit and the unmapped circuit portion; wherein, the condition constraint is: the standard interface after modular packaging of the mapped complete circuit that has a corresponding relationship with the connected circuit elements;

[0102] Based on the modular packaging design model, and considering the constraints and partial circuit characteristics of the unmapped circuit portion, a modular packaging design scheme for the unmapped circuit portion is determined. The partial circuit characteristics are defined as the connection relationships between circuit elements in the unmapped circuit portion. The modular packaging design model is an AI model that automatically performs modular packaging design based on the current circuit condition, obtained through machine learning using records of manual integrated circuit modular packaging design based on the connection relationships between circuit elements.

[0103] Based on the modular packaging design schemes of the mapped complete circuit and the unmapped circuit portions in the target template, sub-circuit modules are determined. Specifically, sub-circuit modules are: the circuit modules corresponding to the mapped complete circuits and the circuit modules corresponding to the packaged circuits of the modular packaging designs for the unmapped circuit portions.

[0104] The working principle and beneficial effects of the above technical solution are as follows:

[0105] Since the complete circuit is preset based on experience, there may be cases where local circuits have not been modularly packaged in the past. Therefore, when it is impossible to determine the complete circuit group that can just form the first integrated circuit, the target template that meets the mapping standard and has the widest three-dimensional template coverage should be determined, so as to make the most of the known package design and save design resources.

[0106] Simultaneously, based on the target connection relationships between the mapped complete circuits and unmapped circuit parts in the target template, the conditional constraints for modular packaging design of the unmapped circuit parts are determined. These constraints are the standard interfaces of the mapped complete circuits after modular packaging, which correspond to the connected circuit elements. By introducing a modular packaging design model and developing a modular packaging design scheme for the unmapped circuit parts based on the conditional constraints and some circuit characteristics, the design efficiency is higher when historical design experience cannot be fully relied upon. Furthermore, the setting of sub-circuit modules is more appropriate.

[0107] In one embodiment, the modular encapsulation step for obtaining the processing path output includes:

[0108] When the processing path is the model processing path of the encapsulation step, the model parsing result is directly used as the modular encapsulation step;

[0109] When the processing path is the encapsulation expert node processing path, obtain the node discussion flow of the encapsulation expert node;

[0110] Parse the node discussion flow, obtain the discussion word sequence, and perform word matching between the discussion words in the discussion word sequence and the standard encapsulation step description words in the standard encapsulation step description lexicon.

[0111] If word matching fails, continue word matching;

[0112] If the word match is successful, the corresponding discussion word will be used as the target discussion word, and the standard encapsulation step corresponding to the target discussion word will be used as the target standard encapsulation step.

[0113] After obtaining the target discussion term, a sub-discussion term sequence is formed by a preset number of discussion terms. The discussion terms in the sub-discussion term sequence are matched with the target standard encapsulation step correction terms in the target standard encapsulation step correction term library in turn.

[0114] If the word match is successful, correct the word according to the target standard encapsulation steps and the target standard encapsulation steps, and determine the output steps;

[0115] If word matching fails, the target standard encapsulation step is directly used as the output step.

[0116] The sequential output steps are treated as modular encapsulation steps.

[0117] The working principle and beneficial effects of the above technical solution are as follows:

[0118] The node discussion flow is the time-series of discussions among packaging expert nodes regarding modular packaging steps; the discussion word sequence is the semantic (discussion word) sequence obtained by parsing the discussion content in chronological order; the standard packaging step description lexicon stores the descriptive semantics (standard packaging step description words) of multiple standard packaging steps; if a word match between a discussion word and a standard packaging step description word fails, it means that the discussion content of the corresponding discussion word is not a packaging step description, and the word match continues with the next discussion word in the discussion word sequence; if a word match is successful, the corresponding discussion word is taken as the target discussion word, and the standard packaging step corresponding to the target discussion word is taken as the target standard packaging step. After the target standard packaging step is matched, different integrated circuit experts may question and correct the target standard packaging step during discussions. Therefore, after obtaining the target discussion word... A sub-discussion word sequence consisting of a preset number of discussion words is generated. Each discussion word in this sub-discussion word sequence is sequentially matched with a target standard encapsulation step correction term from the target standard encapsulation step correction term library. The preset number of words is manually set, for example, 10, and can be customized according to needs. The target standard encapsulation step correction term library includes multiple terms describing the correction process of the target standard encapsulation steps. If a target standard encapsulation step correction term is matched, it indicates that the target standard encapsulation step needs correction. Based on the target standard encapsulation step and its correction term, the corrected target standard encapsulation step is determined, i.e., the output step. If no correction term is matched, it means that the target standard encapsulation step has not been challenged and is directly used as the output step. After all discussion words in the discussion word sequence have been traversed, the sequentially output steps are used as modular encapsulation steps.

[0119] When the encapsulation difficulty is high, this application introduces the node discussion flow of encapsulation expert nodes, analyzes the node discussion flow to obtain the discussion word sequence, identifies the target standard encapsulation steps, introduces target standard encapsulation step correction words to correct the target standard encapsulation steps, and obtains the output steps output in sequence, thereby improving the rationality and accuracy of the extraction of modular encapsulation steps.

[0120] This invention provides a modular packaging method for integrated circuits, such as... Figure 2 As shown, it includes:

[0121] Step 1: Divide the first integrated circuit into multiple independent and fully functional sub-circuit modules;

[0122] Step 2: Based on the partitioning logic of the sub-circuit modules, obtain the standardized interface features and encapsulation features;

[0123] Step 3: Obtain the modular encapsulation steps based on standardized interface features and encapsulation features;

[0124] Step 4: Package the second integrated circuit according to the modular packaging steps;

[0125] Step 3, obtaining modular encapsulation steps based on standardized interface features and encapsulation features, includes:

[0126] Based on the encapsulation difficulty quantification library, the encapsulation difficulty of logic is quantified according to standardized interface characteristics and encapsulation characteristics;

[0127] Input the encapsulation difficulty of the target partitioning logic with the lowest encapsulation difficulty into the encapsulation difficulty comparator;

[0128] Depending on the comparison result of the encapsulation difficulty comparator, the standardized interface features and encapsulation features are input into the corresponding processing path. The processing path where the encapsulation difficulty is less than the comparison value of the encapsulation difficulty comparator is the encapsulation step parsing model processing path, and the processing path where the encapsulation difficulty is greater than or equal to the comparison value of the encapsulation difficulty comparator is the encapsulation expert node processing path.

[0129] Modular encapsulation steps for obtaining the output of the processing path;

[0130] The modular encapsulation step for obtaining the processing path output includes:

[0131] When the processing path is the model processing path of the encapsulation step, the model parsing result is directly used as the modular encapsulation step;

[0132] When the processing path is the encapsulation expert node processing path, obtain the node discussion flow of the encapsulation expert node;

[0133] Parse the node discussion flow, obtain the discussion word sequence, and perform word matching between the discussion words in the discussion word sequence and the standard encapsulation step description words in the standard encapsulation step description lexicon.

[0134] If word matching fails, continue word matching;

[0135] If the word match is successful, the corresponding discussion word will be used as the target discussion word, and the standard encapsulation step corresponding to the target discussion word will be used as the target standard encapsulation step.

[0136] After obtaining the target discussion term, a sub-discussion term sequence is formed by a preset number of discussion terms. The discussion terms in the sub-discussion term sequence are matched with the target standard encapsulation step correction terms in the target standard encapsulation step correction term library in turn.

[0137] If the word match is successful, correct the word according to the target standard encapsulation steps and the target standard encapsulation steps, and determine the output steps;

[0138] If word matching fails, the target standard encapsulation step is directly used as the output step.

[0139] The sequential output steps are treated as modular encapsulation steps.

[0140] In one embodiment, step 1: dividing the first integrated circuit into multiple independent and functionally complete sub-circuit modules, including:

[0141] Based on a preset complete circuit extraction template and according to the circuit characteristics of the first integrated circuit, multiple complete circuits are extracted.

[0142] Extract the first circuit connection relationship in the first integrated circuit of the complete circuit;

[0143] Based on the first circuit connection relationship, a complete circuit group that can just form the first integrated circuit is determined;

[0144] Each complete circuit in the complete circuit group is taken as a sub-circuit module of the partitioning logic corresponding to the complete circuit group.

[0145] In one embodiment, step 2: Based on the partitioning logic of the sub-circuit modules, obtain standardized interface features and encapsulation features, including:

[0146] Obtain the second circuit connection relationship of complete circuit groups with different partitioning logics;

[0147] Based on the second circuit connection relationship, extract standardized interface features and encapsulation features.

[0148] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A modular packaging system for integrated circuits, characterized in that, include: A circuit partitioning module is used to divide the first integrated circuit into multiple independent and fully functional sub-circuit modules; The characterization module is used to obtain standardized interface features and encapsulation features based on the partitioning logic of the sub-circuit modules; The acquisition module is used to obtain modular encapsulation steps based on standardized interface characteristics and encapsulation characteristics. A packaging module for packaging a second integrated circuit according to modular packaging steps; The module obtains modular encapsulation steps based on standardized interface characteristics and encapsulation characteristics, including: Based on the encapsulation difficulty quantification library, the encapsulation difficulty of logic is quantified according to standardized interface characteristics and encapsulation characteristics; Input the encapsulation difficulty of the target partitioning logic with the lowest encapsulation difficulty into the encapsulation difficulty comparator; Depending on the comparison result of the encapsulation difficulty comparator, the standardized interface features and encapsulation features are input into the corresponding processing path. The processing path where the encapsulation difficulty is less than the comparison value of the encapsulation difficulty comparator is the encapsulation step parsing model processing path, and the processing path where the encapsulation difficulty is greater than or equal to the comparison value of the encapsulation difficulty comparator is the encapsulation expert node processing path. The modular encapsulation steps for obtaining the output of the processing path include: When the processing path is the model processing path of the encapsulation step, the model parsing result is directly used as the modular encapsulation step; When the processing path is the encapsulation expert node processing path, obtain the node discussion flow of the encapsulation expert node; Parse the node discussion flow, obtain the discussion word sequence, and perform word matching between the discussion words in the discussion word sequence and the standard encapsulation step description words in the standard encapsulation step description lexicon. If word matching fails, continue word matching; If the word match is successful, the corresponding discussion word will be used as the target discussion word, and the standard encapsulation step corresponding to the target discussion word will be used as the target standard encapsulation step. After obtaining the target discussion term, a sub-discussion term sequence is formed by a preset number of discussion terms. The discussion terms in the sub-discussion term sequence are matched with the target standard encapsulation step correction terms in the target standard encapsulation step correction term library in turn. If the word match is successful, correct the word according to the target standard encapsulation steps and the target standard encapsulation steps, and determine the output steps; If word matching fails, the target standard encapsulation step is directly used as the output step. The sequential output steps are treated as modular encapsulation steps.

2. The modular packaging system for an integrated circuit as described in claim 1, characterized in that, The circuit partitioning module divides the first integrated circuit into multiple independent and fully functional sub-circuit modules, including: Based on a preset complete circuit extraction template and according to the circuit characteristics of the first integrated circuit, multiple complete circuits are extracted. Extract the first circuit connection relationship in the first integrated circuit of the complete circuit; Based on the first circuit connection relationship, a complete circuit group that can just form the first integrated circuit is determined; Each complete circuit in the complete circuit group is taken as a sub-circuit module of the partitioning logic corresponding to the complete circuit group.

3. The modular packaging system for an integrated circuit as described in claim 1, characterized in that, The characterization module obtains standardized interface features and encapsulation features based on the sub-circuit module partitioning logic, including: Obtain the second circuit connection relationship of complete circuit groups with different partitioning logics; Based on the second circuit connection relationship, extract standardized interface features and encapsulation features.

4. A modular packaging method for integrated circuits, characterized in that, include: Step 1: Divide the first integrated circuit into multiple independent and fully functional sub-circuit modules; Step 2: Based on the partitioning logic of the sub-circuit modules, obtain the standardized interface features and encapsulation features; Step 3: Obtain the modular encapsulation steps based on standardized interface features and encapsulation features; Step 4: Package the second integrated circuit according to the modular packaging steps; Step 3, obtaining modular encapsulation steps based on standardized interface features and encapsulation features, includes: Based on the encapsulation difficulty quantification library, the encapsulation difficulty of logic is quantified according to standardized interface characteristics and encapsulation characteristics; Input the encapsulation difficulty of the target partitioning logic with the lowest encapsulation difficulty into the encapsulation difficulty comparator; Depending on the comparison result of the encapsulation difficulty comparator, the standardized interface features and encapsulation features are input into the corresponding processing path. The processing path where the encapsulation difficulty is less than the comparison value of the encapsulation difficulty comparator is the encapsulation step parsing model processing path, and the processing path where the encapsulation difficulty is greater than or equal to the comparison value of the encapsulation difficulty comparator is the encapsulation expert node processing path. The modular encapsulation steps for obtaining the output of the processing path include: When the processing path is the model processing path of the encapsulation step, the model parsing result is directly used as the modular encapsulation step; When the processing path is the encapsulation expert node processing path, obtain the node discussion flow of the encapsulation expert node; Parse the node discussion flow, obtain the discussion word sequence, and perform word matching between the discussion words in the discussion word sequence and the standard encapsulation step description words in the standard encapsulation step description lexicon. If word matching fails, continue word matching; If the word match is successful, the corresponding discussion word will be used as the target discussion word, and the standard encapsulation step corresponding to the target discussion word will be used as the target standard encapsulation step. After obtaining the target discussion term, a sub-discussion term sequence is formed by a preset number of discussion terms. The discussion terms in the sub-discussion term sequence are matched with the target standard encapsulation step correction terms in the target standard encapsulation step correction term library in turn. If the word match is successful, correct the word according to the target standard encapsulation steps and the target standard encapsulation steps, and determine the output steps; If word matching fails, the target standard encapsulation step is directly used as the output step. The sequential output steps are treated as modular encapsulation steps.

5. The modular packaging method for an integrated circuit as described in claim 4, characterized in that, Step 1: Divide the first integrated circuit into multiple independent and fully functional sub-circuit modules, including: Based on a preset complete circuit extraction template and according to the circuit characteristics of the first integrated circuit, multiple complete circuits are extracted. Extract the first circuit connection relationship in the first integrated circuit of the complete circuit; Based on the first circuit connection relationship, a complete circuit group that can just form the first integrated circuit is determined; Each complete circuit in the complete circuit group is taken as a sub-circuit module of the partitioning logic corresponding to the complete circuit group.

6. The modular packaging method for an integrated circuit as described in claim 4, characterized in that, Step 2: Based on the sub-circuit module partitioning logic, obtain standardized interface features and encapsulation features, including: Obtain the second circuit connection relationship of complete circuit groups with different partitioning logics; Based on the second circuit connection relationship, extract standardized interface features and encapsulation features.

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