Shallow trench isolation structure and process method thereof

Abstract

The invention relates to the technical field of semiconductors, in particular to a shallow trench isolation structure and a process method thereof. The shallow trench isolation structure comprises a trench and a filling structure; the bottom of the groove is provided with a vertical side wall, the top of the groove is a trapezoidal opening, the trapezoidal opening is gradually enlarged from outside to inside, and the inclined side wall of the trapezoidal opening is intersected with the vertical side wall; the filling structure is filled in the groove. The process method of the shallow trench isolation structure comprises the following steps: introducing process gas into a process chamber to excite and generate plasma, and carrying out vertical bombardment on a substrate; gradually adjusting the bombardment angle of the plasma, and carrying out inclined bombardment on the bottom of the side wall of the groove; reducing the radio frequency power, gradually adjusting the bombardment angle of the plasma, and carrying out inclined bombardment on the top of the side wall of the groove; and a filling step: filling an insulating material into the groove. According to the shallow trench isolation structure and the process method thereof provided by the invention, the filling defect rate is low, and the reliability and the yield of shallow trench isolation are remarkably improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a shallow trench isolation structure and a process method thereof. Background Art

[0002] In the integrated circuit manufacturing process above 0.35 microns, LOCOS (Local Oxidation of Silicon) technology is widely used and has a long history of development and mature technology. However, this technology uses a field oxidation process, and the depth of the oxide film and the bird's beak effect caused by oxidation in the active area at the edge of the field area limit its further application.

[0003] As semiconductor device feature sizes continue to shrink, the isolation area between devices also needs to be reduced accordingly. STI (shallow trench isolate) technology is often used to replace LOCOS technology to accommodate deep submicron processes below 0.35 microns. However, the shallow trench isolation structures used in related technologies suffer from high fill defect rates and low reliability. Summary of the Invention

[0004] The object of the present invention is to provide a shallow trench isolation structure and a process method thereof, so as to alleviate the technical problems of high filling defect rate and low reliability of the shallow trench isolation structure in the prior art.

[0005] The shallow trench isolation structure provided by the present invention comprises a trench and a filling structure.

[0006] The bottom of the groove has a vertical sidewall, the top of the groove is a trapezoidal opening, the trapezoidal opening gradually expands from the outside to the inside, and the inclined sidewall of the trapezoidal opening intersects with the vertical sidewall; the filling structure fills the groove.

[0007] Preferably, as an implementation method, the ratio of the width difference between the large and small ends of the trapezoidal opening to the width of the small end is 20-30%;

[0008] And / or, the inclination angle of the inclined side wall is 10° to 30°.

[0009] Preferably, as an implementable embodiment, the vertical side wall and the bottom wall are smoothly transitioned through an arc-shaped corner.

[0010] Preferably, as an implementable embodiment, the curvature radius of the arc-shaped corner is 5 to 20 nm.

[0011] Preferably, as an implementation method, a SiON layer is attached to the inner wall of the trench.

[0012] The process method of the shallow trench isolation structure provided by the present invention includes:

[0013] In a first etching step, a process gas is introduced into the process chamber to generate plasma, which vertically bombards the substrate to form the initial morphology of the trench; wherein the initial morphology of the trench is U-shaped;

[0014] In the second etching step, the plasma bombardment angle is gradually adjusted to obliquely bombard the bottom of the sidewall of the trench to widen the bottom of the trench and form the vertical sidewall;

[0015] In a third etching step, the radio frequency power is reduced and the bombardment angle of the plasma is gradually adjusted to obliquely bombard the top of the sidewall of the trench to form the trapezoidal opening;

[0016] The filling step is to fill the trench with insulating material.

[0017] Preferably, as an implementation method, the substrate is a silicon substrate.

[0018] In the first etching step, the process gas includes one or more of fluorine-based gas, Cl2, HBr and O2; and / or, in the second etching step, the process gas includes one or more of fluorine-based gas, Cl2, HBr and O2; and / or, in the third etching step, the process gas includes one or more of fluorine-based gas, Cl2, HBr and O2.

[0019] Preferably, as an implementation method, in the first etching step, the fluorine-based gas includes SF6, and the volume ratio of SF6 to O2 is 2:1 to 4:1; and / or the volume ratio of Cl2, HBr, and O2 is (0.8 to 1.2): (1.8 to 2.2): (0.4 to 0.7);

[0020] And / or, in the second etching step, the fluorine-based gas includes SF6, and the volume ratio of SF6 to O2 is 2:1 to 4:1; and / or, the volume ratio of Cl2, HBr, and O2 is (0.8 to 1.2): (1.8 to 2.2): (0.4 to 0.7);

[0021] And / or, in the third etching step, the fluorine-based gas includes SF6, and the volume ratio of SF6 to O2 is 2:1 to 4:1; and / or, the volume ratio of Cl2, HBr, and O2 is (0.8 to 1.2): (1.8 to 2.2): (0.4 to 0.7).

[0022] Preferably, as an implementation method, the second etching step includes: gradually increasing the bombardment angle of the plasma, obliquely bombarding the bottom of the sidewall of the trench from bottom to top, so as to widen the bottom of the trench and form the vertical sidewall;

[0023] And / or, the third etching step includes: gradually increasing the bombardment angle of the plasma, and obliquely bombarding the top of the sidewall of the trench from bottom to top to form the trapezoidal opening.

[0024] Preferably, as an implementation method, in the second etching step, the radio frequency power is 1200-1500W;

[0025] And / or, in the third etching step, the radio frequency power is 200-300W.

[0026] Preferably, as an implementable method, the filling step includes:

[0027] A first filling step is to form an insulating material by high-density plasma chemical vapor deposition to fill the bottom of the trench;

[0028] In the second filling step, the insulating material is formed by fluidized chemical vapor deposition to fill the remaining portion of the trench.

[0029] Preferably, as an implementation method, in the first filling step, the deposition rate is 3 to 6 nm / min, the gas flow rate is above 300 sccm, and the process pressure is 5 to 10 mTorr;

[0030] And / or, in the second filling step, the deposition rate is 10-14 nm / min, the gas flow rate is 100-150 sccm, and the process pressure is 10-2000 mTorr.

[0031] Preferably, as an implementation method, in the first filling step, the filling height of the insulating material is 40-60% of the depth of the trench.

[0032] Preferably, as an implementable embodiment, the insulating material is SiO2;

[0033] And / or, the substrate is a silicon substrate.

[0034] Preferably, as an implementation method, in the first filling step, the process gas includes SiH4 and O2, wherein the volume proportion of SiH4 is 70-80%, and the volume proportion of O2 is 20-30%;

[0035] And / or, in the second filling step, the process gas includes SiH 4 and O 2 , wherein the volume proportion of SiH 4 is 70-80%, and the volume proportion of O 2 is 20-30%.

[0036] Preferably, as an embodiment, before the filling step, the process further comprises:

[0037] In the deposition step, a SiON layer is deposited on the inner wall of the trench.

[0038] Preferably, as an embodiment, after the filling step, the process further comprises:

[0039] Annealing step: plasma annealing is performed in a nitrogen environment.

[0040] Preferably, as an implementable embodiment, in the annealing step, the RF power is 200-400 W, the process temperature is 400-500° C., and the process time is 20-40 s.

[0041] Preferably, as an embodiment, after the filling step, the process further comprises:

[0042] In the planarization step, excess portions of the top of the insulating material are removed by chemical mechanical polishing, so that the top of the insulating material is flush with the peripheral structure of the trench.

[0043] Preferably, as an implementation method, before the first etching step, the process method further includes:

[0044] Masking step, depositing a hard mask layer on the substrate.

[0045] Compared with the prior art, the present invention has the following beneficial effects:

[0046] The shallow trench isolation structure provided by the present invention has a bottom width of the trench greater than the top width, and is gradually transitioned through a trapezoidal opening. On the one hand, it can delay the premature closure of the top material and is compatible with a wider range of filling processes (such as subsequent annealing or CMP steps), which is conducive to optimizing the filling uniformity and density of the subsequent insulating structure, reducing the residual stress caused by the shrinkage of the insulating structure, reducing the filling defect rate, and enhancing the breakdown voltage; on the other hand, it can reduce the micro-voids (Voids) or seams (Seams) generated during filling, thereby improving the electrical reliability of the shallow trench isolation structure; on the other hand, it can also better control the shape and depth of the trench, help reduce edge effects and leakage current, enhance isolation effect, suppress parasitic capacitance and leakage current, and improve device reliability. In addition, the trapezoidal opening gradually shrinks from the inside to the outside, and the trench sidewall and the insulating material filled therein can also form a mechanical interlocking structure, which is conducive to improving interface bonding strength and fracture toughness, and further improving device reliability.

[0047] Therefore, the shallow trench isolation structure provided by the present invention has a low filling defect rate, and while maintaining process compatibility, it significantly improves the reliability and yield of shallow trench isolation, and has high industrial value.

[0048] The process method of the shallow trench isolation structure provided by the present invention can produce the above-mentioned shallow trench isolation structure, so it has all the technical effects of the above-mentioned shallow trench isolation structure, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0050] Figure 1 Schematic diagram of the cross-sectional structure of a shallow trench isolation structure in the related art;

[0051] Figure 2 A schematic diagram of the principle structure of a trench in a shallow trench isolation structure provided by an embodiment of the present invention;

[0052] Figure 3 A schematic cross-sectional view of a trench in a shallow trench isolation structure provided by an embodiment of the present invention;

[0053] Figure 4 A schematic cross-sectional view of a shallow trench isolation structure provided by an embodiment of the present invention;

[0054] Figure 5 Another schematic cross-sectional view of a shallow trench isolation structure provided by an embodiment of the present invention;

[0055] Figure 6 A first schematic flow chart of a process for a shallow trench isolation structure provided by an embodiment of the present invention;

[0056] Figure 7 A second schematic flow chart of a process for a shallow trench isolation structure provided by an embodiment of the present invention;

[0057] Figure 8 A schematic structural diagram of the process equipment provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0058] In the related art, the trench shape of the shallow trench isolation structure is usually U-shaped (such as Figure 1 As shown in the figure, the trench is V-shaped, with poor isolation effect and high filling defect rate. Chemical vapor deposition (CVD) is usually used to fill the trench with oxide, which easily produces voids. This problem is more prominent in trenches with high aspect ratios.

[0059] Based on this, an embodiment of the present invention provides a shallow trench isolation structure and its process method and process equipment. By setting the top of the trench to a trapezoidal opening structure and filling the interior of the trench with insulating material in two steps, stress concentration can be reduced, filling uniformity can be optimized, filling defect rate can be reduced, and device reliability can be improved.

[0060] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention.

[0061] The present invention will be further described in detail below through specific implementation examples in conjunction with the accompanying drawings.

[0062] See also Figure 2-Figure 5 An embodiment of the present invention provides a shallow trench isolation structure, which includes a trench 100 and a filling structure 200; the bottom of the trench 100 has a vertical sidewall 110, the top of the trench 100 is a trapezoidal opening 120, the trapezoidal opening gradually expands from the outside to the inside, and the inclined sidewall 121 of the trapezoidal opening 120 intersects with the vertical sidewall 110; the filling structure fills the trench.

[0063] The shallow trench isolation structure provided in this embodiment has a bottom width of the trench 100 that is greater than the top width, and gradually transitions through the trapezoidal opening 120. On the one hand, it can delay the premature closure of the top material and is compatible with a wider range of filling processes (such as subsequent annealing or CMP steps), which is beneficial to optimizing the filling uniformity and density of the subsequent insulation structure, reducing the residual stress caused by the shrinkage of the insulation structure 200, reducing the filling defect rate, and enhancing the breakdown voltage; on the other hand, it can reduce the micro-voids (Voids) or seams (Seams) generated during filling, thereby improving the electrical reliability of the shallow trench isolation structure; on the other hand, it can also better control the shape and depth of the trench 100, help reduce edge effects and leakage current, enhance isolation effect, suppress parasitic capacitance and leakage current, and improve device reliability. In addition, the trapezoidal opening 120 gradually shrinks from the inside to the outside, and can also form a mechanical interlocking structure between the trench sidewall and its internal filling structure 200, which is beneficial to improving the interface bonding strength and fracture toughness, further improving device reliability.

[0064] Therefore, the shallow trench isolation structure provided in this embodiment has a low filling defect rate, significantly improves the reliability and yield of shallow trench isolation while maintaining process compatibility, and has high industrial value.

[0065] Specifically, the ratio of the width difference between the inner and outer ends of the trapezoidal opening 120 to the outer end width can be set to 20-30%, which is equivalent to increasing the bottom size of the groove 100 by 20-30%, which can significantly enhance the electrical isolation effect between adjacent devices, suppress parasitic capacitance and leakage current, and enhance reliability.

[0066] Specifically, see Figure 2The inclination angle α of the inclined side wall 121 of the trapezoidal opening 120 can be set to 10° to 30°, which can effectively delay the closure of corners during the filling process, reduce the risk of keyholes or cracks, and thus reduce local stress mutations caused by voids.

[0067] Preferably, the vertical side wall 110 and the bottom wall 130 at the bottom of the groove 100 are smoothly transitioned through the arc corner 140. Compared with the sharp corner at the bottom of the groove in the related art, the arc corner 140 disperses the mechanical stress caused by thermal expansion or mechanical load at the edge of the groove, alleviates the stress concentration problem, and reduces the risk of substrate cracks or isolation layer delamination due to stress concentration. The effect is particularly significant in applications with high aspect ratios (such as 20:1). In addition, the setting of the arc corner 140 can also avoid carrier collision ionization at the sharp corners, reduce the electric field concentration effect, and improve the breakdown voltage and leakage characteristics of the isolation structure.

[0068] Specifically, see Figure 2 The curvature radius R of the arc corner 140 can be set to 5 to 20 nm, which can reduce the stress by 30 to 50%, has a better stress dispersion effect, and can effectively reduce the electric field concentration effect.

[0069] Preferably, see Figure 4 A SiON layer 300 is attached to the inner wall of the trench 100. The SiON layer 300 forms trap energy levels through nitrogen doping, which can effectively capture carriers and suppress leakage current on the inner wall of the trench 100. It also has high density and can suppress oxygen vacancy defects and impurity diffusion. In addition, because the stress characteristics of SiON are between Si3N4 and SiO2, it is more matched with the thermal expansion coefficient of the silicon substrate, so it can reduce the risk of cracks or voids in the insulating structure 200 caused by thermal expansion mismatch, which is beneficial to reducing the filling defect rate.

[0070] Based on the above structure, the stress of the shallow trench isolation structure can be reduced by 30%-50%. The shallow trench isolation structure in this embodiment was subjected to a 1000-hour high temperature reverse bias (HTRB) test and showed no stress-induced failure, indicating high reliability.

[0071] Figure 6 A schematic flow chart of a process method for a shallow trench isolation structure is provided for one embodiment of the present invention. The process method includes:

[0072] S102, a first etching step, introducing a process gas into the process chamber to generate plasma, vertically bombarding the substrate to form an initial morphology of the trench; wherein the initial morphology of the trench is U-shaped;

[0073] S104, a second etching step, gradually adjusting the plasma bombardment angle to obliquely bombard the bottom of the sidewall of the trench to widen the bottom of the trench and form a vertical sidewall;

[0074] By adjusting the bombardment angle of the plasma, the sidewalls at different heights of the bottom of the trench can be bombarded obliquely, so as to form vertical sidewalls 110 of a certain height after the bottom of the trench is widened.

[0075] S106, a third etching step, reducing the radio frequency power and gradually adjusting the plasma bombardment angle to obliquely bombard the top of the sidewall of the trench to form a trapezoidal opening;

[0076] S108, a filling step, filling the trench with insulating material.

[0077] By adjusting the bombardment angle of the plasma, the sidewalls at different heights of the top of the trench can be bombarded obliquely, so as to form a trapezoidal opening 120 at the top of the trench.

[0078] The process method provided in this embodiment can produce the above-mentioned shallow trench isolation structure, and thus has all the technical effects of the above-mentioned shallow trench isolation structure.

[0079] The substrate is selected to be a silicon substrate.

[0080] In the first etching step, a fluorine-based gas can be introduced as a process gas. The fluorine-based gas can chemically react with the silicon material to generate a volatile silicon fluoride gas, which can regulate the silicon etching rate. Cl2 can also be introduced as a process gas. Cl2 can enhance anisotropic etching and facilitate the formation of steep sidewalls. HBr can also be introduced as a process gas. HBr helps to suppress lateral etching so as to obtain an initial trench morphology with a target width. O2 can also be introduced as a process gas. O2 can react with the fluorine-based gas to generate a fluorine-containing polymer, which can regulate the deposition rate of the fluorine-containing polymer. The fluorine-containing polymer is deposited on the mask layer and can inhibit etching of the mask layer. Specifically, SF6 can be selected as the fluorine-based gas, the volume ratio of SF6 to O2 is set to 2:1 to 4:1, and the volume ratio of Cl2, HBr, and O2 is set to (0.8 to 1.2): (1.8 to 2.2): (0.4 to 0.7), preferably 1:2:0.5. Among them, the flow rate of O2 is positively correlated with the deposition rate of fluoropolymer.

[0081] In the second etching step, fluorine-based gas can be introduced as a process gas. The chemical reaction between fluorine-based gas and silicon material has high selectivity and high etching rate. When the plasma bombards the bottom of the side wall of the groove 100, the silicon material at the bottom of the groove 100 can be removed, thereby widening the bottom of the groove 100 and forming an arc corner 140 between the vertical side wall 110 and the bottom wall 130; Cl2 can also be introduced as a process gas to smoothly form the vertical side wall 110 at the bottom of the groove 100; HBr can also be introduced as a process gas to obtain a groove 100 of a target width; O2 can also be introduced as a process gas. O2 can react with the fluorine-based gas to generate a fluorine-containing polymer that can cover the surface of the side wall of the groove 100 to smooth the micro-undulations and reduce the side wall roughness. Specifically, SF6 can be selected as the fluorine-based gas, and the volume ratio of SF6 to O2 can be set to 2:1~4:1, which can control the roughness of the vertical side wall 110 at the bottom of the groove 100 to below 2 mm; the volume ratio of Cl2, HBr, and O2 is set to (0.8~1.2): (1.8~2.2): (0.4~0.7), preferably 1:2:0.5.

[0082] In the third etching step, a fluorine-based gas can be introduced as a process gas. The fluorine-based gas can chemically react with the silicon material to generate volatile silicon fluoride gas. Cl2 can also be introduced as a process gas to smoothly form the inclined sidewall 121 of the top trapezoidal opening 120. HBr can also be introduced as a process gas to obtain the inclined sidewall 121 with a target tilt angle. O2 can also be introduced as a process gas. O2 can react with the fluorine-based gas to generate a fluorine-containing polymer that can cover the inner wall surface of the groove to smooth micro-undulations and reduce the inner wall roughness. Specifically, SF6 can be selected as the fluorine-based gas, and the volume ratio of SF6 to O2 can be set to 2:1 to 4:1, which can control the roughness of the inclined sidewall 121 of the trapezoidal opening 120 to less than 2 mm. The volume ratio of Cl2, HBr, and O2 can be set to (0.8 to 1.2): (1.8 to 2.2): (0.4 to 0.7), preferably 1:2:0.5.

[0083] As an implementation method, in the second etching step, the plasma bombardment angle is gradually increased, and the bottom of the trench sidewall is bombarded obliquely from bottom to top to widen the bottom of the trench and form the vertical sidewall 110. Correspondingly, in the third etching step, the plasma bombardment angle is gradually increased, and the top of the trench sidewall is bombarded obliquely from bottom to top to form the trapezoidal opening 120.

[0084] In the second etching step, the RF power can be set to 1200-1500W. At this high RF power, the silicon material at the bottom of the trench can be preferentially removed. High RF power combined with fluorine-based gas can quickly remove the silicon material at the bottom of the trench.

[0085] In the third etching step, the RF power can be set to 200-300W. At this low RF power, the bombardment intensity of the plasma is weakened, so that the etching rate of the top of the trench is lower than the etching rate of the bottom, forming a tapered transition.

[0086] The above-mentioned filling step may include the following steps: a first filling step, generating an insulating material by high-density plasma chemical vapor deposition to fill the bottom of the trench; a second filling step, generating an insulating material by fluidized chemical vapor deposition to fill the remaining part of the trench.

[0087] That is, in the initial filling stage, high-density plasma chemical vapor deposition (HDPCVD) is used to produce the insulating material, and the bottom of the trench 100 is filled first to achieve uniform coverage of the bottom of the trench 100. After the trench 100 is filled to a certain height using HDPCVD, the deposition method is changed to fluidized chemical vapor deposition (FCVD) to eliminate the top bottleneck effect by utilizing the fluid properties and achieve uniform coverage of the top of the trench 100. Figure 4 As shown, the area below the dotted line in trench 100 is filled with insulating material using HDPCVD, while the area above the dotted line in trench 100 is filled with insulating material using FCVD. By using different deposition methods to fill the bottom and top of trench 100 in stages, void formation can be avoided, and the uniformity of insulating material coverage of trench 100 can be improved, which helps further reduce the filling defect rate and improve device reliability.

[0088] In the first filling step, the deposition rate is set to 3-6 nm / min, the gas flow rate is set to more than 300 sccm, and the process pressure is set to 5-10 mTorr, so as to achieve uniform coverage of the bottom of the trench 100 .

[0089] In the second filling step, the deposition rate is increased to 10-14 nm / min, the gas flow rate is reduced to 100-150 sccm, and the process pressure is increased to 100-2000 mTorr, so as to achieve uniform coverage of the top of the trench 100 .

[0090] In the first filling step, the filling height of the insulating material is set to 40-60% of the depth of the trench 100, that is, the HDPCVD deposits the insulating material to fill the bottom of the trench 100 to 40-60% of the depth of the trench 100, and then the FCVD deposits the insulating material to fill the remaining trench 100, thereby obtaining a good filling effect.

[0091] Specifically, the above-mentioned substrate can be a silicon substrate, and SiO2 can be used as an insulating material. The thermal expansion coefficient of SiO2 and the silicon substrate has a good match, which can reduce the risk of cracks or voids caused by thermal expansion mismatch in the insulating material filled in the groove 100, which is beneficial to reducing the filling defect rate.

[0092] In the first filling step, a mixed gas of SiH4 and O2 can be used as the process gas, and the volume proportion of SiH4 is set to 70-80%, and the volume proportion of O2 is set to 20-30%. Its high fluidity is beneficial to improving the uniformity of the insulating material's coverage of the bottom of the trench 100.

[0093] Correspondingly, in the second filling step, a mixed gas of SiH4 and O2 can also be used as the process gas, and the volume proportion of SiH4 is set to 70-80%, and the volume proportion of O2 is set to 20-30%. Similarly, it is beneficial to improve the uniformity of the insulating material's coverage of the top of the trench 100.

[0094] In the semiconductor manufacturing process, STI liner oxidation is one of the key steps. It is used to grow a thin oxide layer (such as SiO2) on the surface of the trench 100 before filling the trench 100 with an insulating material (such as HDPCVD SiO2) to repair the surface damage caused by the etching of the trench 100, reduce interface defects, and improve the adhesion and electrical properties of the subsequent insulating material. In related technologies, a SiO2 layer is generated on the surface of the trench through a high-temperature (usually above 900°C) thermal oxidation process, and the thermal stress between the mask and the substrate is buffered to repair the surface damage caused by dry etching (RIE); then, a low-temperature plasma-assisted oxidation technology is used to generate a SiO2 layer at a low temperature (200-400°C) by plasma-enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD) to reduce thermal stress. Afterwards, a two-step chemical mechanical polishing (CMP) is used to control the uniformity of the oxide layer thickness (deviation <5%) to avoid the bird's beak effect. However, this related technology needs to be carried out in a high-temperature environment, which can easily lead to changes in substrate material properties, mismatch in thermal expansion coefficients, lattice defects and leakage problems, affecting device reliability, high thermal budget, and limiting advanced process compatibility.

[0095] Based on this, the present embodiment improves the process method. Before the filling step, the process method provided by the present embodiment further includes: a deposition step of depositing a SiON layer 300 on the inner wall of the trench 100 .

[0096] It should be noted that SiON's material properties (such as adhesion and fluidity) support uniform deposition on the inner walls of the high-aspect-ratio trench 100. This eliminates the need for additional photolithography steps to correct fill defects or adjust topography, omitting the need for chemical mechanical polishing (CMP) and preventing mechanical stress damage to the SiON layer 300. SiON deposition temperatures are lower than those of traditional high-temperature oxidation processes, preventing damage to sensitive structures such as ultra-thin gate oxide layers and strained silicon in advanced processes (e.g., interface defects or uncontrolled dopant diffusion) caused by high-temperature (>900°C) thermal oxidation. This helps maintain substrate material properties and thermal expansion coefficient matching, reduces lattice defects and leakage issues, and minimizes the impact on device reliability. This reduces the thermal budget, is compatible with advanced processes (e.g., 40nm and below), and contributes to cost savings.

[0097] After the filling step, the process method provided in this embodiment may further include an annealing step, in which plasma annealing is performed in a nitrogen environment to improve the density of the shallow trench isolation structure after filling.

[0098] In the annealing step, the RF power can be set to 200-400W, the process temperature can be set to 400-500℃, and the process time can be set to 20-40s. Annealing under these process conditions can increase the density of the isolation material to 2.2g / cm 3 The density of the isolation material after the traditional high temperature annealing process can only reach 2.0g / cm 3 Therefore, by using the annealing process provided in this embodiment to anneal the shallow trench isolation structure, the isolation material can obtain a higher density, and the process temperature is low, which is beneficial to maintaining the substrate material properties and thermal expansion coefficient matching, reducing lattice defects and leakage problems, and having little impact on device reliability, which is beneficial to reducing the thermal budget.

[0099] After the filling step, the process method provided in this embodiment may further include a planarization step, in which excess portions of the top portion of the insulating material are removed by chemical mechanical polishing to ensure that the top portion of the insulating material is flush with the peripheral structure 400 of the trench 100. This can prevent gate short circuits or parasitic capacitance issues in subsequent processes. Specifically, the height difference between the top portion of the insulating material and the peripheral structure 400 of the trench 100 can be less than or equal to 3 mm.

[0100] Using the above process method to fill the trench 100 of the shallow trench isolation structure, a filling defect rate of less than 0.1% can be achieved. This significantly reduces the filling defect rate compared to the 1-5% filling defect rate in traditional processes, thereby enhancing reliability. The shallow trench isolation structure's leakage current can be reduced by more than 50%, and device leakage current can be reduced by more than 20%, achieving an isolation voltage between adjacent devices greater than 20V and reducing leakage current to 1nA / μm.

[0101] Prior to the first etching step, the process method provided in this embodiment further includes a masking step in which a hard mask layer is deposited on the substrate. The hard mask layer has a pattern structure that is compatible with the top of the trapezoidal opening 120. Under the protection of the hard mask layer, the substrate is bombarded to form the trench 100 of the shallow trench isolation structure.

[0102] Figure 7 A process method provided in one embodiment of the present invention includes:

[0103] S201, trench etching and morphology optimization

[0104] A hard mask layer is deposited on a silicon substrate and dry-etched to form a trench 100. By adjusting the ratio of etching gases (SF6, Cl2, HBr, O2) and the radio frequency power, the arc-shaped corner 140 at the bottom of the trench 100 and the trapezoidal opening 120 at the top of the trench 100 are controlled.

[0105] S202, multi-step filling process

[0106] The first filling stage: HDPCVD deposits SiO 2 to fill the bottom of the trench 100 to 40-60% of the depth of the trench 100 ; the second filling stage: FCVD deposits SiO 2 to fill the remaining trench 100 .

[0107] S203, low temperature densification treatment

[0108] Plasma annealing was performed in a nitrogen environment.

[0109] S204, flattening and post-processing

[0110] Chemical mechanical polishing (CMP) removes excess oxide and retains the isolation structure; selective wet etching adjusts the height of the isolation layer, and wet etching makes the top of the insulating material flush with the hard mask layer to avoid gate short circuit or parasitic capacitance problems in subsequent processes.

[0111] The present invention may adopt SAQP (Self-Aligned Quadruple Patterning) and STI etching methods in related technologies.

[0112] Figure 8 A process equipment 200 provided in one embodiment of the present invention includes a process chamber 20, an inlet assembly 20A, an upper electrode assembly 20B, a lower electrode assembly 20C, and a controller ( Figure 8 (not shown). The controller includes at least one processor and at least one memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the method of any one of the above embodiments is implemented.

[0113] For example, the controller can be either a host computer or a slave computer. Specifically, the controller can control the opening of the valve of the gas inlet assembly 20A to introduce the corresponding process gas into the process chamber 20. The controller can also control the opening and closing of the valve of the gas inlet assembly 20A to control the flow rate of the process gas. The controller can also control the exhaust assembly 20D to exhaust the interior of the process chamber 20, thereby controlling the gas pressure within the process chamber 20 and removing reaction byproducts.

[0114] The upper electrode assembly 20B includes an RF coil 21, an upper RF power supply 23, and an upper matcher 25. The controller is further configured to control the upper RF power supply 23 to provide upper electrode power to the RF coil 21 via the upper matcher 25, so that the RF coil 21 excites the process gas inside the process chamber 20 to generate plasma.

[0115] The lower electrode assembly 20C includes a carrier 22, a lower RF power supply 24, and a lower matcher 26. The controller is further configured to control the lower RF power supply 24 to provide lower electrode power to the lower electrode of the carrier 22 via the lower matcher 26, thereby applying an RF bias to the lower electrode of the carrier 22 to attract plasma above the object to be etched and bombard the object to be etched. The wafer carrier 22 may be, for example, an electrostatic chuck, a mechanical chuck, or a vacuum chuck.

[0116] The process equipment 200 of the embodiment of the present application may be an inductively coupled plasma (ICP) process equipment or a capacitively coupled plasma (CCP) process equipment. The embodiment of the present application does not limit the type of the process equipment 200.

[0117] The process equipment provided by the embodiment of the present invention has the same technical features as the process method of the shallow trench isolation structure provided by the above embodiment, and can therefore solve the same technical problems and achieve the same technical effects.

[0118] This embodiment further provides a machine-readable storage medium storing machine-executable instructions. When the machine-executable instructions are called and executed by a processor, the machine-executable instructions prompt the processor to implement the above-mentioned process method for the shallow trench isolation structure.

[0119] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described equipment and devices can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0120] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0121] In the description of the present invention, it should be noted that the terms "upper," "lower," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0122] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A shallow trench isolation structure, characterized in that: including trench and filling structures; The bottom of the groove has a vertical sidewall, the top of the groove is a trapezoidal opening, the trapezoidal opening gradually expands from the outside to the inside, and the inclined sidewall of the trapezoidal opening intersects with the vertical sidewall; the filling structure fills the groove.

2. The shallow trench isolation structure according to claim 1, wherein: The ratio of the width difference between the large and small ends of the trapezoidal opening to the width of the small end is 20 to 30%; And / or, the inclination angle of the inclined side wall is 10° to 30°.

3. The shallow trench isolation structure according to claim 1, wherein: The side wall and the bottom wall of the groove are smoothly transitioned through arc-shaped corners.

4. The shallow trench isolation structure according to claim 3, wherein: The curvature radius of the arc-shaped corner is 5 to 20 nm.

5. The shallow trench isolation structure according to any one of claims 1 to 4, wherein: The inner wall of the trench is covered with a SiON layer.

6. A process method for a shallow trench isolation structure, characterized in that: The process comprises: In a first etching step, a process gas is introduced into the process chamber to generate plasma, which vertically bombards the substrate to form an initial morphology of a trench; wherein the initial morphology of the trench is U-shaped; In the second etching step, the plasma bombardment angle is gradually adjusted to obliquely bombard the bottom of the sidewall of the trench to widen the bottom of the trench and form a vertical sidewall; In a third etching step, the radio frequency power is reduced and the bombardment angle of the plasma is gradually adjusted to obliquely bombard the top of the sidewall of the trench to form a trapezoidal opening; The filling step is to fill the trench with insulating material.

7. The process according to claim 6, characterized in that: The substrate is a silicon substrate; In the first etching step, the process gas includes one or more of fluorine-based gas, Cl2, HBr and O2; and / or, in the second etching step, the process gas includes one or more of fluorine-based gas, Cl2, HBr and O2; and / or, in the third etching step, the process gas includes one or more of fluorine-based gas, Cl2, HBr and O2.

8. The process according to claim 7, characterized in that: In the first etching step, the fluorine-based gas includes SF6, and the volume ratio of SF6 to O2 is 2:1 to 4:1; and / or the volume ratio of Cl2, HBr, and O2 is (0.8 to 1.2): (1.8 to 2.2): (0.4 to 0.7); And / or, in the second etching step, the fluorine-based gas includes SF6, and the volume ratio of SF6 to O2 is 2:1 to 4:1; and / or, the volume ratio of Cl2, HBr, and O2 is (0.8 to 1.2): (1.8 to 2.2): (0.4 to 0.7); And / or, in the third etching step, the fluorine-based gas includes SF6, and the volume ratio of SF6 to O2 is 2:1 to 4:1; and / or, the volume ratio of Cl2, HBr, and O2 is (0.8 to 1.2): (1.8 to 2.2): (0.4 to 0.7).

9. The process according to claim 6, characterized in that: The second etching step includes: gradually increasing the bombardment angle of the plasma, obliquely bombarding the bottom of the sidewall of the trench from bottom to top, so as to widen the bottom of the trench and form the vertical sidewall; And / or, the third etching step includes: gradually increasing the bombardment angle of the plasma, and obliquely bombarding the top of the sidewall of the trench from bottom to top to form the trapezoidal opening.

10. The process according to claim 6, characterized in that: In the second etching step, the radio frequency power is 1200-1500W; And / or, in the third etching step, the radio frequency power is 200-300W.

11. The process according to any one of claims 6 to 10, characterized in that: The filling step comprises: A first filling step is to form an insulating material by high-density plasma chemical vapor deposition to fill the bottom of the trench; In the second filling step, the insulating material is formed by fluidized chemical vapor deposition to fill the remaining portion of the trench.

12. The process according to claim 11, characterized in that: In the first filling step, the deposition rate is 3-6 nm / min, the gas flow rate is above 300 sccm, and the process pressure is 5-10 mTorr; And / or, in the second filling step, the deposition rate is 10-14 nm / min, the gas flow rate is 100-150 sccm, and the process pressure is 10-2000 mTorr.

13. The process according to claim 11, characterized in that: In the first filling step, the filling height of the insulating material is 40-60% of the depth of the trench.

14. The process according to claim 11, characterized in that: The insulating material is SiO2; And / or, the substrate is a silicon substrate.

15. The process according to claim 14, characterized in that: In the first filling step, the process gas includes SiH4 and O2, wherein the volume proportion of SiH4 is 70-80% and the volume proportion of O2 is 20-30%; And / or, in the second filling step, the process gas includes SiH 4 and O 2 , wherein the volume proportion of SiH 4 is 70-80%, and the volume proportion of O 2 is 20-30%.

16. The process according to any one of claims 6 to 10, characterized in that: Before the filling step, the process further comprises: In the deposition step, a SiON layer is deposited on the inner wall of the trench.

17. The process according to any one of claims 6 to 10, characterized in that: After the filling step, the process further comprises: Annealing step: plasma annealing is performed in a nitrogen environment.

18. The process according to claim 17, characterized in that: In the annealing step, the radio frequency power is 200-400 W, the process temperature is 400-500° C., and the process time is 20-40 seconds.

19. The process according to any one of claims 6 to 10, characterized in that: After the filling step, the process further comprises: In the planarization step, excess portions of the top of the insulating material are removed by chemical mechanical polishing, so that the top of the insulating material is flush with the peripheral structure of the trench.

20. The process according to any one of claims 6 to 10, characterized in that: Before the first etching step, the process method further includes: A masking step is performed to deposit a hard mask layer on the substrate.

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