Heterojunction battery and preparation method thereof

Abstract

The invention belongs to the field of heterojunction cells, and particularly discloses a heterojunction cell and a preparation method thereof, which are characterized in that heavily doped amorphous silicon is deposited in a corresponding area of a grid line electrode, so that high parasitic absorption, surface dangling bond and interface state density are reduced, and the open voltage and the efficiency of the heterojunction cell are improved. The main technical scheme of the invention is as follows: according to the heterojunction cell, grooves are formed in corresponding areas of grid line electrodes on the front surface and the back surface of an N-type silicon substrate; arranging an intrinsic amorphous silicon layer; the light doping P-type amorphous silicon layer is arranged on the front intrinsic amorphous silicon layer, the light doping N-type amorphous silicon layer is arranged on the back intrinsic amorphous silicon layer, the heavy doping P-type amorphous silicon layer is arranged in a groove corresponding area on the light doping P-type amorphous silicon layer, the heavy doping N-type amorphous silicon layer is arranged in a groove corresponding area on the light doping N-type amorphous silicon layer, and the light doping N-type amorphous silicon layer is arranged in a groove corresponding area on the light doping N-type amorphous silicon layer. The P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer are respectively provided with a transparent conductive oxide layer, and the grid line electrodes are arranged on the transparent conductive oxide layers. The invention is mainly used for power generation.

Description

Technical Field

[0001] The present invention relates to the technical field of heterojunction batteries, and in particular to a heterojunction battery and a preparation method thereof. Background Art

[0002] Mainstream heterojunction (HJT) cells consist of an N-type silicon substrate, a double-sided intrinsic amorphous silicon layer, a double-sided heavily doped amorphous silicon layer (the back N-type amorphous silicon layer: phosphorus-doped amorphous silicon forms the back surface field, the front P-type amorphous silicon layer: boron-doped amorphous silicon forms the emitter), a double-sided TCO layer, and front and back gate lines. The double-sided heavily doped amorphous silicon layer, together with the double-sided intrinsic amorphous silicon thin film and the silicon wafer substrate, forms the pn heterojunction and back surface field, a key structure for HJT cells to achieve photoelectric conversion and effectively separate photogenerated carriers. However, the high doping concentrations of N-type and P-type amorphous silicon distort the amorphous silicon network structure, resulting in more structural defects such as dangling bonds and microvoids. This leads to increased surface recombination and interface state density, resulting in high parasitic absorption, ultimately reducing the threshold voltage and affecting the efficiency of the HJT cell. Summary of the Invention

[0003] In view of this, an embodiment of the present invention provides a heterojunction battery and a preparation method thereof, which are used to reduce the surface recombination and interface state density of the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer of the heterojunction battery, while reducing the parasitic absorption of the film layer.

[0004] To achieve the above objectives, the present invention mainly provides the following technical solutions: In one aspect, an embodiment of the present invention provides a heterojunction battery, comprising: An N-type silicon substrate, the N-type silicon substrate including a front surface and a back surface, and grooves are respectively provided in areas corresponding to the gate line electrodes on the front surface and the back surface of the N-type silicon substrate; Intrinsic amorphous silicon layer, wherein the front side and the back side of the N-type silicon substrate are respectively provided with intrinsic amorphous silicon layers; A P-type doped amorphous silicon layer, the P-type doped amorphous silicon layer including a lightly doped P-type amorphous silicon layer, the lightly doped P-type amorphous silicon layer being disposed on the front intrinsic amorphous silicon layer; An N-type doped amorphous silicon layer, wherein the N-type doped amorphous silicon layer includes a lightly doped N-type amorphous silicon layer, and the lightly doped N-type amorphous silicon layer is disposed on the intrinsic amorphous silicon layer on the back side; The P-type doped amorphous silicon layer further includes a heavily doped P-type amorphous silicon layer, which is disposed on the lightly doped P-type amorphous silicon layer and is located in a region corresponding to the groove; The N-type doped amorphous silicon layer further includes a heavily doped N-type amorphous silicon layer, which is disposed on the lightly doped N-type amorphous silicon layer and located in a region corresponding to the groove; A transparent conductive oxide layer is provided on the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer; The gate line electrodes are respectively arranged on the transparent conductive oxide layer on the front and back sides.

[0005] The intrinsic amorphous silicon layer covers the entire surface of the front and back sides of the N-type silicon substrate respectively; The lightly doped P-type amorphous silicon layer and the lightly doped N-type amorphous silicon layer cover the entire surface of the front and back intrinsic amorphous silicon layers respectively; The transparent conductive oxide layer covers the entire surface of the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer respectively.

[0006] The thickness of the intrinsic amorphous silicon layer is 1-10 nm.

[0007] The thickness of the lightly doped P-type amorphous silicon layer is the same as that of the heavily doped P-type amorphous silicon layer, and the surface of the P-type doped amorphous silicon layer is flat. The thickness of the lightly doped N-type amorphous silicon layer is the same as that of the heavily doped N-type amorphous silicon layer, and the surface of the N-type doped amorphous silicon layer is flat.

[0008] Wherein, the thickness of the lightly doped P-type amorphous silicon layer is 2 to 15 nm; The thickness of the lightly doped N-type amorphous silicon layer is 2 to 15 nm; The thickness of the heavily doped P-type amorphous silicon layer is 2 to 15 nm; The thickness of the heavily doped N-type amorphous silicon layer is 2 to 15 nm.

[0009] Among them, the doping concentration of the lightly doped P-type amorphous silicon layer is 10 18 cm -3 ~10 19 cm -3 ; The doping concentration of the lightly doped N-type amorphous silicon layer is 10 18 cm -3 ~10 19 cm -3 ; The doping concentration of the heavily doped P-type amorphous silicon layer is 10 20 cm -3 ~10 21 cm -3 ; The doping concentration of the heavily doped N-type amorphous silicon layer is 10 20 cm -3 ~10 21 cm -3 .

[0010] The width of the groove is greater than the width of the gate line electrodes on the front and back surfaces.

[0011] The front and back sides of the N-type silicon substrate both have velvet structures.

[0012] On the other hand, the present invention also provides a method for preparing a heterojunction battery, which is used to prepare any of the above heterojunction batteries, and the preparation method comprises: Providing an N-type silicon substrate, and performing groove processing on the gate line electrode corresponding areas on the front and back sides of the N-type silicon substrate; The grooved N-type silicon substrate is subjected to double-sided pre-cleaning, damage layer removal, texturing and post-cleaning in sequence to form a clean texturing silicon wafer surface; Depositing intrinsic amorphous silicon layers on the front and back sides of the textured N-type silicon substrate; Depositing a lightly doped P-type amorphous silicon layer on the surface of the front intrinsic amorphous silicon layer, and then depositing a lightly doped N-type amorphous silicon layer on the surface of the back intrinsic amorphous silicon layer; Depositing heavily doped P-type amorphous silicon on the surface of the lightly doped P-type amorphous silicon layer, and then depositing heavily doped N-type amorphous silicon on the surface of the lightly doped N-type amorphous silicon layer; Removing the heavily doped P-type amorphous silicon in the non-groove corresponding area on the surface of the lightly doped P-type amorphous silicon layer, and removing the heavily doped N-type amorphous silicon in the non-groove corresponding area on the surface of the lightly doped N-type amorphous silicon layer, to form a P-type doped amorphous silicon layer and an N-type doped amorphous silicon layer; Performing texturing treatment on the surfaces of the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer; Depositing transparent conductive oxide layers on the textured P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer respectively; Gate line electrodes are formed on the transparent conductive oxide layers on the front and back surfaces.

[0013] The step of performing a groove process on the gate line electrode corresponding regions on the front and back sides of the N-type silicon substrate is to perform a groove process on the gate line electrode corresponding regions on the front and back sides of the N-type silicon substrate using a picosecond laser; The steps of removing the heavily doped P-type amorphous silicon in the non-groove corresponding area on the surface of the lightly doped P-type amorphous silicon layer and removing the heavily doped N-type amorphous silicon in the non-groove corresponding area on the surface of the lightly doped N-type amorphous silicon layer are as follows: removing the heavily doped P-type amorphous silicon in the non-groove corresponding area on the surface of the lightly doped P-type amorphous silicon layer and removing the heavily doped N-type amorphous silicon in the non-groove corresponding area on the surface of the lightly doped N-type amorphous silicon layer by using a reactive ion etching device or a chain etching device; The step of depositing transparent conductive oxide layers on the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer after the texturing is as follows: depositing transparent conductive oxide layers on the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer after the texturing by magnetron sputtering or evaporation; The step of preparing the gate line electrodes on the transparent conductive oxide layers on the front and back sides is to prepare the gate line electrodes on the transparent conductive oxide layers on the front and back sides by screen printing equipment.

[0014] Beneficial effects The heterojunction battery and its preparation method proposed in the present invention arrange lightly doped P / N-type amorphous silicon on the front and back intrinsic amorphous silicon, and deposit heavily doped P-type amorphous silicon in the corresponding area of ​​the gate line electrode on the lightly doped P-type amorphous silicon on the front, and deposit heavily doped N-type amorphous silicon in the corresponding area of ​​the gate line electrode on the lightly doped N-type amorphous silicon on the back. While ensuring that the gate line electrodes can normally collect photogenerated carriers to generate current, the high parasitic absorption caused by the heavily doped P / N-type amorphous silicon on the front and back is reduced, the surface dangling bonds and interface state density are reduced, the turn-on voltage is improved, and the efficiency of the heterojunction battery is increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A schematic structural diagram of a heterojunction battery in the first stage of a preparation process of a heterojunction battery provided by an embodiment of the present invention; Figure 2 A schematic structural diagram of a heterojunction battery in the second stage of a preparation process of a heterojunction battery provided by an embodiment of the present invention; Figure 3 A schematic structural diagram of a heterojunction battery in the third stage of a preparation process of a heterojunction battery provided by an embodiment of the present invention; Figure 4 A schematic structural diagram of a heterojunction battery in the fourth stage of a preparation process of a heterojunction battery provided by an embodiment of the present invention; Figure 5 A schematic structural diagram of a heterojunction battery provided by an embodiment of the present invention; Figure 6 A flow chart of a method for preparing a heterojunction battery provided by an embodiment of the present invention; Among them, it includes an N-type silicon substrate-100, a groove-101, an intrinsic amorphous silicon layer-110, a lightly doped P-type amorphous silicon layer-120, a heavily doped P-type amorphous silicon layer-130, a lightly doped N-type amorphous silicon layer-140, a heavily doped N-type amorphous silicon layer-150, a transparent conductive oxide layer-160, and a gate line electrode-170. DETAILED DESCRIPTION

[0016] In order to further illustrate the technical means and effects adopted by the present invention to achieve the predetermined purpose of the invention, the following is a detailed description of the specific implementation method, structure, characteristics and effects of the heterojunction battery proposed in accordance with the present invention in combination with the accompanying drawings and preferred embodiments.

[0017] On the one hand, if Figure 5As shown, an embodiment of the present invention provides a heterojunction battery, the heterojunction battery comprising: An N-type silicon substrate 100 includes a front surface and a back surface, and grooves 101 are respectively provided in the gate line electrode corresponding regions on the front surface and the back surface of the N-type silicon substrate 100; Intrinsic amorphous silicon layer 110 , the front side and the back side of the N-type silicon substrate 100 are respectively provided with an intrinsic amorphous silicon layer 110 ; A P-type doped amorphous silicon layer, the P-type doped amorphous silicon layer includes a lightly doped P-type amorphous silicon layer 120, and the lightly doped P-type amorphous silicon layer 120 is disposed on the front intrinsic amorphous silicon layer 110; An N-type doped amorphous silicon layer, the N-type doped amorphous silicon layer includes a lightly doped N-type amorphous silicon layer 140, and the lightly doped N-type amorphous silicon layer 140 is disposed on the intrinsic amorphous silicon layer 110 on the back side; The P-type doped amorphous silicon layer further includes a heavily doped P-type amorphous silicon layer 130 , which is disposed on the lightly doped P-type amorphous silicon layer 120 and located in a region corresponding to the groove 101 ; The N-type doped amorphous silicon layer further includes a heavily doped N-type amorphous silicon layer 150 . The heavily doped N-type amorphous silicon layer 150 is disposed on the lightly doped N-type amorphous silicon layer 140 and is located in a region corresponding to the groove 101 . A transparent conductive oxide layer 160 is provided on each of the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer; The gate line electrodes 170 are respectively disposed on the transparent conductive oxide layer 160 on the front and back sides.

[0018] The gate line electrode corresponding area refers to a portion of the area including the projection area of ​​the gate line electrode 170 on the N-type silicon substrate 100 in a direction perpendicular to the front or back surface, that is, Figure 5 In the embodiment, the area opened by the groove 101 includes at least the projection area of ​​the gate electrode 170 on the front or back in the vertical direction. Here, the coverage area of ​​the groove 101 can overlap with the projection area of ​​the gate electrode 170, or the width of the groove 101 is greater than the width of the gate electrode 170 on the front and back, so as to ensure that the gate electrode 170 is better aligned with the heavily doped N-type amorphous silicon layer 150 / heavily doped P-type amorphous silicon layer 130 in the groove 101, and to ensure that the contact resistance between the gate electrode 170 and the transparent conductive oxide 160 layer and the heavily doped N-type amorphous silicon layer 150 / heavily doped P-type amorphous silicon layer 130 does not increase.

[0019] For heterojunction cells, the front and back sides adopt a symmetrically distributed structure. For the N-type doped polycrystalline silicon on the back side, if the doping concentration is too high, it will also cause the density of dangling bonds on its surface to increase. At the same time, it will also cause the interface state density between the N-type doped amorphous silicon and the intrinsic amorphous silicon and the N-type silicon substrate 100 to increase. The higher N-type doped amorphous silicon layer will also produce more light absorption that does not generate carriers, increasing parasitic absorption, ultimately reducing the open circuit voltage and causing the cell efficiency to decline. In the embodiment of the present application, a groove 101 is formed in the area of ​​the N-type silicon substrate 100 corresponding to the gate line electrode 170, and heavily doped amorphous silicon is introduced into the areas corresponding to the grooves 101 on the front and back sides. This reduces the interface state density, reduces parasitic absorption, and ensures the open circuit voltage and cell efficiency.

[0020] Both the P-type and N-type doped amorphous silicon layers have a composite two-layer structure. In this application, through the provision of groove 101, the surfaces of the lightly doped P-type and N-type amorphous silicon layers 120 and 140 are recessed. The heavily doped P-type and N-type amorphous silicon layers 130 and 150 are then placed within the recesses by filling them. After the formation of the heavily doped P-type and N-type amorphous silicon layers 130 and 150, the top surfaces of the P-type and N-type doped amorphous silicon layers are flat. Compared to directly placing heavily doped amorphous silicon on the gateline electrodes of the front and back surfaces, where the heavily doped amorphous silicon is protruded, the embedded arrangement of this application avoids the need for additional transparent conducting oxide (TCO) to fill the areas outside the gateline electrodes. Due to the high price of the rare element indium in TCO, this application avoids the problem of increasing the overall battery cost due to increased TCO usage.

[0021] The heterojunction battery proposed in an embodiment of the present invention arranges lightly doped P / N-type amorphous silicon on the front and back intrinsic amorphous silicon, and deposits heavily doped P-type amorphous silicon in the corresponding area of ​​the gate line electrode on the front lightly doped P-type amorphous silicon, and deposits heavily doped N-type amorphous silicon in the corresponding area of ​​the gate line electrode on the back lightly doped N-type amorphous silicon. While ensuring that the gate line electrodes can normally collect photogenerated carriers to generate current, the high parasitic absorption caused by the heavily doped amorphous silicon on the front and back is reduced, the surface dangling bonds and interface state density are reduced, the turn-on voltage is improved, and the efficiency of the heterojunction battery is increased.

[0022] In one embodiment, the intrinsic amorphous silicon layer 110 covers the entire front and back surfaces of the N-type silicon substrate 100. The lightly doped P-type amorphous silicon layer 120 and the lightly doped N-type amorphous silicon layer 140 cover the entire front and back surfaces of the intrinsic amorphous silicon layer 110, respectively. The transparent conductive oxide layer 160 covers the entire surfaces of the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer, respectively.

[0023] In one embodiment, the thickness of the intrinsic amorphous silicon layer 110 is 1 to 10 nm. The ultra-thin intrinsic amorphous silicon layer 110 (ia-Si:H) can minimize light absorption loss while meeting passivation requirements. It also shortens the carrier transport distance, allowing more photons to penetrate the intrinsic amorphous silicon layer 110 for absorption and generation of electron-hole pairs. For example, the thickness can be 1 nm, 3 nm, 5 nm, 8 nm, or 10 nm.

[0024] In one embodiment, the thickness of the lightly doped P-type amorphous silicon layer 120 is the same as that of the heavily doped P-type amorphous silicon layer 130, and the surface of the P-type doped amorphous silicon layer is planar. The thickness of the lightly doped N-type amorphous silicon layer 140 is the same as that of the heavily doped N-type amorphous silicon layer 150, and the surface of the N-type doped amorphous silicon layer is planar, thereby reducing the amount of TCO used.

[0025] In one embodiment, the thickness of the lightly doped P-type amorphous silicon layer 120 is 2 to 15 nm. The thickness of the lightly doped N-type amorphous silicon layer 140 is 2 to 15 nm. The thickness of the heavily doped P-type amorphous silicon layer 130 is 2 to 15 nm. The thickness of the heavily doped N-type amorphous silicon layer 150 is 2 to 15 nm. Controlling the doped layer thickness within this range can minimize optical losses, optimize carrier transport, reduce recombination losses within the intrinsic amorphous silicon layer 110, and reduce contact resistance while meeting high doping concentration requirements. For example, the above thicknesses can be 2 nm, 5 nm, 8 nm, 10 nm, 12 nm, or 15 nm.

[0026] In one embodiment, the doping concentration of the lightly doped P-type amorphous silicon layer 120 is 10 18 cm -3 ~10 19 cm -3 The doping concentration of the lightly doped N-type amorphous silicon layer 140 is 10 18 cm -3 ~10 19 cm -3 Then ensure the low interface state density between the non-gate line region doped amorphous silicon and intrinsic amorphous silicon and the intrinsic amorphous silicon layer 110, reduce parasitic absorption, and ensure open circuit voltage and battery efficiency. 18 cm -3 , 20 18 cm -3 , 50 18 cm -3 , 80 18 cm -3 , 10 19 cm -3 .

[0027] The doping concentration of the heavily doped P-type amorphous silicon layer 130 is 1020 cm -3 ~10 21 cm -3 The doping concentration of the heavily doped N-type amorphous silicon layer 150 is 10 20 cm -3 ~10 21 cm -3 This ensures that the lateral resistance of the amorphous silicon layer is reduced, the carrier transport to the gate line area is accelerated, and the contact with the TCO is optimized, thereby reducing the contact resistance. For example, the heavy doping concentration can be 10 20 cm -3 , 20 20 cm -3 , 50 20 cm -3 , 80 20 cm -3 , 10 21 cm -3 .

[0028] In one embodiment, both the front and back surfaces of the N-type silicon substrate 100 have a velvet structure, ensuring a full-surface velvet structure and increasing light absorption. In addition, in some embodiments, the surfaces of the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer have a velvet structure, further increasing light absorption.

[0029] On the other hand, Figure 1-6 As shown, the present invention also provides a method for preparing a heterojunction battery, which is used to prepare any of the above heterojunction batteries, and the preparation method comprises: S1. Provide an N-type silicon substrate 100 and perform groove processing on the gate line electrode corresponding areas on the front and back sides of the N-type silicon substrate 100.

[0030] For example, the gate electrode regions on the front and back sides of the N-type silicon substrate 100 are grooved using a picosecond laser to form grooves 101. The grooves 101 may overlap with the projection of the gate electrode 700 or may be wider than the projection of the gate electrode 700.

[0031] S2. The grooved N-type silicon substrate 100 is subjected to double-sided pre-cleaning, damage layer removal, texturing and post-cleaning in sequence to form a clean texturing silicon wafer surface.

[0032] To achieve increased light absorption. Figure 1 The structure shown.

[0033] S3 , depositing an intrinsic amorphous silicon layer 110 on the front and back sides of the textured N-type silicon substrate 100 .

[0034] For example, the intrinsic amorphous silicon layer 110 is deposited by PECVD equipment to form Figure 2 The structure shown.

[0035] S4 , depositing a lightly doped P-type amorphous silicon layer 120 on the surface of the front intrinsic amorphous silicon layer 110 , and then depositing a lightly doped N-type amorphous silicon layer 140 on the surface of the back intrinsic amorphous silicon layer 110 .

[0036] For example, a lightly doped P-type amorphous silicon layer 120 and a lightly doped N-type amorphous silicon layer 140 are deposited by PECVD equipment to form Figure 3 At this time, the lightly doped P-type amorphous silicon layer 120 and the lightly doped N-type amorphous silicon layer 140 are in a recessed state at the groove 101 according to the structure of the N-type silicon substrate 100 .

[0037] S5 , depositing heavily doped P-type amorphous silicon on the surface of the lightly doped P-type amorphous silicon layer 120 , and then depositing heavily doped N-type amorphous silicon on the surface of the lightly doped N-type amorphous silicon layer 140 .

[0038] For example, heavily doped P-type amorphous silicon and heavily doped N-type amorphous silicon are deposited using PECVD equipment. After doping, the heavily doped P-type amorphous silicon and heavily doped N-type amorphous silicon are not only located at positions corresponding to the grooves 101, but also overflow to areas not corresponding to the grooves 101.

[0039] S6. Remove the heavily doped P-type amorphous silicon in the area corresponding to the non-groove 101 on the surface of the lightly doped P-type amorphous silicon layer 120, and remove the heavily doped N-type amorphous silicon in the area corresponding to the non-groove 101 on the surface of the lightly doped N-type amorphous silicon layer 140, to form a P-type doped amorphous silicon layer and an N-type doped amorphous silicon layer.

[0040] For example, a reactive ion etching device or a chain etching device is used to remove the heavily doped P-type amorphous silicon in the non-groove 101 corresponding area on the surface of the lightly doped P-type amorphous silicon layer 120, and to remove the heavily doped N-type amorphous silicon in the non-groove 101 corresponding area on the surface of the lightly doped N-type amorphous silicon layer 140. A heavily doped P-type amorphous silicon layer 130 and a heavily doped N-type amorphous silicon layer 150 are formed only in the concave area corresponding to the groove 101, that is, Figure 4 The structure shown.

[0041] S7. Performing texturing treatment on the surfaces of the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer.

[0042] Compared with the method of directly patterning the non-gate line electrode corresponding area through reactive ion etching equipment, removing the heavily doped P-type amorphous silicon in the non-gate line electrode corresponding area, and then directly depositing TCO, this embodiment removes the heavily doped P-type amorphous silicon and heavily doped N-type amorphous silicon corresponding to the front and back non-grooves 101 through reactive ion etching equipment or chain etching equipment, and then texturizes the front and back sides of the battery, and then deposits TCO and screen-printed gate line electrodes 700, avoiding the risk that the velvet structure may have been damaged, ensuring the full-surface velvet structure, and increasing light absorption.

[0043] S8. Depositing a transparent conductive oxide layer 160 on the textured P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer respectively.

[0044] For example, the transparent conductive oxide layer 160 is deposited on the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer after texturing by magnetron sputtering or evaporation.

[0045] S9. Forming gate line electrodes 170 on the transparent conductive oxide layer 160 on the front and back surfaces.

[0046] For example, the gate line electrodes 170 are prepared on the transparent conductive oxide layer 160 on the front and back surfaces by screen printing equipment. The gate line electrodes 170 are metal gate line electrodes.

[0047] The preparation method of the heterojunction battery proposed in an embodiment of the present invention arranges lightly doped P / N-type amorphous silicon on the front and back intrinsic amorphous silicon, and deposits heavily doped P-type amorphous silicon in the corresponding area of ​​the gate line electrode on the lightly doped P-type amorphous silicon on the front, and deposits heavily doped N-type amorphous silicon in the corresponding area of ​​the gate line electrode on the lightly doped N-type amorphous silicon on the back. While ensuring that the gate line electrodes can normally collect photogenerated carriers to generate current, the high parasitic absorption caused by the heavily doped amorphous silicon on the front and back is reduced, the surface dangling bonds and interface state density are reduced, the turn-on voltage is improved, and the efficiency of the heterojunction battery is increased.

[0048] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A heterojunction battery, characterized in that: include: An N-type silicon substrate, the N-type silicon substrate comprising a front surface and a back surface, wherein the front surface and the back surface of the N-type silicon substrate are respectively provided with grooves in regions corresponding to the gate line electrodes; An intrinsic amorphous silicon layer, wherein the front side and the back side of the N-type silicon substrate are respectively provided with the intrinsic amorphous silicon layer; A P-type doped amorphous silicon layer, wherein the P-type doped amorphous silicon layer includes a lightly doped P-type amorphous silicon layer, and the lightly doped P-type amorphous silicon layer is disposed on the intrinsic amorphous silicon layer on the front side; An N-type doped amorphous silicon layer, wherein the N-type doped amorphous silicon layer includes a lightly doped N-type amorphous silicon layer, and the lightly doped N-type amorphous silicon layer is disposed on the intrinsic amorphous silicon layer on the back side; The P-type doped amorphous silicon layer further includes a heavily doped P-type amorphous silicon layer, and the heavily doped P-type amorphous silicon layer is disposed on the lightly doped P-type amorphous silicon layer and is located in a region corresponding to the groove; The N-type doped amorphous silicon layer further includes a heavily doped N-type amorphous silicon layer, and the heavily doped N-type amorphous silicon layer is disposed on the lightly doped N-type amorphous silicon layer and located in a region corresponding to the groove; a transparent conductive oxide layer, wherein the transparent conductive oxide layer is respectively disposed on the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer; Gate line electrodes are respectively arranged on the transparent conductive oxide layer on the front and back sides.

2. The heterojunction battery according to claim 1, characterized in that The intrinsic amorphous silicon layer covers the entire surface of the front and back sides of the N-type silicon substrate respectively; The lightly doped P-type amorphous silicon layer and the lightly doped N-type amorphous silicon layer cover the entire surface of the front and back sides of the intrinsic amorphous silicon layer respectively; The transparent conductive oxide layer covers the entire surface of the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer respectively.

3. The heterojunction battery according to claim 1, characterized in that The thickness of the intrinsic amorphous silicon layer is 1-10 nm.

4. The heterojunction battery according to claim 1, characterized in that The thickness of the lightly doped P-type amorphous silicon layer is the same as the thickness of the heavily doped P-type amorphous silicon layer, and the surface of the P-type doped amorphous silicon layer is flat; The thickness of the lightly doped N-type amorphous silicon layer is the same as that of the heavily doped N-type amorphous silicon layer, and the surface of the N-type doped amorphous silicon layer is flat.

5. The heterojunction battery according to claim 1, characterized in that: The thickness of the lightly doped P-type amorphous silicon layer is 2 to 15 nm; The thickness of the lightly doped N-type amorphous silicon layer is 2 to 15 nm; The thickness of the heavily doped P-type amorphous silicon layer is 2 to 15 nm; The thickness of the heavily doped N-type amorphous silicon layer is 2-15 nm.

6. The heterojunction battery according to claim 1, characterized in that: The doping concentration of the lightly doped P-type amorphous silicon layer is 10 18 cm -3 ~10 19 cm -3 ; The doping concentration of the lightly doped N-type amorphous silicon layer is 10 18 cm -3 ~10 19 cm -3 ; The doping concentration of the heavily doped P-type amorphous silicon layer is 10 20 cm -3 ~10 21 cm -3 ; The doping concentration of the heavily doped N-type amorphous silicon layer is 10 20 cm -3 ~10 21 cm -3 .

7. The heterojunction battery according to claim 1, characterized in that: The width of the groove is greater than the width of the gate line electrode.

8. The heterojunction battery according to claim 1, characterized in that: The front and back surfaces of the N-type silicon substrate both have suede structures.

9. A method for preparing a heterojunction battery, characterized in that: For preparing a heterojunction battery as claimed in any one of claims 1 to 8, the preparation method comprises: Providing an N-type silicon substrate, and performing groove processing on the gate line electrode corresponding areas on the front and back sides of the N-type silicon substrate; The grooved N-type silicon substrate is subjected to double-sided pre-cleaning, damage layer removal, texturing and post-cleaning in sequence to form a clean texturing silicon wafer surface; Depositing intrinsic amorphous silicon layers on the front and back sides of the texturized N-type silicon substrate; Depositing a lightly doped P-type amorphous silicon layer on the surface of the front intrinsic amorphous silicon layer, and then depositing a lightly doped N-type amorphous silicon layer on the surface of the back intrinsic amorphous silicon layer; Depositing heavily doped P-type amorphous silicon on the surface of the lightly doped P-type amorphous silicon layer, and then depositing heavily doped N-type amorphous silicon on the surface of the lightly doped N-type amorphous silicon layer; removing the heavily doped P-type amorphous silicon in the non-groove corresponding area on the surface of the lightly doped P-type amorphous silicon layer, and removing the heavily doped N-type amorphous silicon in the non-groove corresponding area on the surface of the lightly doped N-type amorphous silicon layer, to form a P-type doped amorphous silicon layer and an N-type doped amorphous silicon layer; performing a texturing process on the surfaces of the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer; Depositing transparent conductive oxide layers on the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer after texturing respectively; Gate line electrodes are formed on the transparent conductive oxide layer on the front and back surfaces.

10. The method for preparing a heterojunction battery according to claim 9, wherein: The step of performing a groove process on the gate line electrode corresponding regions on the front and back sides of the N-type silicon substrate comprises performing a groove process on the gate line electrode corresponding regions on the front and back sides of the N-type silicon substrate using a picosecond laser; The steps of removing the heavily doped P-type amorphous silicon in the non-groove corresponding area on the surface of the lightly doped P-type amorphous silicon layer, and removing the heavily doped N-type amorphous silicon in the non-groove corresponding area on the surface of the lightly doped N-type amorphous silicon layer are as follows: removing the heavily doped P-type amorphous silicon in the non-groove corresponding area on the surface of the lightly doped P-type amorphous silicon layer, and removing the heavily doped N-type amorphous silicon in the non-groove corresponding area on the surface of the lightly doped N-type amorphous silicon layer respectively by using a reactive ion etching device or a chain etching device; The step of depositing transparent conductive oxide layers on the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer after texturing is respectively depositing transparent conductive oxide layers on the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer after texturing by magnetron sputtering or evaporation; The step of preparing gate line electrodes on the transparent conductive oxide layer on the front and back sides is to prepare gate line electrodes on the transparent conductive oxide layer on the front and back sides by screen printing equipment.

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