Large-size N-type silicon wafer for BC battery, preparation method of large-size N-type silicon wafer and BC battery

Abstract

The invention relates to the technical field of photovoltaic cells, in particular to a large-size N-type silicon wafer for a BC cell, a preparation method of the large-size N-type silicon wafer and the BC cell. The size of the large-size N-type silicon wafer is larger than or equal to 230 mm * 230 mm, the thickness of the large-size N-type silicon wafer is 90-130 microns, the edge of the large-size N-type silicon wafer is an arc chamfer, and the edge is wrapped with a SiNx layer; the large-size N-type silicon wafer comprises a central area and an edge area surrounding the central area, and the content of doped element antimony in the edge area is smaller than or equal to 1 * 10 < 15 > atoms / cm < 3 >. And the content of the doped element antimony in the central region is 1 * 10 < 16 >-5 * 10 < 16 > atoms / cm < 3 >. By arranging the edge arc chamfer, wrapping the SiNx layer and performing edge low doping, the mechanical strength can be ensured, the fragment rate can be reduced, meanwhile, edge carrier recombination can be reduced, the open-circuit voltage can be improved, and the power output of the battery can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of photovoltaic cells, and in particular to a large-size N-type silicon wafer for a BC cell, a preparation method thereof, and a BC cell. Background Art

[0002] Back-contact (BC) solar cells, or BC cells for short, are a type of high-efficiency solar cell that places all electrodes on the back of the cell to reduce shading losses on the front. Currently, mainstream BC cell technologies include interdigitated back contact (IBC) and heterojunction back contact (HBC), with the core material typically being N-type silicon wafers.

[0003] Conventional N-type silicon wafers are one of the core materials for photovoltaic cells. They are formed into N-type semiconductors by doping with elements such as phosphorus (P) or arsenic (As). They have advantages such as long minority carrier lifetime and low light-induced degradation (LID). In existing technologies, the typical characteristics of N-type silicon wafers are as follows: Structural design: Using single crystal silicon or polycrystalline silicon substrate, prepared by the Czochralski (CZ) method or the melting zone (FZ) method, the thickness is usually 150~200μm, and the size is mainly M2 (156.75mm×156.75mm) or G1 (158.75mm×158.75mm).

[0004] Doping process: An N-type layer is formed by phosphorus diffusion or ion implantation, and the surface is covered with a passivation layer.

[0005] Battery application: Mainly used for high-efficiency battery structures such as TOPCon and HJT, with the highest conversion efficiency in the laboratory being approximately 24%~25%.

[0006] However, the N-type silicon wafers currently used in BC cells have the following limitations: The mainstream wafer size is 182mm×182mm or 210mm×210mm, with a thickness of approximately 160-180μm. Increasing the size leads to insufficient mechanical strength. As the wafer size increases (e.g., G12, 210mm×210mm), thinning (<150μm) can lead to increased fragmentation, making larger wafer sizes difficult.

[0007] In view of this, the present invention is proposed. Summary of the Invention

[0008] The first purpose of the present invention is to provide a large-size N-type silicon wafer for BC batteries. The present invention has developed an N-type silicon wafer with a thickness of 90-130 μm and a size of ≥230 mm × 230 mm. xLow antimony doping at the edges (the antimony doping content at the edge is lower than that at the center) reduces edge carrier recombination, increases open-circuit voltage (Voc), and boosts battery power output while maintaining mechanical strength and reducing fragmentation. This solves the problem of increased fragmentation caused by insufficient mechanical strength when increasing the size of N-type silicon wafers used in BC cells.

[0009] The second object of the present invention is to provide a method for preparing large-size N-type silicon wafers for BC batteries.

[0010] A third object of the present invention is to provide a BC battery.

[0011] In order to achieve the above-mentioned purpose of the present invention, the following technical solutions are adopted: The present invention first provides a large-size N-type silicon wafer for BC batteries, wherein the size of the large-size N-type silicon wafer is ≥230mm×230mm, the thickness of the large-size N-type silicon wafer is 90-130μm, the edge of the large-size N-type silicon wafer is an arc chamfer, and the edge of the large-size N-type silicon wafer is wrapped with SiN x The large-size N-type silicon wafer includes a central region and an edge region surrounding the central region, wherein the content of the doping element antimony in the edge region is ≤1×10 15 atoms / cm 3 The content of the doping element antimony in the central region is 1×10 16 ~5×10 16 atoms / cm 3 .

[0012] Furthermore, the radius of the arc chamfer is 0.3-1.5 mm.

[0013] Furthermore, the width of the edge area is 2-4 mm.

[0014] Furthermore, the SiN x The thickness of the layer is 80~200nm.

[0015] Furthermore, the resistivity of the edge region is ≥10Ω·cm, and the resistivity of the central region is 0.5-3Ω·cm.

[0016] Furthermore, the radial resistivity fluctuation of the large-size N-type silicon wafer is less than 5%.

[0017] Furthermore, the front side of the large-size N-type silicon wafer has a front side passivation layer, and the front side passivation layer comprises Al2O3 / SiN x stack; the Al2O3 / SiN x The thickness of the Al2O3 layer in the stack is 8-10 nm.x SiN in the stack x The thickness of the layer is 60~80nm.

[0018] Furthermore, the back side of the large-size N-type silicon wafer has a back side passivation layer, and the back side passivation layer comprises SiO2 / polysilicon / SiN x stack, the SiO2 / polysilicon / SiN x The thickness of the SiO2 layer in the stack is 1.9~2.1nm, and the SiO2 / polysilicon / SiN x The thickness of the polysilicon layer in the stack is 149-151 nm, and the SiO2 / polysilicon / SiN x SiN in the stack x The thickness of the layer is 99-101 nm; the back passivation layer also has a selective emitter, and the phosphorus concentration in the selective emitter is ≥1×10 20 atoms / cm 3 ; A staggered point contact back electrode is also provided on the back passivation layer, and the material of the staggered point contact back electrode is copper-silver plating, and the copper-silver plating includes a copper layer and a silver layer covering the copper layer, wherein the thickness of the copper layer is 19~21μm, and the thickness of the silver layer is 0.8~1μm; the total area of ​​the copper-silver plating accounts for ≤5% of the area of ​​the back passivation layer.

[0019] The present invention further provides a method for preparing the above-mentioned large-size N-type silicon wafer for BC batteries, comprising the following steps: (a) preparing single-crystalline silicon by a Czochralski method, wherein the doping element includes antimony, to obtain a single-crystalline silicon rod; (b) cutting the single-crystalline silicon rod into slices, and performing surface treatment to obtain a silicon wafer; (c) forming a front passivation layer and a back passivation layer on the front and back of the silicon wafer, respectively; (d) selectively laser doping the back passivation layer to form a selective emitter; (e) forming an arc chamfer on the edge of the silicon wafer by laser, and then wrapping SiN on the edge by plasma enhanced chemical vapor deposition. x layer.

[0020] Furthermore, in step (a), the Czochralski method includes a magnetic field-assisted Czochralski method, and the axial temperature gradient of the magnetic field-assisted Czochralski method is 10-15°C / cm.

[0021] Furthermore, in step (a), during the process of preparing single crystal silicon by the Czochralski method, the growth rate of the single crystal silicon is 1.2-1.5 mm / min.

[0022] Furthermore, in step (a), during the process of preparing single crystal silicon by the Czochralski method, the pulling speed is 1.3-1.8 mm / min.

[0023] Furthermore, in step (a), during the process of preparing single crystal silicon by the Czochralski method, the flow rate of argon gas is 80-100 L / min.

[0024] Furthermore, in step (a), during the Czochralski method for preparing single-crystalline silicon, a doping gas mask technique is employed, with SbH3 used as a dopant, to control the antimony doping concentrations in the edge region and the central region, respectively, and the SbH3 gas flow rate is adjusted through resistivity monitoring and / or photoluminescence detection; wherein the resistivity monitoring method comprises: using a four-point probe scanner to control the radial resistivity fluctuation of the single-crystalline silicon to be less than 5%; and the photoluminescence detection method comprises: using online PL imaging to identify low-lifetime regions caused by antimony aggregation, with a threshold value controlled to be less than 500 μs.

[0025] Furthermore, in step (a), during the process of preparing single crystal silicon by the Czochralski method, low temperature ion implantation of He + To form a nanocavity layer; He + The dose is 1×10 14 ~1.01×10 14 ions / cm 2 , energy is 50~60keV.

[0026] Furthermore, in step (b), the diamond wire used for cutting includes a resin bonded diamond wire, and the wire diameter of the diamond wire is 50-80 μm.

[0027] Furthermore, in step (b), the cutting speed is 1.2-1.5 m / s.

[0028] Furthermore, in step (b), the coolant used for cutting includes polyethylene glycol, and the coolant also contains silicon carbide abrasive and / or nano-SiO2 particles, wherein the median particle size of the silicon carbide abrasive is 3-5 μm, and the median particle size of the nano-SiO2 particles is 80-100 nm.

[0029] Furthermore, in step (b), the surface treatment method includes: polishing, chemical thinning and texturing in sequence; wherein the polishing method includes: double-sided chemical mechanical polishing, and the polishing is performed to a surface roughness Ra <0.5nm; the chemical thinning method includes: using a mixed acid solution of HF and HNO3 to isotropically corrode both sides to remove the cutting damage layer; the texturing method includes: using laser etching on the front side to form an inverted pyramid texturing structure, wherein the height of the inverted pyramid texturing structure is 23~25μm.

[0030] Furthermore, in step (c), the front passivation layer comprises Al2O3 / SiN x The back passivation layer includes SiO2 / polysilicon / SiNx Overlay.

[0031] Furthermore, in step (d), the selective laser doping method includes: selectively ablating a portion of the back passivation layer by pulse laser, and doping phosphorus to form N + Local heavily doped area; wherein the wavelength of the pulsed laser is 530~540nm, and the energy density of the pulsed laser is 2.8~3J / cm 2 , the scanning speed of the pulse laser is 5~6m / s.

[0032] Furthermore, in step (e), during the plasma enhanced chemical vapor deposition process, the zone pressure is controlled to be 0.1-0.3 bar.

[0033] Furthermore, after step (e), the method further includes step (f) of preparing an interlaced point contact back electrode: using an ultraviolet laser to create a plurality of interlaced grooves on the back of the silicon wafer, followed by copper electroplating and silver coating, to form a copper-plated silver electrode material. The ultraviolet laser has a wavelength of 350-360 nm, a pulse width of 8-10 ps, ​​and an energy of 0.8-1 μJ. The width of each groove is 20-32 μm, the length-to-width ratio of each groove is 2:1, and the distance between two adjacent grooves is 1.4-1.6 mm. The electroplating solution used for copper electroplating is a mixture of CuSO4, H2SO4 and additives; the concentration of CuSO4 in the mixture of CuSO4, H2SO4 and additives is 150-250 g / L, and the concentration of H2SO4 in the mixture of CuSO4, H2SO4 and additives is 50-100 g / L; the additives include PEG and a chlorine source, the chlorine source includes HCl and / or NaCl, the concentration of PEG in the mixture of CuSO4, H2SO4 and additives is 0.05-0.5 g / L, and the Cl in the mixture of CuSO4, H2SO4 and additives is 0. - The concentration of copper is 0.03~0.1g / L. The current density of the copper electroplating is 1.9~2.1A / dm 2 The copper electroplating time is 15 to 15.5 minutes. The silver covering method includes: using an immersion plating method to immerse the silicon wafer in a mixed solution of AgNO3 and a complexing agent to perform a replacement reaction; the complexing agent includes ammonia water, the concentration of AgNO3 in the mixed solution of AgNO3 and the complexing agent is 0.3 to 0.35 mol / L, and the NH3 in the mixed solution of AgNO3 and the complexing agent reacts with AgNO3 to form a silver coating. + The molar ratio is ≥2:1.

[0034] The present invention also provides a BC battery, comprising the above-mentioned large-size N-type silicon wafer for BC batteries.

[0035] Compared with the prior art, the present invention has the following beneficial effects: (1) The present invention develops an N-type silicon wafer with a thickness of 90-130 μm and a size of ≥230 mm × 230 mm, by setting an edge arc chamfer and wrapping SiN x The antimony doping content in the edge region is less than that in the center region, which can reduce the edge carrier recombination, increase the open circuit voltage (Voc), and improve the battery power output while ensuring mechanical strength and reducing the fragmentation rate.

[0036] (2) The present invention reduces the production cost of N-type silicon wafers, wherein the silicon wafer size increases by about 12%, the silicon wafer area increases by about 80%, the silicon material cost per unit power is diluted, the module power increases by 10% to 15%, the single cell power increases to 8.5W (the traditional 210mm silicon wafer is 7.2W), and the unit power cost is reduced by 18% to 22%.

[0037] (3) The present invention sets the front passivation layer to be Al2O3 / SiN x The surface recombination rate can be reduced to below 20cm / s, where Al2O3 / SiN is set on the front side. x stacking, fixed negative charge density>1×10 12 cm -2 ; SiO2 / polysilicon / SiN is set on the back x The stacked layers can achieve tunneling passivation contact (TOPCon). In addition, by providing a front passivation layer of a specific composition and thickness and a back passivation layer of a specific composition and thickness, the present invention can reduce the surface recombination rate to below 10 cm / s.

[0038] (4) The present invention designs staggered point contact electrodes on the back side, with the contact area accounting for ≤5%, which can reduce metal composite.

[0039] (5) The present invention adopts a transverse magnetic field to suppress melt convection, which can reduce the stripe defects caused by antimony doping; by controlling the axial temperature gradient of the magnetic field-assisted vertical pulling method and the growth rate of single crystal silicon, the longitudinal resistivity uniformity of ±1.8% can be achieved; by reducing the crystal pulling speed, the radial segregation of antimony can be reduced; by increasing the argon flow rate, the doping fluctuation caused by antimony volatilization can be suppressed; resistivity monitoring can improve the resistivity uniformity; photoluminescence detection can improve the antimony doping uniformity.

[0040] (6) The present invention can reduce the saw mark depth (<8μm) by controlling the material, wire diameter and cutting speed of the diamond wire; by controlling the wire diameter of the diamond wire and the composition of the coolant, the cutting loss can be controlled to ≤90μm, the cutting loss is reduced by 20%, and the overall production cost is reduced by 15%; and a low-cost cutting and polishing (surface treatment) process is adopted to increase the silicon wafer yield to more than 98%. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0042] Figure 1 A top view of a large-size N-type silicon wafer provided by the present invention; Figure 2 This is a schematic diagram of the layer structure of the large-size N-type silicon wafer provided by the present invention. DETAILED DESCRIPTION

[0043] The technical scheme of the present invention will be clearly and completely described below in conjunction with the accompanying drawings and specific embodiments, but it will be understood by those skilled in the art that the following described embodiments are part of embodiments of the present invention, rather than all embodiments, and are only used to illustrate the present invention, and should not be considered as limiting the scope of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative work are within the scope of protection of the present invention. Those who do not specify specific conditions in the embodiments are carried out according to normal conditions or the conditions recommended by the manufacturer. Those whose reagents or instruments are not specified by the manufacturer are conventional products that can be purchased commercially.

[0044] In the first aspect, the present invention provides a large-size N-type silicon wafer for BC cells (back contact (BC) solar cells), aiming to improve cell conversion efficiency, reduce production costs, and enhance the mechanical properties of the silicon wafer. The large-size N-type silicon wafer has a size of ≥230mm×230mm (i.e., length×width), a thickness of 90-130μm, and an arc chamfered edge. The edge of the large-size N-type silicon wafer is coated with SiN x layer.

[0045] The size of the large-size N-type silicon wafer is, for example, 230 mm×230 mm (length×width), and the thickness of the large-size N-type silicon wafer can be, for example, 90 μm, 100 μm, 110 μm, 120 μm, or 130 μm.

[0046] The large-size N-type silicon wafer includes a central region and an edge region surrounding the central region, wherein the content of the doping element antimony in the edge region is less than the content of the doping element antimony in the central region. Specifically, the content of the doping element antimony in the edge region is ≤1×10 15 atoms / cm 3 The content of the doping element antimony in the central region is 1×10 16 ~5×10 16 atoms / cm 3 .

[0047] The content of the doping element antimony in the edge region can be, for example, 1×10 15 atoms / cm 3 , 9×10 14 atoms / cm 3 , 7×10 14 atoms / cm 3 , 5×10 14 atoms / cm 3 , 3×10 14 atoms / cm 3 or 1×10 14 atoms / cm 3 .

[0048] The content of doping element antimony in the central region can also be 2×10 16 atoms / cm 3 , 3×10 16 atoms / cm 3 or 4×10 16 atoms / cm 3 .

[0049] The top view of the large-size N-type silicon wafer provided by the present invention is shown in FIG. Figure 1 See Figure 1 As shown, the edge area of ​​the large-size N-type silicon wafer is provided with SiN x layer, and the four inner corners of the edge area are arc corners.

[0050] The present invention has developed an N-type silicon wafer with a thickness of 90-130 μm and a size of ≥230 mm×230 mm, by setting an edge arc chamfer and wrapping SiN x The antimony doping content in the edge region is less than that in the center region, which can reduce the edge carrier recombination, increase the open circuit voltage (Voc), and improve the battery power output while ensuring mechanical strength and reducing the fragmentation rate.

[0051] The present invention reduces the production cost of N-type silicon wafers, with the silicon wafer size increased by approximately 12% and the silicon wafer area increased by approximately 80%, thereby diluting the silicon material cost per unit power, increasing the module power by 10% to 15%, and the power of a single cell increased to 8.5W (compared to 7.2W for traditional 210mm silicon wafers).

[0052] In some specific embodiments, the fragmentation rate of the large-size N-type silicon wafer provided by the present invention (230mm 2 ) <0.5%, preferably <0.05% (automatic line transmission), where the test method is vibration test (5~50Hz, 2h).

[0053] In some specific embodiments, the mechanical strength of the large-size N-type silicon wafer provided by the present invention satisfies a four-point bending strength of ≥550 MPa (test method: ISO 14704 standard).

[0054] In some specific embodiments, the radius of the arc chamfer is 0.3-1.5 mm, for example, 0.5 mm, 0.8 mm, 1.0 mm, 1.2 mm, or 1.4 mm. This helps reduce edge fragmentation (less than 2%), improve passivation film uniformity (deviation less than 10%), increase laser grooving yield (95%-98%), reduce module DH1000 degradation (1.5%-2.0%), and reduce cell Isc loss (0.2%-0.5%).

[0055] In some specific embodiments, the width of the edge region is 2-4 mm, for example, 2.3 mm, 2.5 mm, 2.8 mm, 3.0 mm, 3.3 mm, 3.5 mm or 3.8 mm. This is beneficial to improve the laser grooving yield (95%-98%) and reduce the edge recombination current density (<5 nA / cm 2 ), improve the uniformity of the passivation film (deviation is less than 10%), reduce the component hidden crack rate (EL test) (<1.5%), and reduce the thin film (130μm) fragmentation rate (4%~6%).

[0056] In some specific embodiments, the SiN x The thickness of the layer is 80-200nm, such as 100nm, 120nm, 150nm, 160nm or 180nm. This helps to reduce the average reflectivity (400-1100nm) (<3%), increase the minority carrier lifetime (1.2-1.5ms), improve Voc, reduce PID decay (96h) (<2%), and avoid silicon wafer warping.

[0057] In some specific embodiments, the resistivity of the edge region is ≥10Ω·cm, such as 11Ω·cm, 12Ω·cm, 13Ω·cm, 14Ω·cm, 15Ω·cm, 16Ω·cm, 18Ω·cm or 20Ω·cm; the resistivity of the central region is 0.5-3Ω·cm, such as 0.6Ω·cm, 0.8Ω·cm, 1Ω·cm, 1.3Ω·cm, 1.5Ω·cm, 1.8Ω·cm, 2Ω·cm, 2.3Ω·cm or 2.6Ω·cm. This is beneficial to reduce the edge leakage current density (<2nA / cm 2 ), reduce Voc loss (<5mV), reduce laser contact resistance fluctuation (±5%), reduce component hidden crack rate (EL test) (<1.5%), and reduce thin film (130μm) fragmentation rate (2%~4%).

[0058] In some specific embodiments, the radial resistivity fluctuation of the large-size N-type silicon wafer is less than 5%. Low radial resistivity fluctuation means improved resistivity uniformity.

[0059] In some specific embodiments, the front side of the large-size N-type silicon wafer has a front side passivation layer, and the front side passivation layer comprises Al2O3 / SiN x The present invention sets the front passivation layer to be Al2O3 / SiN x The surface recombination rate can be reduced to below 20 cm / s.

[0060] Furthermore, the Al2O3 / SiN x The thickness of the Al2O3 layer in the stack is 8-10 nm, for example 9 nm; the Al2O3 / SiN x SiN in the stack x The thickness of the layer is 60-80 nm, for example 65 nm, 70 nm or 75 nm.

[0061] In some specific embodiments, the back side of the large-size N-type silicon wafer has a back side passivation layer, and the back side passivation layer comprises SiO2 / polysilicon / SiN x Stacked layers (from the back of the large size N-type silicon wafer to the outside, in order of SiO2 layer, polysilicon layer and SiN x layer).

[0062] Furthermore, the SiO2 / polysilicon / SiN x The thickness of the SiO2 layer in the stack is 1.9~2.1nm (ultra-thin, tunneling layer (allowing carriers to selectively tunnel to the polysilicon layer), chemical passivation: saturating the dangling bonds on the silicon surface and reducing the interface state density), for example 2nm.

[0063] The SiO2 / polysilicon / SiN x The thickness of the polysilicon layer in the stack (field effect passivation: highly doped polysilicon provides fixed charges to form a back surface field (BSF) to reduce recombination; carrier collection: serves as a contact layer to form an ohmic contact with the metal electrode) is 149~151nm, for example 150nm.

[0064] The SiO2 / polysilicon / SiN x SiN in the stack x The thickness of the layer (hydrogen atom (H) replenishment: releases H atoms during annealing to repair SiO2 / silicon interface defects; protective layer: prevents polysilicon from being oxidized or contaminated in subsequent processes (such as laser grooving)) is 99~101nm, for example 100nm.

[0065] The present invention adopts a double-sided passivation structure: Al2O3 / SiN is set on the front side. x stacking, fixed negative charge density>1×10 12 cm -2 ; SiO2 / polysilicon / SiN is set on the back x The stacking can realize tunneling passivation contact (TOPCon).

[0066] Furthermore, by providing a front passivation layer of specific composition and thickness, as well as a back passivation layer of specific composition and thickness, the present invention can reduce the surface recombination velocity to below 10 cm / s (preferably 8 cm / s). This solves the problem of limited passivation effectiveness of existing passivation layers on N-type silicon wafers, resulting in a high surface recombination velocity (SRV) (above 100 cm / s) and carrier recombination losses.

[0067] Furthermore, the back passivation layer also has a selective emitter, and the phosphorus concentration in the selective emitter is ≥1×10 20 atoms / cm 3 , for example 2×10 20 atoms / cm 3 , 3×10 20 atoms / cm 3 , 4×10 20 atoms / cm 3 or 5×10 20 atoms / cm 3 This helps reduce contact resistance (<1mΩ·cm 2 ), reducing the surface recombination velocity (<1×10 3 cm / s), reducing Voc loss (5~10mV), obtaining a wide laser process window (high energy tolerance), and adapting to battery types BC / TOPCon-IBC.

[0068] Furthermore, an interlaced point-contact back electrode is disposed on the selective emitter of the back passivation layer. The interlaced point-contact back electrode is made of copper-silver-plated copper, and the copper-silver-plated copper layer comprises a copper layer and a silver layer covering the copper layer. The copper layer has a thickness of 19 to 21 μm, for example, 20 μm; the silver layer has a thickness of 0.8 to 1 μm, for example, 0.9 micrometer; and the total area of ​​the copper-silver-plated copper layer accounts for ≤5% of the area of ​​the back passivation layer, for example, 4%, 3%, 2%, or 1%.

[0069] Using copper-silver plating and controlling the thickness of the copper and silver layers is beneficial to controlling material costs, reducing contact resistance, improving anti-PID performance (attenuation <2%), reducing silicon wafer warping, adapting to large sizes, reducing fragmentation rates, and having good process compatibility (electroplating / laser transfer).

[0070] This invention moves all electrodes to the back side, eliminating grid lines from blocking the front side, and can improve light absorption efficiency by 6% to 8% (light absorption loss ≤ 2%). This solves the problem of low light absorption efficiency caused by incident light loss (approximately 5% to 8%) due to metal grid lines blocking the front side.

[0071] In addition, the back of the present invention is designed with staggered point contact electrodes, and the contact area accounts for ≤5%, which can reduce metal composite.

[0072] The schematic diagram of the layer structure of the large-size N-type silicon wafer provided by the present invention is shown in FIG. Figure 2 As shown, it can be seen that the large-size N-type silicon wafer includes a front passivation layer, an N-type silicon wafer body, a back passivation layer, a selective emitter and a staggered point contact back electrode stacked in sequence.

[0073] In some specific embodiments, the cell efficiency of the large-size N-type silicon wafer provided by the present invention is ≥24.8% (IBC structure, AM1.5G), wherein the testing method is IV test + EL imaging.

[0074] In some specific embodiments, the minority carrier lifetime of the large-size N-type silicon wafer provided by the present invention meets the following requirements: bulk lifetime>2ms, surface SRV<5cm / s, wherein the testing method is QSSPC+microwave photoconductive attenuation.

[0075] In a second aspect, the present invention provides a method for preparing the large-size N-type silicon wafer for BC batteries, comprising the following steps: (a) Single crystal silicon is prepared by the Czochralski method, wherein the doping element includes antimony, to obtain a single crystal silicon rod.

[0076] (b) Cutting the single crystal silicon rod into slices and performing surface treatment to obtain silicon wafers.

[0077] (c) forming a front passivation layer and a back passivation layer on the front and back of the silicon wafer, respectively.

[0078] (d) Selectively laser doping the back passivation layer to form a selective emitter for selective contact.

[0079] The laser doping in step (d) is low-temperature doping, which can reduce silicon wafer warping, enhance thermal stability, and increase the yield to over 98%. This solves the problem of silicon wafer warping and insufficient thermal stability caused by high-temperature processes (such as diffusion and annealing), which affects the reliability of subsequent battery modules.

[0080] In some specific embodiments, the warpage of the large-sized N-type silicon wafer produced by the present invention is less than 0.1 mm / m.

[0081] (e) The edge of the silicon wafer is chamfered by laser, and then SiN is wrapped at the edge by plasma enhanced chemical vapor deposition (PECVD). x layer to prevent leakage.

[0082] The above method can produce large-sized N-type silicon wafers, which not only ensures mechanical strength and reduces fragmentation rate, but also reduces edge carrier recombination, increases open circuit voltage (Voc), and improves battery power output.

[0083] In some specific embodiments, in step (a), the Czochralski method includes a magnetic field-assisted Czochralski method (MCZ method), and the axial temperature gradient of the magnetic field-assisted Czochralski method is 10-15°C / cm, for example, 11°C / cm, 12°C / cm, 13°C / cm or 14°C / cm.

[0084] The present invention adopts a transverse magnetic field (MCZ) to suppress melt convection, thereby reducing stripe defects caused by antimony doping.

[0085] In some specific embodiments, in step (a), during the process of preparing single crystal silicon by the Czochralski method, the growth rate of the single crystal silicon is 1.2-1.5 mm / min, for example, 1.3 mm / min or 1.4 mm / min.

[0086] The present invention can achieve longitudinal resistivity uniformity of ±1.8% by controlling the axial temperature gradient of the magnetic field-assisted Czochralski method and the growth rate of single crystal silicon.

[0087] In some specific embodiments, in step (a), during the Czochralski method for preparing single crystal silicon, the pulling speed is 1.3 to 1.8 mm / min, for example, 1.4 mm / min, 1.5 mm / min, 1.6 mm / min, or 1.7 mm / min. By reducing the pulling speed, the present invention can reduce radial segregation of antimony.

[0088] In some specific embodiments, in step (a), during the Czochralski method for preparing single crystal silicon, the argon flow rate is 80 to 100 L / min, for example, 85 L / min, 90 L / min, or 95 L / min. By increasing the argon flow rate, the present invention can suppress doping fluctuations caused by antimony volatilization.

[0089] In some specific embodiments, in step (a), during the Czochralski method for preparing single-crystalline silicon, a doping gas mask technique is used, SbH3 is used as a dopant, and the antimony doping concentrations in the edge region and the center region are controlled respectively, and the gas flow rate of the SbH3 is adjusted by resistivity monitoring and / or photoluminescence (PL) detection.

[0090] The resistivity monitoring method includes using a four-point probe scanner (1mm resolution) to control the radial resistivity fluctuation of the single-crystal silicon to less than 5%, preferably less than 2%. This improves resistivity uniformity and addresses the existing issues of poor resistivity uniformity and radial resistivity fluctuation exceeding 5% with increased size.

[0091] Furthermore, the photoluminescence detection method includes online PL imaging to identify low-lifetime regions caused by antimony accumulation, with a threshold value of <500μs. This improves antimony doping uniformity and addresses the existing issues of poor doping uniformity and uneven efficiency distribution at the edges of large silicon wafers.

[0092] In some specific embodiments, in step (a), during the process of preparing single crystal silicon by the Czochralski method, low temperature ion implantation of He + To form a nanocavity layer, which can inhibit crack propagation through the pinning effect. + The dose is 1×10 14 ~1.01×10 14 ions / cm 2 , energy is 50~60keV.

[0093] In some specific embodiments, in step (b), the diamond wire used for cutting includes a resin bonded diamond wire, and the diameter of the diamond wire is 50-80 μm, such as 55 μm, 60 μm, 65 μm, 70 μm or 75 μm.

[0094] In some specific embodiments, in step (b), the cutting speed is 1.2-1.5 m / s, for example, 1.3 m / s or 1.4 m / s.

[0095] The present invention can reduce the saw mark depth (<8μm) by controlling the material, wire diameter and cutting speed of the diamond wire.

[0096] In some specific embodiments, in step (b), the cutting coolant includes polyethylene glycol and further contains silicon carbide abrasive and / or nano-SiO2 particles. The use of nano-SiO2 particles can reduce the brittle edge chipping of antimony-doped silicon.

[0097] The median particle size of the silicon carbide abrasive is 3-5 μm, for example, 4 μm; the median particle size of the nano-SiO2 particles is 80-100 nm, for example, 85 nm, 90 nm, or 95 nm.

[0098] By controlling the diameter of the diamond wire and the composition of the coolant, this invention can control cutting losses to ≤90μm, reducing cutting losses by 20% and overall production costs by 15%. This further reduces the production cost of N-type silicon wafers and can be directly integrated into existing BC battery production lines without the need for equipment modification. This solves the problem of high production costs caused by high cutting losses of large-sized silicon wafers.

[0099] In some specific embodiments, in step (b), the surface treatment method includes: polishing, chemical thinning and texturing in sequence. Wherein, the polishing method includes: double-sided chemical mechanical polishing (CMP), and the polishing is to a surface roughness of Ra<0.5nm. The chemical thinning method includes: using a mixed acid solution of HF and HNO3 (the molar ratio of HF to HNO3 in the mixed acid solution is preferably 1:3) to perform isotropic etching on both sides to remove the cutting damage layer, wherein the thickness uniformity is ±1.5μm. The texturing method includes: using laser etching on the front side to form an inverted pyramid velvet structure, wherein the height of the inverted pyramid velvet structure is 23~25μm, for example, 24μm.

[0100] This invention uses low-cost cutting and polishing (surface treatment) processes to increase the yield of silicon wafers to over 98%, solving the existing problem of low yield and high cost of large-size silicon wafer production, which relies on high-precision equipment.

[0101] In some specific embodiments, in step (c), the front passivation layer can enhance the surface passivation effect, and includes Al2O3 / SiN x Overlay.

[0102] In some specific embodiments, in step (c), the back passivation layer comprises SiO2 / polysilicon / SiN x stack, which enables tunneling passivated contact (TOPCon).

[0103] In some specific embodiments, in step (d), the selective laser doping method includes: selectively ablating a portion of the back passivation layer by pulse laser, and doping phosphorus (for example, using a laser to open a micron-sized contact hole (using a laser to open a groove) on the back passivation layer, and then achieving local high-concentration doping (N + )) to form N + Local heavily doped region (N⁺ back surface field (BSF)).

[0104] The wavelength of the pulse laser is 530-540 nm (530-540 nm pulse laser is used to locally activate the antimony doped region (n + ), contact resistance <1mΩ·cm 2 , while retaining the minority carrier lifetime >1ms in the lightly doped main region to form a selective emitter).

[0105] The energy density of the pulsed laser is 2.8-3 J / cm 2 , for example 2.9 J / cm 2 .

[0106] The scanning speed of the pulse laser is 5-6 m / s, for example 5.5 m / s.

[0107] In some specific embodiments, in step (e), during the plasma enhanced chemical vapor deposition process, the zone pressure is controlled to be 0.1-0.3 bar, for example, 0.2 bar, to avoid local stress exceeding the limit.

[0108] In some specific embodiments, after step (e), the following step (f) is further included: preparing a staggered point contact back electrode: using an ultraviolet laser to open a plurality of staggered grooves on the back of the silicon wafer (to expose the N + area), followed by copper electroplating and silver covering to form a copper-plated silver electrode material.

[0109] The wavelength of the ultraviolet laser is 350-360 nm, for example, 355 nm; the pulse width is 8-10 ps, ​​for example, 9 ps; and the energy is 0.8-1 μJ, for example, 0.9 μJ.

[0110] Furthermore, the width of each of the grooves is 20-32 μm, for example, 23 μm, 25 μm, 28 μm or 30 μm; the ratio of the length to the width of each of the grooves is 2:1; and the distance between two adjacent grooves is 1.4-1.6 mm, for example, 1.5 mm.

[0111] Furthermore, the electroplating solution used for copper electroplating is a mixture of CuSO4, H2SO4 and additives. The concentration of CuSO4 in the mixture of CuSO4, H2SO4 and additives is 150~250g / L, such as 160g / L, 180g / L, 200g / L or 230g / L. The concentration of H2SO4 in the mixture of CuSO4, H2SO4 and additives is 50~100g / L, such as 60g / L, 70g / L or 90g / L. Further, the additives include PEG and a chlorine source, the chlorine source includes HCl and / or NaCl, the concentration of PEG in the mixture of CuSO4, H2SO4 and additives is 0.05~0.5g / L, such as 0.1g / L, 0.2g / L, 0.3g / L or 0.4g / L; the concentration of Cl in the mixture of CuSO4, H2SO4 and additives is 0.1g / L, 0.2g / L, 0.3g / L or 0.4g / L. - The concentration of PEG is 0.03-0.1 g / L, such as 0.05 g / L, 0.06 g / L or 0.08 g / L. PEG includes, but is not limited to, PEG-8000.

[0112] Among them, PEG (polyethylene glycol) as an inhibitor can react with Cl - Synergistically form an adsorption layer to slow down the Cu 2+ Deposition rate and improve coating uniformity.

[0113] Among them, Cl - Forming complex with PEG to enhance the inhibitory effect. - Too low a concentration will cause PEG to fail. - Too high a concentration may cause rough coating.

[0114] Furthermore, the current density of the copper electroplating is 1.9~2.1A / dm 2 , for example 2.0A / dm 2 ; The copper electroplating time is 15~15.5min.

[0115] Furthermore, the silver coating method includes: using an immersion plating method to immerse the silicon wafer in a mixed solution of AgNO3 and a complexing agent to perform a replacement reaction. The complexing agent includes ammonia water, and the concentration of AgNO3 in the mixed solution of AgNO3 and the complexing agent is 0.3 to 0.35 mol / L, such as 0.31 mol / L, 0.32 mol / L or 0.34 mol / L; the NH3 in the mixed solution of AgNO3 and the complexing agent reacts with AgNO3 to form a silver coating. + The molar ratio is ≥2:1.

[0116] In some specific embodiments, the complexing agent may also be sodium thiosulfate, sodium citrate or EDTA (ethylenediaminetetraacetic acid).

[0117] In a third aspect, the present invention provides a BC battery, comprising the above-mentioned large-size N-type silicon wafer for BC batteries.

[0118] By optimizing the structure of large-size N-type silicon wafers and their preparation methods, the present invention can achieve a laboratory conversion rate of over 26.5% (the laboratory conversion rate of existing N-type silicon wafers such as G1 (158.75mm×158.75mm) is ≤24.5%), and the mass production efficiency exceeds 25%.

[0119] The embodiments of the present invention will be described in detail below with reference to the examples, but it will be understood by those skilled in the art that the following examples are merely illustrative of the present invention and should not be construed as limiting the scope of the invention. Where specific conditions are not specified in the examples, the methods were performed according to conventional conditions or the conditions recommended by the manufacturer. Where the manufacturers of the reagents or instruments are not specified, they are all commercially available conventional products.

[0120] Example 1 The method for preparing a large-size N-type silicon wafer for BC batteries provided in this embodiment includes the following steps: (1) Single crystal silicon was prepared by a magnetic field-assisted Czochralski method, wherein the doping elements included antimony, to obtain a single crystal silicon rod, wherein the axial temperature gradient of the magnetic field-assisted Czochralski method was 13°C / cm, the growth rate of the single crystal silicon was 1.3mm / min, the pulling speed was 1.5mm / min, and the flow rate of argon was 90L / min. Specifically, a doping gas mask technique was adopted, with SbH3 as the dopant, to control the antimony doping concentration in the edge area and the center area respectively, and the gas flow rate of SbH3 was adjusted by resistivity monitoring and photoluminescence detection; wherein the resistivity monitoring method included: using a four-point probe scanner to control the radial resistivity fluctuation of the single crystal silicon to be less than 5%. The photoluminescence detection method included: online PL imaging to identify the low lifetime area caused by antimony aggregation, and controlling the threshold value to be less than 500μs. In addition, in the process of preparing single crystal silicon, low temperature ion implantation of He + To form a nanocavity layer, where He + The dose is 1×10 14 ions / cm 2 , energy is 55keV.

[0121] (2) A single crystal silicon rod was cut into slices using a resin-bonded diamond wire with a wire diameter of 60 μm, and then surface treated to obtain silicon wafers. The cutting speed was 1.2 m / s. The coolant used for cutting included polyethylene glycol, and the coolant also contained silicon carbide abrasive, and the median particle size of the silicon carbide abrasive was 5 μm. The surface treatment method included polishing, chemical thinning, and texturing in sequence; the polishing method included double-sided chemical mechanical polishing to a surface roughness Ra < 0.5 nm; the chemical thinning method included isotropic etching of both sides using a mixed acid solution of HF and HNO3 (wherein the molar ratio of HF to HNO3 was 1:3) to remove the cutting damage layer; the texturing method included laser etching on the front side to form an inverted pyramid texture structure, wherein the height of the inverted pyramid texture structure was 23 μm.

[0122] (3) Form a front passivation layer and a back passivation layer on the front and back of the silicon wafer respectively. The front passivation layer is Al2O3 / SiN x Multilayer, back passivation layer is SiO2 / polysilicon / SiN x Overlay.

[0123] (4) Selective laser doping of the back passivation layer. Specifically, the back passivation layer is selectively ablated locally by pulse laser and doped with phosphorus to form N + The local heavily doped region is used to obtain a selective emitter. The wavelength of the pulsed laser is 532nm and the energy density of the pulsed laser is 3J / cm 2 , the scanning speed of the pulse laser is 5m / s.

[0124] (5) The edge of the silicon wafer is chamfered by laser, and then SiN is wrapped at the edge by plasma enhanced chemical vapor deposition. x During the plasma enhanced chemical vapor deposition process, the zone pressure was controlled at 0.2 bar.

[0125] (6) Preparation of staggered point contact back electrodes: A UV laser is used to open several staggered grooves on the back of the silicon wafer, wherein the wavelength of the UV laser is 355nm, the pulse width is 10ps, and the energy is 0.8μJ; the width of each groove is 25μm, the ratio of the length to the width of each groove is 2:1, and the distance between two adjacent grooves is 1.5mm. Then copper electroplating and silver covering are carried out in sequence to form a copper-plated silver electrode material. The plating solution used for copper electroplating is a mixture of CuSO4, H2SO4 and additives; the concentration of CuSO4 in the mixture is 200g / L, and the concentration of H2SO4 is 50g / L; the additives include PEG and a chlorine source, and the chlorine source includes HCl. The concentration of PEG in the mixture is 0.3g / L, and the concentration of Cl is 0. -The concentration is 0.05g / L. The current density of copper electroplating is 2A / dm 2 The copper electroplating time is 15 minutes. The silver covering method includes: using the immersion plating method, immersing the silicon wafer in a mixed solution of AgNO3 and a complexing agent to perform a replacement reaction; the complexing agent includes ammonia water, the concentration of AgNO3 in the mixed solution of AgNO3 and the complexing agent is 0.33 mol / L, and the NH3 in the mixed solution of AgNO3 and the complexing agent reacts with Ag. + The molar ratio is ≥2:1.

[0126] The large-sized N-type silicon wafer prepared in this embodiment has a size of 230 mm × 230 mm and a thickness of 100 μm. The edge of the large-sized N-type silicon wafer is a circular chamfer with a radius of 1 mm, and the edge of the large-sized N-type silicon wafer is wrapped with SiN x layer, SiN x The thickness of the layer is 100nm. The large-size N-type silicon wafer includes a central area and an edge area surrounding the central area. The width of the edge area is 3mm, the resistivity of the edge area is 10Ω·cm, and the resistivity of the central area is 1.5Ω·cm. The content of the doping element antimony in the edge area is 1×10 15 atoms / cm 3 The content of doping element antimony in the central region is 3×10 16 atoms / cm 3 The radial resistivity fluctuation of the large-sized N-type silicon wafer is less than 5%. The front side of the large-sized N-type silicon wafer has a front passivation layer, which is Al2O3 / SiN x The Al2O3 / SiN stack x The thickness of the Al2O3 layer in the stack is 10nm, and the SiN x The thickness of the layer is 80nm. The back of the large-size N-type silicon wafer has a back passivation layer, which includes SiO2 / polysilicon / SiN x The SiO2 / polysilicon / SiN stack x The thickness of the SiO2 layer in the stack is 2nm, the thickness of the polysilicon layer is 150nm, and the thickness of the SiN x The thickness of the layer is 100nm; there is also a selective emitter on the back passivation layer, and the phosphorus concentration in the selective emitter is 1×10 20 atoms / cm 3 ; An interlaced point contact back electrode is also provided on the back passivation layer. The material of the interlaced point contact back electrode is copper-silver plating. The copper-silver plating includes a copper layer and a silver layer covering the copper layer, wherein the thickness of the copper layer is 20 μm and the thickness of the silver layer is 1 μm; the total area of ​​the copper-silver plating accounts for 5% of the area of ​​the back passivation layer.

[0127] Example 2 The method for preparing a large-size N-type silicon wafer for a BC battery provided in this embodiment includes the following steps: (1) Single crystal silicon is prepared by magnetic field assisted Czochralski method, wherein the doping elements include antimony, and a single crystal silicon rod is obtained, wherein the axial temperature gradient of magnetic field assisted Czochralski method is 10℃ / cm, the growth rate of single crystal silicon is 1.5mm / min, the pulling speed is 1.3mm / min, and the flow rate of argon is 80L / min. Specifically, the doping gas mask technology is adopted, SbH3 is used as the dopant, and the antimony doping concentration in the edge area and the center area is controlled respectively, and resistivity monitoring is performed, wherein the resistivity monitoring method includes: using a four-point probe scanner to control the radial resistivity fluctuation of single crystal silicon to be less than 5%. In addition, in the process of preparing single crystal silicon, low temperature ion implantation of He + To form a nanocavity layer, where He + The dose is 1.01×10 14 ions / cm 2 , energy is 50keV.

[0128] (2) A single crystal silicon rod was cut into slices using a resin-bonded diamond wire with a wire diameter of 50 μm, and then surface treated to obtain silicon wafers. The cutting speed was 1.3 m / s. The coolant used for cutting included polyethylene glycol, and the coolant also contained nano-SiO2 particles, the median particle size of the nano-SiO2 particles being 100 nm. The surface treatment method included polishing, chemical thinning, and texturing in sequence; the polishing method included double-sided chemical mechanical polishing to a surface roughness Ra < 0.5 nm; the chemical thinning method included isotropic etching of both sides using a mixed acid solution of HF and HNO3 (wherein the molar ratio of HF to HNO3 was 1:3) to remove the cutting damage layer; the texturing method included laser etching on the front side to form an inverted pyramid texture structure, wherein the height of the inverted pyramid texture structure was 24 μm.

[0129] (3) Form a front passivation layer and a back passivation layer on the front and back of the silicon wafer respectively. The front passivation layer is Al2O3 / SiN x Multilayer, back passivation layer is SiO2 / polysilicon / SiN x Overlay.

[0130] (4) Selective laser doping of the back passivation layer. Specifically, the back passivation layer is selectively ablated locally by pulse laser and doped with phosphorus to form N + The local heavily doped region is used to obtain a selective emitter. The wavelength of the pulsed laser is 540nm and the energy density of the pulsed laser is 2.8J / cm 2 , the scanning speed of the pulse laser is 6m / s.

[0131] (5) The edge of the silicon wafer is chamfered by laser, and then SiN is wrapped at the edge by plasma enhanced chemical vapor deposition. x During the plasma enhanced chemical vapor deposition process, the partition pressure was controlled at 0.1 bar.

[0132] (6) Preparation of staggered point contact back electrodes: A UV laser is used to open several staggered grooves on the back of the silicon wafer, wherein the UV laser wavelength is 350nm, the pulse width is 8ps, and the energy is 1μJ; the width of each groove is 20μm, the length to width ratio of each groove is 2:1, and the distance between two adjacent grooves is 1.4mm. Then copper electroplating and silver covering are carried out in sequence to form a copper-plated silver electrode material. The plating solution used for copper electroplating is a mixture of CuSO4, H2SO4 and additives; the concentration of CuSO4 in the mixture is 150g / L, and the concentration of H2SO4 is 100g / L; the additives include PEG and a chlorine source, and the chlorine source includes NaCl. The concentration of PEG in the mixture is 0.1g / L, and the concentration of Cl is 0. - The concentration is 0.03g / L. The current density of copper electroplating is 1.9A / dm 2 The copper electroplating time is 15.5min. The silver covering method includes: using immersion plating method, immersing the silicon wafer in a mixed solution of AgNO3 and a complexing agent to carry out a replacement reaction; the complexing agent includes ammonia water, the concentration of AgNO3 in the mixed solution of AgNO3 and the complexing agent is 0.3mol / L, and the NH3 in the mixed solution of AgNO3 and the complexing agent reacts with AgNO3. + The molar ratio is 3:1.

[0133] The large-sized N-type silicon wafer prepared in this embodiment has a size of 230 mm × 230 mm and a thickness of 90 μm. The edge of the large-sized N-type silicon wafer is a circular chamfer with a radius of 0.3 mm, and the edge of the large-sized N-type silicon wafer is wrapped with SiN x layer, SiN x The thickness of the layer is 80nm. The large-size N-type silicon wafer includes a central area and an edge area surrounding the central area. The width of the edge area is 2mm, the resistivity of the edge area is 15Ω·cm, and the resistivity of the central area is 0.5Ω·cm. The content of the doping element antimony in the edge area is 5×10 14 atoms / cm 3 The content of doping element antimony in the central region is 1×10 16 atoms / cm 3 The radial resistivity fluctuation of the large-sized N-type silicon wafer is less than 5%. The front side of the large-sized N-type silicon wafer has a front passivation layer, which is Al2O3 / SiN x The Al2O3 / SiN stack xThe thickness of the Al2O3 layer in the stack is 9nm, and the SiN x The thickness of the layer is 70nm. The back of the large-size N-type silicon wafer has a back passivation layer, which includes SiO2 / polysilicon / SiN x The SiO2 / polysilicon / SiN stack x The thickness of the SiO2 layer in the stack is 1.9nm, the thickness of the polysilicon layer is 149nm, and the thickness of the SiN x The thickness of the layer is 99nm; there is also a selective emitter on the back passivation layer, and the phosphorus concentration in the selective emitter is 3×10 20 atoms / cm 3 ; An interlaced point contact back electrode is also provided on the back passivation layer. The material of the interlaced point contact back electrode is copper-silver plating. The copper-silver plating includes a copper layer and a silver layer covering the copper layer. The thickness of the copper layer is 21μm and the thickness of the silver layer is 0.9μm. The total area of ​​the copper-silver plating accounts for 4% of the area of ​​the back passivation layer.

[0134] Example 3 The method for preparing a large-size N-type silicon wafer for BC batteries provided in this embodiment includes the following steps: (1) Single crystal silicon was prepared by magnetic field assisted Czochralski method, wherein the doping elements included antimony, to obtain single crystal silicon rods, wherein the axial temperature gradient of magnetic field assisted Czochralski method was 15℃ / cm, the growth rate of single crystal silicon was 1.2mm / min, the pulling speed was 1.8mm / min, and the flow rate of argon gas was 100L / min. Specifically, the doping gas mask technology was adopted, SbH3 was used as the dopant, and the antimony doping concentration in the edge area and the center area was controlled respectively, and the gas flow rate of SbH3 was adjusted by photoluminescence detection; wherein the photoluminescence detection method includes: online PL imaging to identify the low lifetime area caused by antimony aggregation, and controlling the threshold value <500μs. In addition, in the process of preparing single crystal silicon, He was implanted by low temperature ion + To form a nanocavity layer, where He + The dose is 1×10 14 ions / cm 2 , energy is 60keV.

[0135] (2) A single crystal silicon rod was cut into slices using a resin-bonded diamond wire with a wire diameter of 80 μm, and then surface treated to obtain silicon wafers. The cutting speed was 1.5 m / s. The coolant used for cutting included polyethylene glycol, and the coolant also contained silicon carbide abrasive and nano-SiO2 particles in a mass ratio of 1:1. The median particle size of the silicon carbide abrasive was 3 μm, and the median particle size of the nano-SiO2 particles was 80 nm. The surface treatment method included polishing, chemical thinning, and texturing in sequence. The polishing method included double-sided chemical mechanical polishing to a surface roughness Ra < 0.5 nm. The chemical thinning method included isotropic etching of both sides using a mixed acid solution of HF and HNO3 (wherein the molar ratio of HF to HNO3 was 1:3) to remove the cutting damage layer. The texturing method included laser etching on the front side to form an inverted pyramid texture structure, wherein the height of the inverted pyramid texture structure was 25 μm.

[0136] (3) Form a front passivation layer and a back passivation layer on the front and back of the silicon wafer respectively. The front passivation layer is Al2O3 / SiN x Multilayer, back passivation layer is SiO2 / polysilicon / SiN x Overlay.

[0137] (4) Selective laser doping of the back passivation layer. Specifically, the back passivation layer is selectively ablated locally by pulse laser and doped with phosphorus to form N + The local heavily doped region is used to obtain a selective emitter. The wavelength of the pulsed laser is 530nm and the energy density of the pulsed laser is 2.9J / cm 2 , the scanning speed of the pulse laser is 5.5m / s.

[0138] (5) The edge of the silicon wafer is chamfered by laser, and then SiN is wrapped at the edge by plasma enhanced chemical vapor deposition. x During the plasma enhanced chemical vapor deposition process, the zone pressure was controlled at 0.3 bar.

[0139] (6) Preparation of staggered point contact back electrodes: A UV laser is used to open several staggered grooves on the back of the silicon wafer, wherein the wavelength of the UV laser is 360nm, the pulse width is 9ps, and the energy is 0.9μJ; the width of each groove is 32μm, the ratio of the length to the width of each groove is 2:1, and the distance between two adjacent grooves is 1.6mm. Then copper electroplating and silver covering are carried out in sequence to form a copper-plated silver electrode material. The plating solution used for copper electroplating is a mixture of CuSO4, H2SO4 and additives; the concentration of CuSO4 in the mixture is 230g / L, and the concentration of H2SO4 is 80g / L; the additives include PEG and a chlorine source, and the chlorine source includes NaCl. The concentration of PEG in the mixture is 0.5g / L, and the concentration of Cl is 0. - The concentration is 0.1g / L. The current density of copper electroplating is 2.1A / dm 2 The copper electroplating time is 15 minutes. The silver covering method includes: using the immersion plating method, immersing the silicon wafer in a mixed solution of AgNO3 and a complexing agent to perform a replacement reaction; the complexing agent includes ammonia water, the concentration of AgNO3 in the mixed solution of AgNO3 and the complexing agent is 0.35 mol / L, and the NH3 in the mixed solution of AgNO3 and the complexing agent reacts with Ag. + The molar ratio is 4:1.

[0140] The large-sized N-type silicon wafer prepared in this embodiment has a size of 230 mm × 230 mm and a thickness of 130 μm. The edge of the large-sized N-type silicon wafer is a circular chamfer with a radius of 1.5 mm. The edge of the large-sized N-type silicon wafer is wrapped with SiN x layer, SiN x The thickness of the layer is 200nm. The large-size N-type silicon wafer includes a central region and an edge region surrounding the central region. The width of the edge region is 4mm, the resistivity of the edge region is 13Ω·cm, and the resistivity of the central region is 3Ω·cm. The content of the doping element antimony in the edge region is 5×10 14 atoms / cm 3 The content of doping element antimony in the central region is 5×10 16 atoms / cm 3 The radial resistivity fluctuation of the large-sized N-type silicon wafer is less than 5%. The front side of the large-sized N-type silicon wafer has a front passivation layer, which is Al2O3 / SiN x The Al2O3 / SiN stack x The thickness of the Al2O3 layer in the stack is 8nm, and the SiN x The thickness of the layer is 60nm. The back of the large-size N-type silicon wafer has a back passivation layer, which includes SiO2 / polysilicon / SiN x The SiO2 / polysilicon / SiN stack xThe thickness of the SiO2 layer in the stack is 2.1nm, the thickness of the polysilicon layer is 151nm, and the thickness of the SiN x The thickness of the layer is 101nm; there is also a selective emitter on the back passivation layer, and the phosphorus concentration in the selective emitter is 3×10 20 atoms / cm 3 ; An interlaced point contact back electrode is also provided on the back passivation layer. The material of the interlaced point contact back electrode is copper-silver plating. The copper-silver plating includes a copper layer and a silver layer covering the copper layer. The thickness of the copper layer is 19μm and the thickness of the silver layer is 0.8μm. The total area of ​​the copper-silver plating accounts for 2% of the area of ​​the back passivation layer.

[0141] Comparative Example 1 The existing N-type silicon wafer G1 (158.75mm×158.75mm).

[0142] Comparative Example 2 The large-size N-type silicon wafer for BC batteries and its preparation method provided in this embodiment are basically the same as those in Example 1, except that the edges of the silicon wafer are not chamfered and the edges are not wrapped with SiN. x In addition, the content of antimony doping elements in the edge region is equal to that in the center region, both of which are 1×10 15 atoms / cm 3 .

[0143] Comparative Example 3 The large-size N-type silicon wafer for BC batteries and its preparation method provided in this embodiment are basically the same as those in Example 1, except that: the front side of the large-size N-type silicon wafer has no front passivation layer, and the back side has no back passivation layer.

[0144] Comparative Example 4 The large-size N-type silicon wafer for BC batteries and the preparation method thereof provided in this embodiment are basically the same as those in Example 1, except that: in step (1), the axial temperature gradient of the magnetic field-assisted Czochralski method is 5°C / cm, the growth rate of single crystal silicon is 0.5 mm / min, the pulling speed is 2.5 mm / min, and the flow rate of argon gas is 50 L / min.

[0145] Comparative Example 5 The large-size N-type silicon wafer for BC batteries and the preparation method thereof provided in this embodiment are basically the same as those in Example 1, except that: in step (2), the coolant does not contain silicon carbide abrasive, no surface treatment is performed, and the wire diameter of the diamond wire is 100 μm and the cutting speed is 0.5 m / s.

[0146] Experimental example The performance tests were conducted on the large-size N-type silicon wafers prepared in each embodiment and each comparative example, and the results are shown in Table 1.

[0147] Table 1 Performance test results of various N-type silicon wafers

[0148] As can be seen from Table 1, the large-size N-type silicon wafers prepared in various embodiments have the advantages of high mechanical strength, low fragmentation rate, high cell efficiency, low light absorption loss, high open circuit voltage (Voc), and high fill factor (FF).

[0149] Specifically, in Example 1-Example 3: arc chamfer (0.3~1.5mm) + SiN x Edge wrapping significantly improves mechanical strength (>550MPa) and the fragmentation rate is <1.5%. x ) Edge stress concentration caused a fragmentation rate of 4.5%. Comparative Example 5 (rough cutting / no surface treatment) showed cutting damage, resulting in the lowest mechanical strength (400 MPa) and a fragmentation rate of up to 12%.

[0150] At the same time, in Examples 1 to 3: a combined passivation layer (front passivation layer Al2O3 / SiN x Stacked + back passivation layer SiO2 / polysilicon / SiN x stack) + selective emitter (phosphorus concentration ≥ 1×10 20 atoms / cm 3 ), the cell efficiency reached 26.3%-26.7%. However, in Comparative Example 3 (no passivation layer), recombination losses increased dramatically, resulting in a cell efficiency of only 22.5%. In Comparative Example 1 (G1 size), the small size limited the optical design, resulting in a cell efficiency of only 24.0%.

[0151] In addition, in Example 1-Example 3: using inverted pyramid velvet (height 23~25μm) + optimizing Al2O3 / SiN x SiN in the stack x The thickness is 60-80nm, which controls the light absorption loss below 3%. However, the surface reflection loss of comparative example 5 (untextured) reaches 9%.

[0152] In addition, in Examples 1 to 3: high-resistance edge (resistivity of edge area ≥ 10Ω·cm) + SiN x The encapsulation reduces PID attenuation (a high voltage difference between the cell and the frame / ground causes ion migration (e.g., Na⁺) that damages the passivation layer, resulting in power drop) to less than 2%, demonstrating high reliability. In contrast, in Comparative Example 3 (without a passivation layer), metal diffusion leads to PID failure (>10%).

[0153] It can be seen that each embodiment has the following advantages: (1) Arc chamfer + SiN xEdge wrapping: Reduces the fragmentation rate to <1.5%, suitable for thinning (90-130μm). (2) Combined passivation layer + selective emitter: Efficiency exceeds 26.5%, Voc>730mV. (3) Copper-silver electrode (20μm Cu+1μm Ag): Balances cost and performance, FF>83%. However, the traditional G1 silicon wafer (Comparative Example 1) has low efficiency due to size limitations; Comparative Examples 4 and 5 have poor mechanical, optical, and electrical performance due to unsuitable parameters for preparing single crystal silicon and unsuitable cutting parameters. Therefore, the technical routes of each embodiment provide a highly reliable and efficient solution for the mass production of large-size N-type BC cells.

[0154] In summary, the present invention provides an edge arc chamfer and wraps SiN x Low doping at the layer and edge can reduce edge carrier recombination, increase open circuit voltage, and boost battery power output while ensuring mechanical strength and reducing fragmentation. Furthermore, by optimizing the structure of large-size N-type silicon wafers and their fabrication methods, the overall performance of large-size N-type silicon wafers and the BC batteries made from them can be further improved.

[0155] Although the present invention has been illustrated and described using specific embodiments, it should be appreciated that the above embodiments are merely intended to illustrate the technical solutions of the present invention rather than to limit them. Those skilled in the art should understand that the technical solutions described in the above embodiments may be modified, or some or all of the technical features thereof may be replaced by equivalents, without departing from the spirit and scope of the present invention. However, these modifications or replacements do not deviate from the essence of the corresponding technical solutions within the scope of the technical solutions of the embodiments of the present invention. Therefore, this means that all such replacements and modifications within the scope of the present invention are included in the appended claims.

Claims

1. A large-size N-type silicon wafer for BC batteries, characterized in that: The size of the large-size N-type silicon wafer is ≥230 mm×230 mm, the thickness of the large-size N-type silicon wafer is 90-130 μm, the edge of the large-size N-type silicon wafer is an arc chamfer, and the edge of the large-size N-type silicon wafer is wrapped with a SiNx layer; The large-size N-type silicon wafer includes a central area and an edge area surrounding the central area, and the content of the doping element antimony in the edge area is ≤1×10 15 atoms / cm 3 The content of the doping element antimony in the central region is 1×10 16 ~5×10 16 atoms / cm 3 .

2. The large-size N-type silicon wafer for BC batteries according to claim 1, characterized in that: At least one of the following conditions is met: (1) The radius of the arc chamfer is 0.3~1.5mm; (2) The width of the edge area is 2 to 4 mm; (3) The SiN x The thickness of the layer is 80~200nm.

3. The large-size N-type silicon wafer for BC batteries according to claim 1, characterized in that: At least one of the following conditions is met: (1) The resistivity of the edge region is ≥10Ω·cm, and the resistivity of the central region is 0.5~3Ω·cm; (2) The radial resistivity fluctuation of the large-size N-type silicon wafer is less than 5%.

4. The large-size N-type silicon wafer for BC batteries according to claim 1, characterized in that: At least one of the following conditions is met: (1) The front side of the large-size N-type silicon wafer has a front passivation layer, and the front passivation layer includes Al2O3 / SiN x stack; the Al2O3 / SiN x The thickness of the Al2O3 layer in the stack is 8-10 nm. x SiN in the stack x The thickness of the layer is 60~80nm; (2) The back of the large-size N-type silicon wafer has a back passivation layer, which includes SiO2 / polysilicon / SiN x stack, the SiO2 / polysilicon / SiN x The thickness of the SiO2 layer in the stack is 1.9~2.1nm, and the SiO2 / polysilicon / SiN x The thickness of the polysilicon layer in the stack is 149-151 nm, and the SiO2 / polysilicon / SiN x SiN in the stack x The thickness of the layer is 99-101 nm; the back passivation layer also has a selective emitter, and the phosphorus concentration in the selective emitter is ≥1×10 20 atoms / cm 3 ; A staggered point contact back electrode is also provided on the back passivation layer, and the material of the staggered point contact back electrode is copper-silver plating, and the copper-silver plating includes a copper layer and a silver layer covering the copper layer, wherein the thickness of the copper layer is 19~21μm, and the thickness of the silver layer is 0.8~1μm; the total area of ​​the copper-silver plating accounts for ≤5% of the area of ​​the back passivation layer.

5. The method for preparing a large-size N-type silicon wafer for BC batteries according to any one of claims 1 to 4, characterized in that: The steps include: (a) preparing single crystal silicon by the Czochralski method, wherein the doping element includes antimony, to obtain a single crystal silicon rod; (b) cutting the single crystal silicon rod into slices and performing surface treatment to obtain silicon wafers; (c) forming a front passivation layer and a back passivation layer on the front and back of the silicon wafer, respectively; (d) performing selective laser doping on the back passivation layer to form a selective emitter; (e) The edge of the silicon wafer is chamfered by laser, and then SiN is wrapped around the edge by plasma enhanced chemical vapor deposition. x layer.

6. The method for preparing a large-size N-type silicon wafer for BC batteries according to claim 5, characterized in that: At least one of the following conditions is met: (1) In step (a), the Czochralski method includes a magnetic field-assisted Czochralski method, wherein the axial temperature gradient of the magnetic field-assisted Czochralski method is 10-15°C / cm; (2) In step (a), during the process of preparing single crystal silicon by the Czochralski method, the growth rate of the single crystal silicon is 1.2-1.5 mm / min; (3) In step (a), during the process of preparing single crystal silicon by the Czochralski method, the pulling speed is 1.3-1.8 mm / min; (4) In step (a), during the Czochralski method for preparing single crystal silicon, the flow rate of argon gas is 80-100 L / min; (5) In step (a), during the process of preparing single crystal silicon by the Czochralski method, a doping gas mask technique is used, SbH3 is used as a dopant, and the antimony doping concentration in the edge region and the center region is controlled respectively, and the gas flow rate of the SbH3 is adjusted by resistivity monitoring and / or photoluminescence detection; wherein the resistivity monitoring method includes: using a four-point probe scanner to control the radial resistivity fluctuation of the single crystal silicon to be less than 5%; the photoluminescence detection method includes: online PL imaging to identify the low lifetime region caused by antimony aggregation, and controlling the threshold value to be less than 500μs; (6) In step (a), during the process of preparing single crystal silicon by the Czochralski method, low temperature ion implantation of He + To form a nanocavity layer; He + The dose is 1×10 14 ~1.01×10 14 ions / cm 2 , energy is 50~60keV.

7. The method for preparing a large-size N-type silicon wafer for BC batteries according to claim 5, characterized in that: At least one of the following conditions is met: (1) In step (b), the diamond wire used for cutting includes a resin bonded diamond wire, and the wire diameter of the diamond wire is 50 to 80 μm; (2) In step (b), the cutting speed is 1.2-1.5 m / s; (3) In step (b), the coolant used for cutting includes polyethylene glycol, and the coolant also contains silicon carbide abrasive and / or nano-SiO2 particles, wherein the median particle size of the silicon carbide abrasive is 3-5 μm, and the median particle size of the nano-SiO2 particles is 80-100 nm; (4) In step (b), the surface treatment method includes: polishing, chemical thinning and texturing in sequence; wherein, the polishing method includes: double-sided chemical mechanical polishing, and the polishing is performed to a surface roughness Ra < 0.5 nm; the chemical thinning method includes: using a mixed acid solution of HF and HNO3 to isotropically etch both sides to remove the cutting damage layer; the texturing method includes: using laser etching to form an inverted pyramid texturing structure on the front side, wherein the height of the inverted pyramid texturing structure is 23~25 μm.

8. The method for preparing a large-size N-type silicon wafer for BC batteries according to claim 5, characterized in that: At least one of the following conditions is met: (1) In step (c), the front passivation layer includes Al2O3 / SiN x The back passivation layer includes SiO2 / polysilicon / SiN x laminated; (2) In step (d), the selective laser doping method includes: selectively ablating a portion of the back passivation layer by pulse laser, and doping phosphorus to form N + Local heavily doped area; wherein the wavelength of the pulsed laser is 530~540nm, and the energy density of the pulsed laser is 2.8~3J / cm 2 , the scanning speed of the pulse laser is 5~6m / s; (3) In step (e), during the plasma enhanced chemical vapor deposition process, the partition pressure is controlled to be 0.1~0.3 bar.

9. The method for preparing a large-size N-type silicon wafer for BC batteries according to claim 5, characterized in that: After step (e), the method further includes step (f), preparing a staggered point contact back electrode: using an ultraviolet laser to open a plurality of staggered grooves on the back of the silicon wafer, and then sequentially performing copper electroplating and silver coating to form a copper-plated silver electrode material; The wavelength of the ultraviolet laser is 350-360 nm, the pulse width is 8-10 ps, ​​and the energy is 0.8-1 μJ. The width of each groove is 20-32 μm, the ratio of the length to the width of each groove is 2:1, and the distance between two adjacent grooves is 1.4-1.6 mm; The electroplating solution used for copper electroplating is a mixture of CuSO4, H2SO4 and additives; the concentration of CuSO4 in the mixture of CuSO4, H2SO4 and additives is 150-250 g / L, and the concentration of H2SO4 in the mixture of CuSO4, H2SO4 and additives is 50-100 g / L; the additives include PEG and a chlorine source, the chlorine source includes HCl and / or NaCl, the concentration of PEG in the mixture of CuSO4, H2SO4 and additives is 0.05-0.5 g / L, and the Cl in the mixture of CuSO4, H2SO4 and additives is 0. - The concentration is 0.03~0.1g / L; The current density of the copper electroplating is 1.9~2.1A / dm 2 , the copper electroplating time is 15~15.5min; The silver covering method comprises: immersing the silicon wafer in a mixed solution of AgNO3 and a complexing agent by immersion plating to perform a replacement reaction; the complexing agent comprises ammonia water, the concentration of AgNO3 in the mixed solution of AgNO3 and the complexing agent is 0.3-0.35 mol / L, and the NH3 in the mixed solution of AgNO3 and the complexing agent reacts with AgNO3 to form a silver coating. + The molar ratio is ≥2:

1.

10. A BC battery, characterized in that: The invention comprises a large-size N-type silicon wafer for BC batteries as claimed in any one of claims 1 to 4.

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