GaN HEMT trap density characterization method based on drain-source resistance change
By monitoring the changes in the drain-source resistance of GaN HEMTs and combining them with Bayesian iteration technology, the problems of complex trap density characterization and low resolution in existing technologies are solved, and simple and efficient trap density calculation is achieved, improving the effects of device reliability assessment and process optimization.
Patent Information
- Application Number
- CN202510603211.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-12
- Publication Date
- 2025-10-10
AI Technical Summary
Existing technologies have difficulty accurately characterizing the trap density in GaN HEMT devices, especially quantifying the contribution of a single trap to the device's dynamic resistance. Furthermore, the testing methods are complex and have low resolution.
By monitoring the dynamic changes of the drain-source resistance of GaN HEMT under constant bias conditions and combining the Bayesian iteration technique, the transient contribution of each trap energy level to the drain-source resistance is separated, and the trap density of each energy level is calculated.
It achieves simple and efficient trap density characterization, which can directly reflect the impact of traps on the dynamic conduction characteristics of the device and provide data support for device reliability evaluation and process optimization.
Smart Images
Figure CN120761808A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to GaN HEMT drain-source resistance testing and trap density characterization, and belongs to the field of power semiconductor device testing and reliability. Background Art
[0002] Gallium nitride high electron mobility transistors (GaN HEMTs) have important applications in 5G communications, power electronics, aerospace, and other fields due to their high breakdown field strength, high electron saturation velocity, and excellent high-temperature resistance. However, the charge traps present in GaN materials and heterojunction interfaces can significantly affect the dynamic characteristics of the device, leading to problems such as current collapse, threshold voltage drift, and transconductance degradation. These traps mainly originate from material defects, surface states, or deep energy level centers in the buffer layer. The process of capturing and releasing carriers changes the two-dimensional electron gas (2DEG) concentration, thereby affecting the on-resistance and switching characteristics of the device. Therefore, accurately characterizing the trap density and its energy level distribution is crucial to optimizing device reliability.
[0003] Currently, the main methods for characterizing GaN HEMT trap density include capacitance-voltage (CV) testing, deep-level transient spectroscopy (DLTS), optical excitation techniques, and transient current testing. However, these methods have significant limitations: CV testing has difficulty distinguishing between interface states and bulk traps; while DLTS can provide trap energy level information, it requires complex peripheral circuitry and a low-temperature environment, resulting in low test efficiency; and optical methods are limited by the wavelength of the light source and the efficiency of carrier excitation. Furthermore, while transient current methods can only obtain trap amplitudes to qualitatively reflect the magnitude of the trap density, quantitative calculation of the trap density has not yet been achieved. Furthermore, existing technologies focus primarily on the overall trap effect, making it difficult to quantify the contribution of individual traps to the device's dynamic resistance. Therefore, there is an urgent need to develop a simple, efficient method that can distinguish between different trap energy level densities to guide device process optimization and reliability improvement.
[0004] To address the above issues, the present invention proposes a method for calculating the trap density of GaN HEMTs based on changes in drain-source resistance. By monitoring the dynamic changes in the drain-source resistance of the GaN HEMT under constant bias conditions and combining Bayesian iteration techniques, the contribution of each trap energy level to the transient drain-source resistance is isolated, and the trap density at each energy level is calculated. Compared with traditional methods, this method does not require a low-temperature environment and can directly reflect the impact of traps on the device's conduction characteristics, offering the advantages of simple testing and high resolution. This method is suitable for dynamic reliability assessment of power switching devices and provides data support for trap suppression processes such as GaN HEMT surface passivation and buffer layer optimization. Summary of the Invention
[0005] The present invention discloses a GaN HEMT trap density characterization method based on drain-source resistance changes, aiming to solve the problems of complex and low-resolution existing characterization technologies. This method monitors the transient response of the drain-source resistance under constant bias conditions, combines it with a Bayesian iterative algorithm, separates the contribution of different trap energy levels to the transient change of the drain-source resistance, and calculates the trap density of each energy level. Compared with traditional DLTS, CV and other methods, the present invention does not require a low-temperature environment or a complex test system, can directly reflect the impact of traps on the dynamic conduction characteristics of the device, and has the advantages of simple testing, strong applicability, and high resolution. This method provides an effective characterization means for the reliability assessment of GaN HEMT, and also provides a reference for GaN HEMT performance improvement and process optimization.
[0006] A GaN HEMT trap density characterization method based on drain-source resistance variation is characterized by:
[0007] 1. Connect the device under test to the gate drive, gate-source voltage, drain-source voltage, drain-source voltage control switch, test current, and test current control switch. The gate-source voltage is connected to the device under test via the gate drive and provides a gate fill voltage for the device under test. The drain-source voltage control switch is connected to the drain-source voltage and the device under test and controls the application of the drain voltage during the trap fill phase and the switching of the drain test current during the trap test phase. Furthermore, the test current control switch is connected to the test current via the drain-source voltage control switch and drain-source voltage to the device under test and provides a constant test current to the device drain and source after the trap fill phase switches to the trap test phase.
[0008] 2. After the device under test is connected to the test circuit, a gate fill voltage Vgf is provided through the gate drive and gate-source voltage, and a drain fill voltage Vdf is provided through the drain-source voltage and the drain-source voltage control switch, with a fill time of tf. The gate fill voltage Vgf ranges from -10V≤Vgf≤-1V, the drain fill voltage Vdf ranges from 0V≤Vdf≤50V, and the fill time tf ranges from 1s≤tf≤200s. After the tf time is filled, a drain test current Idm is applied to the device under test through the test current and the test current control switch, and a gate test voltage Vgm is provided through the gate-source voltage for a test time of tm. The transient drain-source voltage change over time Vds(t) is obtained, and the transient change curve of the drain-source resistance Rds(t) = Vds(t) / Idm is extracted. The starting time of this curve is the switching time t0. Among them, the range of the gate test voltage Vgm is -2V≤Vgm≤1V, the range of the drain test current Idm is 20mA≤Idm≤200mA, the starting time of the transient change curve of the drain-source resistance is the switching time t0, which is in the range of 2μs≤t0≤20μs, and the range of the test time tm is t0≤tf≤200s.
[0009] 3. Based on this, the transient change in drain-source resistance under this bias condition, ΔRds(t), can be obtained by subtracting the drain-source resistance Vds(t) corresponding to the start time from the drain-source resistance Vds(t) corresponding to time t: ΔRds(t=ti) = Vds(t=ti) - Vds(t=t0), where t0≤ti≤tf, and 0≤ΔRds(t=ti)≤10. Under this bias condition, the drain-source resistance shows a monotonically decreasing trend over time, indicating that trapped electrons within the device are gradually released.
[0010] 4. Based on the transient threshold voltage change ΔRds(t), a time constant spectrum is constructed using the Bayesian iterative method. The vertical axis values are summed, swapped with the horizontal axis, and differentiated to construct a differential amplitude spectrum. The number of trap peaks is identified as m, indicating that m electron traps are identified within the device under this bias condition. These are named Ei. For example, the difference in the horizontal axis corresponding to the i-th peak is the amplitude of the Ei electron trap, or the change in drain-source resistance caused by the Ei trap, ΔRds(t=tm)-i, where 1≤i≤m and 1≤m≤10. The specific results of the drain-source resistance change are visually represented in the form of a bar graph.
[0011] 5. Based on the change in drain-source resistance caused by each trap, the formula Calculate the trap density nt-i of each energy level. s is the two-dimensional electron gas concentration, L dep,max is the maximum lateral depletion region width related to the fill voltage, q is the charge, W is the device gate width, and μ is the carrier mobility. Based on the change in drain-source resistance ΔRds(t=tm)-i caused by the i traps obtained in step 4, the trap density nt-i can be calculated, where W is in the range of 10mm≤W≤500mm and nt-i is in the range of 1E10≤nt-i≤1E18.
[0012] This paper proposes, for the first time, a method for characterizing GaN HEMT trap density based on changes in drain-source resistance. By monitoring the transient response of the drain-source resistance under constant bias conditions and combining it with Bayesian iteration techniques, this method effectively separates the contribution of each trap energy level to the change in drain-source resistance, thereby accurately calculating the trap density at each energy level. The present invention has the beneficial effects of being simple, fast, and easy to operate, directly reflecting the impact of traps on the device's dynamic conduction characteristics, providing an efficient and accurate characterization tool for GaN HEMT device reliability assessment and process optimization. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] Figure 1: This is a diagram of the test device involved in the present invention, in which: 1-device under test, 2-gate drive, 3-gate-source voltage, 4-drain-source voltage, 5-drain-source voltage control switch, 6-test current, 7-test current control switch.
[0014] Figure 2 : The drain-source resistance change curve and differential amplitude spectrum involved in the present invention.
[0015] Figure 3 : The present invention involves the GaN HEMT drain-source resistance change and trap density results. DETAILED DESCRIPTION
[0016] The following, combined with the accompanying drawings and specific embodiments, provides a more detailed description of GaN HEMT trap density characterization based on drain-source resistance variations. A depletion-mode GaN HEMT is selected as the device under test, with an off-state breakdown voltage of 100V and a maximum operating current of 6A. The method of the present invention includes the following steps:
[0017] Step 1: Connect the device under test to the test circuit, as shown in the diagram below. Figure 1 As shown. Connect 1-DUT with 2-gate drive, 3-gate-source voltage, 4-drain-source voltage, 5-drain-source voltage control switch, 6-test current, and 7-test current control switch. Among them, 3-gate-source voltage is connected to 1-DUT through 2-gate drive and provides gate fill voltage for the DUT; 5-drain-source voltage control switch is connected to 4-drain-source voltage and 1-DUT, and controls the application of drain voltage during the trap fill phase and the switching of drain test current during the trap test phase. In addition, 7-test current control switch is connected to 6-test current through 5-drain-source voltage control switch and 4-drain-source voltage and 1-DUT, and provides a constant test current to the device drain and source after the trap fill is switched to the trap test.
[0018] Step 2: After connecting the DUT to the test circuit (1), a -7V gate fill voltage Vgf is provided via (2) Gate Drive and (3) Gate-Source Voltage. A drain fill voltage Vdf of 11V is provided via (4) Drain-Source Voltage and (5) Drain-Source Voltage Control Switch, with a fill time tf of 60s. After the tf time is filled, a 100mA drain test current Idm is applied to the DUT (1) via (6) Test Current and (7) Test Current Control Switches, and a 0V gate test voltage Vgm is provided via (3) Gate-Source Voltage. The test time tm is 100s. The transient drain-source voltage change over time, Vds(t), is obtained, and the transient change curve of the drain-source resistance, Rds(t) = Vds(t) / Idm, is extracted. The starting time of this curve is the switching time t0, which is 5μs under the bias conditions.
[0019] Step 3: Based on this, the drain-source resistance Vds(t) corresponding to the time t can be subtracted from the drain-source resistance Vds(t) corresponding to the start time to obtain the transient change in drain-source resistance ΔRds(t) under the bias condition. Therefore, the drain-source resistance change corresponding to t=100s is ΔRds(t=100s)=Vds(t=100s)-Vds(t0=5μs), and the result is as follows: Figure 2 As shown in (a), under this bias condition, the drain-source resistance decreases monotonically over time, indicating that trapped electrons in the device are gradually released. The transient threshold voltage change ΔRds (t = 100s) collected during the tm time is 0.11659.
[0020] Step 4: Based on the transient threshold voltage change ΔRds(t), the time constant spectrum is constructed using the Bayesian iteration method. The vertical axis values are added and then exchanged with the horizontal axis and differential calculation is performed to construct the differential amplitude spectrum as shown in the following figure: Figure 2 (b) shows that the number of trap peaks m = 3 is identified, indicating that three electron traps are identified inside the device under this bias condition and are named E1, E2, and E3. For example, the difference in the horizontal coordinates corresponding to the i-th peak is the amplitude of the Ei electron trap, that is, the change in drain-source resistance caused by the Ei trap ΔRds(t = tm)-i. The specific results of the drain-source resistance change are intuitively represented in the form of a bar graph as shown below. Figure 3 The results show that the drain-source resistance change ΔRds(t=100s)-1 caused by E1 trap filling is 0.07083, the drain-source resistance change ΔRds(t=100s)-2 caused by E2 trap filling is 0.01712, and the drain-source resistance change ΔRds(t=100s)-3 caused by E3 trap filling is 0.029.
[0021] Step 5: Based on the change in drain-source resistance caused by each trap, the formula Calculate the trap density of each energy level. s is the two-dimensional electron gas concentration, L dep,max is the maximum lateral depletion region width related to the filling voltage, q is the charge, W is the device gate width, and μ is the carrier mobility. Based on the drain-source resistance change ΔRds(t=tm)-i caused by the i traps obtained in step 4, the trap density nt-i can be calculated respectively, and the results are as follows Figure 3 (b) shows that the trap density nt-1 of E1 is 1.77E12, the trap density nt-2 of E2 is 8.28E11, and the trap density of E3 is 2.39E12.
Claims
1. A method for characterizing GaN HEMT trap density based on drain-source resistance variation, characterized by: 1) connecting the device under test with a gate drive, a gate-source voltage, a drain-source voltage, a drain-source voltage control switch, a test current, and a test current control switch; wherein the gate-source voltage is connected to the device under test through the gate drive and provides a gate fill voltage for the device under test; the drain-source voltage control switch is connected to the drain-source voltage and the device under test and controls the application of the drain voltage during the trap fill phase and the switching of the drain test current during the trap test phase; the test current control switch is connected to the test current through the drain-source voltage control switch and the drain-source voltage and the device under test, and provides a constant test current to the drain and source of the device under test after the trap fill is switched to the trap test; 2) After the device under test is connected to the test circuit, a gate fill voltage Vgf is provided through the gate drive and gate-source voltage, and a drain fill voltage Vdf is provided through the drain-source voltage and the drain-source voltage control switch, and the filling time is tf; after the tf time is filled, a drain test current Idm is applied to the device under test through the test current and the test current control switch, and a gate test voltage Vgm is provided through the gate-source voltage, and the test time is tm; the transient drain-source voltage change with time Vds(t) is obtained, and the transient change curve of the drain-source resistance Rds(t) = Vds(t) / Idm is extracted, and the starting time of the curve is the switching time t0; 3) Subtract the drain-source resistance Vds(t) corresponding to the start time from the drain-source resistance Vds(t) corresponding to time t to obtain the transient change in drain-source resistance ΔRds(t) under the bias condition, i.e., ΔRds(t=ti)=Vds(t=ti)-Vds(t=t0). Under this bias condition, the drain-source resistance shows a monotonically decreasing trend with time, indicating that the trapped electrons inside the device under test are gradually released; 4) Based on the transient threshold voltage change ΔRds(t), a time constant spectrum is constructed using the Bayesian iteration method. The vertical axis values are added, swapped with the horizontal axis, and differentiated to construct a differential amplitude spectrum. The number of trap peaks is identified as m, indicating that m electron traps are identified within the device under this bias condition, and are named Ei. That is, the difference in the horizontal axis corresponding to the i-th peak is the amplitude of the Ei electron trap. The specific results of the drain-source resistance change are intuitively represented in the form of a bar graph. 5) Based on the drain-source resistance change ΔRds(t=tm)-i caused by each trap, the formula Calculate the trap density nt-i of each energy level; where n s is the two-dimensional electron gas concentration, L dep,max is the maximum lateral depletion region width related to the filling voltage, q is the charge amount, W is the device gate width, and μ is the carrier mobility.
2. The method for characterizing GaN HEMT trap density based on drain-source resistance variation according to claim 1, wherein: The method for obtaining the trap density is based on the transient change Rds(t) of the drain-source resistance of the GaN HEMT under test. By monitoring the transient response Rds(t) of the drain-source voltage under a constant drain-source test current Idm during the trap release process, the transient change of the drain-source resistance is obtained: Rds(t) = Vds(t) / Idm.
3. The method for characterizing GaN HEMT trap density based on drain-source resistance variation according to claim 1, wherein: The gate fill voltage Vgf ranges from -10V≤Vgf≤-1V, the drain fill voltage Vdf ranges from 0V≤Vdf≤50V, and the fill time tf ranges from 1s≤tf≤200s; The range of the gate test voltage Vgm is -2V≤Vgm≤1V, the range of the drain test current Idm is 20mA≤Idm≤200mA, the starting time of the transient change curve of the drain-source resistance is the switching time t0, which is in the range of 2μs≤t0≤20μs, and the range of the test time tm is t0≤tf≤200s.
4. The method for characterizing GaN HEMT trap density based on drain-source resistance variation according to claim 1, wherein: The trap density is quantitatively calculated by obtaining the transient change in the drain-source resistance of the GaN HEMT, ΔRds(t), which is the drain-source resistance Vds(t) corresponding to time t minus the drain-source resistance Vds(t) corresponding to the start time (t=t0). ΔRds(t=ti)=Vds(t=ti)-Vds(t=t0), where t0≤ti≤tf, and 0≤ΔRds(t=ti)≤10.
5. The method for characterizing GaN HEMT trap density based on drain-source resistance variation according to claim 1, wherein: The Bayesian iteration method is used to process the transient change of drain-source resistance, and the drain-source resistance change caused by each trap is quantitatively obtained from the difference in the horizontal coordinates of the differential amplitude spectrum peak value, ΔRds(t=tm)-i, where 1≤i≤m, m is the number of identified trap peaks, and 1≤m≤10.
6. The method for characterizing GaN HEMT trap density based on drain-source resistance variation according to claim 1, wherein: Based on the drain-source resistance change ΔRds(t=tm)-i of each trap identified in the peak spectrum, the density of each trap can be directly calculated. The range of W is 10mm≤W≤500mm, and the range of trap density nti is 1E10≤nt-i≤1E18.