Thread scheduling system and method, electronic equipment and storage medium

Abstract

The invention relates to a thread scheduling system and method, electronic equipment and a storage medium. The system comprises an instruction cache module, an instruction register module and an execution module. The instruction caching module is used for pre-reading instruction data of a plurality of threads; the instruction register module is used for storing pre-read instruction data of the multiple threads and determining a target thread and a target instruction of the target thread according to the instruction data of the multiple threads in a clock period; and the instruction register module is used for sending a target instruction of the target thread to the execution module. According to the embodiment of the invention, the time consumption of thread scheduling in an instruction pipeline scene is effectively reduced, and the utilization rate of the execution module is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a thread scheduling system and method, an electronic device, and a storage medium. Background Art

[0002] In graphics processing unit (GPU) design, the instruction cache is crucial for thread execution efficiency in the streaming multiprocessor (SM) instruction pipeline. Traditional GPUs suffer from high instruction pipeline latency. For common high-concurrency graphics scenarios, high thread parallelism can mask latency. However, under new demands, common computing tasks lack high thread parallelism. In these situations, high instruction pipeline latency can expose numerous issues, such as insufficient Arithmetic and Logic Unit (ALU) resource utilization and long execution times. Therefore, to better meet these demands, higher requirements are being placed on instruction pipeline latency. Summary of the Invention

[0003] The present disclosure provides a technical solution of a thread scheduling system and method, an electronic device, and a storage medium.

[0004] According to one aspect of the present disclosure, a thread scheduling system is provided, comprising: an instruction cache module, an instruction register module, and an execution module; the instruction cache module is used to pre-read instruction data of multiple threads; the instruction register module is used to store the pre-read instruction data of the multiple threads, and within one clock cycle, determine a target thread and a target instruction of the target thread based on the instruction data of the multiple threads; the instruction register module is used to send the target instruction of the target thread to the execution module.

[0005] In one possible implementation, the instruction register module is specifically used to: perform an instruction dependency check on the instruction with the highest instruction sequence priority in the instruction data stored for each thread within one clock cycle; determine the thread that passes the instruction dependency check as the target thread, and determine the instruction with the highest instruction sequence priority in the instruction data of the thread as the target instruction of the target thread.

[0006] In one possible implementation, the system includes: a thread scheduling module; the thread scheduling module is used to determine a thread for this scheduling within a clock cycle according to a preset scheduling rule, and allocate a register pointer for the thread for this scheduling, wherein the register pointer allocated to the thread for this scheduling is used to indicate the instruction sequence priority of the instructions that the thread needs to read for this scheduling.

[0007] In one possible implementation, the instruction cache module is specifically used to: for any scheduling of any thread, read the instructions that the thread needs to read for this scheduling according to the program counter PC address of the thread this scheduling; and send the instructions read by the thread this scheduling to the instruction register module for storage according to the register pointer allocated for the thread this scheduling.

[0008] In one possible implementation, the instruction cache module includes: an instruction cache tag submodule, a judgment submodule, and an instruction cache storage submodule; the instruction cache tag submodule is used to perform a cache search for the thread for any scheduling of any thread based on the PC address of the thread for this scheduling, and determine the cache search result for the thread for this scheduling; the judgment submodule is used to read the instructions that the thread needs to read for this scheduling from the instruction cache storage submodule based on the first instruction read request of the thread for this scheduling for any scheduling of any thread.

[0009] In one possible implementation, the instruction cache tag submodule is specifically used to: for any scheduling of any thread, when the cache search result of the thread's current scheduling is a cache hit, send the first instruction read request of the thread's current scheduling to the judgment submodule, wherein the first instruction read request of the thread's current scheduling includes: the cache line identifier of the thread's current scheduling hit, and the PC address of the thread's current scheduling.

[0010] In one possible implementation, the instruction cache module includes: a search failure processing sub-module; the instruction cache tag sub-module is specifically used to: for any scheduling of any thread, when the cache search result of the thread's current scheduling is a cache miss, determine a target cache line for the thread's current scheduling; send a search failure record request for the thread's current scheduling to the search failure processing sub-module, wherein the search failure record request for the thread's current scheduling includes: the target cache line identifier corresponding to the thread's current scheduling and the PC address of the thread's current scheduling.

[0011] In one possible implementation, the instruction cache tag submodule is also used to: for any scheduling of any thread, when the cache search result of the thread's current scheduling is a cache miss, send a second instruction read request for the thread's current scheduling to the next-level instruction storage module corresponding to the instruction cache module, wherein the second instruction read request for the thread's current scheduling includes: the PC address of the thread's current scheduling.

[0012] In one possible implementation, the search failure processing submodule is specifically used to: record the search failure record requests of multiple threads; within one clock cycle, check whether the earliest search failure record request corresponding to the scheduling time of each thread meets the preset conditions, wherein the preset conditions are used to indicate that the data corresponding to the thread's current scheduling has been stored in the cache storage module; determine a thread that meets the preset conditions, and send the first instruction read request of the thread's current scheduling to the judgment submodule.

[0013] In one possible implementation, when the judgment submodule simultaneously receives the first instruction read request sent by the instruction cache tag submodule and the first instruction read request sent by the search failure processing submodule within one clock cycle, the priority of the first instruction read request sent by the search failure processing submodule is higher than the first instruction read request sent by the instruction cache tag submodule.

[0014] According to one aspect of the present disclosure, a thread scheduling method is provided, comprising: utilizing an instruction cache module to pre-read instruction data of multiple threads; utilizing an instruction register module to store the pre-read instruction data of the multiple threads, and determining a target thread and a target instruction of the target thread based on the instruction data of the multiple threads within one clock cycle; and utilizing the instruction register module to send the target instruction of the target thread to an execution module.

[0015] According to one aspect of the present disclosure, an electronic device is provided, including: the above-mentioned thread scheduling system.

[0016] According to one aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to call the instructions stored in the memory to execute the above method.

[0017] According to one aspect of the present disclosure, a computer-readable storage medium is provided, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the above method is implemented.

[0018] In an embodiment of the present disclosure, a thread scheduling system includes: an instruction cache module, an instruction register module, and an execution module; the instruction data of multiple threads are pre-read through the instruction cache module, and the pre-read instruction data of multiple threads are stored in the instruction register module, so that the instruction register module can determine the target thread and the target instruction of the target thread from the stored instruction data of multiple threads within one clock cycle, and send the target instruction of the target thread to the execution module, effectively reducing the thread scheduling time in the instruction pipeline scenario and improving the utilization rate of the execution module.

[0019] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, rather than limiting the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings herein are incorporated into and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and, together with the specification, are used to explain the technical solutions of the present disclosure.

[0021] Figure 1 A block diagram of a thread scheduling system according to an embodiment of the present disclosure is shown.

[0022] Figure 2 A schematic diagram of a thread scheduling system according to an embodiment of the present disclosure is shown.

[0023] Figure 3 A flowchart of a thread scheduling method according to an embodiment of the present disclosure is shown.

[0024] Figure 4 A block diagram of an electronic device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0025] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0026] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0027] The term "and / or" herein simply describes an association relationship between associated objects, indicating that three relationships can exist. For example, "A and / or B" can represent the existence of three situations: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" herein refers to any combination of at least two of any one or more of a plurality of items. For example, "at least one of A, B, and C" can represent any one or more elements selected from the set consisting of A, B, and C.

[0028] In addition, numerous specific details are provided in the following detailed description to better illustrate the present disclosure. Those skilled in the art will appreciate that the present disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art are not described in detail in order to highlight the main points of the present disclosure.

[0029] Multiple computing tasks can be executed simultaneously within an SM. A single computing task (for example, a single assembly instruction) may be executed by several threads, each executing the same code segment (for example, each thread corresponds to the same 1,000 instructions). A thread is the smallest unit of scheduling in the operating system. A thread consists of a thread identity document (ID) and a current instruction pointer (IP), which indicates the address of the next instruction to be executed by the thread. Each thread has its own independent program counter (PC), also known as the instruction pointer register (IPR). The PC primarily stores the address of the next instruction to be executed. For any thread, after the CPU completes executing the current instruction, it reads the address of the next instruction from the thread's PC so that the CPU can correctly execute the next instruction. During thread execution, the thread's PC is continuously updated to point to the address of the next instruction to be executed, ensuring that the thread executes instructions in the correct order.

[0030] Instruction pipelining improves the processor's efficiency in executing instructions by breaking down the operation of an instruction into multiple small steps, each completed by a dedicated circuit. For example, the execution of an instruction goes through three stages: instruction fetch, decoding, and execution. Each stage takes one clock cycle. Without instruction pipelining, this instruction would take three clock cycles to execute. However, with instruction pipelining, as one instruction completes the "fetch" phase and enters the "decoding" phase, the next instruction can be "fetched," thus improving instruction execution efficiency.

[0031] Stream processors (SMs) are hardware units designed specifically to process data streams (e.g., video, audio, or graphics data). They perform a large number of simple operations in a highly parallel manner to rapidly process the data stream. Stream processors are widely used in high-performance computing devices such as GPUs and application-specific integrated circuits (ASICs).

[0032] In GPU design, the instruction cache is a module in the SM used to fetch instructions. Its upstream is the thread scheduling module. When the thread scheduling module schedules the current instruction pointer (PC address) of a thread, it needs to do a cache lookup in the instruction cache. When the cache hits (hit), the corresponding instruction is read and sent downstream; when the cache misses (miss), the failure flag is also sent downstream, and after unified processing by the downstream module, it is fed back to the thread scheduling module. In related technologies, for a PC address that misses the cache, it is necessary to wait for it to be scheduled to the thread again before it can be successfully executed by the subsequent module, wasting a scheduling opportunity.

[0033] Therefore, an instruction may be rescheduled because the instruction cache did not contain the information for it when it was first scheduled. Since each scheduling can be considered a valuable opportunity, scheduling efficiency needs to be improved. In a traditional instruction pipeline, for a particular thread, the pipeline structure is serially scheduled. If an instruction cache misses, subsequent instructions cannot be scheduled and instruction information cannot be read, which is not conducive to reducing the latency of the entire thread.

[0034] For example, the current computing task corresponds to 10 threads. Within one clock cycle, the thread scheduling module selects one thread from the 10 threads for scheduling. If the instruction that the thread needs to read for this scheduling hits the instruction cache, the instruction read from the instruction cache for this thread's scheduling is further checked for instruction dependency. If the instruction dependency check fails, the PC address of this instruction and the related reasons are fed back to the thread scheduling module. The thread scheduling module will have the opportunity to schedule the PC address again after the related reasons are met. The thread scheduling module failed to schedule this thread this time, and this scheduling of this thread caused the other 9 threads that had cache hits and passed the instruction dependency check to lose an opportunity to be scheduled.

[0035] To solve the above problems, the present disclosure provides a thread scheduling system that can reduce thread scheduling time in instruction pipeline scenarios and improve the utilization rate of execution modules. The thread scheduling system provided by the present disclosure is described in detail below.

[0036] Figure 1 FIG. 1 is a block diagram of a thread scheduling system according to an embodiment of the present disclosure. Figure 1 As shown, the thread scheduling system includes: an instruction cache module, an instruction register module, and an execution module; the instruction cache module is used to pre-read the instruction data of multiple threads; the instruction register module is used to store the pre-read instruction data of multiple threads, and within one clock cycle, determine the target thread and the target instruction of the target thread based on the instruction data of multiple threads; the instruction register module is used to send the target instruction of the target thread to the execution module.

[0037] In an embodiment of the present disclosure, a thread scheduling system includes: an instruction cache module, an instruction register module, and an execution module; the instruction data of multiple threads are pre-read through the instruction cache module, and the pre-read instruction data of multiple threads are stored in the instruction register module, so that the instruction register module can determine the target thread and the target instruction of the target thread from the stored instruction data of multiple threads within one clock cycle, and send the target instruction of the target thread to the execution module, effectively reducing the thread scheduling time in the instruction pipeline scenario and improving the utilization rate of the execution module.

[0038] In one possible implementation, the instruction register module is specifically used to: perform an instruction dependency check on the instruction with the highest instruction sequence priority in the instruction data stored for each thread within one clock cycle; determine the thread that passes the instruction dependency check as the target thread, and determine the instruction with the highest instruction sequence priority in the instruction data of the thread as the target instruction of the target thread.

[0039] Because the instruction register module stores instruction data for multiple threads, within a clock cycle, the instruction register can perform an instruction dependency check on the instruction with the highest instruction order priority in the stored instruction data for each thread. As long as any one of the multiple threads passes the dependency check, that thread is determined as the target thread, and the instruction with the highest instruction order priority for that thread is determined as the target instruction of the target thread, thereby completing the scheduling of the target instruction in the target thread. Compared to the thread scheduling methods used in related technologies, the embodiments of the present disclosure utilize the instruction register module to reduce the probability of threads that meet the scheduling conditions not being scheduled.

[0040] In addition, in the related art, threads that meet the scheduling conditions cannot be scheduled, resulting in a low utilization rate of the execution module. For example, if the thread scheduling module scheduling success rate is 70%, the execution module utilization rate can be simply considered to be 70%.

[0041] Since the embodiment of the present disclosure is provided with an instruction register module, it can be considered that during stable operation, the instruction register module can always select the target instruction of the target thread and send it to the execution module in each clock cycle. Therefore, it can be considered that the utilization rate of the execution module is approximately 100%.

[0042] In one example, if multiple threads are determined to have passed dependency checking within a clock cycle, a thread that passed the dependency checking is selected as the target thread based on a preset selection condition, and the target instruction of the target thread is sent to the execution module. The preset selection condition can be flexibly set based on actual application scenarios and is not specifically limited in this disclosure.

[0043] In one possible implementation, the thread scheduling system includes: a thread scheduling module; the thread scheduling module is used to determine a thread for current scheduling according to preset scheduling rules within a clock cycle, and allocate a register pointer for the current scheduling of the thread, wherein the register pointer allocated to the current scheduling of the thread is used to indicate the instruction sequence priority of the instructions that the thread needs to read for the current scheduling.

[0044] The thread scheduling module in the thread scheduling system is an upstream module of the instruction cache module. It is responsible for scheduling the various threads within the SM. Within a clock cycle, the thread scheduling module selects a thread that meets the requirements from among multiple threads to be scheduled according to preset scheduling rules. The preset scheduling rules can be flexibly configured according to the actual application scenario and are not specifically limited in this disclosure.

[0045] The thread scheduling module allocates a register pointer for each scheduling of each thread to indicate the instruction sequence priority of multiple instructions in each thread, thereby ensuring the execution order of multiple instructions in each thread.

[0046] For example, thread 1 includes 1000 instructions. When the thread scheduling module schedules the first instruction (ins1) in thread 1, it assigns register pointer 1 to ins1. When the thread scheduling module schedules the second instruction (ins2) in thread 1, it assigns register pointer 2 to ins2. When the thread scheduling module schedules the third instruction (ins3) in thread 1, it assigns register pointer 3 to ins3. And so on.

[0047] Since a register pointer is assigned to each instruction in thread 1, assume that for the three instructions above, the first instruction cache hits (ins1 hit), the second misses (ins2 misses), and the third hits (ins3 hits) in the instruction cache. In this case, ins3 can overtake in the instruction register. In other words, ins3 enters the instruction register for storage before ins2. However, when ins2 enters the instruction register, it can still find the correct storage location based on the assigned register pointer 2, indicating that ins2's instruction order priority is higher than ins3.

[0048] Figure 2 FIG. 1 is a schematic diagram showing a thread scheduling system according to an embodiment of the present disclosure. Figure 2 As shown, the thread scheduling system includes: a thread scheduling module and an instruction cache module.

[0049] Within one clock cycle, for the thread selected by the thread scheduling module for this scheduling, the thread scheduling module sends the PC address of the thread to the downstream instruction cache module based on the current instruction pointer of the thread, so as to complete the instruction fetch operation of the thread for this scheduling based on the instruction cache module.

[0050] For example, within a clock cycle, the thread scheduling module selects thread 1 from multiple threads that need to be scheduled according to the preset scheduling rules, and then the thread scheduling module sends a scheduling request to the instruction cache module. The scheduling request includes: thread 1 (thread identifier) ​​and the PC address of thread 1 scheduled this time.

[0051] like Figure 2 As shown, the thread scheduling module sends a scheduling request to the instruction cache module.

[0052] In addition, the thread scheduling module can also send relevant information of thread 1's current scheduling to the instruction register module: thread 1 (thread identifier), the PC address of thread 1's current scheduling, and the register pointer allocated to thread 1's current scheduling, so that the instructions of thread 1's current scheduling can be accurately stored in the corresponding position of the instruction register module later.

[0053] In one possible implementation, the instruction cache module is specifically used to: for any scheduling of any thread, read the instructions that the thread needs to read for this scheduling according to the PC address of the thread for this scheduling; and send the instructions read by the thread for this scheduling to the instruction register module for storage according to the register pointer allocated for this scheduling of the thread.

[0054] For any one thread for any one scheduling, the instruction cache module reads the instructions that the thread needs to read according to the PC address of the thread this time, and completes the instruction fetching operation of the thread this time. Further, the instruction cache module sends the instructions read by the thread this time to the instruction register module for storage according to the register pointer allocated by the thread this time, and prepares for the subsequent execution of the instructions of the thread this time.

[0055] As shown in Figure 2 The thread scheduling system includes an instruction register module. The instruction register module is used to store the instruction data of multiple threads read from the instruction cache module.

[0056] In a possible implementation, the instruction cache module includes an instruction cache tag submodule, a decision submodule, and an instruction cache storage submodule. The instruction cache tag submodule is used to, for any one thread for any one scheduling, perform cache lookup on the thread this time according to the PC address of the thread this time, and determine the cache lookup result of the thread this time. The decision submodule is used to, for any one thread for any one scheduling, read the instructions that the thread this time needs to read from the instruction cache storage submodule based on the first instruction read request of the thread this time.

[0057] The instruction cache storage submodule includes multiple cache lines, and each cache line is used to store instruction data. The instruction cache tag submodule has the same cache line structure as the instruction cache storage submodule, but the instruction cache tag submodule does not store instruction data, but is used to record the cache line information of each cache line in the instruction cache storage submodule.

[0058] For example, the instruction cache storage submodule includes N cache lines: cache lines 1-N, and each cache line is used to store instruction data. The instruction cache tag submodule also includes N cache lines, which correspond to the N cache lines included in the instruction cache storage submodule one by one, and are used to record the cache line information of the N cache lines in the instruction cache storage submodule. The cache line information in the instruction cache tag submodule can be as shown in Table 1.

[0059] Table 1

[0060] Cache line identifier Cache line status tag Lock count (lock_cnt) Cache line 1 valid tag1 1 Cache line 2 invalid 0 0 Cache line 3 invalid 0 0 …… …… …… …… Cache line N invalid 0 0

[0061] As shown in Table 1, for any cache line, the cache line status of the cache line in the instruction cache tag submodule is used to indicate whether the instruction data in the cache line in the instruction cache storage submodule is valid, or whether it has expired, etc. The cache line status of cache line 1 in the instruction cache tag submodule is valid, which is used to indicate that the instruction data in cache line 1 in the instruction cache storage submodule is valid; the cache line status of cache lines 2 / 3 in the instruction cache tag submodule is invalid, which is used to indicate that the instruction data in cache lines 2 / 3 in the instruction cache storage submodule is invalid, or the instruction data in cache lines 2 / 3 has expired, or there is no instruction data in cache lines 2 / 3. And so on, no further explanation is given.

[0062] As shown in Table 1, for any cache line, if instruction data is stored in the cache line in the instruction cache storage submodule, a corresponding tag is stored in the tag field corresponding to the cache line in the instruction cache tag submodule, and the tag is the upper several bits of the PC address.

[0063] As shown in Table 1, for any cache line, if the lock count corresponding to the cache line in the instruction cache tag submodule is non-zero, the instruction data stored in the cache line in the instruction cache storage submodule cannot be replaced.

[0064] For any scheduling of any thread, the thread scheduling module sends the PC address of the thread for this scheduling to the instruction cache tag submodule. The instruction cache tag submodule performs a cache search for the thread for this scheduling based on the tag (several bits higher) in the PC address to determine the cache search result for the thread for this scheduling.

[0065] For any scheduling of any thread, if the tag in the PC address of the thread's current scheduling is stored in the instruction cache tag submodule, the cache lookup result of the thread's current scheduling is determined to be a cache hit; otherwise, the cache lookup result of the thread's current scheduling is determined to be a cache miss.

[0066] Taking Table 1 above as an example, for thread 1 scheduling PC address 1, when the tag in PC address 1 is tag1, since tag1 is stored in the instruction cache tag submodule, it is determined that the cache search result of thread 1 scheduling PC address 1 is a cache hit, and the hit cache line is cache line 1.

[0067] Taking Table 1 above as an example, for thread 2's scheduling of PC address 2, when the tag in PC address 2 is tag2, since tag2 is not stored in the instruction cache tag submodule, it is determined that the cache search result of thread 2 scheduling PC address 2 is a cache miss.

[0068] In one possible implementation, the instruction cache tag submodule is specifically used to: for any scheduling of any thread, if the cache search result of the thread's current scheduling is a cache hit, send the first instruction read request of the thread's current scheduling to the judgment submodule, wherein the first instruction read request of the thread's current scheduling includes: the cache line identifier of the thread's current scheduling hit, and the PC address of the thread's current scheduling.

[0069] For any scheduling of any thread, if the cache search result of this scheduling of the thread is a cache hit, the instruction cache tag sub-module sends the first instruction read request of this scheduling of the thread to the judgment sub-module, so that the judgment sub-module can perform subsequent instruction fetching operations from the instruction cache storage sub-module based on the cache line identifier of this scheduling hit of the thread included in the first instruction read request and the PC address of this scheduling of the thread.

[0070] Taking the above-mentioned scheduling of PC address 1 by thread 1 as an example, since the cache search result of thread 1 scheduling PC address 1 is a cache hit, and the hit cache line is cache line 1, the instruction cache tag sub-module sends the first instruction read request for thread 1 scheduling PC address 1 to the judgment sub-module. The first instruction read request includes: thread 1 (thread identifier), cache line 1 (hit cache line identifier), and PC address 1.

[0071] like Figure 2 As shown, the instruction cache module includes an instruction cache tag submodule and a decision submodule, and the instruction cache tag submodule sends a first instruction read request to the decision submodule.

[0072] In one possible implementation, the instruction cache module includes: a search failure processing sub-module; an instruction cache tag sub-module, which is specifically used to: for any scheduling of any thread, if the cache search result of the thread's current scheduling is a cache miss, determine a target cache line for the thread's current scheduling; send a search failure record request for the thread's current scheduling to the search failure processing sub-module, wherein the search failure record request for the thread's current scheduling includes: the target cache line identifier corresponding to the thread's current scheduling and the PC address of the thread's current scheduling.

[0073] For any scheduling of any thread, if the cache lookup result of this thread scheduling is a cache miss, the instruction cache tag submodule determines a target cache line for this thread scheduling, which is used to subsequently store the instructions corresponding to the PC address of this thread scheduling.

[0074] Taking the above-mentioned scheduling of PC address 2 by thread 2 as an example, since the cache lookup result of PC address 2 scheduled by thread 2 is a cache miss, the instruction cache tag submodule determines a target cache line for thread 2 to schedule PC address 2: cache line 2, and updates the cache line state of cache line 2 to the waiting state (fetched), the tag to tag2, and the lock count to 1. At this time, Table 1 in the instruction cache tag submodule is updated to the following Table 2.

[0075] Table 2

[0076] Cache line identifier Cache line status tag Lock count (lock_cnt) Cache line 1 valid tag1 1 Cache line 2 Waiting (fetched) tag2 1 Cache line 3 invalid 0 0 …… …… …… …… Cache line N invalid 0 0

[0077] In a possible implementation, the search failure processing submodule is specifically configured to record search failure record requests of multiple threads.

[0078] The search failure processing submodule can record the search failure for each thread. The following Table 3 can exemplarily represent the search failure record of each thread by the search failure processing submodule.

[0079] Table 3

[0080]

[0081] As shown in Table 3, the search failure processing submodule has N entries for each thread: entry (1) to entry (N), which indicate the scheduling order of each search failure record in the thread. The specific value of N can be flexibly set according to actual conditions and is not specifically limited in this disclosure.

[0082] As shown in Table 3, the valid status corresponding to each record item of each thread is used to indicate whether the current search failure record is valid. When the valid status is 1, it indicates whether the current search failure record is valid; when the valid status is 0, it indicates whether the current search failure record is invalid.

[0083] For any record item of any thread, the valid state corresponding to the record item is 1, indicating that the scheduling instruction corresponding to the record item has not yet been stored in the instruction cache storage submodule.

[0084] For any scheduling of any thread, if the cache search result of this thread scheduling is a cache miss, the instruction cache tag sub-module sends a search failure record request for this thread scheduling to the search failure processing sub-module, wherein the search failure record request for this thread scheduling includes: the target cache line identifier corresponding to this thread scheduling and the PC address of this thread scheduling.

[0085] Taking the aforementioned thread 2 scheduling for PC address 2 as an example, since the cache lookup result for thread 2 scheduling for PC address 2 is a cache miss, the instruction cache tag sub-module sends a request to the lookup failure processing sub-module to record the lookup failure for thread 2 scheduling for PC address 2. The request includes: thread 2 (thread identifier), cache line 2 (target cache line identifier), and PC address 2. If thread 2 scheduling for PC address 2 is the first cache miss in thread 2, then Table 3 in the lookup failure processing sub-module is updated to Table 4 below.

[0086] Table 4

[0087]

[0088] As shown in Table 4, the tag corresponding to the first record entry (1) corresponding to thread 2 is updated to tag2, and the valid state is updated to 1. At this time, it means that the instruction corresponding to PC address 2 of thread 2 has not yet been stored in the instruction cache storage submodule.

[0089] In one possible implementation, the instruction cache tag submodule is also used to: for any scheduling of any thread, when the cache search result of the thread's current scheduling is a cache miss, send a second instruction read request for the thread's current scheduling to the next-level instruction storage module corresponding to the instruction cache module, wherein the second instruction read request for the thread's current scheduling includes: the PC address of the thread's current scheduling.

[0090] For any scheduling of any thread, if the cache search result of this thread scheduling is a cache miss, the instruction cache tag sub-module sends a second instruction read request for this thread scheduling to the next-level instruction storage module corresponding to the instruction cache module, so as to read the instruction of this thread scheduling from the next-level instruction storage module to the instruction cache storage sub-module.

[0091] like Figure 2 As shown, the instruction cache tag submodule sends a second instruction read request to the next-level instruction storage module.

[0092] Taking the above-mentioned scheduling of PC address 2 by thread 2 as an example, since the cache search result of PC address 2 scheduled by thread 2 is a cache miss, the instruction cache tag sub-module sends a second instruction read request for PC address 2 scheduled by thread 2 to the next-level instruction storage module corresponding to the instruction cache module. The second instruction read request for PC address 2 scheduled by thread 2 includes: thread 2 (thread identifier), cache line 2 (target cache line identifier), and PC address 2.

[0093] The specific form of the next-level instruction storage module can be flexibly set according to the actual scenario, and the next-level instruction storage module can serve one SM or multiple SMs, which is not specifically limited in this disclosure.

[0094] The next level instruction storage module responds to the second instruction read request of PC address 2 scheduled by thread 2, and sends the instruction corresponding to PC address 2 scheduled by thread 2 to cache line 2 in the instruction cache storage submodule for storage.

[0095] After the instruction corresponding to PC address 2 scheduled by thread 2 is stored in cache line 2 in the instruction cache storage submodule, Table 2 in the instruction cache tag submodule is updated to the following Table 5.

[0096] Table 5

[0097] Cache line identifier Cache line status tag Lock count (lock_cnt) Cache line 1 valid tag1 1 Cache line 2 valid tag2 1 Cache line 3 invalid 0 0 …… …… …… …… Cache line N invalid 0 0

[0098] As shown in Table 5, the cache line state corresponding to cache line 2 is updated to valid.

[0099] In one possible implementation, the search failure processing submodule is specifically used to: within one clock cycle, check whether the earliest search failure record request at the scheduling time corresponding to each thread meets the preset conditions, wherein the preset conditions are used to indicate that the data corresponding to the thread's current scheduling has been stored in the cache storage module; determine a thread that meets the preset conditions, and send the first instruction read request of the thread's current scheduling to the judgment submodule.

[0100] Since the search failure processing submodule records the search failure record request corresponding to each scheduling failure of each thread cache hit, within one clock cycle, the search failure processing submodule can check whether the earliest search failure record request corresponding to the scheduling time of each thread meets the preset conditions.

[0101] Taking Thread 2 as an example, the earliest scheduled search failure request corresponding to Thread 2 recorded in the search failure processing submodule is the search failure request for Thread 2 scheduled at PC Address 2. Therefore, the search failure processing submodule checks whether the search failure request for Thread 2 scheduled at PC Address 2 meets the preset conditions.

[0102] The search failure processing submodule checks whether the cache line corresponding to tag 2 in the instruction cache tag submodule is in a valid state based on tag 2 indicated by PC address 2. If the cache line corresponding to tag 2 in the instruction cache tag submodule is in a valid state, it is determined that thread 2's scheduling PC address 2 meets the preset condition; otherwise, the preset condition is not met.

[0103] After the search failure processing submodule determines that thread 2 scheduling PC address 2 meets the preset conditions, it sends a first instruction read request for thread 2 scheduling PC address 2 to the judgment submodule. The first instruction read request includes: thread 2 (thread identifier), cache line 2 (target cache line identifier), and PC address 2.

[0104] In one example, within one clock cycle, the search failure processing submodule determines that there are multiple threads that meet the preset conditions, arbitrarily selects a thread that meets the preset conditions, and sends the first instruction read request of the thread scheduled this time to the decision submodule.

[0105] like Figure 2 As shown, the instruction cache module includes a search failure processing submodule, and the search failure processing submodule sends a first instruction read request to the judgment submodule.

[0106] In one possible implementation, when the judgment sub-module simultaneously receives the first instruction read request sent by the instruction cache tag sub-module and the first instruction read request sent by the search failure processing sub-module within one clock cycle, the priority of the first instruction read request sent by the search failure processing sub-module is higher than the first instruction read request sent by the instruction cache tag sub-module.

[0107] Combined with the above description, it can be seen that the first instruction read request sent by the instruction cache tag submodule to the judgment submodule is issued after a cache hit, while the first instruction read request sent by the search failure processing submodule to the judgment submodule is issued after a cache miss and after reading data from the next-level instruction storage module. In other words, the thread scheduling time corresponding to the first instruction read request sent by the search failure processing submodule to the judgment submodule (the time when the thread scheduling module issues the scheduling request) must be earlier than the thread scheduling time of the first instruction read request sent by the instruction cache tag submodule to the judgment submodule. Therefore, in order to read the data with an earlier thread scheduling time as quickly as possible, when the judgment submodule receives the first instruction read request sent by the instruction cache tag submodule and the first instruction read request sent by the search failure processing submodule at the same time within one clock cycle, the priority of the first instruction read request sent by the search failure processing submodule is higher than the first instruction read request sent by the instruction cache tag submodule. In other words, the judgment submodule gives priority to sending the first instruction read request sent by the search failure processing submodule to the instruction cache storage submodule.

[0108] In one example, the instruction cache storage submodule is specifically used to: for any scheduling of any thread, respond to the first instruction read request of the thread's current scheduling, read the instruction that the thread needs to read for this scheduling according to the cache line identifier and PC address included in the first instruction read request of the thread's current scheduling; send the read instruction, PC address, and thread identifier of the thread's current scheduling to the instruction register module; the instruction register module determines the register pointer allocated to the thread's current scheduling according to the PC address and thread identifier of the thread's current scheduling, and stores the read instruction of the thread's current scheduling to the storage location indicated by the register pointer.

[0109] Assume that the thread scheduling module schedules a thread, and the delay of each instruction scheduled by this thread through the instruction cache module is 3 clock cycles. This thread has 1000 instructions, which can always be cached in the instruction cache. The dependency check of each instruction scheduled by this thread can be successful. Using the serial scheduling method in the related art, the total duration of this thread in the scheduling part is 3000 clock cycles. In the embodiment of the present disclosure, the pipeline method is used for scheduling, and the total duration of this thread in the scheduling part is (3+1000) clock cycles, which effectively reduces the thread scheduling time in the instruction pipeline scenario.

[0110] In an embodiment of the present disclosure, a thread scheduling system includes: an instruction cache module, an instruction register module, and an execution module; the instruction data of multiple threads are pre-read through the instruction cache module, and the pre-read instruction data of multiple threads are stored in the instruction register module, so that the instruction register module can determine the target thread and the target instruction of the target thread from the stored instruction data of multiple threads within one clock cycle, and send the target instruction of the target thread to the execution module, effectively reducing the thread scheduling time in the instruction pipeline scenario and improving the utilization rate of the execution module.

[0111] Figure 3 A flowchart of a thread scheduling method according to an embodiment of the present disclosure is shown. The method can be applied to the above Figure 1 and / or Figure 2 The thread scheduling system shown in Figure 3 As shown, the method includes:

[0112] In step S31 , the instruction cache module is used to pre-read instruction data of multiple threads.

[0113] In step S32, the pre-read instruction data of multiple threads are stored using the instruction register module, and within one clock cycle, the target thread and the target instruction of the target thread are determined according to the instruction data of the multiple threads.

[0114] In step S33, the target instruction of the target thread is sent to the execution module using the instruction register module.

[0115] In one possible implementation, an instruction register module is used to store pre-read instruction data of multiple threads, and within one clock cycle, a target thread and a target instruction of the target thread are determined based on the instruction data of the multiple threads, including:

[0116] Using the instruction register module, within one clock cycle, an instruction dependency check is performed on the instruction with the highest instruction order priority in the instruction data of each thread stored;

[0117] A thread that passes the instruction dependency check is determined as a target thread, and an instruction with the highest instruction sequence priority in the instruction data of the thread is determined as a target instruction of the target thread.

[0118] In a possible implementation, the method further includes:

[0119] Using the thread scheduling module, within one clock cycle, according to the preset scheduling rules, a thread for this scheduling is determined, and a register pointer is allocated for this scheduling of the thread. The register pointer allocated for this scheduling of the thread is used to indicate the instruction sequence priority of the instructions that the thread needs to read for this scheduling.

[0120] In one possible implementation, an instruction cache module is used to pre-read instruction data of multiple threads, including: for any scheduling of any thread, the instruction cache module is used to read the instruction required for the thread in this scheduling according to the program counter PC address of the thread in this scheduling;

[0121] According to the register pointer allocated to the thread for this scheduling, the instruction read by the thread for this scheduling is sent to the instruction register module for storage.

[0122] In one possible implementation, for any scheduling of any thread, the instruction cache module is used to read the instructions required for the thread's current scheduling according to the program counter PC address of the thread's current scheduling, including:

[0123] For any scheduling of any thread, the instruction cache tag submodule in the instruction cache module is used to perform a cache search for the thread's current scheduling based on the PC address of the thread's current scheduling, and determine the cache search result for the thread's current scheduling;

[0124] For any scheduling of any thread, the judgment submodule in the instruction cache module is used to read the instruction required by the thread for this scheduling from the instruction cache storage submodule in the instruction cache module based on the first instruction read request of the thread for this scheduling.

[0125] In a possible implementation, the method further includes:

[0126] For any scheduling of any thread, when the instruction cache tag submodule determines that the cache search result of the thread's current scheduling is a cache hit, the first instruction read request of the thread's current scheduling is sent to the judgment submodule, wherein the first instruction read request of the thread's current scheduling includes: the cache line identifier of the thread's current scheduling hit, and the PC address of the thread's current scheduling.

[0127] In a possible implementation, the method further includes:

[0128] For any scheduling of any thread, if the instruction cache tag submodule determines that the cache lookup result of this thread scheduling is a cache miss, a target cache line is determined for this thread scheduling;

[0129] Send a search failure record request for this thread's current scheduling to the search failure processing submodule in the instruction cache module, wherein the search failure record request for this thread's current scheduling includes: the target cache line identifier corresponding to this thread's current scheduling and the PC address of this thread's current scheduling.

[0130] In a possible implementation, the method further includes:

[0131] For any scheduling of any thread, when the instruction cache tag submodule determines that the cache search result of the thread's current scheduling is a cache miss, a second instruction read request for the thread's current scheduling is sent to the next-level instruction storage module corresponding to the instruction cache module, wherein the second instruction read request for the thread's current scheduling includes: the PC address of the thread's current scheduling.

[0132] In a possible implementation, the method further includes:

[0133] Use the search failure processing submodule to record the search failure record requests of multiple threads;

[0134] Within a clock cycle, check whether the earliest failed search record request at the scheduling time corresponding to each thread meets a preset condition, wherein the preset condition is used to indicate that the data corresponding to the thread's current scheduling has been stored in the cache storage module;

[0135] Determine a thread meeting a preset condition, and send a first instruction read request of this time scheduling of the thread to the decision submodule.

[0136] In a possible implementation, the method further includes:

[0137] In a case where the decision submodule simultaneously receives the first instruction read request sent by the instruction cache tag submodule and the first instruction read request sent by the lookup failure processing submodule within one clock cycle, the priority of the first instruction read request sent by the lookup failure processing submodule is higher than that of the first instruction read request sent by the instruction cache tag submodule.

[0138] It can be understood that the above-mentioned various method embodiments mentioned in the disclosure can be combined with each other to form combined embodiments without deviating from the principle logic. Limited by the length, the disclosure will not be repeated. Those skilled in the art can understand that in the above-mentioned method of the specific implementation, the specific execution order of each step should be determined according to its function and possible internal logic.

[0139] In addition, the disclosure also provides an electronic device, a computer readable storage medium, and a program, all of which can be used to implement any of the thread scheduling methods provided by the disclosure. The corresponding technical solutions and descriptions are referred to the method part and will not be repeated.

[0140] The method has specific technical association with the internal structure of the computer system, and can solve the technical problem of how to improve the hardware operation efficiency or execution effect (including reducing data storage amount, reducing data transmission amount, improving hardware processing speed, etc.), thereby obtaining the technical effect of improving the internal performance of the computer system in accordance with the natural law.

[0141] In some embodiments, the apparatus provided by the embodiments of the disclosure has functions or includes modules that can be used to execute the methods described in the above method embodiments, and the specific implementation can refer to the description of the above method embodiments. For the sake of brevity, it will not be repeated here.

[0142] The embodiments of the disclosure also provide a computer readable storage medium having computer program instructions stored thereon, wherein the computer program instructions are executed by a processor to implement the above method. The computer readable storage medium can be a volatile or non-volatile computer readable storage medium.

[0143] The embodiments of the disclosure also provide an electronic device, which includes the above Figure 1 and / or Figure 2 thread scheduling system shown in the figure.

[0144] An embodiment of the present disclosure further proposes an electronic device, comprising: a processor; and a memory for storing instructions executable by the processor; wherein the processor is configured to call the instructions stored in the memory to execute the above method.

[0145] An embodiment of the present disclosure also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code. When the computer-readable code runs in a processor of an electronic device, the processor in the electronic device executes the above method.

[0146] The electronic device may be provided as a terminal, a server, or other forms of devices.

[0147] Figure 4 FIG. 1 is a block diagram of an electronic device according to an embodiment of the present disclosure. Figure 4 , the electronic device 1900 can be provided as a server or a terminal device. Figure 4 The electronic device 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932 for storing instructions executable by the processing component 1922, such as an application. The application stored in the memory 1932 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute the instructions to perform the above-described method.

[0148] The electronic device 1900 may further include a power supply component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input / output interface 1958. The electronic device 1900 may operate based on an operating system stored in the memory 1932, such as a Microsoft Server operating system (Windows Server 2003). TM ), a graphical user interface operating system launched by Apple (Mac OS X TM ), a multi-user, multi-process computer operating system (Unix TM ), a free and open source Unix-like operating system (Linux TM ), an open-source Unix-like operating system (FreeBSD TM ) or similar.

[0149] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions that can be executed by the processing component 1922 of the electronic device 1900 to perform the above method.

[0150] The present disclosure may be a system, method and / or computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present disclosure.

[0151] Computer-readable storage media can be a tangible device that can hold and store the instructions used by the instruction execution device. Computer-readable storage media can be, for example, (but not limited to) an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (non-exhaustive list) of computer-readable storage media include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, for example, a punch card or a convex structure in a groove on which instructions are stored, and any suitable combination thereof. Computer-readable storage media used herein is not interpreted as a transient signal itself, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagated by waveguides or other transmission media (for example, light pulses by fiber optic cables), or electrical signals transmitted by wires.

[0152] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in the computer-readable storage medium in each computing / processing device.

[0153] The computer program instructions for performing the operations of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, and conventional procedural programming languages ​​such as "C" language or similar programming languages. Computer-readable program instructions may be executed entirely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., utilizing an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be personalized by utilizing the state information of the computer-readable program instructions. The electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present disclosure.

[0154] Various aspects of the present disclosure are described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0155] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device is generated that implements the functions / actions specified in one or more blocks in the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, where these instructions cause the computer, programmable data processing device, and / or other device to operate in a specific manner. Thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing various aspects of the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0156] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operational steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0157] The flow charts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the systems, methods and computer program products according to multiple embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and the part of the module, program segment or instruction contains one or more executable instructions for realizing the prescribed logical function. In some alternative implementations, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the prescribed function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0158] The computer program product may be implemented in hardware, software, or a combination thereof. In one embodiment, the computer program product is implemented as a computer storage medium. In another embodiment, the computer program product is implemented as a software product, such as a software development kit (SDK).

[0159] The above description of the various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced with each other and will not be repeated herein for the sake of brevity.

[0160] Those skilled in the art will understand that in the above-mentioned method of the specific implementation method, the writing order of each step does not mean a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0161] If the technical solutions of the present application involve personal information, the product applying the technical solutions of the present application has been explicitly informed of the personal information processing rules before processing the personal information, and has obtained the personal independent consent. If the technical solutions of the present application involve sensitive personal information, the product applying the technical solutions of the present application has obtained the personal independent consent before processing the sensitive personal information, and at the same time meets the requirement of "explicit consent". For example, at the personal information collection device such as camera, a clear and prominent mark is set to inform that it has entered the personal information collection range and will collect personal information. If the individual voluntarily enters the collection range, it is considered to agree to collect personal information. Or on the device for processing personal information, through the pop-up information or by asking the individual to upload his personal information, the individual's authorization is obtained under the condition that the device uses obvious mark / information to inform the individual of the personal information processing rules. The personal information processing rules can include personal information processor, personal information processing purpose, processing method and personal information type, etc.

[0162] The above has described various embodiments of the present disclosure, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes are obvious to those skilled in the art without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles, practical application or improvement of technology in the market of the embodiments, or to enable other ordinary skilled in the art to understand the embodiments disclosed herein.

Claims

1. A thread scheduling system, characterized in that: include: Instruction cache module, instruction register module, execution module; The instruction cache module is used to pre-read instruction data of multiple threads; The instruction register module is configured to store the pre-read instruction data of the multiple threads, and determine a target thread and a target instruction of the target thread according to the instruction data of the multiple threads within one clock cycle; The instruction register module is used to send the target instruction of the target thread to the execution module.

2. The system according to claim 1, wherein: The instruction register module is specifically used to: In one clock cycle, an instruction dependency check is performed on the instruction with the highest instruction order priority in the stored instruction data of each thread; A thread that passes the instruction dependency check is determined as the target thread, and an instruction with the highest instruction sequence priority in the instruction data of the thread is determined as the target instruction of the target thread.

3. The system according to claim 1, wherein: The system includes: a thread scheduling module; The thread scheduling module is used to determine a thread for this scheduling according to preset scheduling rules within a clock cycle, and allocate a register pointer for this thread for this scheduling, wherein the register pointer allocated to this thread for this scheduling is used to indicate the instruction sequence priority of the instructions that the thread needs to read for this scheduling.

4. The system according to claim 3, characterized in that The instruction cache module is specifically used to: For any scheduling of any thread, read the instructions that the thread needs to read for this scheduling according to the program counter PC address of this scheduling; According to the register pointer allocated for the current scheduling of the thread, the instruction read by the current scheduling of the thread is sent to the instruction register module for storage.

5. The system according to claim 4, characterized in that The instruction cache module includes: an instruction cache tag submodule, a judgment submodule, and an instruction cache storage submodule; The instruction cache tag submodule is used to perform a cache search for any thread scheduling according to the PC address of the thread scheduling, and determine the cache search result of the thread scheduling; The judgment submodule is configured to read, for any scheduling of any thread, the instruction required to be read for the current scheduling of the thread from the instruction cache storage submodule based on the first instruction read request of the current scheduling of the thread.

6. The system according to claim 5, characterized in that The instruction cache tag submodule is specifically used to: For any scheduling of any thread, if the cache search result of the thread's current scheduling is a cache hit, the first instruction read request of the thread's current scheduling is sent to the judgment submodule, wherein the first instruction read request of the thread's current scheduling includes: the cache line identifier of the thread's current scheduling hit, and the PC address of the thread's current scheduling.

7. The system according to claim 5, characterized in that The instruction cache module includes: a search failure processing submodule; The instruction cache tag submodule is specifically used to: For any scheduling of any thread, if the cache lookup result of this scheduling of the thread is a cache miss, a target cache line is determined for this scheduling of the thread; Sending a search failure record request for this thread's current scheduling to the search failure processing submodule, wherein the search failure record request for this thread's current scheduling includes: a target cache line identifier corresponding to this thread's current scheduling and a PC address for this thread's current scheduling.

8. The system according to claim 7, characterized in that The instruction cache tag submodule is further used to: For any scheduling of any thread, if the cache search result of the thread's current scheduling is a cache miss, a second instruction read request for the thread's current scheduling is sent to the next-level instruction storage module corresponding to the instruction cache module, wherein the second instruction read request for the thread's current scheduling includes: the PC address of the thread's current scheduling.

9. The system according to claim 7, wherein: The search failure processing submodule is specifically used to: Recording failed lookup requests from multiple threads; Within a clock cycle, checking whether the earliest search failure record request corresponding to the scheduling time of each thread meets a preset condition, wherein the preset condition is used to indicate that the data corresponding to the current scheduling of the thread has been stored in the cache storage module; A thread that meets the preset condition is determined, and a first instruction read request for the thread currently scheduled is sent to the judgment submodule.

10. The system according to claim 7, wherein: When the judgment submodule simultaneously receives the first instruction read request sent by the instruction cache tag submodule and the first instruction read request sent by the search failure processing submodule within one clock cycle, the priority of the first instruction read request sent by the search failure processing submodule is higher than the first instruction read request sent by the instruction cache tag submodule.

11. A thread scheduling method, characterized in that: include: Use the instruction cache module to pre-read the instruction data of multiple threads; Using an instruction register module, storing the pre-read instruction data of the multiple threads, and determining a target thread and a target instruction of the target thread according to the instruction data of the multiple threads within one clock cycle; The target instruction of the target thread is sent to the execution module by utilizing the instruction register module.

12. An electronic device, characterized in that: include: The thread scheduling system according to any one of claims 1 to 10.

13. An electronic device, characterized in that: include: processor; a memory for storing processor-executable instructions; The processor is configured to call the instructions stored in the memory to execute the method of claim 11.

14. A computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the method according to claim 11 is implemented.

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