Segmented fusion SPICE to IBIS model conversion method and system

Abstract

The invention relates to a segmented fusion SPICE to IBIS model conversion method and system, and the method comprises the steps: obtaining data, precisely extracting voltage / current curve data from a simulation result of SPICE simulation, carrying out the transient analysis, guaranteeing that a finally generated IBIS model can accurately reflect the electrical behavior of the SPICE model, increasing the voltage / current sampling point density of DC scanning in the SPICE simulation, and obtaining the electrical behavior of the SPICE model. Particularly, in a non-linear severe change region, a segmentation interval is adaptively adjusted according to curvature change, so that the accuracy of curve data extraction is ensured; a compensation item is added in a [Model] section of the IBIS model to compensate the packaging parasitic effect, the accuracy of model conversion is improved, meanwhile, simulation data under the multi-PVT condition is compressed through PCA, redundant information is reduced, the model generation efficiency is improved, and high-precision and high-efficiency conversion from the SPICE model to the IBIS model is achieved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design, and relates to a segmented fusion SPICE to IBIS model conversion method and system. Background Art

[0002] IBIS (Input / Output Buffer Informational Specification) is a behavioral model that describes the behavior of the input, output, and I / O buffers of an integrated circuit device. It simulates the interaction between the buffers and the on-board circuit system, without involving internal circuit details. The core of the IBIS model is the buffer model, as these buffers generate simulated waveforms that simulators can use to simulate transmission line effects and high-speed phenomena such as crosstalk and EMI (electromagnetic interference).

[0003] The SPICE (Simulation Program with Integrated Circuit Emphasis) model is a general-purpose, circuit-level analog circuit simulator based on physics principles. It is a core technology for integrated circuit design and verification. It accurately simulates the electrical behavior of components such as transistors, resistors, and capacitors in a circuit by solving nonlinear differential equations (such as Kirchhoff's current-voltage law). It can predict the time-domain response (such as transient switching processes) and frequency-domain characteristics (such as amplifier bandwidth and phase margin) of complex circuits. The underlying logic of the SPICE model relies on the physical equations of semiconductor devices, such as the Berkeley Short-channel IGFET Model (BSIM) for MOSFETs, a mathematical model used to describe the behavior of field-effect transistors. It directly describes the device's voltage-current relationship (VI characteristic) and charge-voltage relationship (QV characteristic) through mathematical formulas, thereby modeling microscopic physical phenomena such as subthreshold conduction, channel length modulation effects, and thermal noise.

[0004] In actual integrated circuit design, when the SPICE model of an integrated circuit needs to be converted to an IBIS model, the SPICE model may contain millions of transistors and parasitic parameters, while the IBIS model requires a simplified behavioral description. Direct conversion can lead to information loss or decreased accuracy. Therefore, how to achieve high-precision and high-efficiency conversion from SPICE models to IBIS models has become one of the technical problems to be solved in the industry. Summary of the Invention

[0005] In response to the problems existing in the above-mentioned traditional methods, the present invention proposes a segmented fusion SPICE to IBIS model conversion method and a segmented fusion SPICE to IBIS model conversion system, which can achieve high-precision and high-efficiency SPICE model to IBIS model conversion.

[0006] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: On the one hand, a segmented fusion SPICE to IBIS model conversion method is provided, comprising the steps of: Obtain a SPICE model of the integrated circuit, randomly sample key parameters in the SPICE model's corresponding circuit, and then generate simulation data under different PVT conditions through corner simulation. The I / O buffer characteristics under different process corners extracted from the simulation data are integrated into the typ, min, and max fields of the IBIS model. Extract key features from simulation data under different PVT conditions through data compression algorithm; After writing the SPICE model file based on the extracted key features, the SPICE process library file corresponding to the wafer is called to perform multi-PVT simulation; Obtain the Vt curve of the simulation signal in the multi-PVT simulation through transient analysis, generate discrete VI data points and convert them into the table format of the IBIS model; Increase the voltage or current sampling point density of the DC scan and use a dynamic piecewise linear algorithm to segment the simulation results; the simulation results include Vt curves or discrete VI data points; Compensate for package parasitics in the [Model] section of the IBIS model; Remove internal logic not related to I / O buffers; By comparing and verifying the consistency of the simulation results of the IBIS model and the original SPICE model, the parameters of the IBIS model are optimized and the IBIS model is generated.

[0007] On the other hand, a segmented fusion SPICE to IBIS model conversion system is also provided, including: The SPICE simulation engine is used to obtain the SPICE model of the integrated circuit, randomly sample key parameters in the SPICE model's corresponding circuit, and then generate simulation data under different PVT conditions through corner simulation. Based on the extracted key characteristics, the SPICE model file is written and the SPICE process library file corresponding to the wafer is called to perform multi-PVT simulation. The I / O buffer characteristics under different process corners extracted from the simulation data are integrated into the typ, min, and max fields of the IBIS model. Data extraction module, used to obtain the Vt curve of the simulation signal in the multi-PVT simulation through transient analysis, generate discrete VI data points and convert them into the table format of the IBIS model; Dynamic segmentation module, used to increase the density of voltage or current sampling points in DC sweeps, segmenting simulation results using a dynamic piecewise linear algorithm, compensating for package parasitics in the [Model] section of the IBIS model, and removing internal logic unrelated to the I / O buffer. Simulation results include Vt curves or discrete VI data points. Multi-PVT fusion module, used to extract key features from simulation data under different PVT conditions through data compression algorithm; The verification module is used to verify the consistency of the simulation results of the IBIS model and the original SPICE model by comparison, optimize the parameters of the IBIS model and generate the IBIS model.

[0008] One of the above technical solutions has the following advantages and beneficial effects: The above-mentioned segmented fusion SPICE to IBIS model conversion method and system accurately extracts voltage / current curve data from the SPICE simulation results after acquiring data, and performs transient analysis to ensure that no information that affects the accuracy of the IBIS model is missed, ensuring that the final generated IBIS model can accurately reflect the electrical behavior of the SPICE model. At the same time, the voltage / current sampling point density of the DC scan is increased in the SPICE simulation. In particular, in areas with drastic nonlinear changes, the segmentation interval is adaptively adjusted according to the curvature change, rather than uniform segmentation, to ensure the accuracy of curve data extraction; and compensation items are added to the [Model] section of the IBIS model to compensate for the package parasitic effects, thereby improving the accuracy of the model conversion. PCA is used to compress the simulation data under multiple PVT conditions, reducing redundant information and improving the efficiency of model generation, thereby achieving high-precision and high-efficiency SPICE model to IBIS model conversion. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0010] Figure 1 A schematic diagram of an IBIS model structure in one embodiment; Figure 2 1. A flow chart of a segmented fusion SPICE to IBIS model conversion method according to an embodiment; Figure 3 A block diagram of the model conversion process architecture in one embodiment; Figure 4 1 is a flow chart of a dynamic piecewise linear algorithm according to an embodiment; Figure 5 FIG. 1 is a module functional block diagram of a segmented fusion SPICE to IBIS model conversion system in one embodiment. DETAILED DESCRIPTION

[0011] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and Examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the description of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0012] It should be noted that, when referred to in this document as an "embodiment", it means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The presentation of this phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be understood by those skilled in the art that the embodiments described herein may be combined with other embodiments. The term "and / or" used in this document refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0013] The following describes the implementation of the present invention in detail with reference to the accompanying drawings in the embodiments of the present invention.

[0014] IBIS describes a buffer's input and output impedance (in the form of VI curves), rise and fall times, and pull-up and pull-down conditions under different circumstances. Engineers can then use this model to analyze SI (Signal Integrity), crosstalk, EMC (Electromagnetic Compatibility), and timing for circuit systems on printed circuit boards (PCBs).

[0015] The simulation input for a SPICE model is typically presented as a netlist, which clearly defines the component connections and parameters. For example, "M1 Drain Gate Source Bulk NMOS W=1u L=0.18u" represents an NMOS transistor with a channel width of 1 micron and a length of 0.18 microns. SPICE models support multiple analysis modes, including transient analysis (for observing signal changes over time), DC (sweep) analysis (for determining the static operating point), and AC small signal analysis (for plotting frequency response curves). In practical applications, SPICE models primarily serve the transistor-level design of integrated circuits, such as analog circuits (operational amplifiers and phase-locked loops), RF circuits (low-noise amplifiers and mixers), and high-precision digital units (such as sense amplifiers). They are particularly indispensable for reliability verification, which requires analyzing nonlinear effects (such as harmonic distortion and temperature drift) and extreme operating conditions (high temperature and high voltage).

[0016] However, SPICE models also have significant limitations: their computational complexity is extremely high, and simulations of large-scale circuits can take hours or even days. Model construction relies heavily on detailed process parameters (such as doping concentration and oxide thickness), which often involve confidential information from the wafer fab. Furthermore, the netlist can expose internal chip design details, leading to the risk of intellectual property (IP) leakage. To address these challenges, SPICE model technology has continued to evolve in recent years, such as accelerating parallel computing with GPUs, simplifying equation solutions using reduced order modeling, and introducing machine learning algorithms to automatically fit device parameters, thereby improving simulation efficiency while maintaining accuracy. Despite this, SPICE models remain the irreplaceable "gold standard" in the field of electronic design, particularly dominating high-precision analog circuit analysis and nanometer-scale process verification.

[0017] Corner simulation is to simulate the circuit by presetting the extreme process conditions (i.e., "process corners") to verify its performance under the worst-case scenario. Common process corner combinations include: FF (Fast-Fast): The transistor is fast (low threshold voltage, short channel length) and the interconnection resistance is low.

[0018] SS (Slow-Slow): The transistor speed is slow (high threshold voltage, long channel length) and the interconnect resistance is high.

[0019] TT (Typical-Typical): Typical process parameters.

[0020] FS (Fast-Slow) and SF (Slow-Fast): mixed extreme conditions of different modules.

[0021] PVT is the abbreviation of Process, Voltage and Temperature, which represents the three core factors affecting the performance of circuits: Process represents the fluctuation of transistor parameters in the manufacturing process, the deviation of interconnection resistance / capacitance. Voltage represents the fluctuation of power supply voltage (such as nominal voltage of 1.2V, actual fluctuation of ±10%), local voltage change caused by noise. Temperature represents the chip working temperature range (such as-40°C to 125°C), temperature change causes parameters such as carrier mobility and threshold voltage to drift.

[0022] In the prior art, by selecting characteristic parameters affecting the accuracy of the IBIS model, and comparing the differences between the SPICE model and the IBIS model, the accuracy is ensured; by aligning and simplifying the polygons of the multi-layer integrated circuit layout, the electromagnetic field of the multi-layer integrated circuit is calculated, and the higher completeness of the IBIS model is obtained. However, the SPICE model may contain millions of transistors and parasitic parameters, while the IBIS model needs a simplified behavior description, and direct conversion may cause information loss or accuracy decline. The IBIS model relies on V-I curve and V-t curve to describe the behavior of the buffer, while the SPICE simulation is based on time-domain transient analysis, and how to extract accurate table data from the SPICE simulation result is a big challenge.

[0023] The nonlinear effects in the SPICE model (such as subthreshold conduction of MOSFET and channel length modulation) are difficult to fully reproduce by the piecewise linear model of the IBIS model, and the traditional piecewise linearization (PWL) method may not be sufficient in the inflection point region, which may cause errors at high frequencies or extreme voltages. Complex SPICE models may also have non-convergence problems in transient simulation, especially when high-gain feedback loops are involved; in addition, full-band simulation is time-consuming. The efficiency of multi-PVT condition coverage is low, and the process corner (Corner) and Monte Carlo analysis are time-consuming and difficult to integrate into a single IBIS model; the structure of the IBIS model is as shown in Figure 1 .

[0024] Therefore, in one embodiment, as shown in Figure 2 , a piecewise fusion SPICE to IBIS model conversion method can include the following steps S10-S24: S10, obtaining a SPICE model of the integrated circuit, randomly sampling key parameters in the circuit corresponding to the SPICE model, and then generating simulation data under different PVT conditions through corner simulation; wherein, the I / O buffer characteristics under different process corners are extracted from the simulation data and integrated into the typ, min, and max fields of the IBIS model; I / O refers to input / output.

[0025] S12, extract key features from simulation data under different PVT conditions through data compression algorithm; S14, writing a SPICE model file based on the extracted key features and then calling the SPICE process library file corresponding to the wafer to perform multi-PVT simulation; S16, obtaining a Vt curve of a simulation signal in a multi-PVT simulation through transient analysis, generating discrete VI data points and converting them into a table format of an IBIS model; S18, increasing the voltage or current sampling point density of the DC scan, and using a dynamic piecewise linear algorithm to segment the simulation results; the simulation results include Vt curves or discrete VI data points; S20, compensate for package parasitics in the [Model] section of the IBIS model; S22, remove internal logic not related to the I / O buffer; S24, verifying the consistency of the simulation results of the IBIS model and the original SPICE model by comparison, optimizing the parameters of the IBIS model and generating the IBIS model.

[0026] It is understandable that Figure 3 As shown, data is first acquired. This involves randomly sampling key circuit parameters (such as transistor size, resistance, and capacitance) from the SPICE model of the integrated circuit to simulate the impact of process variations during manufacturing on circuit performance. Corner simulation generates simulation data under different PVT conditions. I / O buffer characteristics (such as drive capability and rise / fall time) at different process corners are extracted from these data. These I / O buffer characteristics are then integrated into the typ, min, and max fields of the IBIS model, enabling multi-PVT data fusion and ensuring that the IBIS model covers the full range of process variations.

[0027] Then, key features are extracted from the simulation data under different PVT conditions through data compression algorithms (such as principal component analysis PCA) to reduce the size of the IBIS file.

[0028] Then write the SPICE model file and call the SPICE process library file corresponding to the wafer to perform multi-PVT simulation, that is, SPICE simulation. Figure 3 Among them, HSPICE is high-performance circuit simulation software.

[0029] Then, through transient analysis, the Vt curve is obtained, discrete VI data points are generated, and converted into a tabular format for the IBIS model. Specifically, the time domain waveforms of the rising and falling edges of the signal are simulated under a standard load (such as a 50Ω resistor or capacitor load) to obtain the Vt curve of the voltage changing over time and generate discrete VI data points. The discrete VI data points generated by the simulation are converted into discrete VI data points in a tabular format for the IBIS model through interpolation or piecewise linearization. The monotonicity and rationality of the tabular data can be automatically verified, outliers (such as non-monotonic VI curve segments) can be eliminated, and corrections can be made through methods such as linear interpolation, spline interpolation, or local regression to ensure model stability.

[0030] Add a DC sweep to segment the generated Vt curve / discrete VI data points. Specifically, increase the density of voltage / current sampling points in the DC sweep (which measures the response characteristics of a device or circuit at different DC operating points by gradually adjusting the DC voltage or current) in the SPICE simulation, especially in areas with severe nonlinear changes (such as near the inflection point). A dynamic segmentation strategy (also known as a dynamic piecewise linear algorithm) can be used to adaptively adjust the segmentation interval based on the curvature of the VI curve or Vt curve corresponding to the discrete VI data points generated by the SPICE simulation, rather than uniformly segmenting.

[0031] Then, in the [Model] section of the IBIS model, parameters such as "C_comp" are used to compensate for package parasitic effects. The [Model] section is the core configuration area, used to define the basic electrical characteristics and behavioral parameters of the device's I / O buffers. "C_comp" is a virtual capacitor parameter used to offset the effects of package parasitic inductance in the IBIS model.

[0032] Next, remove internal logic unrelated to the I / O buffer (such as non-critical paths in the ESD (electrostatic discharge) protection circuitry). Adjust the step size based on the signal rise time (typically 1 / 10 of the rise time). Simulate low-frequency and high-frequency behavior separately, then combine the results.

[0033] Finally, optimize the parameters and generate the IBIS model. As you can see, the consistency of the simulation results (e.g., signal overshoot and edge rate) is verified by comparing the IBIS model with the original SPICE model. Cross-validation can be used to compare the transient responses (e.g., step response and / or eye diagram) of the SPICE and IBIS models under the same test stimulus. If discrepancies are found, manually adjust the data and key simulation parameters, or redefine the test conditions. By optimizing the load configuration or simulation step size, for example, to ensure that the error is less than 3%, the IBIS model parameters can be optimized.

[0034] Next, we expand the [Temperature Range] and [Voltage Range] sections of the IBIS model: These multiple data sets are integrated into the same IBIS file, distinguished by sub-parameters (such as the typ / min / max fields). In the IBIS model, [Temperature Range] and [Voltage Range] are two extended sections used to describe the device's electrical characteristics under different temperature and voltage conditions, respectively.

[0035] Finally, the IBIS data and the package RLC parasitics (i.e., resistance R, inductance L, and capacitance C) are integrated to form an IBIS model. RLC parasitics are extracted from chip package simulations. During the extraction process, the package must be modeled, and the modeled parameters must be consistent with the actual package parameters to ensure accurate RLC parasitic extraction. The RLC parasitic model includes chip pads, bond wires, substrate, frame, solder balls, and epoxy resin. The path from the I / O chip output to the PCB board is through the chip pads, bond wires, substrate, or frame. The substrate includes internal wiring to external solder balls. Chip pads can be made of copper-nickel-gold or copper-aluminum alloy, while bond wires can be made of 4N / 2N gold, copper-gold alloy, or aluminum. Substrates can include BT and ABF substrates. The frame can be pure copper.

[0036] The above-mentioned segmented fusion SPICE to IBIS model conversion method accurately extracts voltage / current curve data from the SPICE simulation results after acquiring data, and performs transient analysis to ensure that no information that affects the accuracy of the IBIS model is missed, ensuring that the final generated IBIS model can accurately reflect the electrical behavior of the SPICE model. At the same time, the voltage / current sampling point density of the DC scan is increased in the SPICE simulation. Especially in areas with drastic nonlinear changes, the segmentation interval is adaptively adjusted according to the curvature change, rather than uniform segmentation, to ensure the accuracy of curve data extraction. In addition, compensation terms are added to the [Model] section of the IBIS model to compensate for the package parasitic effects, thereby improving the accuracy of the model conversion. PCA is used to compress the simulation data under multiple PVT conditions, reducing redundant information and improving the efficiency of model generation, thereby achieving high-precision and high-efficiency SPICE model to IBIS model conversion.

[0037] In general, extracting Vt waveform data from SPICE simulations is a critical step in the model conversion process. Because the IBIS model primarily relies on VI and Vt curves to describe the buffer's behavior, it is necessary to accurately extract these curve data from the SPICE simulation results. To ensure the accuracy of curve data extraction, the following strategy was adopted: In SPICE simulations, the density of voltage and current sampling points in DC sweeps has been increased, especially in areas of intense nonlinearity (such as near inflection points). The segmentation intervals have been adaptively adjusted based on curvature changes, rather than uniformly segmented. Compensation terms (such as "C_comp" parameters) have been added to the [Model] section of the IBIS model to compensate for package parasitics. This resolves errors in the IBIS piecewise linear model at high frequencies or extreme voltages during model conversion, improving the accuracy of the model conversion.

[0038] Convert high-dimensional data into a low-dimensional representation while preserving the main change patterns in the data. For example, in the process of converting SPICE models to IBIS models, PCA is used to compress simulation data under multiple PVT conditions, reducing redundant information and improving model generation efficiency. Perform transient simulations to capture the changes in voltage and current over time. By setting appropriate simulation time steps and termination conditions, ensure that all key time nodes are captured, especially dynamic processes such as rising and falling edges. For each voltage or current node of interest, record its complete waveform during the simulation time. This includes detailed analysis of all key nodes on the critical signal path to ensure that no information that may affect the accuracy of the IBIS model is missed.

[0039] Finally, the extracted waveform data undergoes post-processing, such as interpolation or piecewise linearization, to convert it into the tabular format required by the IBIS model. This process involves data smoothing, denoising, and format conversion to ensure that the resulting IBIS model accurately reflects the electrical behavior of the SPICE model. In this way, the dynamic segmentation strategy reduces nonlinear errors and improves conversion accuracy. PCA compresses simulation data under multiple PVT conditions, reducing redundant information and improving model generation efficiency, thereby achieving highly accurate and efficient conversion from SPICE models to IBIS models.

[0040] In one embodiment, the step of extracting key features from simulation data under different PVT conditions using a data compression algorithm may include the following processing: Align each set of simulation data by time point to form a standardized matrix; Calculate the covariance matrix based on the standardized matrix; Perform eigenvalue decomposition on the covariance matrix to obtain eigenvalues ​​and eigenvectors; Select principal components based on eigenvalues ​​and eigenvectors; Data is projected according to principal components and normalized matrices to obtain a low-dimensional representation of key features.

[0041] It can be understood that the process of extracting key features and reducing the size of IBIS files through data compression algorithms (such as principal component analysis PCA) is to classify simulation data under different PVT conditions according to typ / min / max labels, and remove redundant data through PCA processing to improve model generation efficiency. Multi-condition simulation is performed in the SPICE model, covering FF / SS / TT process corners, voltage ±10%, and temperature from -40°C to 125°C. A composite model file that complies with the IBIS standard is generated, supporting the on-demand call of different condition data. Specifically, the specific steps of PCA processing are: First, standardize the data. Align each set of simulation data (such as Vt curve) by time point to form a standardized matrix X ∈R m×n , where m is the number of simulations (e.g. 1000 Monte Carlo samplings) and n is the number of time sampling points (e.g. 1000 time points). X Each column (time point) is normalized:

[0042] in, X [ i , j ] is the first i The sample in j Simulation data at each time point, For the j The mean of the time points, For the j The standard deviation of each time point.

[0043] Then, the covariance matrix is ​​calculated based on the normalized matrix. n×n Reflects the correlation between different time points:

[0044] in, for The transpose of .

[0045] Next, perform eigenvalue decomposition on the covariance matrix C to obtain eigenvalues ​​and eigenvectors. The eigenvalues ​​λ1≥λ2≥⋯≥λ n , the eigenvalue represents the variance contribution of each principal component; the eigenvector v 1, v 2,…, v n : corresponds to the direction of the principal component.

[0046] Then, the principal components are selected based on the eigenvalues ​​and eigenvectors. The number of principal components to be retained is determined based on the cumulative variance contribution rate. k (usually retain more than 95% of the variance):

[0047] For example, if the first three principal components contribute 95% of the variance, then k =3.

[0048] Finally, data projection is performed based on the principal component and normalized matrix. The original simulation data is projected into the principal component space to obtain the low-dimensional representation of the key features Z∈R m×n :

[0049] In one embodiment, when restoring simulation data under different PVT conditions, the simulation data is approximately reconstructed through inverse transformation based on the low-dimensional representation and the mean of the simulation data.

[0050] Optionally, you can further choose to reconstruct the data. If you need to restore the data, you can approximate reconstruction through inverse transformation:

[0051] in, is the mean value of the simulation data, thereby achieving efficient data restoration processing.

[0052] In one embodiment, the process of segmenting the simulation results using a dynamic piecewise linear algorithm may include the following steps: The second-order derivative of the simulation results is calculated to identify the extreme curvature points of the curve; the simulation step size is set to be less than 1 / 10 of the rise time of the excitation signal; On the curve, the extreme point of curvature is used as the segment boundary to generate non-uniform segment intervals; The overall deviation between the simulated value and the fitted value of the curve is measured by error comparison; According to the results of error comparison, linear fitting is performed on each non-uniform segmented interval to generate IBIS table data.

[0053] It is understandable that Figure 4 As shown in the figure, the dynamic piecewise linear algorithm used above adaptively adjusts the segment density based on the curvature of the VI curve or Vt curve generated by SPICE simulation. It increases sampling points in areas with high curvature (strong nonlinearity) and reduces sampling points in areas with low curvature (weak nonlinearity).

[0054] Specifically, first calculate the second-order derivative of the SPICE simulation results (such as the VI curve or Vt curve) to identify the extreme points of the curve's curvature. The stimulus signal is a step voltage with a rise time of 100 ps (picoseconds), and the load condition is a 50Ω resistor in parallel with a 2pF (picofarads). The simulation step size is set to 1ps (which, according to the Nyquist theorem, should be at least 1 / 10 of the rise time). Output: Generate a time-voltage waveform file (tr0 format).

[0055] To perform curvature analysis and segmentation, the first step is to calculate the curvature and calculate the second-order derivative of the voltage waveform V(t):

[0056] Then, the curvature extreme points on the curve are used as segment boundaries to generate non-uniform segmented intervals.

[0057] Compare the errors:

[0058] That is, the overall deviation between the simulation value and the fitting value of the curve is measured by error comparison. N is the total number of data points, The simulation results are i The simulation value of the point, For the fitting curve in this i Finally, a linear fit is performed on each non-uniform segmented interval to generate IBIS table data.

[0059] It should be understood that although Figure 2The steps in the diagram are shown in the order indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Figure 2 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0060] In one embodiment, Figure 5 As shown, a segmented fusion SPICE to IBIS model conversion system is also provided, comprising a SPICE simulation engine, a data extraction module, a dynamic segmentation module, a multi-PVT fusion module, and a verification module. The SPICE simulation engine is used to obtain the SPICE model of the integrated circuit, randomly sample key parameters in the circuit corresponding to the SPICE model, and then generate simulation data under different PVT conditions through corner simulation. A SPICE model file is compiled based on the extracted key features, and then the SPICE process library file corresponding to the wafer is called to perform multi-PVT simulation. The I / O buffer characteristics under different process corners extracted from the simulation data are integrated into the typ, min, and max fields of the IBIS model.

[0061] The data extraction module is used to obtain the Vt curve of the simulation signal in multi-PVT simulation through transient analysis, generate discrete VI data points, and convert them into a tabular format for the IBIS model. The dynamic segmentation module is used to increase the density of voltage or current sampling points in the DC sweep, segment the simulation results using a dynamic piecewise linear algorithm, compensate for package parasitics in the [Model] section of the IBIS model, and remove internal logic unrelated to the I / O buffer; the simulation results include Vt curves or discrete VI data points. The multi-PVT fusion module is used to extract key features from simulation data under different PVT conditions using a data compression algorithm. The verification module is used to verify the consistency of the simulation results of the IBIS model and the original SPICE model through comparison, optimize the IBIS model parameters, and generate the IBIS model.

[0062] The above-mentioned segmented fusion SPICE to IBIS model conversion system accurately extracts voltage / current curve data from the SPICE simulation results after acquiring data, and performs transient analysis to ensure that no information that affects the accuracy of the IBIS model is missed, ensuring that the final generated IBIS model can accurately reflect the electrical behavior of the SPICE model. At the same time, the voltage / current sampling point density of the DC scan is increased in the SPICE simulation. Especially in areas with drastic nonlinear changes, the segmentation interval is adaptively adjusted according to the curvature change, rather than uniform segmentation, to ensure the accuracy of curve data extraction. In addition, compensation items are added to the [Model] section of the IBIS model to compensate for the package parasitic effects, thereby improving the accuracy of model conversion. PCA is used to compress the simulation data under multiple PVT conditions, reducing redundant information and improving model generation efficiency, thereby achieving high-precision and high-efficiency SPICE model to IBIS model conversion.

[0063] In one embodiment, the data compression algorithm is principal component analysis, which forms a standardized matrix by aligning each set of simulation data according to the time point, calculates the covariance matrix based on the standardized matrix, performs eigenvalue decomposition on the covariance matrix to obtain eigenvalues ​​and eigenvectors, selects principal components based on the eigenvalues ​​and eigenvectors, and projects the data based on the principal components and the standardized matrix to obtain a low-dimensional representation of the key features.

[0064] In one embodiment, when restoring simulation data under different PVT conditions, the simulation data is approximately reconstructed through inverse transformation based on the low-dimensional representation and the mean of the simulation data.

[0065] In one embodiment, the process of segmenting the simulation results using a dynamic piecewise linear algorithm includes: calculating the second-order derivative of the simulation results to identify the extreme curvature points of the curve; setting the simulation step size to be less than 1 / 10 of the rise time of the excitation signal; generating non-uniform segmented intervals on the curve using the extreme curvature points as segment boundaries; measuring the overall deviation between the simulated value and the fitted value of the curve through error comparison; and performing linear fitting on each non-uniform segmented interval based on the results of the error comparison to generate IBIS table data.

[0066] It can be understood that the explanation of each feature in the above-mentioned segmented fusion SPICE to IBIS model conversion system can be understood in the same way as the corresponding explanation in each embodiment of the segmented fusion SPICE to IBIS model conversion method. Each module in the above-mentioned segmented fusion SPICE to IBIS model conversion system can be implemented in whole or in part by software, hardware, and a combination thereof. Each of the above-mentioned modules can be embedded in or independent of a device with data processing functions in the form of hardware, or can be stored in the memory of the aforementioned device in the form of software, so that the processor can call and execute the operations corresponding to each of the above modules. The aforementioned device can be, but is not limited to, various types of integrated circuit design / simulation computers already available in the art.

[0067] Those skilled in the art will appreciate that all or part of the processes in the above-described method embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the above-described method embodiments. Any reference to memory, storage, database, or other media used in the various embodiments provided herein may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus DRAM (RDRAM), and DDR DRAM.

[0068] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0069] The above embodiments merely illustrate several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of the present invention.

Claims

1. A segmented fusion SPICE to IBIS model conversion method, characterized in that: Including steps: Obtain a SPICE model of the integrated circuit, randomly sample key parameters in the SPICE model's corresponding circuit, and then generate simulation data under different PVT conditions through corner simulation. The I / O buffer characteristics under different process corners extracted from the simulation data are integrated into the typ, min, and max fields of the IBIS model. Extract key features from simulation data under different PVT conditions through data compression algorithm; After writing the SPICE model file based on the extracted key features, the SPICE process library file corresponding to the wafer is called to perform multi-PVT simulation; Obtain the Vt curve of the simulation signal in the multi-PVT simulation through transient analysis, generate discrete VI data points and convert them into the table format of the IBIS model; Increase the voltage or current sampling point density of the DC scan and use a dynamic piecewise linear algorithm to segment the simulation results; the simulation results include Vt curves or discrete VI data points; Compensate for package parasitics in the [Model] section of the IBIS model; Remove internal logic not related to I / O buffers; By comparing and verifying the consistency of the simulation results of the IBIS model and the original SPICE model, the parameters of the IBIS model are optimized and the IBIS model is generated.

2. The segmented fusion SPICE to IBIS model conversion method according to claim 1, characterized in that: The steps of extracting key features from simulation data under different PVT conditions using a data compression algorithm include: Align each set of simulation data by time point to form a standardized matrix; Calculate the covariance matrix based on the standardized matrix; Perform eigenvalue decomposition on the covariance matrix to obtain eigenvalues ​​and eigenvectors; Select principal components based on eigenvalues ​​and eigenvectors; Data is projected according to principal components and normalized matrices to obtain a low-dimensional representation of key features.

3. The segmented fusion SPICE to IBIS model conversion method according to claim 2, characterized in that: When restoring simulation data under different PVT conditions, the simulation data is approximately reconstructed through inverse transformation based on the low-dimensional representation and the mean of the simulation data.

4. The segmented fusion SPICE to IBIS model conversion method according to any one of claims 1 to 3, characterized in that: The process of segmenting the simulation results using the dynamic piecewise linear algorithm includes: The second-order derivative of the simulation results is calculated to identify the extreme curvature points of the curve; the simulation step size is set to be less than 1 / 10 of the rise time of the excitation signal; On the curve, the extreme point of curvature is used as the segment boundary to generate non-uniform segment intervals; The overall deviation between the simulated value and the fitted value of the curve is measured by error comparison; According to the results of error comparison, linear fitting is performed on each non-uniform segmented interval to generate IBIS table data.

5. A segmented fusion SPICE to IBIS model conversion system, characterized by: include: The SPICE simulation engine is used to obtain the SPICE model of the integrated circuit, randomly sample key parameters in the SPICE model's corresponding circuit, and then generate simulation data under different PVT conditions through corner simulation. Based on the extracted key characteristics, the SPICE model file is written and the SPICE process library file corresponding to the wafer is called to perform multi-PVT simulation. The I / O buffer characteristics under different process corners extracted from the simulation data are integrated into the typ, min, and max fields of the IBIS model. Data extraction module, used to obtain the Vt curve of the simulation signal in the multi-PVT simulation through transient analysis, generate discrete VI data points and convert them into the table format of the IBIS model; Dynamic segmentation module, used to increase the density of voltage or current sampling points in DC sweeps, segmenting simulation results using a dynamic piecewise linear algorithm, compensating for package parasitics in the [Model] section of the IBIS model, and removing internal logic unrelated to the I / O buffer. Simulation results include Vt curves or discrete VI data points. Multi-PVT fusion module, used to extract key features from simulation data under different PVT conditions through data compression algorithm; The verification module is used to verify the consistency of the simulation results of the IBIS model and the original SPICE model by comparison, optimize the parameters of the IBIS model and generate the IBIS model.

6. The segmented fusion SPICE to IBIS model conversion system according to claim 5, characterized in that: The data compression algorithm is principal component analysis. Each set of simulation data is aligned by time points to form a standardized matrix. The covariance matrix is ​​calculated based on the standardized matrix. The covariance matrix is ​​decomposed into eigenvalues ​​and eigenvectors. The principal components are selected based on the eigenvalues ​​and eigenvectors. The data is projected based on the principal components and the standardized matrix to obtain a low-dimensional representation of the key features.

7. The segmented fusion SPICE to IBIS model conversion system according to claim 6, characterized in that: When restoring simulation data under different PVT conditions, the simulation data is approximately reconstructed through inverse transformation based on the low-dimensional representation and the mean of the simulation data.

8. The segmented fusion SPICE to IBIS model conversion system according to any one of claims 5 to 7, characterized in that: The process of segmenting the simulation results using the dynamic piecewise linear algorithm includes: The second-order derivative of the simulation results is calculated to identify the extreme curvature points of the curve; the simulation step size is set to be less than 1 / 10 of the rise time of the excitation signal; On the curve, the extreme point of curvature is used as the segment boundary to generate non-uniform segment intervals; The overall deviation between the simulated value and the fitted value of the curve is measured by error comparison; According to the results of error comparison, linear fitting is performed on each non-uniform segmented interval to generate IBIS table data.

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