Ramp signal generation circuit and ramp signal generation method for power converter

Abstract

The invention provides a ramp signal generation circuit and a ramp signal generation method for a power converter. The ramp signal generating circuit compensates the slope of the ramp signal according to the slope compensation curve, and non-linearly adjusts the slope of the ramp signal in a predetermined duty ratio interval of a current ripple offset point of the power converter. The ramp signal generation circuit disclosed by the invention is particularly suitable for a multi-phase power converter and a multi-level power converter, and can effectively solve the problem of gate pulse mixing near a current ripple offset point. By adopting the slope modulation technology, the circuit optimizes the dynamic response performance while keeping the stability of the system. In a working interval of a non-current ripple offset point, the circuit maintains a lower slope signal slope to ensure the system bandwidth. In the preset duty ratio interval near the current ripple offset point, the slope of the ramp signal is smoothly improved in a nonlinear adjustment mode, so that the problem of system oscillation caused by sudden change of the slope in a traditional scheme is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power supply, in particular to a ramp signal generation circuit and a ramp signal generation method for a power converter. BACKGROUND

[0002] In electronic products, power converters have been widely used to provide power supply voltage for electronic devices inside the electronic products. For example, the power supply voltage of the electronic devices is higher than the battery voltage, and the power converter is used to convert the battery voltage into the power supply voltage of the electronic devices so that the electronic devices can work correctly. The power converter can adopt a current mode or a voltage control mode, the current mode refers to that the power converter controls in a closed loop by detecting an inductor current signal, and has advantages of simple loop compensation and fast dynamic response. In the constant switching frequency current mode control, such as peak current mode (PCM), valley current mode (VCM) and average current mode (ACM), are widely used in the industry.

[0003] In the current mode control, the ramp compensation technology is an important means to improve the stability of the system, and the basic principle is to introduce a ramp signal related to the output voltage or current in the control loop, which is used to suppress the ripple and fluctuation in the switching converter. The traditional ramp compensation circuit usually adopts a fixed slope sawtooth signal, and the inductor current signal is compared with the ramp signal by a comparator to generate an error signal to adjust the duty cycle of the switching tube.

[0004] However, in the application of multi-phase interleaved parallel or multi-level topology, due to the superposition effect of inductor current, the system will have current ripple cancellation phenomenon at a certain duty cycle point (such as D=0.5 when two-phase interleaved parallel), which will cause the traditional fixed slope compensation scheme to have switching drive signal jitter (Jitter) problem near the ripple cancellation point. In the existing current mode control, the method of increasing the slope compensation slope is usually used to suppress the Jitter phenomenon, but this method will cause over-compensation problem in the working interval of the system at the non-ripple cancellation point. Over-compensation will make the current mode control degenerate into voltage mode control, which will cause the system phase to decrease at low frequency and the bandwidth to decrease, thereby affecting the dynamic response performance. In addition, slope switching can also be performed near the ripple cancellation point, but this sudden slope adjustment will cause fluctuations in the control loop and the output voltage, which is not conducive to the stable operation of the system. SUMMARY

[0005] In view of the above technical problems, the purpose of the present application is to provide a ramp signal generation circuit and a ramp signal generation method for a power converter, in which nonlinear slope compensation is performed near the ripple cancellation point, so as to optimize the dynamic response performance while ensuring the stability of the system.

[0006] According to a first aspect of the present application, a ramp signal generating circuit for a power converter is provided. The power converter includes an inductor, multiple sets of switching transistors for controlling charging and discharging processes of the inductor, and a current control loop for driving the multiple sets of switching transistors. The power converter generates an output voltage using a combined inductor current generated by switching actions of the multiple sets of switching transistors. The ramp signal generating circuit includes: a charging control module, generating a charging control signal according to the input voltage and the output voltage; a transconductance amplifier, generating a charging current according to the charging control signal; capacitor, connected between the output of the transconductance amplifier and ground, A switch, connected in parallel with the capacitor, During a switching cycle of the power converter, the charging current is used to charge the capacitor and discharge the capacitor via the switch to generate the ramp signal for adjusting the first slope of the detection signal of the combined inductor current. The charging control module controls the magnitude of the charging control signal according to a relationship curve between the duty cycle of the power converter and the amplitude of the charging control signal. In continuous first and second duty cycle intervals, the charging control module adjusts the second slope of the ramp signal according to a linear curve and a nonlinear curve, respectively.

[0007] Optionally, the first duty cycle interval does not include the current ripple cancellation point of the power converter, and the second duty cycle interval includes the current ripple cancellation point of the power converter, and the current ripple cancellation point represents the duty cycle corresponding to the minimum current ripple generated by the switching action of the multiple groups of switching tubes.

[0008] Optionally, in the first duty cycle interval, the charging control signal is equal to the first control signal.

[0009] Optionally, the nonlinear curve may be any one of a broken line curve and a smooth curve.

[0010] Optionally, the broken line curve includes a rising stage, a peak stage and a falling stage, and the current ripple offset point is located in the peak stage.

[0011] Optionally, in the peak phase, the charging control module adds the first control signal and the second control signal to obtain the charging control signal. In the rising phase, the charging control module adds the first control signal and the third control signal to obtain the charging control signal. In the falling phase, the charging control module adds the first control signal and the fourth control signal to obtain the charging control signal.

[0012] Optionally, the charging control module comprises: a first operational amplifier for obtaining the first control signal; and a charging compensation module for selecting one of the second control signal, the third control signal and the fourth control signal to generate a charging compensation signal according to the input voltage and the output voltage, wherein the charging control module adds the first control signal and the charging compensation signal to obtain the charging control signal.

[0013] Optionally, the charging compensation module comprises: a second operational amplifier for obtaining the second control signal; a third operational amplifier and a fourth operational amplifier cascaded with each other to obtain the third control signal; a fifth operational amplifier and a sixth operational amplifier cascaded with each other to obtain the fourth control signal.

[0014] Optionally, when the power converter is a step-down converter, the first operational amplifier obtains the first control signal according to the input voltage, the second operational amplifier obtains the second control signal according to the input voltage, the positive input terminal of the third operational amplifier receives the input voltage, the positive input terminal of the fourth operational amplifier receives the output voltage, the negative input terminal of the fourth operational amplifier receives the output signal of the third operational amplifier, the fourth operational amplifier outputs the third control signal, the positive input terminal of the fifth operational amplifier receives the input voltage, the positive input terminal of the sixth operational amplifier receives the output signal of the fifth operational amplifier, the negative input terminal of the sixth operational amplifier receives the output voltage, and the sixth operational amplifier outputs the fourth control signal; when the power converter is a step-up converter, the first operational amplifier obtains the first control signal according to the output voltage, the second operational amplifier obtains the second control signal according to the output voltage, the positive input terminal of the third operational amplifier receives the output voltage, the positive input terminal of the fourth operational amplifier receives a difference signal of the output voltage and the input voltage, the negative input terminal of the fourth operational amplifier receives the output signal of the third operational amplifier, the fourth operational amplifier outputs the third control signal, the positive input terminal of the fifth operational amplifier receives the output voltage, the positive input terminal of the sixth operational amplifier receives the output signal of the fifth operational amplifier, the negative input terminal of the sixth operational amplifier receives the difference signal of the output voltage and the input voltage, and the sixth operational amplifier outputs the fourth control signal; When the power converter is a buck-boost converter, the first operational amplifier obtains the first control signal based on the sum of the output voltage and the input voltage, the second operational amplifier obtains the second control signal based on the sum of the output voltage and the input voltage, the positive input terminal of the third operational amplifier receives the sum of the output voltage and the input voltage, the positive input terminal of the fourth operational amplifier receives the output voltage, the negative input terminal of the fourth operational amplifier receives the output signal of the third operational amplifier, and the fourth operational amplifier outputs the third control signal, the positive input terminal of the fifth operational amplifier receives the sum of the output voltage and the input voltage, the positive input terminal of the sixth operational amplifier receives the output signal of the fifth operational amplifier, the negative input terminal of the sixth operational amplifier receives the output voltage, and the sixth operational amplifier outputs the fourth control signal.

[0015] Optionally, the duty cycle in the second duty cycle interval includes a rising phase start duty cycle D1, a rising phase end duty cycle D2, a falling phase start duty cycle D3, and a falling phase end duty cycle D4, and the circuit parameters of the charging compensation module are set to comply with the following formula: , , , , Wherein, Vin and Vo represent the input voltage and output voltage of the power converter respectively, the gains of the second to fourth operational amplifiers are represented by k1 to k3 respectively, and the gain coefficients of the fifth and sixth operational amplifiers are represented by k5 and k6 respectively.

[0016] Optionally, the first operational amplifier includes a first input terminal, a first output terminal having the same polarity as the first input terminal, and a second output terminal having an opposite polarity to the first input terminal; The second output end receives the charging compensation signal respectively, and the first output end outputs the charging control signal; and, a difference between the first output terminal and the second output terminal is equal to a product of a gain of the first operational amplifier and a signal at the first input terminal; Wherein, when the power converter is a buck converter, the first input terminal of the first operational amplifier receives the input voltage; When the power converter is a boost converter, the first input terminal of the first operational amplifier receives the output voltage; When the power converter is a buck-boost converter, the first input terminal of the first operational amplifier receives the sum of the output voltage and the input voltage.

[0017] Optionally, the charging compensation module further includes: A first diode and a second diode, both of which have their anodes commonly connected to the output terminal of the fourth operational amplifier, a cathode of the first diode connected to the output terminal of the second operational amplifier, and a cathode of the second diode connected to the output terminal of the sixth operational amplifier; the charging compensation signal is generated at the anodes of the first diode and the second diode.

[0018] Optionally, the power converter includes N current ripple cancellation points, and the relationship curve between the duty cycle of the power converter and the amplitude of the charging control signal includes N second duty cycle intervals corresponding to the N current ripple cancellation points of the power converter, where N is an integer greater than or equal to 1.

[0019] Optionally, when N is greater than 1, the peak values ​​of the charging compensation signal in the N second duty cycle intervals increase sequentially.

[0020] Optionally, the ramp signal generating circuit includes N selection switches and N charging compensation modules, the N charging compensation modules are respectively connected to the first operational amplifier via corresponding selection switches, and the amplitudes of the second control signals generated by the N charging compensation modules increase sequentially.

[0021] Optionally, the power converter includes any one selected from a multi-phase power converter and a multi-level power converter.

[0022] According to a second aspect of the present application, a ramp signal generating circuit for a power converter is provided. The power converter includes an inductor, multiple sets of switching transistors for controlling charging and discharging processes of the inductor, and a current control loop for driving the multiple sets of switching transistors. The power converter generates an output voltage using a combined inductor current generated by switching actions of the multiple sets of switching transistors. The ramp signal generating circuit includes: a duty cycle calculation module, configured to calculate a duty cycle according to an input voltage and an output voltage of the power converter; A slope compensation module, configured to obtain the slope of the ramp signal according to a preset slope compensation curve, and calculate the digital value of the ramp signal in real time; and a digital-to-analog converter, configured to generate a ramp signal according to the slope, The slope compensation curve includes a continuous first duty cycle interval and a second duty cycle interval, and the slope compensation module adjusts the slope of the ramp signal according to a linear curve and a nonlinear curve respectively.

[0023] According to a third aspect of the present application, a control circuit for a power converter is provided, comprising a slope signal generation circuit as disclosed in any of the embodiments of the present application.

[0024] According to a fourth aspect of the present application, a power converter is provided, comprising a control circuit as disclosed in any of the embodiments of the present application.

[0025] According to a fifth aspect of the present application, a slope signal generation method for a power converter is provided, the power converter comprising an inductor, a plurality of groups of switching tubes for controlling a charging process and a discharging process of the inductor, and a current control loop for driving the plurality of groups of switching tubes, the power converter generating an output voltage using a combined inductor current generated by switching actions of the plurality of groups of switching tubes, the slope signal generation method comprising: obtaining a current ripple cancellation point of the power converter, the current ripple cancellation point representing a duty cycle corresponding to a minimum value of the combined inductor current generated by the switching actions of the plurality of groups of switching tubes; obtaining an input voltage and an output voltage of the power converter; and, generating a slope signal according to the input voltage and the output voltage, wherein, in generating the slope signal, a slope of the slope signal is compensated according to a slope compensation curve, the slope of the slope signal being non-linearly adjusted in a predetermined duty cycle interval of the current ripple cancellation point of the power converter; the slope of the slope signal is first increased and then decreased by the non-linear adjustment, the current ripple cancellation point being located in a maximum value part of the slope of the slope signal.

[0026] The present application has at least the following beneficial effects: The slope signal generation circuit and the slope signal generation method for a power converter provided by the present application control the size of the charging control signal according to the slope compensation curve (such as the relationship curve between the duty cycle of the power converter and the amplitude of the charging control signal) to adjust the slope of the slope signal according to the linear curve and the non-linear curve in the continuous first duty cycle interval and the second duty cycle interval, respectively, so that the slope of the slope signal can be adjusted in real time according to different duty cycles when the slope compensation is performed, and the problem of the slope of the slope signal jumping near the current ripple cancellation point does not occur. Compared with the traditional scheme, the slope modulation scheme disclosed by the present application can effectively solve the problem of gate pulse mixing near the current ripple cancellation point, effectively avoid over-compensation of the working point at the non-current ripple cancellation point, and the smooth switching of the slope of the slope signal also avoids the problem of oscillation of the system control loop and the output voltage, so that good stability and dynamic response performance can be achieved.

[0027] In a further preferred embodiment, the second duty cycle interval is set to include the current ripple cancellation point of the power converter, and the nonlinear curve corresponding to the second duty cycle interval is set to have a rising stage, a peak stage and a falling stage, so that when the slope of the ramp signal is nonlinearly adjusted within the second duty cycle interval, the slope value of the ramp signal can be controlled to first be linearly increased and then linearly decreased at a duty cycle near the current ripple cancellation point, so that the system can only use a higher slope slope compensation near the current ripple cancellation point, and work at a lower slope slope compensation at non-current ripple cancellation points in more areas, which not only ensures that the gate pulse mixing problem is avoided at the current ripple cancellation point, but also well ensures that the system can achieve higher system bandwidth and dynamic response performance at more non-current ripple cancellation points.

[0028] In a further preferred embodiment, in multi-phase or multi-level applications of power converters, it is only necessary to increase the number of second duty cycle intervals according to the actual application (for example, N-1 second duty cycle intervals corresponding to N-phase switching tubes) to solve the gate pulse mixing problem existing in multi-phase or multi-level power converters. It can be well applied to multi-phase power converters and multi-level power converters and has strong versatility.

[0029] It should be noted that the above general description and the following detailed description are merely exemplary and explanatory and do not limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic circuit diagram of a single-phase power converter is shown.

[0031] Figure 2 Show Figure 1 The typical operating waveform of the peak current control mode of the power converter shown.

[0032] Figure 3 A schematic circuit diagram of a multi-phase power converter is shown.

[0033] Figure 4 A schematic circuit diagram of a multi-level power converter is shown.

[0034] Figure 5 Show Figure 3 and Figure 4 A graph showing the relationship between current ripple and duty cycle for a power converter.

[0035] Figure 6 FIG. 4 is a schematic block diagram of a ramp signal generating circuit according to a first embodiment of the present application.

[0036] Figure 7 Show Figure 6 The slope compensation curve of the ramp signal generating circuit is shown.

[0037] Figure 8a A schematic circuit diagram of a ramp signal generating circuit according to a second embodiment of the present application is shown.

[0038] Figure 8b A schematic circuit diagram of a ramp signal generating circuit according to a third embodiment of the present application is shown.

[0039] Figure 8c A schematic circuit diagram of a ramp signal generating circuit according to a fourth embodiment of the present application is shown.

[0040] Figure 9 A schematic circuit diagram of a ramp signal generating circuit according to a fifth embodiment of the present application is shown. Figure 8a A charging compensation curve of the ramp signal generating circuit shown.

[0041] Figure 10 A schematic circuit diagram of a ramp signal generating circuit according to a fifth embodiment of the present application is shown.

[0042] Figure 11 A charging compensation curve of the ramp signal generating circuit shown. Figure 10 A charging compensation curve of the ramp signal generating circuit shown.

[0043] Figure 12 A schematic flow chart of an implementation procedure of a ramp signal generating method according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0044] The preferred embodiments of the present application are described in detail below with reference to the accompanying drawings, but the present application is not limited only to these embodiments. The present application encompasses any alternative, modification, equivalent method and scheme made within the spirit and scope of the present application.

[0045] Figure 1 A schematic circuit diagram of a single-phase power converter is shown. The power converter 100 comprises, for example, switching transistors Q1 and Q2, an inductor L, and a control circuit 101. Figure 1 In the embodiment shown, the power converter 100 adopts a buck (BUCK) topology, in which the switching transistor Q1 and the inductor L are connected in series between an input terminal and an output terminal, and the switching transistor Q2 is connected between the inductor L and a ground terminal and a middle node of the switching transistor Q1. An output capacitor Co is connected between the output terminal and the ground terminal, for obtaining a waveform of a smoothed output voltage Vo.

[0046] Although not shown in the figure, the power converter 100 further comprises a resistance network connected in series between the output terminal and the ground terminal, for obtaining a voltage feedback signal Vfb of the output voltage Vo. The power converter 100 further comprises a current detection device (for example, a sampling resistor) connected between the switching transistor Q1 and the output terminal, for obtaining a current detection signal Vsen of the inductor current iL.

[0047] The control circuit 101 includes a ramp signal generator 110, an error amplifier 102, a subtractor 103, a proportional circuit 104, a comparator 105, and an RS flip-flop 106. The positive and negative inputs of the error amplifier 102 receive a reference voltage Vref and a voltage feedback signal Vfb, respectively. The error amplifier 102 converts the differential voltage between the voltage feedback signal Vfb and the reference voltage Vref into a compensation signal Vc1. A capacitor C102 can be connected between the output of the error amplifier 102 and ground to obtain a smooth voltage waveform for the compensation signal Vc1. The ramp signal generator 110 generates a ramp signal. The subtractor 103 subtracts the compensation signal Vc1 from the ramp signal to obtain a compensation signal Vc2. The proportional circuit 104 obtains a proportional signal of the current detection signal Vsen. The positive and negative inputs of the comparator 105 receive the proportional signal of the current detection signal Vsen and the compensation signal Vc2, respectively, and compare the two to generate a reset signal. In some embodiments, the proportional circuit 104 may be omitted.

[0048] Furthermore, the control circuit 101 is further provided with a clock module (not shown) to generate a clock signal CLK, which serves as a set signal for the RS flip-flop 106. The RS flip-flop 106 generates a switch control signal PWM based on the set signal and the reset signal to control the complementary conduction of the switches Q1 and Q2. Here, the example in which both the switches Q1 and Q2 are NMOS is used for illustration.

[0049] refer to Figure 2 For example, the RS flip-flop 106 outputs a high-level switching control signal PWM at the rising edge of the clock signal CLK, and outputs a low-level switching control signal PWM when the current detection signal Vsen reaches the compensation signal Vc2. During the high-level period of the switching control signal PWM (e.g., the HS phase), the switch Q1 is turned on and the switch Q2 is turned off. During this period, the input terminal of the power converter 100 receives the input voltage Vin, charging the inductor L. The inductor current iL flows sequentially through the switch Q1 and the inductor L. During the low-level period of the switching control signal PWM (e.g., the LS phase), the switch Q1 is turned off and the switch Q2 is turned on. At this time, the inductor L is connected to the load via the switch Q2 to form a loop, supplying power to the output terminal, thereby generating the output voltage Vo. During successive switching cycles, the output capacitor Co filters the output voltage Vo to obtain a smooth voltage waveform.

[0050] Continue to refer Figure 1The ramp signal generator 110 specifically includes: a transconductance amplifier 120, a capacitor C11, and a switch Q11. The transconductance amplifier 120 is used to generate a charging current according to a charging control signal; the capacitor C11 is connected between the output terminal of the transconductance amplifier 120 and ground; the switch Q11 is connected in parallel with the capacitor C11, and the switch Q11 is controlled to be turned on or off by the switching control signal PWM. Therefore, during the switching cycle of the power converter 100, the charging current output by the transconductance amplifier 120 is used to charge the capacitor C11 and discharge it through the switch Q11 in the on state, thereby generating a ramp signal with a fixed slope to compensate for the dynamic performance of the system.

[0051] Since the gain of the transconductance amplifier 120 is usually a fixed value, the slope value of the ramp signal can be adjusted by changing the magnitude of the charging control signal received by the transconductance amplifier 120, thereby adjusting the slope value of the compensation signal Vc2. The existing typical technology is to make the slope value of the ramp signal a signal related to the input voltage Vin or the output voltage Vo (such as Figure 1 In the embodiment, the charging control signal received by the transconductance amplifier 120 is changed to the output voltage Vo), thereby achieving the purpose of adjusting the slope value of the ramp signal under different duty cycles.

[0052] When the current mode control scheme is extended to multi-phase interleaved parallel applications or multi-level applications, there are multiple current ripple cancellation points in the system. For example, Figure 3 shows a schematic circuit diagram of a multiphase power converter, Figure 4 A schematic circuit diagram of a multi-level power converter is shown. Multi-phase power converters with interleaved parallel connections are typically used in systems with high load current requirements. These systems typically employ multi-phase interleaved parallel connections to reduce the current stress of each phase circuit and improve the overall system conversion efficiency. For example, multi-phase buck converters have been widely used in VR systems. Conversely, multi-level power converters typically utilize low-voltage devices in series to meet higher voltage requirements, using multiple flying capacitors to reduce the voltage stress of power devices such as MOSFETs.

[0053] For example, Figure 3The illustrated example uses a two-phase interleaved parallel power converter as an example. The power circuit portion of the power converter 300 includes switches Q1-Q4, inductors L1 and L2, and capacitor Co. The control circuit portion of the power converter 300 includes an error amplifier 310, an adder 320, proportional circuits 350 and 340, a comparator 360, a constant on-time control unit 380, and RS flip-flops 370 and 390. Switches Q1 and Q2 are connected in series between the input voltage Vin terminal and ground, while switches Q3 and Q4 are connected in series between the input voltage Vin terminal and ground. A first end of the inductor L1 is connected to the common connection node of the switches Q1 and Q2, and a second end of the inductor L1 is connected to the output terminal. A first end of the inductor L2 is connected to the common connection node of the switches Q3 and Q4, and a second end of the inductor L2 is connected to the output terminal. Capacitor Co is connected between the output terminal and ground. The positive and negative input terminals of the error amplifier 310 receive a reference voltage Vref and a voltage feedback signal Vfb, respectively, to convert the differential voltage between the voltage feedback signal Vfb and the reference voltage Vref into a compensation signal Vc1. A capacitor may be connected between the output terminal of the error amplifier 310 and ground to obtain a smooth voltage waveform for the compensation signal Vc1. The adder 320 is configured to add the compensation signal Vc1 to the ramp signal 1 to obtain the compensation signal Vc2. The proportional circuit 340 is configured to obtain a proportional signal of the current detection signal Vsen1 of the inductor L1, and the proportional circuit 350 is configured to obtain a proportional signal of the current detection signal Vsen2 of the inductor L2. The comparator 360 receives the proportional signal of the current detection signal Vsen1, the proportional signal of the current detection signal Vsen2, and the compensation signal Vc2, respectively, and compares them to generate a set signal. The constant on-time control unit 380 is configured to generate a reset signal based on a preset constant on-time threshold. In some embodiments, the proportional circuits 340 and 350 may be omitted.

[0054] Furthermore, the control circuit portion of power converter 300 is further provided with a ramp signal generator (not shown) to generate a ramp signal. RS flip-flop 370 generates switching control signals PWM1 and PWM4 for switches Q1 and Q4 based on a set signal and a reset signal. RS flip-flop 390 generates switching control signals PWM2 and PWM3 for switches Q2 and Q3 based on a set signal and a reset signal. This description assumes that switches Q1 through Q4 are all NMOS transistors.

[0055] Figure 4The illustrated example uses a three-phase power converter as an example. The power circuit portion of the power converter 400 includes switches Q1-Q4, an inductor L, a capacitor CFLY, and a capacitor COUT. The control circuit portion of the power converter 400 includes an error amplifier 401, a subtractor 402, subtractors 405 and 406, an adder 403, a proportional circuit 407, comparator circuits 408 and 409, and RS flip-flops 410 and 411. Switches Q1, Q2, Q3, and Q4 are sequentially connected in series between the input voltage Vin terminal and ground. The first end of the inductor L is connected to the common connection node of the switches Q2 and Q3, and the second end of the inductor L is connected to the output terminal. The first end of the capacitor CFLY is connected to the common connection node of the switches Q1 and Q2, and the second end of the capacitor CFLY is connected to the common connection node of the switches Q3 and Q4. The capacitor COUT is connected between the output terminal and ground. The positive and negative inputs of the error amplifier 401 receive a reference voltage Vref and a voltage feedback signal Vfb, respectively, to convert the differential voltage between the voltage feedback signal Vfb and the reference voltage Vref into a compensation signal Vc. A capacitor can be connected between the output of the error amplifier 401 and ground to obtain a smooth voltage waveform for the compensation signal Vc. The positive and negative inputs of the error amplifier 404 receive a proportional signal of the input voltage (e.g., 1 / 2 Vin) and a voltage signal Vcfly across the capacitor CFLY, respectively, to convert the differential voltage between the proportional signal of the input voltage (e.g., 1 / 2 Vin) and the voltage signal Vcfly across the capacitor CFLY into a compensation signal Vc0. A capacitor can be connected between the output of the error amplifier 404 and ground to obtain a smooth voltage waveform for the compensation signal Vc0. The subtractor 402 is configured to subtract the compensation signal Vc from the ramp signal 1, and the adder 403 is configured to add the output signal of the subtractor 402 to the compensation signal Vc0 to obtain the compensation signal VcH. Subtractor 405 is configured to subtract the compensation signal Vc from ramp signal 2. Subtractor 406 is configured to subtract the output signal of subtractor 405 from the compensation signal Vc0 to obtain a compensation signal VcL. Proportional circuit 407 is configured to obtain a proportional signal of the current detection signal Vsen of inductor L. Comparator 408 receives the proportional signal of current detection signal Vsen and the compensation signal VcH, respectively, and compares them to generate a third reset signal. Comparator 409 receives the proportional signal of current detection signal Vsen and the compensation signal VcL, respectively, and compares them to generate a fourth reset signal. In some embodiments, proportional circuit 407 may be omitted.

[0056] Furthermore, the control circuit portion of power converter 400 is further provided with a ramp signal generator (not shown) to generate a ramp signal, and a clock module (not shown) to generate a clock signal CLK, which serves as a set signal for RS flip-flops 410 and 411. RS flip-flop 410 generates switching control signals PWM1 and PWM4 for switches Q1 and Q4 based on the set signal and a third reset signal. RS flip-flop 411 generates switching control signals PWM2 and PWM3 for switches Q2 and Q3 based on the set signal and a fourth reset signal. This description assumes that switches Q1-Q4 are all NMOS transistors.

[0057] For multi-phase interleaved parallel applications and multi-level applications of power converters, there are multiple current ripple cancellation points in the system due to the merging of inductor currents in the circuit. Figure 5 As shown, for a two-phase interleaved parallel buck power converter or a three-level buck power converter, the output current ripple amplitude approaches zero at a duty cycle of 0.5, making it impossible to compare a stable gate pulse signal sequence with a reference value. This results in pulse width oscillation near this duty cycle, a phenomenon known as "jitter." This means that the MOSFET drive pulse will experience high-frequency jitter near this duty cycle. As the number of interleaved parallel phases increases, the duty cycle at which current ripple cancellation occurs also increases. This can seriously impact the application of ripple amplitude control strategies, causing stability issues such as gate pulse mixing near each current ripple cancellation point. For circuits with more interleaved parallel phases or more levels, the number of current ripple cancellation points increases. For a four-phase interleaved parallel circuit or a five-level circuit, for example, there are three current ripple cancellation points in the system: D = 0.25, D = 0.5, and D = 0.75.

[0058] For multi-phase interleaved parallel applications and multi-level applications of power converters, based on the compensation problems of traditional solutions in solving the above-mentioned gate pulse jitter problem near the current ripple cancellation point or the problem of large fluctuations in the control loop and output voltage, this application further optimizes the ramp signal generation scheme in these application scenarios. By performing nonlinear slope compensation near the ripple cancellation point, the dynamic response performance is optimized while ensuring system stability.

[0059] Figure 6 FIG. 4 shows a schematic block diagram of a ramp signal generating circuit according to a first embodiment of the present application. Figure 7 Shown Figure 6 The slope compensation curve of the ramp signal generating circuit is shown in FIG. Figure 8a FIG2 shows a schematic circuit diagram of a ramp signal generating circuit according to a second embodiment of the present application. Figure 8bFIG. 4 shows a schematic circuit diagram of a ramp signal generating circuit according to a third embodiment of the present application. Figure 8c FIG. 4 shows a schematic circuit diagram of a ramp signal generating circuit according to a fourth embodiment of the present application. Figure 9 Shown Figure 8a The charging compensation curve of the ramp signal generating circuit is shown in FIG. Figure 10 The schematic circuit diagram of the ramp signal generating circuit of the fifth embodiment of the present application is shown. Among them, the ramp signal generating circuit provided by each embodiment of the present application can be applied to not only Figure 3 and Figure 4 The present invention can be applied to any of the multi-phase buck power converter topologies and multi-level buck power converter topologies, and can also be applied to any of the other topologies such as multi-phase boost power converter topologies, multi-phase buck-boost power converter topologies, multi-level boost power converter topologies, and multi-level buck-boost power converter topologies. Figure 3 and Figure 4 It can be understood that the common features of these power converters are that they all include an inductor, multiple sets of switching tubes for controlling the charging and discharging processes of the inductor, and a current control loop for driving the multiple sets of switching tubes. These power converters use the combined inductor current generated by the switching action of the multiple sets of switching tubes to generate the output voltage Vo.

[0060] Figure 6 An implementation scheme of the ramp signal generating circuit in this application is shown. Figure 6 As shown, the ramp signal generating circuit 10 includes: a duty cycle calculation module 11, a slope compensation module 12 and a digital-to-analog converter 13. The duty cycle calculation module 11 is used to calculate the duty cycle of the control signal of multiple groups of switch tubes in the power converter based on the input voltage Vin and the output voltage Vo of the power converter. The slope compensation module 12 is used to obtain the slope K2 of the ramp signal according to a preset slope compensation curve, and to calculate the digital value of the ramp signal in real time. The digital-to-analog converter 13 is used to generate a ramp signal according to the digital value of the ramp signal. The slope compensation curve includes a continuous first duty cycle interval and a second duty cycle interval, and the slope compensation module adjusts the slope K2 of the ramp signal according to a linear curve and a nonlinear curve in the continuous first duty cycle interval and the second duty cycle interval respectively.

[0061] Optionally, the duty cycle calculation module 11 may calculate the duty cycles of the control signals of the multiple groups of switching tubes in the power converter by using a digital circuit or an analog circuit.

[0062] refer to Figure 7, the aforementioned first duty cycle interval corresponds to, for example, 0~D1, and the second duty cycle interval corresponds to, for example, D1~D4. The linear range (Linear Range) 0~D1 corresponding to the first duty cycle interval does not include the current ripple cancellation point Dc of the power converter, and the nonlinear range (Nolinear Range) D1~D4 corresponding to the second duty cycle interval includes the current ripple cancellation point Dc of the power converter. The current ripple cancellation point Dc represents the duty cycle corresponding to the minimum value of the current ripple generated by the switching action of multiple groups of switching tubes. Taking a two-phase interleaved parallel power converter or a three-level power converter as an example, each switching cycle of the power converter includes only one first duty cycle interval and one second duty cycle interval.

[0063] Optionally, in the second duty cycle interval, the nonlinear curve in the slope compensation curve can be any one of a broken line curve and a smooth curve. For example, taking the nonlinear curve as a broken line curve as an example, Figure 7 As shown, in this embodiment, the broken line curve includes a rising phase (corresponding to phases D1 to D2), a peak phase (corresponding to phases D2 to D3), and a falling phase (corresponding to phases D3 to D4). During the rising phase, the slope K2 of the ramp signal increases linearly with increasing duty cycle D; during the peak phase, the slope K2 of the ramp signal remains constant with increasing duty cycle D, wherein the current ripple offset point Dc is located within this peak phase; during the falling phase, the slope K2 of the ramp signal decreases linearly with increasing duty cycle D. For example, when duty cycle D is D1 or D4, the slope K2 of the ramp signal is K21; when duty cycle D is D2 or D3, the slope K2 of the ramp signal is K21 + K22.

[0064] The technical solution of the present invention modulates different duty cycles. At duty cycles near the current ripple cancellation point Dc (i.e., in the second duty cycle range), the slope K2 of the ramp signal is controlled to first increase linearly and then decrease linearly. This allows the system to use a higher-slope slope compensation only near the current ripple cancellation point Dc, while operating with a lower-slope slope compensation at more areas where the current ripple is not cancelled. This prevents gate pulse mixing at the current ripple cancellation point Dc while ensuring higher system bandwidth and dynamic response performance at more non-current ripple cancellation points. Furthermore, this digital implementation has a simple structure.

[0065] like Figure 8a 、 Figure 8b and Figure 8cAs shown, the ramp signal generating circuit 20 includes: a charging control module 21, a transconductance amplifier 120, a capacitor C11, and a switch Q11. The charging control module 21 is configured to generate a charging control signal based on an input voltage Vin and an output voltage Vo. The transconductance amplifier 120 is configured to generate a charging current Ichg based on the charging control signal. The capacitor C11 is connected between the output terminal of the transconductance amplifier 120 and ground. The switch Q11 is connected in parallel with the capacitor C11. The switch Q11 is controlled to be turned on or off by a reset signal. Therefore, during a switching cycle of the power converter, the capacitor C11 is charged by the charging current Ichg output by the transconductance amplifier 120 and discharged via the on-state switch Q11 to generate a ramp signal for adjusting the first slope of the detection signal of the combined inductor current. In this embodiment, the charging control module 21 is also used to control the size of the charging control signal according to the relationship curve between the duty cycle of the power converter and the amplitude of the charging control signal. In the continuous first duty cycle interval and second duty cycle interval, the charging control module 21 adjusts the second slope of the ramp signal according to the linear curve and the nonlinear curve respectively.

[0066] refer to Figure 9 The aforementioned first duty cycle interval corresponds to, for example, 0~D1, and the second duty cycle interval corresponds to, for example, D1~D4. The linear range (Linear Range) 0~D1 corresponding to the first duty cycle interval does not include the current ripple cancellation point Dc of the power converter, and the nonlinear range (Nolinear Range) D1~D4 corresponding to the second duty cycle interval includes the current ripple cancellation point Dc of the power converter. The current ripple cancellation point Dc represents the duty cycle corresponding to the minimum current ripple generated by the switching action of multiple groups of switching tubes. For a two-phase interleaved parallel power converter or a three-level power converter, each switching cycle includes only one first duty cycle interval and one second duty cycle interval.

[0067] In some embodiments, in the first duty cycle interval, the charging control signal is constant, for example, equal to the first control signal V1. Optionally, in the second duty cycle interval, the nonlinear curve in the slope compensation curve can be any one of a broken line curve and a smooth curve. For example, taking the nonlinear curve as a broken line curve, as an example, Figure 9As shown, in this embodiment, the broken line curve includes a rising phase (corresponding to phases D1 to D2, where D1 is the starting duty cycle of the rising phase and D2 is the ending duty cycle of the rising phase), a peak phase (corresponding to phases D2 to D3, where D2 is the starting duty cycle of the peak phase and D3 is the ending duty cycle of the peak phase), and a falling phase (corresponding to phases D3 to D4, where D3 is the starting duty cycle of the falling phase and D4 is the ending duty cycle of the falling phase). Furthermore, during the rising phase, the charging control signal increases linearly with increasing duty cycle D; during the peak phase, the charging control signal remains unchanged with increasing duty cycle D, and the current ripple offset point Dc is located within the peak phase; during the falling phase, the charging control signal decreases linearly with increasing duty cycle D. For example, when the duty cycle D is D1 or D4, the charging control signal is equal to the first control signal V1; when the duty cycle D is D2 or D3, the charging control signal is equal to the sum of the first control signal V1 and the second control signal V2, that is, V1+V2.

[0068] In this application, the charging control module 21 generates multiple control signals based on the input voltage Vin and the output voltage Vo, thereby obtaining the charging control signal by performing different combination processing on the multiple control signals under different duty cycles. Specifically, during the peak phase, the charging control module 21 adds the first control signal V1 and the second control signal V2 to obtain the charging control signal; during the rising phase, the charging control module 21 adds the first control signal V1 and the third control signal V3 to obtain the charging control signal; and during the falling phase, the charging control module 21 adds the first control signal V1 and the fourth control signal V4 to obtain the charging control signal.

[0069] For example, in a two-phase interleaved parallel buck power converter or a three-level buck power converter, Figure 8a As shown, the charging control module 21 generates a first control signal V1 and a second control signal V2 according to the input voltage Vin, and generates a third control signal V3 and a fourth control signal V4 according to the input voltage Vin and the output voltage Vo, wherein the first control signal V1 and the second control signal V2 are both proportional to the input voltage Vin (for example, V1=k4·Vin, V2=k1·Vin, k1 and k4 represent proportional coefficients), the third control signal V3 is proportional to the difference between the output voltage Vo and the input voltage Vin (or the proportional signal of the input voltage Vin) (for example, V3=k3·(Vo-k2·Vin), k2 and k3 represent proportional coefficients), and the fourth control signal V4 is proportional to the difference between the input voltage Vin (or the proportional signal of the input voltage Vin) and the output voltage Vo (for example, V4=k6·(k5·Vin-Vo), k5 and k6 represent proportional coefficients).

[0070] Alternatively, in a two-phase interleaved parallel boost power converter or a three-level boost power converter, as Figure 8b As shown, the charging control module 21 generates a first control signal V1 and a second control signal V2 according to the output voltage Vo, and generates a third control signal V3 and a fourth control signal V4 according to the input voltage Vin and the output voltage Vo, wherein the first control signal V1 and the second control signal V2 are both proportional to the output voltage Vo (for example, V1=k4·Vo, V2=k1·Vo, k1 and k4 represent proportional coefficients), the third control signal V3 is, for example, equal to k3·(Vo - Vin - k2·Vo), k2 and k3 represent proportional coefficients, and the fourth control signal V4 is, for example, equal to k6·(k5·Vo -Vo-Vin), k5 and k6 represent proportional coefficients.

[0071] Alternatively, in a two-phase interleaved buck-boost power converter or a three-level buck-boost power converter, as Figure 8c As shown, the charging control module 21 generates a first control signal V1, a second control signal V2, a third control signal V3 and a fourth control signal V4 according to the input voltage Vin and the output voltage Vo, respectively, wherein the first control signal V1=k4·(Vo+Vin), the second control signal V2=k1·(Vo+Vin), k1 and k4 represent proportional coefficients, the third control signal V3=k3·(Vo-k2·(Vo+Vin)), k2 and k3 represent proportional coefficients, and the fourth control signal V4=k6·(k5·(Vo+Vin)-Vo), k5 and k6 represent proportional coefficients.

[0072] When implementing it, refer to Figure 8a 、 Figure 8b and Figure 8c The charging control module 21 includes: an operational amplifier 810 and a charging compensation module 22, wherein the operational amplifier 810 is used to obtain a first control signal V1. At this time, the aforementioned proportional coefficient k4 is the gain of the operational amplifier 810; the charging compensation module 22 is used to generate a second control signal V2, a third control signal V3 and a fourth control signal V4 according to the input voltage Vin and the output voltage Vo, and select one of the second control signal V2, the third control signal V3 and the fourth control signal V4 to generate a charging compensation signal. The charging control module 21 obtains the charging control signal by adding the first control signal V1 to the charging compensation signal.

[0073] It can be understood that within the second duty cycle interval, the peak value of the charging compensation signal is equal to the amplitude of the second control signal V2.

[0074] In some embodiments, as Figure 8a 、 Figure 8b and Figure 8cAs shown, the operational amplifier 810 includes a first input terminal, a first output terminal with the same polarity as the first input terminal, and a second output terminal with an opposite polarity to the first input terminal. The difference between the first output terminal and the second output terminal of the operational amplifier 810 is equal to the product of the signal at its first input terminal and the gain of the operational amplifier 810. In these embodiments, the second output terminal of the operational amplifier 810 receives the charging compensation signal, and the first output terminal of the operational amplifier 810 outputs the charging control signal. The charging control module 21 adjusts the potential of the second output terminal of the operational amplifier 810 to adjust the charging control signal. Figure 8a In the embodiment shown, the first output terminal of the operational amplifier 810 receives the input voltage Vin, so that the operational amplifier 810 obtains the first control signal V1 according to the input voltage Vin; Figure 8b In the embodiment shown, the first output terminal of the operational amplifier 810 receives the output voltage Vo, so that the operational amplifier 810 obtains the first control signal V1 according to the output voltage Vo; Figure 8c In the illustrated embodiment, the first output terminal of the operational amplifier 810 receives the sum of the output voltage Vo and the input voltage Vin, ie, Vo+Vin, so that the operational amplifier 810 obtains the first control signal V1 according to the sum Vo+Vin of the output voltage Vo and the input voltage Vin.

[0075] In other embodiments, the output terminals of the operational amplifier 810 and the charging compensation module 22 are both connected to the input terminals of an adder (not shown), so that the adder adds the first control signal V1 and the charging compensation signal.

[0076] Furthermore, the charging compensation module 22 includes at least operational amplifiers 820-860. Operational amplifier 840 is used to obtain the second control signal V2; operational amplifiers 820 and 830 are cascaded to obtain the third control signal V3; and operational amplifiers 850 and 860 are cascaded to obtain the fourth control signal V4. In this case, the aforementioned proportional coefficient k1 is the gain of operational amplifier 840, the proportional coefficient k2 is the gain of operational amplifier 820, the proportional coefficient k3 is the gain of operational amplifier 830, the proportional coefficient k5 is the gain of operational amplifier 850, and the proportional coefficient k6 is the gain of operational amplifier 860.

[0077] When the power converter is a step-down converter, the duty cycle D of the power converter satisfies D=Vo / Vin. Figure 8aIn the illustrated embodiment, the input terminal of the operational amplifier 840 receives the input voltage Vin, so that the operational amplifier 840 obtains the second control signal V2 based on the input voltage Vin; the positive input terminal of the operational amplifier 820 receives the input voltage Vin, the positive input terminal of the operational amplifier 830 receives the output voltage Vo, the negative input terminal of the operational amplifier 830 receives the output terminal signal of the operational amplifier 820, and the output terminal of the operational amplifier 830 outputs the third control signal V3; the positive input terminal of the operational amplifier 850 receives the input voltage Vin, the positive input terminal of the operational amplifier 860 receives the output terminal signal of the operational amplifier 850, the negative input terminal of the operational amplifier 860 receives the output voltage Vo, and the output terminal of the operational amplifier 860 outputs the fourth control signal V4.

[0078] When the power converter is a boost converter, the duty cycle D of the power converter satisfies D=1-Vin / Vo=(Vo-Vin) / Vo. Figure 8b In the illustrated embodiment, the input terminal of the operational amplifier 840 receives the output voltage Vo, so that the operational amplifier 840 obtains the second control signal V2 based on the output voltage Vo; the positive input terminal of the operational amplifier 820 receives the output voltage Vo, the positive input terminal of the operational amplifier 830 receives the difference signal between the output voltage Vo and the input voltage Vin, the negative input terminal of the operational amplifier 830 receives the output terminal signal of the operational amplifier 820, and the output terminal of the operational amplifier 830 outputs the third control signal V3; the positive input terminal of the operational amplifier 850 receives the output voltage Vo, the positive input terminal of the operational amplifier 860 receives the output terminal signal of the operational amplifier 850, the negative input terminal of the operational amplifier 860 receives the difference signal between the output voltage Vo and the input voltage Vin, and the output terminal of the operational amplifier 860 outputs the fourth control signal V4.

[0079] When the power converter is a buck-boost converter, the duty cycle D of the power converter satisfies D=Vo / (Vo+Vin). Figure 8cIn the illustrated embodiment, the input terminal of the operational amplifier 840 receives the sum of the output voltage Vo and the input voltage Vin, so that the operational amplifier 840 obtains the second control signal V2 based on the sum of the output voltage Vo and the input voltage Vin; the positive input terminal of the operational amplifier 820 receives the sum of the output voltage Vo and the input voltage Vin, the positive input terminal of the operational amplifier 830 receives the output voltage Vo, the negative input terminal of the operational amplifier 830 receives the output terminal signal of the operational amplifier 820, and the output terminal of the operational amplifier 830 outputs the third control signal V3; the positive input terminal of the operational amplifier 850 receives the sum of the output voltage Vo and the input voltage Vin, the positive input terminal of the operational amplifier 860 receives the output terminal signal of the operational amplifier 850, the negative input terminal of the operational amplifier 860 receives the output voltage Vo, and the output terminal of the operational amplifier 860 outputs the fourth control signal V4.

[0080] exist Figure 8a 、 Figure 8b and Figure 8c In the example, the gain parameters of the operational amplifiers 820 to 860 are set in accordance with the following formula, so that Figure 9 The slope compensation curve shown in: (1), (2), (3), (4).

[0081] It should be noted that in the above embodiments, when the voltage at the positive input terminal of the operational amplifier 830 or the operational amplifier 860 is less than the voltage at the negative input terminal, the voltage at the output terminal of the operational amplifier 830 or the operational amplifier 860 is zero, which is equivalent to achieving zero clamping of the output terminal signal of the operational amplifier 830 or the operational amplifier 860.

[0082] Furthermore, the charge compensation module 22 further includes a diode D11 and a diode D12, wherein the anodes of the diodes D11 and D12 are commonly connected to the output of the operational amplifier 830, while the cathode of the diode D11 is connected to the output of the operational amplifier 840, and the cathode of the diode D12 is connected to the output of the operational amplifier 860. In these embodiments, the charge compensation module 22 generates a charge compensation signal at the anodes of the diodes D11 and D12, which is equivalent to using the diodes D11 and D12 to select the second control signal V2, the third control signal V3, and the fourth control signal V4. This allows for automatic signal selection without requiring a control signal, resulting in a simple circuit structure.

[0083] Combine Figure 8a 、 Figure 8b、 Figure 8c and Figure 9 During operation, when the duty cycle of the system is less than D1, the voltage at the output terminal of the operational amplifier 830 is zero, thereby clamping the negative output terminal of the operational amplifier 810 to zero. At this time, the voltage value of the charging control signal is equal to the first control signal V1, and the slope of the ramp signal is constant at a small value; When the system duty cycle is less than D2 and greater than D1, diodes D11 and D12 are both non-conductive. At this time, the voltage value of the charging control signal at the positive output terminal of the operational amplifier 810 is equal to the sum of the first control signal V1 and the third control signal V3. The slope of the ramp signal increases linearly with the increase of the output voltage Vo. When the system duty cycle is less than D3 and greater than D2, diode D11 is conductive and D12 is non-conductive. At this time, the voltage value of the charging control signal at the positive output terminal of the operational amplifier 810 is equal to the sum of the first control signal V1 and the second control signal V2, and the slope of the ramp signal is constant at a large value. When the system duty cycle is greater than D3 and less than D4, due to the competitive effect of diodes D11 and D12, diode D12 is turned on and D11 is turned off. At this time, the voltage value of the charging control signal at the positive output terminal of the operational amplifier 810 is equal to the sum of the first control signal V1 and the fourth control signal V4. The slope of the ramp signal decreases linearly with the increase of the output voltage Vo. When the system duty cycle is greater than D4, the voltage at the output of the operational amplifier 860 is zero, thereby clamping the negative output of the operational amplifier 810 to zero. At this time, the voltage value of the charging control signal is equal to the first control signal V1, and the slope of the ramp signal is constant at a small value.

[0084] For example, if Figure 9 In the example, D1=0.3, D2=0.4, D3=0.6, and D4=0.7, then when this application is adopted Figure 8a 、 Figure 8b or Figure 8c When the ramp signal generated by the scheme performs slope compensation on the power converter, a higher slope slope compensation can be used only near the current ripple cancellation point, while a lower slope slope compensation is used at the non-current ripple cancellation point in more areas. This ensures that when a two-phase staggered parallel or three-level power converter operates at a duty cycle corresponding to the current ripple cancellation point, a stable gate pulse signal sequence can be obtained, that is, the driving pulses of multiple groups of switching tubes in the power converter will not experience high-frequency jitter near the duty cycle, and the output voltage of the system will not experience large fluctuations, and the system stability and dynamic response performance are better.

[0085] Furthermore, the power converter may include N current ripple cancellation points. Correspondingly, the relationship curve between the duty cycle of the power converter and the amplitude of the charging control signal includes N second duty cycle intervals corresponding to the N current ripple cancellation points of the power converter, where N is an integer greater than or equal to 1. In a two-phase power converter or a three-level power converter, N is equal to 1; in a power converter with more than two phases or a power converter with more than three levels, N is an integer greater than or equal to 2.

[0086] In some embodiments, when N is greater than 1, the peak values ​​of the charging compensation signal in the N second duty cycle intervals increase sequentially.

[0087] In a power converter with two or more phases or a power converter with three or more levels, the ramp signal generating circuit 20 is implemented in a specific manner. Figure 8a 、 Figure 8b or Figure 8c The difference of the example shown is that it includes N selection switches and N charging compensation modules 22, wherein the N charging compensation modules 22 are respectively connected to the operational amplifier 810 via corresponding selection switches, and the amplitudes of the second control signals V2 generated by the N charging compensation modules 22 increase in sequence. It should be noted that at this time, in a power converter with more than two phases or a step-down power converter with more than three levels, the input terminal of the operational amplifier 810 in the ramp signal generating circuit 20 receives the input voltage Vin, and the structure of each charging compensation module 22 in the ramp signal generating circuit 20 is the same as that of the embodiment shown in FIG. Figure 8a The structures of the charging compensation modules 22 in the examples shown are basically the same, and the only difference is that the gains of the operational amplifiers in the charging compensation modules 22 are different; in a power converter with two or more phases or a boost power converter with three or more levels, the input end of the operational amplifier 810 in the ramp signal generating circuit 20 receives the output voltage Vo, and the structures of the charging compensation modules 22 in the ramp signal generating circuit 20 are the same as those in the examples shown. Figure 8b The structures of the charging compensation modules 22 in the examples shown are basically the same, and the only difference is that the gains of the operational amplifiers in each charging compensation module 22 are different; in a power converter with two or more phases or a buck-boost power converter with three or more levels, the input end of the operational amplifier 810 in the ramp signal generating circuit 20 receives the sum of the input voltage Vin and the output voltage Vo, that is, Vo+Vin, and the structures of the charging compensation modules 22 in the ramp signal generating circuit 20 are the same as those in the examples shown. Figure 8c The structures of the charging compensation modules 22 in the illustrated examples are substantially the same, with the only difference being that the gains of the operational amplifiers in the charging compensation modules 22 are different.

[0088] Take N equal to 3 as an example, and take a four-phase interleaved parallel or five-level buck power converter as an example, refer to Figure 10 , Figure 10 The ramp signal generating circuit 20 shown is Figure 8a The embodiments shown are essentially the same, differing in that: Figure 10 In the illustrated embodiment, the ramp signal generating circuit 20 includes three charging compensation modules 22 and three selection switches Q11 to Q13 respectively connected between the three charging compensation modules 22 and the operational amplifier 810. The charging compensation module 22 connected to the selection switch Q11 is configured to provide a charging compensation signal 1 based on the input voltage Vin and the output voltage Vo; the charging compensation module 22 connected to the selection switch Q12 is configured to provide a charging compensation signal 2 based on the input voltage Vin and the output voltage Vo; and the charging compensation module 22 connected to the selection switch Q13 is configured to provide a charging compensation signal 3 based on the input voltage Vin and the output voltage Vo.

[0089] Figure 10 In the illustrated embodiment, preferably, the selection switches Q11 - Q13 are respectively configured to switch when the charge compensation signal output by the corresponding branch is zero, so as to avoid affecting the slope value of the generated ramp signal and causing a sudden change in the slope of the ramp signal.

[0090] At the same time, if Figure 11 As shown, the relationship curve between the duty cycle of a four-phase interleaved parallel or five-level power converter and the amplitude of the charging control signal includes three second duty cycle intervals (including D1-D4, D5-D8, and D9-D12) corresponding to the three current ripple cancellation points of the power converter. For example, in the second duty cycle interval D1-D4, the duty cycle corresponding to the current ripple cancellation point is, for example, 0.25; in the second duty cycle interval D5-D8, the duty cycle corresponding to the current ripple cancellation point is, for example, 0.5; and in the second duty cycle interval D9-D12, the duty cycle corresponding to the current ripple cancellation point is, for example, 0.75.

[0091] Furthermore, by flexibly configuring the gain parameters of each operational amplifier in each of the 22 charging compensation modules, the peak values ​​of the charging compensation signal in the three second duty cycle intervals are configured to increase sequentially. For example, peak value 1 of the charging compensation signal in the second duty cycle interval D1-D4 is smaller than peak value 2 in the second duty cycle interval D5-D8, and peak value 2 of the charging compensation signal in the second duty cycle interval D5-D8 is smaller than peak value 3 in the second duty cycle interval D9-D12.

[0092] Since, in the second duty cycle interval D1-D4, the peak value of the charging compensation signal 1 is equal to the amplitude of the second control signal V21 generated by the charging compensation module 22 connected to the selection switch Q11; in the second duty cycle interval D5-D8, the peak value of the charging compensation signal 2 is equal to the amplitude of the second control signal V22 generated by the charging compensation module 22 connected to the selection switch Q12; in the second duty cycle interval D9-D12, the peak value of the charging compensation signal 3 is equal to the amplitude of the second control signal V23 generated by the charging compensation module 22 connected to the selection switch Q13, it is equivalent to configuring the amplitudes V21, V22, and V23 of the second control signals generated by the three charging compensation modules 22 to increase sequentially.

[0093] For example, if Figure 11 In the example, D1=0.15, D2=0.2, D3=0.3, D4=0.35, D5=0.4, D6=0.45, D7=0.55, D8=0.6, D9=0.65, D10=0.7, D11=0.8, D12=0.85, then in the example of this application Figure 10 When the ramp signal generated by the buck-type scheme shown or other schemes such as the boost-type or buck-boost scheme performs slope compensation on the power converter, it is possible to use a higher slope slope compensation only near the three current ripple offset points, and operate at a lower slope slope compensation at the non-current ripple offset points in more areas, so that when the four-phase staggered parallel or five-level power converter operates at the duty cycle corresponding to each current ripple offset point, a stable gate pulse signal sequence can be obtained, that is, the driving pulses of the multiple groups of switching tubes in the power converter will not have high-frequency jitter near these duty cycles, and the output voltage of the system will not have large fluctuations, and the stability and dynamic response performance of the system are better. Furthermore, the embodiment of the present application also provides a ramp signal generation method for a power converter, which can be applied to the power converter disclosed in any embodiment of the present application. Specifically, refer to Figure 12 , the ramp signal generating method comprises executing the following steps: Step 121 : obtaining a current ripple cancellation point of the power converter, where the current ripple cancellation point represents a duty cycle corresponding to a minimum value of a combined inductor current generated by switching actions of multiple groups of switching tubes.

[0094] Step 122: Obtain the input voltage and output voltage of the power converter.

[0095] Step 123, generating a ramp signal based on the input voltage and the output voltage, wherein, when generating the ramp signal, the slope of the ramp signal is compensated according to the slope compensation curve, and the slope of the ramp signal is nonlinearly adjusted in a predetermined duty cycle interval of the current ripple cancellation point of the power converter; through the nonlinear adjustment, the slope of the ramp signal is first increased and then decreased, and the current ripple cancellation point is located at the maximum slope portion of the ramp signal.

[0096] In specific implementation, the specific implementation of each step in the ramp signal generating method for a power converter described above and the technical effects that can be brought about after implementation can refer to the relevant contents of the power converter and its ramp signal generating circuit described in the aforementioned embodiments, which will not be repeated here.

[0097] In summary, the technical solution of the present invention modulates different duty cycles, linearly increases the slope value of the slope compensation at a duty cycle near the current ripple offset point, and then linearly decreases it, which has at least the following advantages: 1. A higher slope compensation can be used only near the current ripple cancellation point, while a lower slope compensation can be used at more areas where the current ripple is not cancelled. This can avoid gate pulse mixing at the current ripple cancellation point while also ensuring higher system bandwidth and dynamic response performance at more areas where the current ripple is not cancelled. 2. The slope of the ramp signal generated during slope compensation changes continuously with the duty cycle, without any state jumps during switching. This smooth switching can avoid oscillations in the system control loop and output voltage. 3. It has a high degree of adjustable freedom and can easily configure the slope of the ramp signal under different duty cycles; 4. It can be applied to a variety of typical topology changes, has universality, and can optimize system bandwidth and stability margin.

[0098] Finally, it should be noted that the above embodiments are merely examples for the purpose of illustrating the present application and are not intended to limit the embodiments. Those skilled in the art will readily appreciate that other variations or modifications based on the above descriptions are possible. It is not necessary and impossible to enumerate all embodiments here. Obvious variations or modifications arising therefrom remain within the scope of protection of this application.

Claims

1. A ramp signal generating circuit for a power converter, the power converter comprising an inductor, multiple sets of switching transistors for controlling the charging and discharging processes of the inductor, and a current control loop for driving the multiple sets of switching transistors. The power converter generates an output voltage using a combined inductor current generated by the switching action of the multiple sets of switching transistors, characterized in that: The ramp signal generating circuit comprises: a charging control module, generating a charging control signal according to the input voltage and the output voltage of the power converter; a transconductance amplifier, generating a charging current according to the charging control signal; a capacitor connected between the output terminal of the transconductance amplifier and ground; A switch, connected in parallel with the capacitor, During a switching cycle of the power converter, the charging current is used to charge the capacitor and discharge the capacitor via the switch to generate the ramp signal for adjusting the first slope of the detection signal of the combined inductor current. The charging control module controls the magnitude of the charging control signal according to a relationship curve between the duty cycle of the power converter and the amplitude of the charging control signal. In continuous first and second duty cycle intervals, the charging control module adjusts the second slope of the ramp signal according to a linear curve and a nonlinear curve, respectively.

2. The ramp signal generating circuit according to claim 1, wherein: The first duty cycle interval does not include the current ripple cancellation point of the power converter, and the second duty cycle interval includes the current ripple cancellation point of the power converter. The current ripple cancellation point represents the duty cycle corresponding to the minimum current ripple generated by the switching action of the multiple groups of switching tubes.

3. The ramp signal generating circuit according to claim 1, wherein: In the first duty cycle interval, the charging control signal is equal to the first control signal.

4. The ramp signal generating circuit according to claim 2, wherein: The nonlinear curve may be a broken line curve or a smooth curve.

5. The ramp signal generating circuit according to claim 4, wherein: The broken line curve includes a rising stage, a peak stage and a falling stage, and the current ripple offset point is located in the peak stage.

6. The ramp signal generating circuit according to claim 5, wherein: In the peak phase, the charging control module adds the first control signal and the second control signal to obtain the charging control signal. In the rising phase, the charging control module adds the first control signal and the third control signal to obtain the charging control signal. In the falling phase, the charging control module adds the first control signal and the fourth control signal to obtain the charging control signal.

7. The ramp signal generating circuit according to claim 6, wherein: The charging control module includes: a first operational amplifier, configured to obtain the first control signal; and a charging compensation module, configured to select one of the second control signal, the third control signal, and the fourth control signal according to the input voltage and the output voltage to generate a charging compensation signal, The charging control module adds the first control signal to a charging compensation signal to obtain the charging control signal.

8. The ramp signal generating circuit according to claim 7, wherein: The charging compensation module includes: a second operational amplifier, configured to obtain the second control signal; A third operational amplifier and a fourth operational amplifier are cascaded to each other to obtain the third control signal; The fifth operational amplifier and the sixth operational amplifier are cascade-connected to each other to obtain the fourth control signal.

9. The ramp signal generating circuit according to claim 8, wherein: The power converter is a buck converter; The first operational amplifier obtains the first control signal according to the input voltage; The second operational amplifier obtains the second control signal according to the input voltage; The positive input terminal of the third operational amplifier receives the input voltage, the positive input terminal of the fourth operational amplifier receives the output voltage, the negative input terminal of the fourth operational amplifier receives the output terminal signal of the third operational amplifier, and the fourth operational amplifier outputs the third control signal; The positive input terminal of the fifth operational amplifier receives the input voltage, the positive input terminal of the sixth operational amplifier receives the output terminal signal of the fifth operational amplifier, the negative input terminal of the sixth operational amplifier receives the output voltage, and the sixth operational amplifier outputs the fourth control signal.

10. The ramp signal generating circuit according to claim 8, wherein: The power converter is a boost converter; The first operational amplifier obtains the first control signal according to the output voltage; The second operational amplifier obtains the second control signal according to the output voltage; The positive input terminal of the third operational amplifier receives the output voltage, the positive input terminal of the fourth operational amplifier receives the difference signal between the output voltage and the input voltage, the negative input terminal of the fourth operational amplifier receives the output terminal signal of the third operational amplifier, and the fourth operational amplifier outputs the third control signal; The positive input terminal of the fifth operational amplifier receives the output voltage, the positive input terminal of the sixth operational amplifier receives the output terminal signal of the fifth operational amplifier, the negative input terminal of the sixth operational amplifier receives the difference signal between the output voltage and the input voltage, and the sixth operational amplifier outputs the fourth control signal.

11. The ramp signal generating circuit according to claim 8, wherein: The power converter is a buck-boost converter; The first operational amplifier obtains the first control signal according to the sum of the output voltage and the input voltage; The second operational amplifier obtains the second control signal according to the sum of the output voltage and the input voltage; The positive input terminal of the third operational amplifier receives the sum of the output voltage and the input voltage, the positive input terminal of the fourth operational amplifier receives the output voltage, the negative input terminal of the fourth operational amplifier receives the output terminal signal of the third operational amplifier, and the fourth operational amplifier outputs the third control signal; The positive input terminal of the fifth operational amplifier receives the sum of the output voltage and the input voltage, the positive input terminal of the sixth operational amplifier receives the output signal of the fifth operational amplifier, the negative input terminal of the sixth operational amplifier receives the output voltage, and the sixth operational amplifier outputs the fourth control signal.

12. The ramp signal generating circuit according to any one of claims 8 to 11, characterized in that: The duty cycle in the second duty cycle interval includes a rising phase start duty cycle D1, a rising phase end duty cycle D2, a falling phase start duty cycle D3, and a falling phase end duty cycle D4. The circuit parameters of the charging compensation module are set to comply with the following formula: ， ， ， ， The gains of the second to fourth operational amplifiers are denoted as k1 to k3, respectively, and the gain coefficients of the fifth and sixth operational amplifiers are denoted as k5 and k6, respectively.

13. The ramp signal generating circuit according to claim 7, wherein: The first operational amplifier includes a first input terminal, a first output terminal having the same polarity as the first input terminal, and a second output terminal having an opposite polarity to the first input terminal; The second output terminal receives the charging compensation signal, and the first output terminal outputs the charging control signal; and, a difference between the first output terminal and the second output terminal is equal to a product of a gain of the first operational amplifier and a signal at the first input terminal; Wherein, when the power converter is a buck converter, the first input terminal of the first operational amplifier receives the input voltage; When the power converter is a boost converter, the first input terminal of the first operational amplifier receives the output voltage; When the power converter is a buck-boost converter, the first input terminal of the first operational amplifier receives the sum of the output voltage and the input voltage.

14. The ramp signal generating circuit according to any one of claims 8 to 11, characterized in that: The charging compensation module also includes: a first diode and a second diode, wherein the anodes of the first diode and the second diode are commonly connected to the output terminal of the fourth operational amplifier, the cathode of the first diode is connected to the output terminal of the second operational amplifier, and the cathode of the second diode is connected to the output terminal of the sixth operational amplifier; The charge compensation signal is generated at anodes of the first diode and the second diode.

15. The ramp signal generating circuit according to claim 7, wherein: The power converter includes N current ripple cancellation points, and the relationship curve between the duty cycle of the power converter and the amplitude of the charging control signal includes N second duty cycle intervals corresponding to the N current ripple cancellation points of the power converter, where N is an integer greater than or equal to 1.

16. The ramp signal generating circuit according to claim 15, wherein: When N is greater than 1, the peak values ​​of the charging compensation signal in the N second duty cycle intervals increase sequentially.

17. The ramp signal generating circuit according to claim 16, wherein: The ramp signal generating circuit includes N selection switches and N charging compensation modules. The N charging compensation modules are respectively connected to the first operational amplifier via corresponding selection switches. The amplitudes of the second control signals generated by the N charging compensation modules increase sequentially.

18. The ramp signal generating circuit according to claim 1, wherein: The power converter includes any one selected from a multi-phase power converter and a multi-level power converter.

19. A ramp signal generating circuit for a power converter, the power converter comprising an inductor, a plurality of switching transistors for controlling the charging and discharging processes of the inductor, and a current control loop for driving the plurality of switching transistors, the power converter generating an output voltage using a combined inductor current generated by the switching actions of the plurality of switching transistors, characterized in that: The ramp signal generating circuit comprises: a duty cycle calculation module, configured to calculate a duty cycle according to an input voltage and an output voltage of the power converter; A slope compensation module, configured to obtain the slope of the ramp signal according to a preset slope compensation curve, and calculate the digital value of the ramp signal in real time; and a digital-to-analog converter, configured to generate a ramp signal according to the slope, The slope compensation curve includes a continuous first duty cycle interval and a second duty cycle interval, and the slope compensation module adjusts the slope of the ramp signal according to a linear curve and a nonlinear curve respectively.

20. A control circuit for a power converter, characterized in that: include: The ramp signal generating circuit according to any one of claims 1 to 18, or the ramp signal generating circuit according to claim 19.

21. A power converter, characterized in that: include: The control circuit according to claim 20.

22. A ramp signal generation method for a power converter, wherein the power converter comprises an inductor, a plurality of switching transistors for controlling the charging and discharging processes of the inductor, and a current control loop for driving the plurality of switching transistors, wherein the power converter generates an output voltage by using a combined inductor current generated by the switching action of the plurality of switching transistors, wherein: The ramp signal generating method comprises: Obtaining a current ripple offset point of the power converter, where the current ripple offset point represents a duty cycle corresponding to a minimum value of a combined inductor current generated by switching actions of the multiple groups of switching tubes; obtaining an input voltage and an output voltage of the power converter; and generating a ramp signal according to the input voltage and the output voltage, In which, when generating a ramp signal, the slope of the ramp signal is compensated according to the slope compensation curve, and the slope of the ramp signal is nonlinearly adjusted in a predetermined duty cycle interval of the current ripple cancellation point of the power converter; through the nonlinear adjustment, the slope of the ramp signal first increases and then decreases, and the current ripple cancellation point is located at the maximum slope part of the ramp signal.

Images