Multi-cell uplink data access method, device, system and electronic equipment

Abstract

The application provides a multi-cell uplink data access method, device, system and electronic equipment, and belongs to the technical field of data processing. The method comprises the following steps: calculating the system frame offset and the sampling point offset of each synchronization cell according to the actual system frame number, the local system frame number, the actual sampling point count and the local sampling point count of each synchronization cell; sending a data storage trigger signal and / or a data reading trigger signal based on the system frame offset and the sampling point offset of each synchronization cell; the local system frame number and the local sampling point count are obtained by latching the local system frame counter and the local sampling point counter when the FPGA chip starts to store downlink data; and the actual system frame number and the actual sampling point count are determined after cell search using downlink data. The application can realize multi-cell uplink data access under a set of synchronized timing for multiple cells, reduce the difficulty of timing synchronization maintenance for multi-cell data processing, and improve the expansion flexibility.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data processing, in particular to a multi-cell uplink data access method, device, system and electronic equipment. BACKGROUND

[0002] Because the base station positions of different cells and the positions of different terminal devices (such as mobile phones) in the cell are different, the time difference of the downlink signals of different base stations reaching the monitoring device in the multi-target detection system becomes huge, so the synchronization timing needs to be maintained.

[0003] At present, the monitoring device side generally maintains a set of synchronization timing for each base station, and multiple base stations maintain multiple sets of synchronization timing.

[0004] However, because each cell maintains a set of synchronization timing, it leads to complex multi-cell synchronization maintenance, high maintenance difficulty and poor expansion effect. SUMMARY

[0005] The present application provides a multi-cell uplink data access method, device, system and electronic equipment to solve the defects of complex multi-cell synchronization maintenance, high maintenance difficulty and poor expansion effect caused by each cell maintaining a set of synchronization timing, and to realize a multi-cell uplink data access scheme with easy synchronization maintenance and flexible expansion.

[0006] The present application provides a multi-cell uplink data access method, comprising:

[0007] According to the actual system frame number and the local system frame number of each synchronization cell, the system frame offset of each synchronization cell is calculated;

[0008] According to the actual sampling point count and the local sampling point count of each synchronization cell, the sampling point offset of each synchronization cell is calculated;

[0009] Based on the system frame offset and the sampling point offset of each synchronization cell, a data storage trigger signal and / or a data read trigger signal is sent;

[0010] The local system frame number and the local sampling point count are obtained by latching the local system frame counter and the local sampling point counter when the FPGA chip starts to store the downlink data; the actual system frame number and the actual sampling point count are determined after cell search using the downlink data;

[0011] The data storage trigger signal is used to trigger the FPGA chip to store the uplink data of each synchronization cell to the data storage; the data read trigger signal is used to trigger the FPGA chip to read the target uplink data from the target address of the data storage.

[0012] According to the multi-cell uplink data access method provided in the application, the data storage trigger signal is sent based on the system frame offset and the sampling point offset of each synchronization cell, and the data storage trigger signal comprises:

[0013] The aligned system frame offset and the aligned sampling point offset of each synchronization cell are determined according to the reference system frame offset and the reference sampling point offset; the reference system frame offset and the reference sampling point offset are the system frame offset and the sampling point offset of any cell in the synchronization cells; the storage starting position of each synchronization cell is determined according to the aligned system frame offset and the aligned sampling point offset; and the data storage trigger signal is sent at the storage moment corresponding to the storage starting position of the synchronization cell of each synchronization cell, so as to trigger the FPGA chip to store the uplink data of the synchronization cell into the exclusive uplink storage space of the synchronization cell in the data storage.

[0014] According to the multi-cell uplink data access method provided in the application, the data read trigger signal is sent based on the system frame offset and the sampling point offset of each synchronization cell, and the data read trigger signal comprises:

[0015] The target address of the target uplink data is determined according to the target system frame number, the system frame offset and the sampling point offset of the target uplink data to be read; and the data read trigger signal is sent based on the target address, so as to trigger the FPGA chip to read the target uplink data from the target address in the data storage.

[0016] According to the multi-cell uplink data access method provided in the application, the data read trigger signal is sent based on the target address for each synchronization cell, and the data read trigger signal comprises:

[0017] The readable system frame interval is determined according to the current cycle local starting system frame number and the real-time local system frame number of the synchronization cell; if the target system frame number is located in the readable system frame interval, the data read trigger signal is sent based on the target address; the current cycle local starting system frame number is determined based on the local starting system frame number of the exclusive uplink storage space of the synchronization cell recorded by the FPGA chip at the beginning of the current system frame storage cycle; and the real-time local system frame number is determined based on the local system frame number of the latest stored uplink data in the exclusive uplink storage space of the synchronization cell in the current system frame storage cycle.

[0018] According to the multi-cell uplink data access method provided in the application, the data read trigger signal is sent based on the target address, and the method further comprises:

[0019] If the target system frame number is not located in the readable system frame interval, return to the step of determining the readable system frame interval according to the current period local starting system frame number and the real time local system frame number of the synchronization cell.

[0020] The application further provides a multi-cell uplink data access device, comprising:

[0021] A system frame offset determination module is configured to calculate the system frame offset of each synchronization cell according to the actual system frame number and the local system frame number of each synchronization cell.

[0022] A sampling point offset determination module is configured to calculate the sampling point offset of each synchronization cell according to the actual sampling point count and the local sampling point count of each synchronization cell.

[0023] An access signal sending module is configured to send a data storage trigger signal and / or a data reading trigger signal based on the system frame offset and the sampling point offset of each synchronization cell.

[0024] The local system frame number and the local sampling point count are obtained by latching the local system frame counter and the local sampling point counter when the FPGA chip starts to store downlink data; the actual system frame number and the actual sampling point count are determined after cell search using the downlink data.

[0025] The data storage trigger signal is used to trigger the FPGA chip to store the uplink data of each synchronization cell to the data storage; and the data reading trigger signal is used to trigger the FPGA chip to read target uplink data from a target address of the data storage.

[0026] The application further provides a multi-cell uplink data access system, comprising:

[0027] An FPGA chip;

[0028] A data storage connected to the FPGA chip;

[0029] A central processing unit connected to the FPGA chip and configured to execute the multi-cell uplink data access method.

[0030] The application further provides an electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor executes the computer program to implement the multi-cell uplink data access method.

[0031] The application further provides a non-transitory computer readable storage medium having a computer program stored thereon, wherein the computer program is executed by a processor to implement the multi-cell uplink data access method.

[0032] The application further provides a computer program product comprising a computer program which, when executed by a processor, implements the multi-cell uplink data access method according to any one of the above.

[0033] The multi-cell uplink data access method, device, system and electronic device provided by the application obtain the system frame offset and the sampling point offset of each synchronization cell by using the local system frame number and the local sampling point count obtained by latching the local system frame counter and the local sampling point counter at the time of starting to store the downlink data, in combination with the actual system frame number and the actual sampling point count obtained by performing cell search on the downlink data, so as to realize multi-cell uplink data access under a set of synchronization timing, reduce the difficulty of maintaining the timing synchronization of multi-cell data processing, and improve the expansion flexibility. BRIEF DESCRIPTION OF DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the application or the prior art, the drawings needed in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0035] Figure 1 is an example diagram of cell uplink and downlink signal transmission in the related art.

[0036] Figure 2 is one of the flowcharts of the multi-cell uplink data access method provided by the application.

[0037] Figure 3 is one of the structural diagrams of the multi-cell uplink data access system provided by the application.

[0038] Figure 4 is another flowchart of the multi-cell uplink data access method provided by the application.

[0039] Figure 5 is an example diagram of multi-cell uplink data storage provided by the application.

[0040] Figure 6 is an example diagram of periodic storage of uplink data provided by the application.

[0041] Figure 7 is a third flowchart of the multi-cell uplink data access method provided by the application.

[0042] Figure 8 is a structural diagram of the multi-cell uplink data access device provided by the application.

[0043] Figure 9This is the second structural diagram of the multi-cell uplink data access system provided in this application.

[0044] Figure 10 This is a schematic diagram of the structure of the electronic device provided in this application. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0046] It should be noted that, in the description of this application, the term "comprising" or any other variation thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances. Furthermore, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0047] The following is combined Figures 1-10 This application describes the multi-cell uplink data access method, apparatus, system, and electronic equipment provided.

[0048] Figure 1 This is an example diagram of uplink and downlink signal transmission in a cell within the relevant technology, such as... Figure 1 As shown, the solid purple line represents downlink signal transmission from the base station (cell) to the mobile phone, the solid green line represents uplink signal transmission from the mobile phone to the base station, the dashed purple line represents downlink signal transmission from the base station (cell) to the monitoring equipment, the dashed green line represents uplink signal transmission from the mobile phone to the monitoring equipment, and the arrows indicate the direction of signal transmission.

[0049] The monitoring equipment needs to simultaneously monitor terminal signals in different cells. Therefore, it must first synchronize downlink with multiple base stations (cells) to determine the location (time) of the mobile phone's uplink signal, thereby acquiring the mobile phone's uplink data. Since the locations of the base stations and the mobile phones within each cell are different, the arrival times of the downlink signals from different base stations at the monitoring equipment within the multi-target detection system vary. When GPS or BeiDou signals are disabled, the differences in the arrival times of the downlink signals from each base station and the uplink signals from the mobile phone at the monitoring equipment become significant.

[0050] At present, the common practice of the monitoring device side is to make a set of synchronization maintenance timing for each base station, and multiple base stations maintain multiple sets of synchronization timing, resulting in the problems of complex structure of maintenance control implementation, high maintenance difficulty and inflexible expansion.

[0051] Therefore, the present application provides a multi-cell uplink data access method, device, system and electronic equipment, which adopts a unified spatial time-sharing synchronization mode for multi-cell downlink synchronization, i.e., a unified downlink storage space is opened, and downlink data is time-division stored for time-division downlink synchronization. After synchronization of multiple cells, multiple uplink storage spaces are opened, one of which is taken as a reference to uniformly trigger storage of uplink data of multiple cells in different storage spaces, and a periodic storage strategy is implemented, downlink synchronization position parameters are recorded according to time division, random scheduling is performed, and uplink data of each cell is obtained on demand to support multi-standard (4G / 5G, etc.), multi-cell synchronization time-division processing, unified storage of multi-cell service data, and dynamic random scheduling to obtain target data.

[0052] Figure 2 is one of the flowcharts of the multi-cell uplink data access method provided by the present application, as shown in Figure 2 The multi-cell uplink data access method includes but is not limited to steps 201 to 203.

[0053] It should be noted that the execution subject of the multi-cell uplink data access method provided by the present application is a corresponding multi-cell uplink data storage device, which can be a central processing unit (CPU), a server and a computer device, such as a mobile phone, a tablet computer, a notebook computer, a palm computer, a vehicle-mounted electronic device, a wearable device, an ultra-mobile personal computer (UMPC), a netbook or a personal digital assistant (PDA), etc.

[0054] Step 201: According to the actual system frame number and the local system frame number of each synchronization cell, the system frame deviation of each synchronization cell is calculated.

[0055] Step 202: According to the actual sampling point count and the local sampling point count of each synchronization cell, the sampling point deviation of each synchronization cell is calculated.

[0056] The local system frame number and the local sampling point count are obtained by latching a local system frame counter and a local sampling point counter when the FPGA (Field-Programmable Gate Array) chip starts to store the downlink data; the actual system frame number and the actual sampling point count are determined after cell search is performed using the downlink data.

[0057] Figure 3 is one of the structural diagrams of the multi-cell uplink data access system provided in the present application, as shown in Figure 3 The execution subject of the multi-cell uplink data access method provided in the present application is taken as an example of a CPU, and the multi-cell uplink data access system includes an antenna radio frequency module, an FPGA chip, a data storage, and a CPU. The FPGA chip is connected with the antenna radio frequency module, the data storage, and the CPU. The solid arrow represents the transmission direction of air interface data (including uplink data and downlink data), and the dashed arrow represents the transmission direction of control signals.

[0058] The data storage can be any one of a DDR (Double Data Rate Memory), a GDDR (Graphics DDR), a LPDDR (Low Power DDR), a DRAM (Dynamic Random Access Memory), and a SDRAM (Synchronous DRAM).

[0059] Specifically, in combination with Figure 2 and Figure 3 As shown, for each synchronization cell, when the FPGA chip starts to store the downlink data of the synchronization cell in the unified downlink storage space opened in the data storage through a downlink storage channel, the local system frame counter and the local sampling point counter are latched to obtain the local system frame number and the local sampling point count. After the downlink data of the synchronization cell is stored in the data storage, the CPU controls the FPGA chip to perform cell search using the stored downlink data. After successful search, the cell search result including the search position and the actual air interface frame number is obtained. According to the cell search result, the actual system frame number and the actual sampling point count can be determined. According to the actual system frame number and the local system frame number of the synchronization cell, the system frame offset of the synchronization cell can be calculated. According to the actual sampling point count and the local sampling point count of the synchronization cell, the sampling point offset of the synchronization cell can be calculated.

[0060] For different synchronization cells, the foregoing steps of latching the local system frame counter and the local sampling point counter when starting to store the downlink data in the unified downlink storage space, performing cell search to obtain the actual system frame number and the actual sampling point count when the downlink data is completed, and calculating the system frame offset and the sampling point offset can be repeated to obtain the system frame offset and the sampling point offset of each synchronization cell.

[0061] It can be understood that the local system frame number and the local sampling point count obtained by the FPGA chip latching the local system frame counter and the local sampling point counter can be reported to the CPU at the time of latching or can be reported to the CPU after the downlink data is completely stored. The application does not limit the time when the FPGA chip reports the local system frame number and the local sampling point count to the CPU.

[0062] It should be noted that the execution order of steps 201 and 202 can be to execute step 201 first and then execute step 202, or to execute step 202 first and then execute step 201, or to execute steps 201 and 202 at the same time. The application does not limit this.

[0063] In a specific embodiment, Figure 4 is a second flowchart of the multi-cell uplink data access method provided by the application, which is combined with Figure 3 and Figure 4 to take the synchronization of four cells, synchronization cell 0 to synchronization cell 3, as an example. The CPU first opens the antenna radio frequency switch of the cell to be sampled in the antenna radio frequency module, and configures the radio frequency cell frequency and the ADC sampling chip, for example, based on ADS58C20 (DL downlink channel) sampling. The CPU also starts the local system frame counter and the local sampling point counter of the FPGA chip and configures the sampling path of the downlink storage channel cell in the FPGA chip.

[0064] The CPU manually triggers the random trigger mode, stores the downlink data of synchronization cell 0 to the downlink storage space of the data storage through the downlink storage channel of the FPGA chip, latches the local system frame counter and the local sampling point counter of the FPGA chip, obtains the local system frame number and the local sampling point count of synchronization cell 0, and reports them to the CPU. After storing the downlink data of a preset size, such as 1 second of downlink data (overlapping and repeatedly storing after 1 second period), i.e., 100 system frames, the CPU starts to perform cell search, reads and uses the downlink data of the downlink storage space to perform cell search. If the cell search is successful, the cell search result including the search position and the actual air interface frame number is obtained, the actual system frame number and the starting symbol position (the starting position of the symbol sampling point) of the downlink data storage are calculated, and then the actual system frame number and the actual sampling point count of synchronization cell 0 are obtained.

[0065] According to the local system frame counter, the local sampling point counter, the actual system frame number and the actual sampling point counter of the synchronization cell 0, the system frame deviation delta_sys0 between the actual system frame number and the local system frame number of the synchronization cell 0 and the sampling point deviation delta_cnt0 between the actual sampling point counter and the local sampling point counter of the synchronization cell 0 are calculated and recorded, and the search of the synchronization cell 0 is completed.

[0066] It is further judged whether all the four cells are searched, and since the deviation calculation of the synchronization cell 1 to the synchronization cell 3 is still needed, the step of configuring the sampling path of the FPGA chip is returned until all the four synchronization cells are searched, and four groups of deviation values corresponding to the synchronization cell 0 to the synchronization cell 3 are obtained, each group of deviation values including the system frame deviation and the sampling point deviation. Finally, the downlink storage channel of the FPGA chip is closed.

[0067] In step 203, based on the system frame deviation and the sampling point deviation of each synchronization cell, a data storage trigger signal and / or a data reading trigger signal are sent.

[0068] The data storage trigger signal is used to trigger the FPGA chip to store the uplink data of each synchronization cell to the data storage; and the data reading trigger signal is used to trigger the FPGA chip to read the target uplink data from the target address of the data storage.

[0069] Specifically, after the system frame deviation and the sampling point deviation of each synchronization cell are obtained, the CPU can send different data storage trigger signals (control signals) to the FPGA chip according to the system frame deviation and the sampling point deviation of different synchronization cells, so as to trigger the FPGA chip to store the uplink data of different synchronization cells to the exclusive uplink storage space corresponding to each synchronization cell in the data storage through different uplink storage channels.

[0070] In addition, the CPU can also determine the target address of the service demand data in the data storage, and send different data reading trigger signals (control signals) to the FPGA chip according to the system frame deviation and the sampling point deviation of different synchronization cells, so as to trigger the FPGA chip to read the target uplink data required by the service from the target address of the exclusive uplink storage space corresponding to each synchronization cell in the data storage.

[0071] The multi-cell uplink data access method provided in the application obtains the system frame number and the local sampling point count of the local system frame counter and the local sampling point counter at the time of starting to store the downlink data, and obtains the system frame offset and the sampling point offset of each synchronization cell by combining the actual system frame number and the actual sampling point count obtained by performing cell search on the downlink data, so as to realize multi-cell uplink data access under a set of synchronization timing of multiple cells, reduce the difficulty of maintaining the timing synchronization of multi-cell data processing, and improve the expansion flexibility.

[0072] Based on the above embodiment, as an optional embodiment, the data storage trigger signal is sent based on the system frame offset and the sampling point offset of each synchronization cell, and the data storage trigger signal comprises:

[0073] According to the reference system frame offset and the reference sampling point offset, the alignment system frame offset and the alignment sampling point offset of each synchronization cell are determined; the reference system frame offset and the reference sampling point offset are the system frame offset and the sampling point offset of any cell in the synchronization cells; according to the alignment system frame offset and the alignment sampling point offset, the storage starting position of each synchronization cell is determined; for each synchronization cell, the data storage trigger signal is sent at the storage time corresponding to the storage starting position of the synchronization cell, so as to trigger the FPGA chip to store the uplink data of the synchronization cell into the exclusive uplink storage space of the synchronization cell in the data storage.

[0074] Specifically, after the synchronization of the cells, the CPU selects any cell in the synchronization cells as a reference cell, and determines the system frame offset and the sampling point offset of the reference cell as the reference system frame offset and the reference sampling point offset. Further, according to the reference system frame offset and the reference sampling point offset, the system frame offset and the sampling point offset of each synchronization cell are aligned to obtain the alignment system frame offset and the alignment sampling point offset of each synchronization cell. Still further, according to the alignment system frame offset and the alignment sampling point offset, the storage starting position of the uplink data in the exclusive uplink storage space corresponding to each synchronization cell is determined.

[0075] For each synchronization cell in the synchronization cells, the CPU can send the data storage trigger signal to the FPGA chip at the storage time corresponding to the storage starting position of the synchronization cell, specifically, when the target starting system frame and the starting sampling point match the local system frame counter and the local sampling point counter of the FPGA chip, so as to trigger the FPGA chip to store the uplink data of the synchronization cell into the exclusive uplink storage space of the synchronization cell in the data storage, and start the storage. It can be understood that, since the CPU sends the data storage trigger signal to the FPGA chip at the storage time corresponding to the storage starting position of the synchronization cell, it can be ensured that the storage starting position of the uplink data of the synchronization cell is the same each time.

[0076] It can be understood that the CPU can send multiple data storage trigger signals to the corresponding FPGA chips in parallel, or can send a single data storage trigger signal to the corresponding FPGA chip in sequence.

[0077] Figure 5 FIG. 1 is an example diagram of multi-cell uplink data storage provided by the present application, as shown in FIG. 1, taking storage of uplink data of four cells, i.e., synchronization cell 0~synchronization cell 3, as an example. Figure 5 As shown in FIG. 1, taking storage of uplink data of four cells, i.e., synchronization cell 0~synchronization cell 3, as an example, after synchronization of the four cells, four sets of offset values composed of system frame offset and sampling point offset are obtained, and the offset values of the cells are: [delta_sys0, delta_cnt0], [delta_sys1, delta_cnt1], [delta_sys2, delta_cnt2] and [delta_sys3, delta_cnt3] in turn.

[0078] Taking synchronization cell 0 as a reference cell, the system frame offset and the sampling point offset of the reference cell are taken as the reference system frame offset and the reference sampling point offset, and the storage starting position of the uplink data of the synchronization cell 0 is aligned with the air interface time frame, i.e., the starting position of a certain n system frame of the synchronization cell 0, and the CPU sends the data storage trigger signal of the synchronization cell 0 at the storage moment corresponding to the storage starting position. By analogy, in the case of position reason or GPS being closed, the synchronization cell 1 starts to store data at the end position of the 2nd sym of the subframe 0 of the system frame n; the storage starting point of the synchronization cell 2 is a certain position of the symbol 12 of the subframe 9 of the system frame n-1; the synchronization cell 3 is exactly aligned with the synchronization cell 0 in the air interface, and the storage starting position is also the starting position of a certain n system frame; the CPU sends the data storage trigger signal of the synchronization cell 1, 2 and 3 to the FPGA chip at the storage moment corresponding to the storage starting position of the three synchronization cells.

[0079] The multi-cell uplink data access method provided by the present application takes any one of the multiple cells as a reference cell, uses the system frame offset and the sampling point offset of the reference cell as the reference to align the system frame offset and the sampling point offset of the multiple cells, to further determine the storage starting position of the multiple cells, and triggers storage of the uplink data of the corresponding cell only at the storage moment corresponding to the storage starting position of the synchronization cell, thereby realizing storage of the uplink data of the multiple cells under only one set of synchronization timing, reducing the difficulty of synchronization timing maintenance of the multi-cell data storage, and improving the expansion flexibility.

[0080] Based on the above embodiment, as an optional embodiment, the sending of the data read trigger signal based on the system frame offset and the sampling point offset of each synchronization cell comprises:

[0081] determine the target address of the target uplink data according to the target system frame number of the target uplink data to be read, the system frame offset and the sampling point offset; and send the data read trigger signal based on the target address, so as to trigger the FPGA chip to read the target uplink data from the target address of the data storage.

[0082] Specifically, the CPU determines the target system frame number of the target uplink data to be read in the exclusive uplink storage space of the corresponding synchronization cell according to the service requirement, and determines the target address of the target uplink data according to the target system frame number and the system frame offset and the sampling point offset of the corresponding synchronization cell.

[0083] The CPU further generates and sends a data read trigger signal to the FPGA chip based on the target address, so as to trigger the FPGA chip to read the target uplink data from the target address of the data storage and return to the CPU, so as to meet the service requirement of the CPU.

[0084] It can be understood that in the case of different service requirements, the target uplink data to be read can involve multiple synchronization cells at the same time, and at this time the CPU can send multiple data read trigger signals for different cells based on the target addresses corresponding to the synchronization cells, so as to trigger the FPGA chip to read the target uplink data from the target addresses of different exclusive uplink storage spaces of the data storage.

[0085] The multi-cell uplink data access method provided in the application determines the target address according to the target system frame number of the target uplink data, the system frame offset and the sampling point offset of each synchronization cell, and then sends a data read trigger signal to the FPGA chip based on the target address, thereby realizing multi-cell uplink data reading under a set of synchronization timing for multiple cells, reducing the difficulty of maintaining the timing synchronization of multi-cell data reading, and improving the expansion flexibility.

[0086] Based on the above embodiment, as an optional embodiment, for each synchronization cell, the sending of the data read trigger signal based on the target address comprises:

[0087] determining a readable system frame interval according to the current cycle local starting system frame number and the real-time local system frame number of the synchronization cell; if the target system frame number is located in the readable system frame interval, sending the data read trigger signal based on the target address; the current cycle local starting system frame number is determined based on the local starting system frame number of the exclusive uplink storage space of the synchronization cell recorded by the FPGA chip at the beginning of the current system frame storage cycle; and the real-time local system frame number is determined based on the local system frame number of the latest stored uplink data in the exclusive uplink storage space of the synchronization cell in the current system frame storage cycle.

[0088] Based on the above embodiment, as an optional embodiment, the sending the data read trigger signal based on the target address further comprises: if the target system frame number is not located in the readable system frame interval, returning to the step of determining the readable system frame interval according to the current cycle local starting system frame number and the real-time local system frame number of the synchronization cell.

[0089] In some cases, the uplink data is stored in a periodic storage mode. For example, the storage period is 1 second, and after 1 second, the dedicated uplink storage space is overwritten to repeatedly store uplink data.

[0090] Figure 6 is an example diagram of the periodic storage of uplink data provided by the present application, as Figure 6 As shown, the size of the dedicated uplink storage space corresponding to a certain synchronization cell is between positions ① and ④. In the current cycle, the uplink data has been stored from the storage starting position ① to position ③, and the target address of the target uplink data to be read needs to be located between positions ① and ③. For example, if the target address of the target uplink data is located at position ②, it is readable data, and if the target address of the target uplink data is located between positions ③ and ④, it is not readable data. Therefore, in order to avoid the situation that the target uplink data to be read is not readable, the CPU first performs a readability decision before sending the data read trigger signal.

[0091] Specifically, in the case of periodic storage of uplink data, the CPU obtains the local starting system frame number of the dedicated uplink storage space of the synchronization cell recorded by the FPGA chip at the beginning of the current system frame storage period, and determines the current cycle local starting system frame number by combining the system frame offset of the synchronization cell. The CPU also obtains the local system frame number of the latest stored uplink data in the dedicated uplink storage space of the synchronization cell within the current system frame storage period, and determines the real-time local system frame number by combining the system frame offset of the synchronization cell. The CPU further determines the readable system frame interval by combining the current cycle local starting system frame number and the real-time local system frame number, and judges whether the target system frame number of the target uplink data is located in the readable system frame interval.

[0092] If the target system frame number is located in the readable system frame interval, the CPU sends the data read trigger signal to the FPGA chip based on the target address to trigger the FPGA chip to read the target uplink data from the target address.

[0093] If the target system frame number is not located in the readable system frame interval, the step of determining the readable system frame interval according to the current cycle local starting system frame number and the real-time local system frame number of the synchronization cell is returned to, and the judgment of whether the target system frame number is located in the readable system frame interval is re-performed until the target system frame number is located in the readable system frame interval.

[0094] Figure 7 is a third flowchart of the multi-cell uplink data access method provided in the present application, as shown in the figure, in a specific embodiment, the CPU configures a storage period a and a period storage length b, in units of 1 system frame. For example, a = b = 100, so the initial system frame storage period is [a, a + b - 1] = [100, 199], and the subsequent system frame storage periods are [200, 299], [300, 399], [400, 499], and so on. Figure 7

[0095] The CPU also configures a local starting system frame and a starting sampling point. When the local starting system frame matches the local system frame count of the FPGA chip and the starting sampling point matches the local sampling point count of the FPGA chip, the periodic storage of the air interface data of the multiple cells begins.

[0096] In each current storage period, the FPGA chip records the local starting system frame number and the local sampling point count of the exclusive uplink storage space of the synchronous cell at the beginning of the current system frame storage period and reports them to the CPU. The CPU determines the current period local starting system frame number according to the received local starting system frame number and the system frame offset determined at the time of cell synchronization.

[0097] The CPU also determines the real-time local system frame number in real time by combining the local system frame number reported by the FPGA chip and the system frame offset determined at the time of cell synchronization when the target system frame is readable.

[0098] The CPU determines whether the target system frame number is located within the readable system frame interval. If yes, a data read trigger signal is sent to the FPGA chip based on the target address, and the target uplink data is read from the target address. If no, the step of determining the readable system frame interval is returned to until the target system frame number is located within the readable system frame interval. In this way, the target uplink data of all cells is read in turn.

[0099] Taking a storage period of 100 frames (i.e., 1 second) as an example, if the current period local starting system frame number is 200, the target system frame number of the target uplink data is 240, and the real-time local system frame number is 280, then the target system frame number 240 is located within the readable system frame interval [200, 280], and the target uplink data is readable, so a data read trigger signal is sent based on the target address of the target uplink data.

[0100] ​For example, if the storage period is 200 frames, the local starting system frame number of the current period is 7, the target system frame number of the target uplink data is 115, and the real-time local system frame number is 110, the target system frame number 115 is not located in the readable system frame interval [7, 110], and the target uplink data is currently not readable, but is readable in the current storage period.

[0101] For example, if the storage period is 64 frames, the local starting system frame number of the current period is 100, the target system frame number of the target uplink data is 166, and the real-time local system frame number is 150, the target system frame number is located outside the readable system frame interval [100, 164], and the target system frame of the uplink data is not readable in the current storage period and is readable in the next storage period [165, 229].

[0102] The multi-cell uplink data access method provided in the application avoids the situation that the target uplink data to be read is not readable, improves the success rate of data reading, by judging whether the target system frame number of the target uplink data is located in the readable system frame interval in the case of periodic storage of uplink data, and sending a data reading trigger signal only when the target system frame number is located in the readable system frame interval.

[0103] Figure 8 FIG. 1 is a structural schematic diagram of the multi-cell uplink data access device provided in the application, as shown in FIG. 1, the multi-cell uplink data access device includes but is not limited to a system frame deviation determination module 801, a sampling point deviation determination module 802, and an access signal sending module 803. Figure 8

[0104] The system frame deviation determination module 801 is configured to calculate the system frame deviation of each synchronization cell according to the actual system frame number and the local system frame number of each synchronization cell.

[0105] The sampling point deviation determination module 802 is configured to calculate the sampling point deviation of each synchronization cell according to the actual sampling point count and the local sampling point count of each synchronization cell.

[0106] The access signal sending module 803 is configured to send a data storage trigger signal and / or a data reading trigger signal based on the system frame deviation and the sampling point deviation of each synchronization cell.

[0107] The local system frame number and the local sampling point count are obtained by latching the local system frame counter and the local sampling point counter when the FPGA chip starts to store downlink data; and the actual system frame number and the actual sampling point count are determined after cell search using the downlink data.

[0108] ​The data storage trigger signal is used to trigger the FPGA chip to store the uplink data of each synchronization cell into the data memory; the data read trigger signal is used to trigger the FPGA chip to read the target uplink data from the target address of the data memory.

[0109] It should be noted that the multi-cell uplink data access device provided in this application can execute the multi-cell uplink data access method described in any of the above embodiments during actual operation, which will not be elaborated in this embodiment.

[0110] The multi-cell uplink data access device provided in this application obtains the local system frame number and local sampling point count by latching the local system frame counter and local sampling point counter when downlink data storage begins, and combines them with the actual system frame number and actual sampling point count obtained by cell search of downlink data to obtain the system frame deviation and sampling point deviation of each synchronized cell. This enables multi-cell uplink data access to maintain only one set of synchronization timing for multiple cells, reducing the difficulty of timing synchronization maintenance in multi-cell data processing and improving expansion flexibility.

[0111] Figure 9 This is the second structural diagram of the multi-cell uplink data access system provided in this application, as shown below. Figure 9 As shown, the multi-cell uplink data access system includes an FPGA chip 901, a data storage device 902 connected to the FPGA chip, and a central processing unit 903 connected to the FPGA chip. It is used to execute the multi-cell uplink data access method provided in any of the above embodiments. The multi-cell uplink data access method includes, but is not limited to, the following steps: calculating the system frame deviation of each synchronized cell based on the actual system frame number and the local system frame number of each synchronized cell; calculating the sampling point deviation of each synchronized cell based on the actual sampling point count and the local sampling point count of each synchronized cell; sending a data storage trigger signal and / or sending a data read trigger signal based on the system frame deviation and the sampling point deviation of each synchronized cell; the local system frame number and the local sampling point count are obtained by latching the local system frame counter and the local sampling point counter when the FPGA chip starts storing downlink data; the actual system frame number and the actual sampling point count are determined after cell search using the downlink data; the data storage trigger signal is used to trigger the FPGA chip to store the uplink data of each synchronized cell into the data storage device; the data read trigger signal is used to trigger the FPGA chip to read the target uplink data from the target address of the data storage device.

[0112] It should be noted that the multi-cell uplink data access system provided in this application can execute the multi-cell uplink data access method described in any of the above embodiments during actual operation, which will not be elaborated in this embodiment.

[0113] The multi-cell uplink data access system provided by the application obtains the system frame offset and the sampling point offset of each synchronization cell by using the local system frame number and the local sampling point count obtained by latching the local system frame counter and the local sampling point counter when starting to store the downlink data, and combining the actual system frame number and the actual sampling point count obtained by performing cell search on the downlink data, so as to realize multi-cell uplink data access under a set of synchronization timing, reduce the difficulty of maintaining the timing synchronization of multi-cell data processing, and improve the expansion flexibility.

[0114] Figure 10 is a structural schematic diagram of an electronic device provided by the application, as shown in Figure 10 The electronic device can include a processor 1010, a communications interface 1020, a memory 1030, and a communications bus 1040, wherein the processor 1010, the communications interface 1020, and the memory 1030 complete mutual communication through the communications bus 1040. The processor 1010 can invoke the logical instructions in the memory 1030 to execute the multi-cell uplink data access method provided by any of the above embodiments, which includes but is not limited to the following steps: calculating the system frame offset of each synchronization cell according to the actual system frame number and the local system frame number of each synchronization cell; calculating the sampling point offset of each synchronization cell according to the actual sampling point count and the local sampling point count of each synchronization cell; sending a data storage trigger signal and / or a data reading trigger signal based on the system frame offset and the sampling point offset of each synchronization cell; the local system frame number and the local sampling point count are obtained by latching the local system frame counter and the local sampling point counter when the FPGA chip starts to store the downlink data; the actual system frame number and the actual sampling point count are determined after performing cell search on the downlink data; the data storage trigger signal is used to trigger the FPGA chip to store the uplink data of each synchronization cell to a data storage; and the data reading trigger signal is used to trigger the FPGA chip to read the target uplink data from the target address of the data storage.

[0115] Further, the logic instructions in the memory 1030 described above can be implemented in the form of software functional units and sold or used as independent products, which can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the parts that make contributions to the prior art or parts of the technical solutions can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0116] In another aspect, the present application also provides a computer program product, which comprises a computer program, the computer program can be stored on a non-transitory computer readable storage medium, and the computer program can be executed by a processor to enable a computer to execute the multi-cell uplink data access method provided by any of the above embodiments, which includes but is not limited to the following steps: calculating the system frame offset of each synchronization cell according to the actual system frame number and the local system frame number of each synchronization cell; calculating the sampling point offset of each synchronization cell according to the actual sampling point count and the local sampling point count of each synchronization cell; sending a data storage trigger signal and / or a data read trigger signal based on the system frame offset and the sampling point offset of each synchronization cell; the local system frame number and the local sampling point count are obtained by latching the local system frame counter and the local sampling point counter when the FPGA chip starts to store downlink data; the actual system frame number and the actual sampling point count are determined after performing cell search using the downlink data; the data storage trigger signal is used to trigger the FPGA chip to store the uplink data of each synchronization cell to the data storage; and the data read trigger signal is used to trigger the FPGA chip to read the target uplink data from the target address of the data storage.

[0117] In yet another aspect, the present application also provides a non-transitory computer readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the multi-cell uplink data access method provided by any of the above embodiments. The multi-cell uplink data access method includes but is not limited to the following steps: calculating the system frame offset of each synchronization cell according to the actual system frame number and the local system frame number of each synchronization cell; calculating the sampling point offset of each synchronization cell according to the actual sampling point count and the local sampling point count of each synchronization cell; sending a data storage trigger signal and / or a data read trigger signal based on the system frame offset and the sampling point offset of each synchronization cell; the local system frame number and the local sampling point count are obtained by latching the local system frame counter and the local sampling point counter when the FPGA chip starts to store downlink data; the actual system frame number and the actual sampling point count are determined after cell search using the downlink data; the data storage trigger signal is used to trigger the FPGA chip to store the uplink data of each synchronization cell to the data storage; and the data read trigger signal is used to trigger the FPGA chip to read the target uplink data from the target address of the data storage.

[0118] The apparatus embodiments described above are merely illustrative, wherein the units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units, i.e., can be located in one place, or can be distributed on multiple network units. Part or all of the modules can be selected to achieve the purpose of the embodiment according to actual needs. Those skilled in the art can understand and implement without creative labor.

[0119] From the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be realized by means of software and necessary general hardware platform, and of course can also be realized by hardware. Based on such understanding, the above technical solutions can be embodied in the form of software product, which can be stored in a computer readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes a plurality of instructions to make a computer device (which can be a personal computer, server, or network device, etc.) execute the method described in each embodiment or some part of the embodiment.

[0120] Finally, it should be noted that the above examples are only used to illustrate the technical solutions of the present application, and are not intended to limit the same; although the present application has been described in detail with reference to the foregoing examples, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing examples, or make equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for multi-cell uplink data access, the method comprising: The method comprises the following steps: calculating system frame offsets of each synchronization cell according to actual system frame numbers and local system frame numbers of each synchronization cell; calculating sampling point offsets of each synchronization cell according to actual sampling point counts and local sampling point counts of each synchronization cell; sending data storage trigger signals and / or data read trigger signals based on the system frame offsets and the sampling point offsets of each synchronization cell; the local system frame numbers and the local sampling point counts are obtained by latching local system frame counters and local sampling point counters when the FPGA chip starts to store downlink data; the actual system frame numbers and the actual sampling point counts are determined after cell search using the downlink data; the data storage trigger signals are used to trigger the FPGA chip to store uplink data of each synchronization cell to a data storage; the data read trigger signals are used to trigger the FPGA chip to read target uplink data from a target address of the data storage.

2. The method of claim 1, wherein, The method for sending data storage trigger signals based on the system frame offsets and the sampling point offsets of each synchronization cell comprises the following steps: determining aligned system frame offsets and aligned sampling point offsets of each synchronization cell according to reference system frame offsets and reference sampling point offsets; the reference system frame offsets and the reference sampling point offsets are the system frame offsets and the sampling point offsets of any cell in each synchronization cell; determining storage start positions of each synchronization cell according to the aligned system frame offsets and the aligned sampling point offsets; for each synchronization cell, sending the data storage trigger signal at a storage time corresponding to the storage start position of the synchronization cell to trigger the FPGA chip to store uplink data of the synchronization cell to a dedicated uplink storage space of the synchronization cell in the data storage.

3. The method of claim 1, wherein, The method for sending data read trigger signals based on the system frame offsets and the sampling point offsets of each synchronization cell comprises the following steps: determining the target address of the target uplink data according to a target system frame number of the target uplink data, the system frame offsets and the sampling point offsets; sending the data read trigger signal based on the target address to trigger the FPGA chip to read the target uplink data from the target address of the data storage.

4. The method of claim 3, wherein, For each synchronization cell, the method for sending the data read trigger signal based on the target address comprises the following steps: determining a readable system frame interval according to a current cycle local start system frame number and a real-time local system frame number of the synchronization cell; if the target system frame number is located in the readable system frame interval, sending the data read trigger signal based on the target address; the current cycle local start system frame number is determined based on a local start system frame number of a dedicated uplink storage space of the synchronization cell recorded by the FPGA chip at the beginning of a current system frame storage cycle; the real-time local system frame number is determined based on a local system frame number of the latest stored uplink data in the dedicated uplink storage space of the synchronization cell in the current system frame storage cycle.

5. The method of claim 4, wherein, The sending the data read trigger signal based on the target address further includes: If the target system frame number is not in the readable system frame interval, returning to the step of determining the readable system frame interval according to the current cycle local start system frame number and the real-time local system frame number of the synchronization cell.

6. A multi-cell uplink data access device, comprising: The method comprises: A system frame offset determination module configured to calculate system frame offsets of the synchronization cells according to actual system frame numbers and local system frame numbers of the synchronization cells; A sampling point offset determination module configured to calculate sampling point offsets of the synchronization cells according to actual sampling point counts and local sampling point counts of the synchronization cells; An access signal sending module configured to send data storage trigger signals and / or data read trigger signals based on the system frame offsets and the sampling point offsets of the synchronization cells; The local system frame number and the local sampling point count are obtained by latching local system frame counters and local sampling point counters when the FPGA chip starts to store downlink data; the actual system frame number and the actual sampling point count are determined after cell search using the downlink data; The data storage trigger signal is used to trigger the FPGA chip to store uplink data of the synchronization cells to a data storage device; The data read trigger signal is used to trigger the FPGA chip to read target uplink data from a target address of the data storage device.

7. A multi-cell uplink data access system, characterized by, The method comprises: An FPGA chip; A data storage device connected to the FPGA chip; A central processing unit connected to the FPGA chip and configured to execute the multi-cell uplink data access method according to any one of claims 1 to 5.

8. An electronic device comprising a memory, a processor, and a computer program stored on the memory and running on the processor, characterized in that, The processor executes the computer program to implement the multi-cell uplink data access method according to any one of claims 1 to 5. 9.A non-transitory computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the multi-cell uplink data access method according to any one of claims 1 to 5.

10. A computer program product comprising a computer program, characterized in that, The computer program is executed by the processor to implement the multi-cell uplink data access method according to any one of claims 1 to 5. The computer program is executed by the processor to implement the multi-cell uplink data access method according to any one of claims 1 to 5.

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