APD chip with isolation groove and preparation method thereof

Abstract

The invention belongs to the technical field of semiconductors, and particularly relates to an APD chip with an isolation groove and a preparation method of the APD chip. The APD chip provided by the invention comprises a first insulating layer arranged on the upper surface of a cap layer except a photosensitive region; the isolation groove at least simultaneously penetrates through the first insulating layer, the non-photosensitive area of the cap layer, the charge layer and the absorption layer, and the isolation groove surrounds the periphery of the photosensitive area. The isolation groove is arranged around the periphery of the photosensitive area, and the depth of the isolation groove is controlled, so that when light irradiates the passivation area, the APD chip of the detector does not generate a signal or the signal is very small due to the isolation effect of the isolation groove, and laser radar pulse broadening can be effectively inhibited. Therefore, the cost is reduced, and the problem of pulse broadening of the laser radar is solved.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to an APD chip with an isolation groove and a preparation method thereof. Background Art

[0002] The traditional laser radar transmission method is through optical fiber transmission. The specific process is that the laser emitted by the laser radar's transmitting unit irradiates the object to be detected, and the reflected light is transmitted through the optical fiber and is detected by the detector APD chip (the top view structure diagram is as follows Figure 1 The optical signal is received by a light source (as shown in the figure), and finally converted into an electrical signal. Because fiber optic transmission is used, the divergence angle of the light beam can be limited, so that the reflected beam only strikes the photosensitive surface of the detector chip. However, this fiber optic transmission method is relatively expensive. To reduce costs, the detector APD chip uses a spatial free-light method to receive light reflected from objects. This eliminates the fiber optic transmission step and reduces costs, but also introduces new problems.

[0003] Because the photosensitive surface of the detector APD chip is the main area that generates photocurrent, areas outside the photosensitive surface of the detector, such as the passivation area (i.e., non-photosensitive area), will also generate weak photocurrent when light shines on these areas. The small photocurrent signals generated in these areas will cause pulse broadening problems under high-frequency pulse signals. Pulse broadening is essentially a deformation of the signal, which will affect the judgment and processing of the lidar signal, and ultimately cause the radar to misjudge or miss. Summary of the Invention

[0004] The present invention aims to provide an APD chip with isolation trenches and a method for manufacturing the same. When light strikes the passivation region of the APD chip, the APD chip generates no signal or a very small signal, thereby suppressing the pulse broadening problem in laser radars. This reduces costs and solves the pulse broadening problem in laser radars.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] The present invention provides an APD chip with an isolation trench, comprising a substrate layer, a buffer layer, an absorption layer, a charge layer, and a cap layer sequentially arranged on the upper surface of the substrate layer; a central area of ​​the cap layer forms a photosensitive area through diffusion; and a first insulating layer arranged on the non-photosensitive upper surface of the cap layer.

[0007] an isolation groove at least penetrating the first insulating layer, the non-photosensitive region of the cap layer, the charge layer, and the absorption layer, and surrounding the periphery of the photosensitive region;

[0008] a second insulating layer disposed on the upper surface of the first insulating layer, the inner wall and the inner bottom of the isolation trench;

[0009] a third insulating layer disposed on the upper surface of the second insulating layer, on the surface of the second insulating layer located on the inner wall and inner bottom of the isolation trench, and on the upper surface of the photosensitive region, wherein the third insulating layer is provided with a contact hole in a region located on the upper surface of the photosensitive region;

[0010] a P-type electrode disposed on a portion of the upper surface of the third insulating layer, wherein the P-type electrode contacts the photosensitive region through the contact hole;

[0011] An N-type electrode is provided on the lower surface of the substrate layer.

[0012] Preferably, the isolation trench passes through the buffer layer, or the bottom surface of the isolation trench is located inside the buffer layer.

[0013] Preferably, the isolation trench also penetrates the buffer layer, and the bottom surface of the isolation trench is located inside the substrate layer.

[0014] Preferably, a metal reflective layer is further provided on the inner wall and inner bottom surface of the isolation groove between the second insulating layer and the third insulating layer.

[0015] Preferably, the metal reflective layer is an Au layer, or a Ti layer and an Au layer stacked sequentially from bottom to top, or a Ti layer, a Pt layer and an Au layer stacked sequentially from bottom to top.

[0016] Preferably, the material of the first insulating layer, the second insulating layer or the third insulating layer is silicon dioxide and / or silicon nitride.

[0017] Preferably, the upper surface of the photosensitive area is circular, the isolation groove is an open circular ring groove, the P-type electrode includes a circular electrode and a pin pad, the pin pad is located outside the circular opening of the isolation groove, and the circular electrode is connected to the pin pad through the circular opening of the isolation groove.

[0018] The present invention provides a method for preparing an APD chip with isolation trenches according to the above technical solution, comprising the following steps:

[0019] A buffer layer, an absorption layer, a charge layer, and a cap layer are sequentially grown on the upper surface of the substrate; the upper surface of the cap layer is patterned by photolithography, and then a first insulating layer is prepared, and diffusion is performed on the upper surface of the cap layer except the first insulating layer to obtain a photosensitive area;

[0020] Grooving is performed on the upper surface of the first insulating layer, at least simultaneously penetrating the first insulating layer, the non-photosensitive area of ​​the cap layer, the charge layer, and the absorption layer to form an isolation groove, thereby obtaining a semi-finished product;

[0021] A second insulating layer, a third insulating layer and a P-type electrode are prepared on the upper surface of the semi-finished product, and an N-type electrode is prepared on the lower surface of the semi-finished product to obtain the APD chip with isolation grooves.

[0022] Preferably, after preparing the second insulating layer on the upper surface of the semi-finished product and before preparing the third insulating layer, the method further comprises: growing a metal reflective layer on the second insulating layer located on the inner wall and inner bottom of the isolation groove.

[0023] Preferably, the isolation trench is prepared by wet etching or dry etching.

[0024] The present invention provides an APD chip with an isolation groove, comprising a substrate layer, a buffer layer, an absorption layer, a charge layer and a cap layer sequentially arranged on the upper surface of the substrate layer; a photosensitive area is formed by diffusion in the central area of ​​the cap layer; a first insulating layer is arranged on the upper surface of a non-photosensitive area (the non-photosensitive area is the area other than the photosensitive area) of the cap layer; an isolation groove at least penetrating the first insulating layer, the non-photosensitive area, the charge layer and the absorption layer of the cap layer, and the isolation groove surrounds the periphery of the photosensitive area; a second insulating layer is arranged on the upper surface of the first insulating layer, the inner wall and the inner bottom of the isolation groove; a third insulating layer is arranged on the upper surface of the second insulating layer, the surface of the second insulating layer located on the inner wall and the inner bottom of the isolation groove, and the upper surface of the photosensitive area, the third insulating layer having a contact hole in the area located on the upper surface of the photosensitive area; a P-type electrode is arranged on the upper surface of a portion of the third insulating layer, and the P-type electrode is in contact with the photosensitive area through the contact hole; and an N-type electrode is arranged on the lower surface of the substrate layer. By providing an isolation trench around the periphery of the photosensitive region and controlling the depth of the isolation trench, the present invention ensures that when light strikes the passivation region, the detector's APD chip generates no signal or a very small signal due to the isolation effect of the isolation trench, effectively suppressing LiDAR pulse broadening. This reduces costs while also resolving the problem of LiDAR pulse broadening. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a top view of a conventional APD chip;

[0026] Figure 2 A top view of the APD chip with isolation trenches provided by the present invention;

[0027] Figure 3 A schematic diagram of the structure for preparing a buffer layer, an absorption layer, a charge layer, a cap layer, a first insulating layer, and a photosensitive region according to an embodiment of the present invention;

[0028] Figure 4 This is a schematic diagram of the structure of preparing the isolation trench and the second insulating layer according to an embodiment of the present invention;

[0029] Figure 5 This is a schematic diagram of the structure of preparing the third insulating layer according to an embodiment of the present invention;

[0030] Figure 6 for Figure 2 Schematic diagram of the local structure of the APD chip with isolation trench along the cross-section A;

[0031] Figure 7 for Figure 2 Schematic diagram of the local structure of the APD chip with isolation trench along the cross-section B;

[0032] In the figure: 1 is the substrate layer, 2 is the buffer layer, 3 is the absorption layer, 4 is the charge layer, 5 is the cap layer, 6 is the first insulating layer, 7 is the photosensitive area, 8 is the isolation groove, 9 is the second insulating layer, 10 is the third insulating layer, 11-1 is the pin pad, 11-2 is the ring electrode, and 12 is the N-type electrode. DETAILED DESCRIPTION

[0033] The present invention provides an APD chip with an isolation trench, comprising a substrate layer, a buffer layer, an absorption layer, a charge layer, and a cap layer sequentially arranged on the upper surface of the substrate layer; a photosensitive region is formed in the central region of the cap layer by diffusion; and a first insulating layer is arranged on the upper surface of the non-photosensitive region of the cap layer.

[0034] an isolation groove at least penetrating the first insulating layer, the non-photosensitive region of the cap layer, the charge layer, and the absorption layer, and surrounding the periphery of the photosensitive region;

[0035] a second insulating layer disposed on the upper surface of the first insulating layer, the inner wall and the inner bottom of the isolation trench;

[0036] a third insulating layer disposed on the upper surface of the second insulating layer, on the surface of the second insulating layer located on the inner wall and inner bottom of the isolation trench, and on the upper surface of the photosensitive region, wherein the third insulating layer is provided with a contact hole in a region located on the upper surface of the photosensitive region;

[0037] a P-type electrode disposed on a portion of the upper surface of the third insulating layer, wherein the P-type electrode contacts the photosensitive region through the contact hole;

[0038] An N-type electrode is provided on the lower surface of the substrate layer.

[0039] In the present invention, unless otherwise specified, all preparation raw materials / components are commercially available products well known to those skilled in the art.

[0040] In the present invention, the APD chip is an avalanche photodiode. Figure 2 A top view of the APD chip with isolation trenches provided by the present invention, Figure 6 for Figure 2Schematic diagram of the local structure of the APD chip with isolation trench along the cross-section A; Figure 7 for Figure 2 The schematic diagram of the local structure of the APD chip with isolation groove along the cross section B. Figure 2 、 Figure 6 and Figure 7 The structure of the APD chip with isolation trenches provided by the present invention is described in detail.

[0041] The APD chip with isolation trenches provided by the present invention comprises a substrate layer 1. In the present invention, the substrate layer 1 is preferably an InP substrate. The thickness of the substrate layer 1 is preferably 80 to 300 μm.

[0042] The APD chip with isolation trenches provided by the present invention comprises a buffer layer 2 arranged on the upper surface of the substrate layer. In the present invention, the buffer layer 2 is preferably an N-type InP buffer layer.

[0043] The APD chip with isolation trenches provided by the present invention comprises an absorption layer 3 disposed on the upper surface of the buffer layer. In the present invention, the absorption layer 3 is preferably an unintentionally doped N-type InGaAs absorption layer.

[0044] The APD chip with isolation trenches provided by the present invention comprises a charge layer 4 disposed on the upper surface of the absorption layer. In the present invention, the charge layer 4 is preferably an N-type InP charge layer.

[0045] The APD chip with isolation trenches provided by the present invention includes a capping layer 5 disposed on the upper surface of the charge layer; the central region of the capping layer 5 forms a photosensitive region 7 through diffusion. In the present invention, the capping layer 5 is preferably an unintentionally doped InP capping layer. The photosensitive region 7 is preferably a P-type semiconductor. In the present invention, the upper surface of the capping layer 5, excluding the region of the photosensitive region 7, is a passivation region, which is a non-photosensitive region.

[0046] As one or more embodiments of the present invention, the upper surface of the photosensitive area 7 is preferably circular.

[0047] The APD chip with isolation grooves provided by the present invention includes a first insulating layer 6 arranged on the upper surface of the cap layer except the photosensitive area. In the present invention, the material of the first insulating layer 6 is preferably silicon nitride (SiN x ) and / or silicon dioxide (SiO2), specifically SiN x The first insulating layer 6 is provided on the upper surface of the passivation region of the cap layer 5. When the material of the first insulating layer 6 is SiN x When the thickness of the first insulating layer 6 is preferably When the material of the first insulating layer 6 is SiO2, the thickness of the first insulating layer 6 is preferably

[0048] In the present invention, the first insulating layer 6 is provided on the upper surface of the passivation region of the cap layer 5 and functions as a passivation protection device.

[0049] The APD chip with isolation grooves provided by the present invention includes an isolation groove 8 that at least simultaneously penetrates the first insulating layer 6, the non-photosensitive area of ​​the cap layer 5, the charge layer 4 and the absorption layer 3, and the isolation groove 8 surrounds the periphery of the photosensitive area 7.

[0050] As one or more embodiments of the present invention, the bottom surface of the isolation trench 8 is located inside the buffer layer.

[0051] As one or more embodiments of the present invention, the isolation trench 8 penetrates the buffer layer 2 .

[0052] As one or more embodiments of the present invention, the isolation trench 8 penetrates the buffer layer 2 , and the bottom surface of the isolation trench is located inside the substrate layer 1 .

[0053] As one or more embodiments of the present invention, a metal reflective layer is further provided on the inner wall and inner bottom surface of the isolation groove 8 between the second insulating layer and the third insulating layer.

[0054] In one or more embodiments of the present invention, the metal reflective layer is preferably an Au layer, or a Ti layer and an Au layer stacked sequentially from bottom to top, or a Ti layer, a Pt layer, and an Au layer stacked sequentially from bottom to top. In the present invention, the thickness of the Au layer of the metal reflective layer is preferably 0.1 to 0.5 μm.

[0055] As one or more embodiments of the present invention, the isolation groove is preferably an open circular groove.

[0056] The APD chip with isolation groove provided by the present invention includes a second insulating layer 9 arranged on the upper surface of the first insulating layer 6, the inner wall and the inner bottom of the isolation groove 8. In the present invention, the material of the second insulating layer 9 is preferably silicon nitride (SiN x ) and / or silicon dioxide (SiO2), specifically SiO2 in the embodiment. The thickness of the second insulating inner layer 9 is preferably 0.2-3 μm.

[0057] In the present invention, the second insulating layer 9 is provided on the upper surface of the first insulating layer 6 and the inner wall and inner bottom of the isolation trench 8 to play the role of passivation protection device.

[0058] The APD chip with isolation groove provided by the application comprises a third insulating layer 10 arranged on the upper surface of the second insulating layer 9, the inner wall and the inner bottom surface of the isolation groove 8, and the upper surface of the photosensitive region 7, and the third insulating layer 10 is provided with a contact hole in the region on the upper surface of the photosensitive region 7. In the application, the material of the third insulating layer 10 is preferably silicon nitride (SiN x ) and / or silicon dioxide (SiO2), and in the embodiment, it is specifically SiN x . In the application, the third insulating layer 10 is preferably SiN x antireflection insulating medium layer to reduce reflected light and increase the transmittance of the device.

[0059] As one or more embodiments of the application, the contact hole is preferably surrounded by the inner periphery of the photosensitive region 7.

[0060] In the application, the third insulating layer 10 is an antireflection insulating medium layer to reduce reflected light and increase the transmittance of the device.

[0061] The APD chip with isolation groove provided by the application comprises a P-type electrode arranged on part of the upper surface of the third insulating layer 10, and the P-type electrode is in contact with the photosensitive region 7 through the contact hole. In the application, the P-type electrode preferably comprises a circular ring electrode 11-2 and a pin pad 11-1, the pin pad 11-1 is preferably located outside the circular ring opening of the isolation groove 8, and the circular ring electrode 11-2 is preferably in communication with the pin pad 11-1 through the circular ring opening of the isolation groove 8.

[0062] In the application, the P-type electrode is preferably in ohmic contact with the photosensitive region 7 through the contact hole.

[0063] In the application, the metal material of the P-type electrode preferably comprises one or a combination of several of Au, Ti, Cr, Ag, Al, Cu, Au, Ge and Pt.

[0064] In the application, the active region of the APD chip with isolation groove is the circular ring electrode 11-2 and the photosensitive region region in the circular ring electrode 11-2.

[0065] The APD chip with isolation groove provided by the application comprises an N-type electrode 12 arranged on the lower surface of the substrate layer 1. In the application, the material of the N-type electrode 12 preferably comprises one or a combination of several of Au, Ge, Cr, Ni, Au, Ge and Pt.

[0066] The APD chip with isolation trenches provided by the present invention is a single chip or an M×N array, wherein M represents the number of rows of the array and N represents the number of columns of the array. In a specific embodiment of the present invention, the M×N array can be an APD array of 1×2, 1×4, 1×8, 1×16, 2×2, 4×4, 16×16, etc.

[0067] The present invention provides a method for preparing an APD chip with isolation trenches according to the above technical solution, comprising the following steps:

[0068] A buffer layer, an absorption layer, a charge layer, and a cap layer are sequentially grown on the upper surface of the substrate; the upper surface of the cap layer is patterned by photolithography, and then a first insulating layer is prepared, and diffusion is performed on the upper surface of the cap layer except the first insulating layer to obtain a photosensitive area;

[0069] Grooving the upper surface of the first insulating layer through the first insulating layer, the non-photosensitive area of ​​the cap layer, the charge layer, and the absorption layer simultaneously to form an isolation groove, thereby obtaining a semi-finished product;

[0070] A second insulating layer, a third insulating layer and a P-type electrode are prepared on the upper surface of the semi-finished product, and an N-type electrode is prepared on the lower surface of the semi-finished product to obtain the APD chip with isolation grooves.

[0071] The present invention sequentially grows a buffer layer, an absorption layer, a charge layer and a cap layer on the upper surface of a substrate; patterns the upper surface of the cap layer by photolithography, and then prepares a first insulating layer, and diffuses the upper surface of the cap layer in areas other than the first insulating layer to obtain a photosensitive area. The present invention has no special requirements for the growth methods of the buffer layer, the absorption layer, the charge layer and the cap layer, and methods well known to those skilled in the art can be used. In the present invention, the preparation method of the first insulating layer preferably includes the following steps: coating a photoresist on the upper surface of the cap layer, and then performing photolithography using a mask to obtain a patterned surface, and then growing a first insulating film on the patterned surface, and removing the remaining photoresist on the patterned surface to obtain the first insulating layer. The growth method of the first insulating film is preferably PECVD or ICP-PECVD. The present invention has no special requirements for the specific implementation of the diffusion.

[0072] After obtaining the photosensitive area, the present invention forms a groove on the upper surface of the first insulating layer that at least simultaneously penetrates the first insulating layer, the non-photosensitive area of ​​the cap layer, the charge layer, and the absorption layer to form an isolation groove (i.e., an isolation groove is prepared on the upper surface of the first insulating layer that at least simultaneously penetrates the first insulating layer, the non-photosensitive area of ​​the cap layer, the charge layer, and the absorption layer), thereby obtaining a semi-finished product. In the present invention, the method for preparing the isolation groove is preferably wet etching or dry etching. The present invention has no special requirements for the specific implementation process of the wet etching or dry etching.

[0073] After obtaining the semi-finished product, the present invention prepares a second insulating layer, a third insulating layer, and a P-type electrode on the upper surface of the semi-finished product, and prepares an N-type electrode on the lower surface of the semi-finished product, thereby obtaining the APD chip with isolation trenches. In the present invention, the method for preparing the second insulating layer preferably includes the following steps: coating the upper surface of the semi-finished product with photoresist, then performing photolithography using a mask to obtain a patterned surface, then growing the entire second insulating layer on the patterned surface, and removing the remaining photoresist on the patterned surface to obtain the second insulating layer.

[0074] In the present invention, after forming the second insulating layer on the upper surface of the semi-finished product and before forming the third insulating layer, the present invention preferably further comprises: growing a metal reflective layer on the second insulating layer located on the inner wall and inner bottom of the isolation trench. The present invention has no particular requirements for the method of growing the metal reflective layer.

[0075] In the present invention, the method for preparing the third insulating layer preferably includes the following steps: coating a photoresist on the upper surface of a semi-finished product having a second insulating layer, then performing photolithography using a mask to obtain a patterned surface, then growing a third insulating layer entirely on the patterned surface, and removing the remaining photoresist on the patterned surface to obtain the third insulating layer. The growth method for growing the entire third insulating layer is preferably PECVD or ICP-PECVD.

[0076] The present invention prepares a P-type electrode on the surface of the third insulating layer. The present invention preferably obtains the required circular electrode and pin pad of the P-type electrode by metal stripping. After the present invention prepares the P-type electrode on the surface of the third insulating inner layer, the present invention preferably further comprises: annealing the obtained P-type electrode, the temperature of the annealing treatment is preferably 350 to 450°C, and the time of the annealing treatment is preferably 10 seconds to 3 minutes. The annealing treatment of the present invention enables the P-type electrode to form a good ohmic contact with the P-type layer through the contact hole.

[0077] Before preparing the N-type electrode on the back side of the semi-finished product, the present invention preferably thins the back side of the substrate of the semi-finished product to obtain a substrate layer after the back side thinning, and prepares the N-type electrode on the lower surface of the substrate layer. After preparing the N-type electrode on the lower surface of the substrate layer, the present invention preferably further comprises: annealing the obtained N-type electrode, the temperature of the annealing treatment is preferably 350 to 450°C, and the time of the annealing treatment is preferably 10s to 3min. The present invention achieves good ohmic contact between the N-type electrode and the substrate layer by annealing the N-type electrode. The specific implementation method of the back side thinning is preferably grinding. The preparation method of the N-type electrode is preferably evaporation.

[0078] In a specific embodiment of the present invention, the annealing treatment of the P-type electrode and the annealing treatment of the N-type electrode can be performed simultaneously or in steps.

[0079] In the present invention, after obtaining the N-type electrode, the present invention preferably further comprises: cutting and cleaving along the cutting lanes to form an APD chip with isolation grooves including a single chip or a matrix structure.

[0080] In order to further illustrate the present invention, the technical solutions provided by the present invention are described in detail below in conjunction with the embodiments, but they should not be construed as limiting the scope of protection of the present invention.

[0081] Example 1

[0082] Step 1: Provide an InP substrate, and then sequentially grow an N-type InP buffer layer, an unintentionally doped N-type InGaAs absorption layer, an N-type InP charge layer, and an unintentionally doped InP cap layer on the surface of the InP substrate. Then, apply photoresist on the surface of the unintentionally doped InP cap layer, perform photolithography using a mask to obtain a patterned surface, and deposit SiN on the patterned surface. x , the deposition thickness is Remove the remaining photoresist and SiN on the photoresist surface x Then, the first insulating layer is obtained. Then, the photosensitive surface area leaking from the unintentionally doped InP cap layer is diffused to form a P-type semiconductor to obtain a photosensitive area. Figure 3 shown.

[0083] Step 2: Etch the first insulating layer, the unintentionally doped InP cap layer, the N-type InP charge layer and the unintentionally doped N-type InGaAs absorption layer from top to bottom by wet etching or dry etching to form an isolation trench.

[0084] Step 3: Coat photoresist on the upper surface of the product in step 2, grow a SiO2 insulating dielectric layer after obtaining a patterned surface by photolithography, remove the photoresist and the SiO2 insulating dielectric layer on the surface of the photoresist, and obtain a second insulating layer on the first insulating layer, the inner wall and the inner bottom surface of the isolation groove. In step 3, ensure that the SiO2 insulating dielectric layer in the photosensitive area and the cutting path is removed; the structural diagram is shown as follows: Figure 4 shown.

[0085] Step 4: Coat photoresist on the upper surface of the product in step 3, and then grow SiN after obtaining a patterned surface through photolithography. x Anti-reflective insulating dielectric film, removal of photoresist and SiN on photoresist x A third insulating layer is formed on the upper surface of the second insulating layer, the surface of the second insulating layer located on the inner wall and inner bottom of the isolation groove, and the surface of the photosensitive area. The third insulating layer has a contact hole on the surface of the photosensitive area. The structural diagram is shown in FIG. Figure 5 shown.

[0086] In SiN x A circular ring electrode of a P-type electrode is grown near the contact hole of the anti-reflective insulating dielectric layer (i.e., the third insulating layer), and a pin pad is grown outside the circular opening of the isolation groove. The circular ring electrode and the long pin pad are connected through the circular opening of the isolation groove to obtain a P-type electrode. The circular ring electrode of the P-type electrode contacts the P-type layer (photosensitive area) through the contact hole; the back side of the substrate is thinned and finally an N-type electrode is evaporated, and the P-type electrode and the N-type electrode are annealed (the annealing temperature is 350-450°C and the time is 10s-3min) to make the P-type layer and the N-type layer form good ohmic contact with the semiconductor.

[0087] Step 5: Cut and dissociate the chip formed by the arrangement of multiple avalanche photodiodes APD along the cutting line, and cut it into a single chip or an M×N array structure.

[0088] Example 2

[0089] Step 1: Provide an InP substrate, and then sequentially grow an N-type InP buffer layer, an unintentionally doped N-type InGaAs absorption layer, an N-type InP charge layer, and an unintentionally doped InP cap layer on the surface of the InP substrate. Then, apply photoresist on the surface of the unintentionally doped InP cap layer, perform photolithography using a mask to obtain a patterned surface, and deposit SiN on the patterned surface. x , the deposition thickness is Remove the remaining photoresist and SiN on the photoresist surface x Then, the first insulating layer is obtained. Then, the photosensitive surface area leaking from the unintentionally doped InP cap layer is diffused to form a P-type semiconductor to obtain a photosensitive area. Figure 3 shown.

[0090] Step 2: Etch the first insulating layer, the unintentionally doped InP cap layer, the N-type InP charge layer and the unintentionally doped N-type InGaAs absorption layer from top to bottom by wet etching or dry etching to form an isolation trench.

[0091] Step 3: Coat photoresist on the upper surface of the product in step 2, grow a SiO2 insulating dielectric layer after obtaining a patterned surface by photolithography, remove the photoresist and the SiO2 insulating dielectric layer on the surface of the photoresist, and obtain a second insulating layer on the first insulating layer, the inner wall and the inner bottom surface of the isolation groove. In step 3, ensure that the SiO2 insulating dielectric layer in the photosensitive area and the cutting path is removed; the structural diagram is shown as follows: Figure 4 shown.

[0092] Step 4: growing a metal reflective layer Au layer on the second insulating layer on the inner wall and inner bottom of the isolation groove obtained in step 3;

[0093] Step 5: coating photoresist on the upper surface of the product of step 4, growing SiN after the photoresist is patterned to obtain a patterned surface x an antireflection insulating dielectric film, removing the photoresist and the SiN on the photoresist, and growing a third insulating layer on the upper surface of the second insulating layer, the inner wall and the inner bottom surface of the isolation groove, and the surface of the photosensitive region to obtain a contact hole on the surface of the photosensitive region x The structure is shown in Figure 5

[0094] The SiN x growing a ring electrode of the P-type electrode near the contact hole of the antireflection insulating dielectric layer (i.e., the third insulating layer), growing a long pin pad outside the ring opening of the isolation groove, and connecting the ring electrode and the long pin pad through the ring opening of the isolation groove to obtain a P-type electrode, the ring electrode of the P-type electrode being in contact with the P-type layer (photosensitive region) through the contact hole; thinning the back surface of the substrate, and finally evaporating an N-type electrode; and annealing the P-type electrode and the N-type electrode (the annealing temperature is 350-450°C, and the annealing time is 10s-3min) to form a good ohmic contact between the P-type layer and the N-type layer and the semiconductor.

[0095] Step 6: cutting and separating the chip formed by the plurality of avalanche photodiodes APD along the cutting path to form a single chip or an M×N array structure.

[0096] Example 3

[0097] The preparation method is basically the same as that of Example 1, except that step 2 is replaced by: forming an isolation groove by wet etching or dry etching from top to bottom to etch the first insulating layer, the unintentionally doped InP cap layer, the N-type InP charge layer, the unintentionally doped N-type InGaAs absorption layer, and the N-type InP buffer layer.

[0098] Example 4

[0099] The preparation method is basically the same as that of Example 1, except that step 2 is replaced by: forming an isolation groove by wet etching or dry etching from top to bottom to etch the first insulating layer, the unintentionally doped InP cap layer, the N-type InP charge layer, the unintentionally doped N-type InGaAs absorption layer, the N-type InP buffer layer, and part of the substrate.

[0100] As can be seen from the above examples, by arranging an isolation groove around the periphery of the photosensitive region and controlling the depth of the isolation groove, the APD chip of the detector does not generate a signal or generates a very small signal when light is irradiated to the passivation region due to the isolation effect of the isolation groove, thereby effectively suppressing the pulse broadening of the laser radar. Thus, the problem of pulse broadening of the laser radar is solved while the cost is reduced.​

[0101] Although the above embodiment provides a detailed description of the present invention, it is only a part of the embodiments of the present invention, not all of the embodiments. Other embodiments can be obtained based on this embodiment without creativity, and these embodiments all fall within the scope of protection of the present invention.

Claims

1. An APD chip with an isolation trench, comprising a substrate layer, a buffer layer, an absorption layer, a charge layer, and a cap layer sequentially disposed on the upper surface of the substrate layer; a photosensitive region formed by diffusion in the central region of the cap layer; and a first insulating layer disposed on the upper surface of the non-photosensitive region of the cap layer. an isolation groove at least penetrating the first insulating layer, the non-photosensitive region of the cap layer, the charge layer, and the absorption layer, and surrounding the periphery of the photosensitive region; a second insulating layer disposed on the upper surface of the first insulating layer, the inner wall and the inner bottom of the isolation trench; a third insulating layer disposed on the upper surface of the second insulating layer, on the surface of the second insulating layer located on the inner wall and inner bottom of the isolation trench, and on the upper surface of the photosensitive region, wherein the third insulating layer is provided with a contact hole in a region located on the upper surface of the photosensitive region; a P-type electrode disposed on a portion of the upper surface of the third insulating layer, wherein the P-type electrode contacts the photosensitive region through the contact hole; An N-type electrode is provided on the lower surface of the substrate layer.

2. The APD chip with isolation trench according to claim 1, characterized in that: The isolation trench also penetrates the buffer layer or the bottom surface of the isolation trench is located inside the buffer layer.

3. The APD chip with isolation trench according to claim 1, characterized in that: The isolation trench also penetrates the buffer layer, and the bottom surface of the isolation trench is located inside the substrate layer.

4. The APD chip with isolation trench according to any one of claims 1 to 3, characterized in that: A metal reflective layer is further provided on the inner wall and inner bottom surface of the isolation groove between the second insulating layer and the third insulating layer.

5. The APD chip with isolation trench according to claim 4, characterized in that: The metal reflective layer is an Au layer, or a Ti layer and an Au layer stacked in sequence from bottom to top, or a Ti layer, a Pt layer and an Au layer stacked in sequence from bottom to top.

6. The APD chip with isolation trench according to claim 1, characterized in that: The material of the first insulating layer, the second insulating layer or the third insulating layer is silicon dioxide and / or silicon nitride.

7. The APD chip with isolation trench according to claim 1, characterized in that: The upper surface of the photosensitive area is circular, the isolation groove is an open circular ring groove, the P-type electrode includes a circular electrode and a pin pad, the pin pad is located outside the circular opening of the isolation groove, and the circular electrode is connected to the pin pad through the circular opening of the isolation groove.

8. The method for preparing the APD chip with isolation trenches according to any one of claims 1 to 7, comprising the following steps: A buffer layer, an absorption layer, a charge layer, and a cap layer are sequentially grown on the upper surface of the substrate; the upper surface of the cap layer is patterned by photolithography, and then a first insulating layer is prepared, and diffusion is performed on the upper surface of the cap layer except the first insulating layer to obtain a photosensitive area; Grooving is performed on the upper surface of the first insulating layer, at least simultaneously penetrating the first insulating layer, the non-photosensitive area of ​​the cap layer, the charge layer, and the absorption layer to form an isolation groove, thereby obtaining a semi-finished product; A second insulating layer, a third insulating layer and a P-type electrode are prepared on the upper surface of the semi-finished product, and an N-type electrode is prepared on the lower surface of the semi-finished product to obtain the APD chip with isolation grooves.

9. The preparation method according to claim 8, characterized in that After forming the second insulating layer on the upper surface of the semi-finished product and before forming the third insulating layer, the method further includes: growing a metal reflective layer on the second insulating layer located on the inner wall and inner bottom of the isolation groove.

10. The preparation method according to claim 8, characterized in that The isolation trench is prepared by wet etching or dry etching.

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