Zero cross detection circuit

Abstract

The invention provides a zero cross detection circuit. The zero-cross detection circuit includes a variable resistor, a first switch, a first capacitor, a first selector, a second selector, a first transistor, and a comparator. The variable resistor is connected to a supply voltage through a reference resistor. The first switch has a first end coupled to a first end of the variable resistor. The first capacitor has a first end coupled to a second end of the first switch. The first selector enables the second end of the first capacitor to receive the switching voltage or the reference grounding voltage according to the first control signal. The first transistor has a first end coupled to a second end of the variable resistor, and a second end of the first transistor receives a reference ground voltage. The second selector enables the control end of the first transistor to be coupled to the first end of the first transistor or the first end of the first capacitor according to a first control signal. The comparator compares the voltage on the second end of the variable resistor with a reference voltage to generate a final zero-crossing detection output signal.

Description

TECHNICAL FIELD

[0001] The present application relates to a zero-crossing detection circuit, and more particularly to a zero-crossing detection circuit for a voltage converter. BACKGROUND

[0002] Various zero-crossing detection techniques have been proposed for voltage converters. However, these techniques all require an accurate comparator to perform the zero-crossing detection action. If the delay time (also referred to as "zero-crossing detection delay") between the occurrence of a true zero-current event and the availability of the zero-crossing detection signal for controlling the power stage is considered, the power switch cannot be controlled at the true zero-crossing point by direct zero-current event detection. Moreover, the zero-crossing detection delay varies with process, voltage, temperature, and other factors. However, the existing approach of combining a preset zero-crossing threshold with the detection delay can further reduce the accuracy of zero-crossing detection.

[0003] Therefore, there is a need to provide a zero-crossing detection circuit that effectively reduces the detection delay of the zero-crossing point. SUMMARY

[0004] The present application is directed to a zero-crossing detection circuit that effectively reduces the detection delay of the zero-crossing point.

[0005] According to an embodiment of the present application, a zero-crossing detection circuit includes a variable resistor, a first switch, a first capacitor, a first selector, a second selector, a first transistor, and a comparator. The variable resistor has a first terminal connected to a supply voltage through a reference resistor. The first switch has a first terminal coupled to the first terminal of the variable resistor. The first capacitor has a first terminal coupled to a second terminal of the first switch. The first selector is configured to cause a second terminal of the first capacitor to receive a switching voltage or a reference ground voltage based on a first control signal. The first transistor has a first terminal coupled to a second terminal of the variable resistor, and a second terminal of the first transistor receives the reference ground voltage. The second selector is configured to cause a control terminal of the first transistor to be coupled to the first terminal of the first transistor or the first terminal of the first capacitor based on the first control signal. The comparator compares a voltage on the second terminal of the variable resistor with a zero-crossing detection reference voltage to generate a final zero-crossing detection output signal. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 A block diagram of a zero-crossing detection circuit according to an embodiment of the present application.

[0007] Figure 2 A circuit diagram of a zero-crossing detection circuit according to an embodiment of the present application.

[0008] Figure 3 An operation waveform diagram of a zero-crossing detection circuit according to an embodiment of the present application.

[0009] Figure 4 Circuit diagram of a zero-crossing detection circuit according to an embodiment of the application.

[0010] Figure 5 Schematic diagram of an implementation of a variable resistor in a zero-crossing detection circuit according to an embodiment of the application. DETAILED DESCRIPTION

[0011] Reference will now be made in detail to exemplary embodiments of the application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used in the different drawings and the description to refer to the same or like parts.

[0012] Reference will now be made in detail to exemplary embodiments of the application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used in the different drawings and the description to refer to the same or like parts. Figure 1 Figure 1 Block diagram of a zero-crossing detection circuit according to an embodiment of the application. The zero-crossing detection circuit 100 comprises a variable resistor Rt, a switch S1, selectors 110, 120, a comparator 130, and a transistor M1. A first terminal of the variable resistor Rt is connected to a supply voltage Vdd through a reference resistor Ro. One terminal of the switch S1 is coupled to the coupling point of the reference resistor Ro and the variable resistor Rt, and the other terminal of the switch S1 is coupled to a first terminal of a capacitor C1. A second terminal of the capacitor C1 is coupled to the selector 110. The selector 110 is also coupled to ground GND to receive a reference ground voltage V GND and to an output (SW) of a power transistor of a voltage converter to receive a switching voltage Vsw. The selector 120 is coupled between the first terminal of the capacitor C1 and a second terminal of the variable resistor Rt, and is also coupled to a control terminal of the transistor M1. A first terminal of the transistor M1 is coupled to the second terminal of the variable resistor Rt, and a second terminal of the transistor M1 receives the reference ground voltage V GND . In addition, the comparator 130 is coupled to the first terminal of the transistor M1 and receives the reference ground voltage V GND . In one embodiment, the comparator 130 can comprise an operational amplifier, the control terminal of the transistor M1 is the gate, the first terminal is the drain, and the second terminal is the source.

[0013] The selectors 110, 120 receive a control signal CT1. According to the control signal CT1, the selector 110 can cause the second terminal of the capacitor C1 to receive the switching voltage Vsw or the reference ground voltage V GND , and the selector 120 can cause the control terminal of the transistor M1 to be coupled to the first terminal of the transistor M1 or to be coupled to the first terminal of the capacitor C1. The switching voltage Vsw is from the output of the power transistor of the voltage converter. Specifically, in a first phase, the selector 110 can cause the second terminal of the capacitor C1 to receive the reference ground voltage V GND ​In the first stage, the selector 110 can cause the first end of the capacitor Cl to receive the operating voltage Vx, and the selector 120 can cause the control end of the transistor Ml to be coupled to the second end of the capacitor Cl. In the second stage, the selector 110 can cause the second end of the capacitor Cl to receive the switching voltage Vsw, and the selector 120 can cause the control end of the transistor Ml to be coupled to the first end of the capacitor Cl. In this embodiment, the first stage and the second stage can be alternately performed.

[0014] Further, in the first stage, the first end of the capacitor Cl receives the operating voltage Vx through the switch S 1, and the second end of the capacitor Cl receives the reference ground voltage V GND At this time, the capacitor Cl can be charged according to the operating voltage Vx.

[0015] In another aspect, in the first stage, the control end of the transistor Ml is coupled to the first end thereof, and forms a diode connection, and the comparator 130 is configured as a voltage buffer, thus, the gate-source voltage Vgs pi of the transistor Ml in the first stage is equal to the drain-source voltage Vds thereof. At this time, the drain-source current Ids of the transistor Ml is equal to: D

[0016]

[0017] wherein R0 is the resistance value of the reference resistor R0, Rt is the resistance value of the variable resistor Rt, μ n is the electron mobility of the N-type metal-oxide-semiconductor field effect transistor (NMOS), C OX is the oxide capacitance per unit area of the transistor Ml, Vtn is the turn-on threshold voltage of the transistor Ml, L is the channel length of the transistor Ml, and W is the channel width of the transistor Ml.

[0018] According to the current Ids D , the mathematical expression of the voltage Vy on the first end of the transistor Ml can be derived as:

[0019]

[0020] Further, the mathematical expression of the voltage Vx can be derived as:

[0021]

[0022] ​In the first stage, the voltage on the first terminal of the capacitor CI can be charged to equal the voltage Vx. It is worth mentioning that the embodiments of the present application can flexibly set the zero-crossing detection reference voltage to an optimal positive value and have the ability to track the change of the switching voltage Vsw by choosing to charge the capacitor CI to the voltage Vx in the first stage. On the other hand, the comparator 130 can generate the zero-crossing detection reference voltage according to the voltage Vy on the first terminal of the transistor Ml at this time in the first stage, i.e., the comparator 130 is configured as a voltage buffer at this time for generating the zero-crossing detection reference voltage according to the voltage Vy (= Vgs_pl) on the first terminal of the transistor Ml in the first stage. The details of the comparator 130 generating the zero-crossing detection reference voltage will be described in the following embodiments. It is worth noting that this zero-crossing detection reference voltage contains the input offset error voltage Vos of the comparator 130, which will be automatically eliminated in the subsequent comparison, thereby reducing the requirement for the design accuracy of the zero-crossing detection comparator, so that smaller device sizes can be used, and the parasitic effects will be smaller, thereby helping to improve the response speed of the comparator.

[0023] Next, the second stage can be entered. In the second stage, the second terminal of the capacitor CI receives the switching voltage Vsw, the switch SI is turned off, and the first terminal of the capacitor CI is changed to be coupled to the control terminal of the transistor Ml. In this way, the capacitor CI can sense the voltage value of the switching voltage Vsw and provide a corresponding voltage to the control terminal (gate) of the transistor Ml according to the change of the switching voltage Vsw. At this time, the transistor Ml is configured as a common-source amplifier with a resistive load and can provide a gain of 30 dB, for example. When the switching voltage Vsw is a negative voltage before the zero-crossing point, the relevant mathematical formula can be as follows:

[0024] I D ×Rt+Vsw<0 (4)

[0025] The voltage Vc1 on the first terminal of the capacitor CI can be represented as:

[0026]

[0027] It can be seen that at this time, the voltage Vy on the first terminal of the transistor Ml received by the comparator 130 is higher than that in the first stage.

[0028] Further, when the switching voltage Vsw is a positive voltage after passing through the zero-crossing point, the relevant mathematical formula can be as follows:

[0029] I D ×Rt+Vsw≥0

[0030]

[0031] It can be known that, at this time, the voltage Vy on the first terminal of the transistor Ml received by the comparator 130 can be lower than that in the first stage.

[0032] That is, the comparator 130 can effectively detect the zero-crossing point of the switching voltage Vsw by comparing the voltage Vy on the first terminal of the transistor Ml with the zero-crossing detection reference voltage (approximately equal to Vgs_p1). The comparator 130 can generate the final zero-crossing detection output signal ZX_DET based on the comparison result.

[0033] Further, according to the above mathematical formula, based on the relationship between the second stage voltage Vc1 and the first stage gate-source voltage Vgs_p1 of the transistor Ml, it can be known that, by adjusting the resistance value of the variable resistor Rt, the zero-crossing detection reference voltage can be flexibly controlled to adjust the time point of the detected zero-crossing point of the switching voltage Vsw. Specifically, by adjusting the resistance value of the variable resistor Rt to detect the time point of the zero-crossing point of the switching voltage Vsw earlier, the time delay of the final zero-crossing detection output signal ZX_DET being output to the external circuit can be effectively compensated, and the accuracy of the zero-crossing detection can be improved. In addition, the zero-crossing detection error caused by process parameter drift and environmental factor variation can also be compensated by adjusting the resistance value of the variable resistor Rt, thereby improving the accuracy of the zero-crossing detection.

[0034] Please refer to Figure 2 , Figure 2 is a circuit diagram of a zero-crossing detection circuit according to an embodiment of the present application. The zero-crossing detection circuit 200 includes a variable resistor Rt, a switch S1, selectors 210, 220, a comparator 230, and a transistor Ml. The selector 210 includes switches S5 and S6, and the switch S6 is coupled between the second terminal of the capacitor C1 and the output terminal SW of the power transistor M2 of the voltage converter. The switch S5 is coupled between the second terminal of the capacitor C1 and the ground GND. The selector 220 includes switches S2 and S4, and the switch S2 is coupled between the first terminal of the transistor Ml and the control terminal thereof. The switch S4 is coupled between the control terminal of the transistor Ml and the first terminal of the capacitor C1. In the first stage, the switches S6 and S4 are turned off, and the switches S1, S5, and S2 are turned on. In the second stage, the switches S6 and S4 are turned on, and the switches S1, S5, and S2 are turned off. The control terminal of the power transistor M2 is used to receive a driving signal NDRV and is controlled by the driving signal NDRV.

[0035] Further, the comparator 230 comprises an operational amplifier OP1, a switch S3, a capacitor C2, and an inverter IV1. The positive input of the operational amplifier OP1 is coupled to the first terminal of the transistor M1, and the negative input of the operational amplifier OP1 is coupled to the first terminal of the capacitor C2. The negative input of the operational amplifier OP1 is further coupled to the output of the operational amplifier OP1 through the switch S3. The output of the operational amplifier OP1 is further coupled to the inverter IV1. The second terminal of the capacitor C2 receives a reference ground voltage V GND In operation, in the first stage, the switch S3 can be turned on. The operational amplifier OP1 can form a voltage buffer. At this time, the voltage Vz on the first terminal of the capacitor C2 can be equal to the sum of the voltage on the first terminal of the transistor M1 and the offset error voltage Vos between the input of the operational amplifier OP1 (= Vy+Vos), where the voltage Vz is the zero-crossing detection reference voltage.

[0036] In the second stage, the switch S3 can be turned off, and the operational amplifier OP1 can form a comparator and generate the comparison result Vo by comparing the voltage Vy in the second stage and the zero-crossing detection reference voltage Vz. Further, through the inverter IV1, the comparator 230 can generate the final zero-crossing detection output signal ZX_DET. In the embodiment, the inverter IV1 can be a Schmitt trigger or an inverter with an N-type transistor (NMOSFET) as the load and a resistor / current source.

[0037] It is worth mentioning that in other embodiments of the present application, the inverter IV1 is not necessarily a component. The comparator 230 can directly output the comparison result Vo as the final zero-crossing detection output signal ZX_DET without any limitation.

[0038] It is worth mentioning that the switches S1-S6 in the embodiment can be any switch component known to those skilled in the art, such as a transistor switch, without any limitation.

[0039] Please refer to Figure 3 , Figure 3 is a waveform diagram of the operation of the zero-crossing detection circuit in the embodiment of the present application. Corresponding to Figure 2 , the power transistor M2 is controlled by the periodically switched driving signal NDRV. Corresponding to the driving signal NDRV, the control signal CT1 comprises the sub-control signals P1 and P2. The sub-control signals P1 and P2 are complementary in phase and periodically switched. The sub-control signals P1 and P2 can be used to define whether the zero-crossing detection circuit 200 is in the first stage or the second stage. When the sub-control signal P1 is a high logic value, the sub-control signal P2 is a low logic value, at which time the zero-crossing detection circuit 200 is in the first stage. When the sub-control signal P2 is a high logic value, the sub-control signal P1 is a low logic value, at which time the zero-crossing detection circuit 200 is in the second stage.

[0040] corresponding to the switching action of the power transistor M2, the voltage converter can generate a switching voltage Vsw, which can be maintained at a high voltage value in the first phase and switched to a voltage value lower than 0V in the second phase. The zero-crossing detection circuit 200 of the present embodiment is used to detect whether the voltage value of the switching voltage Vsw crosses the 0V point from a negative voltage to a positive voltage and detect the zero-crossing point ZC in the second phase. In the present embodiment, the zero-crossing detection circuit 200 detects the zero-crossing point ZC by comparing the voltage Vy with the voltage Vz (reference voltage) on the capacitor C2 at the time point tp. In the present embodiment, the zero-crossing point ZC can be detected by detecting the time point at which the voltage Vy changes from a value greater than the zero-crossing detection reference voltage Vz to a value less than the zero-crossing detection reference voltage Vz. Figure 3

[0041] In the present embodiment, when the voltage Vy is greater than the voltage Vz in the second phase, the comparator 230 can generate a comparison result Vo of a positive voltage value. In contrast, when the voltage Vy is less than the voltage Vz in the second phase, the comparator 230 can generate a comparison result Vo of a negative voltage value. It is noted that in the first phase, the comparator 230 actually constitutes a voltage buffer, and the output result generated is equal to the sum of the voltage on the first terminal of the transistor Ml and the bias error voltage Vos between the input terminal of the operational amplifier OPl (= Vy + Vos), so the inversion threshold of the inverter IVl should be near the NMOS conduction threshold. In contrast, the inverter IVl can generate a final zero-crossing detection output signal ZX_DET according to the comparison result Vo in the second phase. In the present embodiment, the final zero-crossing detection output signal ZX_DET is pulled up to a high logic value at the time point tp.

[0042] In the present embodiment, the plurality of switches S1-S6 work together to generate the zero-crossing detection reference voltage from the comparator 230 and store it on the second capacitor C2 under the control of the first sub-control signal P1, and to determine whether zero-crossing occurs from the comparator under the control of the second sub-control signal P2, with the characteristics of high speed, adjustability, accuracy, and reliability.

[0043] The following refers to Figure 4 , Figure 4 the circuit diagram of the zero-crossing detection circuit of another embodiment of the present application. The zero-crossing detection circuit 400 includes a variable resistor Rt, a switch S1, selectors 410, 420, a comparator 430, a transistor Ml, and switches S8-S10. Figure 4 The zero-crossing detection circuit 400 of the present embodiment has a similar circuit architecture to the zero-crossing detection circuit 200 of the first embodiment, and the same parts will not be described in detail here. Like the zero-crossing detection circuit 200 of the first embodiment, Figure 2 The zero-crossing detection circuit 400 of the present embodiment has a similar circuit architecture to the zero-crossing detection circuit 200 of the first embodiment, and the same parts will not be described in detail here. Like the zero-crossing detection circuit 200 of the first embodiment, Figure 2 ​The difference between the embodiments is that, in the present embodiment, the selector 410 further comprises a switch S7 in addition to the switches S5 and S6. The switch S7 is arranged in the path of the switching voltage Vsw received by the switch S5. Since the voltage of the switching voltage Vsw is special, it can be as high as the input voltage of the power converter or as low as 0 volt; therefore, the switches S6 and S7 need to be high-voltage devices, and the connection potential of the substrate needs to be considered. In addition, two redundant switches S1d1 and S1d2 can be arranged on both sides of the switch S1, and two redundant switches S4d1 and S4d2 and S2d1 and S2d2 can be arranged on both sides of the switches S4 and S2 in the selector 420, which can also be used to reduce the channel charge redistribution effect and control signal leakage charge loss of the switches S1, S4 and S2 during switching.

[0044] In the present embodiment, the zero-crossing detection circuit 400 further comprises switches S8, S9 and S10. The switch S8 is coupled between the first end of the switch S6 and a reference ground terminal AGND; the switch S9 is coupled between the second end of the capacitor C2 and the reference ground terminal AGND; and the switch S10 is coupled between the second end of the capacitor C2 and a reference ground terminal PGND. The reference ground terminal AGND is a ground terminal point belonging to the zero-crossing detection circuit 400, and the reference ground terminal PGND can be a ground terminal point belonging to the voltage converter. The switches S8 and S9 are turned on in the first stage and turned off in the second stage. The switch S10 is turned off in the first stage and turned on in the second stage.

[0045] In the present embodiment, the switches S1-S10 described above can be transistor switches.

[0046] Please refer to Figure 5 , Figure 5 FIG. 5 is a schematic diagram of an embodiment of a variable resistor in the zero-crossing detection circuit of the present application. The variable resistor 500 comprises a bias generator 510, a plurality of transistors M51-M5N and a plurality of bias selectors 521-52N. The bias generator 510 provides a bias voltage VB to the bias selectors 521-52N. The bias selectors 521-52N further receive a reference ground voltage V GND and selection signals A1-AN and AB1-ABN, respectively. The bias selectors 521-52N correspond to the transistors M51-M5N, respectively, and select the bias voltage VB or the reference ground voltage V GND to the control terminals of the corresponding transistors M51-M5N according to the selection signals A1-AN and AB1-ABN, respectively. The transistors M51-M5N are connected in parallel between a first end Rtop and a second end Rbot of the variable resistor 500.

[0047] In the present embodiment, when each transistor M51-M5N receives the bias voltage VB, each transistor M51-M5N can operate in the linear region and provide a resistance value. In contrast, when each transistor M51-M5N receives the reference ground voltage V GND , each transistor M51-M5N can be turned off. Therefore, by selecting the signals A1-AN, AB1-ABN, the number of transistors M51-M5N operating in the linear region can be adjusted, and thus the resistance value of the variable resistor 500 can be adjusted.

[0048] In another aspect, the bias voltage generator 510 includes an operational amplifier OP51, resistors R1, R2, and a transistor MV. The resistors R1, R2, and the transistor MV are connected in series between the power supply voltage Vdd and the ground GND. The positive input terminal of the operational amplifier OP51 receives a reference voltage Vref; the negative input terminal of the operational amplifier OP51 is coupled to the second terminal of the transistor MV; and the output terminal of the operational amplifier OP51 is coupled to the control terminal of the transistor MV. The voltage at the coupling point of the resistor R2 and the transistor MV can be equal to the reference voltage Vref, and can define the drain-source current of the transistor MV. By causing the current generated by the transistor MV to flow through the resistor R1, the bias voltage VB can be generated.

[0049] In the present embodiment, the magnitude of the bias voltage VB can be used to control the resistance value that each transistor M51-M5N can provide. The reference voltage Vref can be the output voltage of the voltage converter. In this way, the variable resistor 500 can track the output voltage of the voltage converter to adjust the magnitude of the resistance value provided, effectively improving the accuracy of the detection action of the zero-crossing detection circuit.

[0050] It is noted that in the present embodiment, the transistors M51-M5N are coupled to each other in parallel. In other embodiments of the present application, the transistors M51-M5N can be coupled to each other in series, or in a partially parallel and partially series manner. That is, Figure 5 the embodiments shown in FIG. 6 are merely illustrative examples, and one of ordinary skill in the art can connect the transistors M51-M5N in any manner without being limited in a specific way. In addition, in the present embodiment, the transistors M51-M5N are N-type transistors. In other embodiments, the transistors M51-M5N can be P-type transistors without being limited in a specific way.

[0051] It is noted that the operational amplifier mentioned in the embodiments of the present application can be implemented by using a folded cascode amplifier, or any operational amplifier known to one of ordinary skill in the art without being limited in a specific way.

[0052] According to the above, the zero-crossing detection circuit of the embodiment of the present application performs the detection action of switching the zero-crossing point of the voltage by the first stage of setting the reference voltage according to the voltage on the first end of the first transistor by the comparator, and the second stage of performing the comparison action of the voltage on the second end of the variable resistor with the reference voltage by the comparator. Further, the zero-crossing detection circuit of the embodiment of the present application can adjust the detection time point by adjusting the resistance value of the variable resistor, real-time and flexible track the output voltage of the power converter, and further improve the accuracy of the zero-crossing detection.

[0053] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A zero-crossing detection circuit, characterized in that: include: a variable resistor having a first end connected to a power supply voltage through a reference resistor; a first switch having a first end coupled to the first end of the variable resistor; a first capacitor having a first end coupled to the second end of the first switch; a first selector, configured to enable the second end of the first capacitor to receive a switching voltage or a reference ground voltage according to a first control signal; a first transistor having a first terminal coupled to the second terminal of the variable resistor, the second terminal of the first transistor receiving the reference ground voltage; a second selector, coupled to the control terminal of the first transistor to the first terminal of the first transistor or to the first terminal of the first capacitor according to the first control signal; as well as The comparator compares the voltage at the second terminal of the variable resistor with a zero-crossing detection reference voltage to generate a final zero-crossing detection output signal.

2. The zero-crossing detection circuit according to claim 1, characterized in that In the first phase, the first switch S1 is turned on, the second selector 120 couples the first terminal of the first transistor to the control terminal of the first transistor, and the first selector enables the second terminal of the first capacitor to receive the reference ground voltage.

3. The zero-crossing detection circuit according to claim 2, characterized in that: In the first stage, the comparator is configured as a voltage buffer to generate the zero-crossing detection reference voltage according to the voltage on the first terminal of the first transistor.

4. The zero-crossing detection circuit according to claim 2, characterized in that: In the second phase, the first switch is turned off, the second selector couples the control terminal of the first transistor to the first terminal of the first capacitor, and the first selector enables the second terminal of the first capacitor to receive the switching voltage.

5. The zero-crossing detection circuit according to claim 4, characterized in that: In the second stage, the comparator eliminates the offset error and generates the final zero-crossing detection output signal.

6. The zero-crossing detection circuit according to claim 4, characterized in that: The first stage and the second stage occur alternately.

7. The zero-crossing detection circuit according to claim 1, wherein: The first selector includes a second switch and a third switch, the third switch is coupled between the second end of the first capacitor and the switching voltage of the zero-crossing detection circuit, and the second switch is coupled between the second end of the first capacitor and the reference ground voltage, wherein the second switch is controlled by a first sub-control signal, and the third switch is controlled by a second sub-control signal.

8. The zero-crossing detection circuit according to claim 7, characterized in that: The second selector includes a fourth switch and a fifth switch, the fifth switch is coupled between the control terminal of the first transistor and the first terminal of the first transistor, and the fourth switch is coupled between the control terminal of the first transistor and the first terminal of the first capacitor, wherein the fifth switch is controlled by the first sub-control signal, and the fourth switch is controlled by the second sub-control signal.

9. The zero-crossing detection circuit according to claim 8, characterized in that: The comparator comprises: an operational amplifier having a positive input terminal coupled to the first terminal of the first transistor, a negative input terminal of the operational amplifier coupled to an output terminal of the operational amplifier, the operational amplifier being configured as a voltage buffer for generating a zero-crossing detection reference voltage for comparison in the comparator; a second capacitor coupled between the negative input terminal of the operational amplifier and the reference ground voltage, storing the zero-crossing detection reference voltage generated by the voltage buffer; and The sixth switch is coupled between the output terminal of the operational amplifier and the negative input terminal of the operational amplifier, and is controlled by the first sub-control signal.

10. The zero-crossing detection circuit according to claim 9, characterized in that: Also includes: An inverter is coupled to the output terminal of the operational amplifier and generates a final zero-crossing detection output signal according to the output of the operational amplifier.

11. The zero-crossing detection circuit according to claim 9, characterized in that: The sixth switch is turned on in the first phase and turned off in the second phase.

12. The zero-crossing detection circuit according to claim 9, characterized in that: The sixth switch includes a plurality of sub-switches connected in series.

13. The zero-crossing detection circuit according to claim 9, characterized in that: Also includes: a second transistor coupled between the second terminal of the second capacitor and the first reference ground terminal; and a third transistor coupled between the second terminal of the second capacitor and the second reference ground terminal; The on and off states of the second transistor and the third transistor are respectively the same as the on and off states of the second switch and the third switch.

14. The zero-crossing detection circuit according to claim 1, characterized in that: The variable resistor comprises: a bias generator for generating a bias voltage; a plurality of second transistors coupled in parallel between the first end and the second end of the variable resistor; and A plurality of bias selectors have different bias voltages corresponding to the plurality of transistors, and the programmable resistors of the bias selectors change the bias voltage according to a selection signal, or change the reference voltage to provide to the control terminals of the corresponding plurality of transistors.

15. The zero-crossing detection circuit according to claim 14, characterized in that: The bias generator comprises: A first resistor and a second resistor are coupled in series between the power supply voltage and the reference ground voltage; a third transistor coupled between the first resistor and the second resistor; and An operational amplifier has a positive input terminal for receiving the output voltage of the voltage converter, a negative input terminal of the operational amplifier is coupled to the coupling terminal of the third transistor and the second resistor, and an output terminal of the operational amplifier is coupled to the control terminal of the third transistor.

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