Physical layer chip link quality detection method and device and electronic equipment

Abstract

The invention discloses a physical layer chip link quality detection method and device and electronic equipment, and belongs to the technical field of computers. The method comprises the following steps: acquiring a physical coding sub-layer descrambling state, a real-time signal-to-noise ratio and a physical layer chip link state of a target physical layer chip; performing detection configuration on the physical coding sub-layer descrambling state, the real-time signal-to-noise ratio and the physical layer chip link state according to a set single detection condition; acquiring a first configuration condition aiming at the real-time signal-to-noise ratio, a second configuration condition aiming at the descrambling state of the physical coding sub-layer and a third configuration condition aiming at the link state of the physical layer chip; determining whether a link of a target physical layer chip is abnormal based on the first configuration condition, the second configuration condition and the third configuration condition; and under the condition that the link of the target physical layer chip is abnormal, determining an abnormity corresponding to a target configuration condition as a link abnormity reason of the target physical layer chip.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a physical layer chip link quality detection method, device, and electronic device. Background Art

[0002] The health of the physical layer (PHY) chip's receive link is a key indicator of the chip's signal reliability. If the receive link is normal, the chip is in a connected state and can parse received messages and communicate normally. If the receive link is abnormal, errors will occur during message parsing, the chip will enter an interrupted state, and normal communication will be impossible.

[0003] Generally speaking, the factors that determine whether the link of the physical layer chip is normal are complex. After determining that the link of the physical layer chip is abnormal, it is difficult to accurately locate the cause of the abnormal link of the physical layer chip. Summary of the Invention

[0004] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a physical layer chip link quality detection method, device and electronic device to solve the problem of being unable to accurately locate the cause of the physical layer chip link abnormality.

[0005] In a first aspect, the present application provides a physical layer chip link quality detection method, comprising:

[0006] Obtain the physical coding sublayer descrambling status, real-time signal-to-noise ratio, and physical layer chip link status of the target physical layer chip;

[0007] Detect and configure the physical coding sublayer descrambling state, the real-time signal-to-noise ratio, and the physical layer chip link state according to the set single detection condition, and obtain a first configuration condition for the real-time signal-to-noise ratio, a second configuration condition for the physical coding sublayer descrambling state, and a third configuration condition for the physical layer chip link state;

[0008] Determining whether a link of the target physical layer chip is abnormal based on the first configuration condition, the second configuration condition, and the third configuration condition;

[0009] In the case of a link abnormality of the target physical layer chip, the abnormality corresponding to the target configuration condition is determined as the cause of the link abnormality of the target physical layer chip; the target configuration condition is one of the first configuration condition, the second configuration condition and the third configuration condition.

[0010] According to the physical layer chip link quality detection method of the present application, the physical coding sublayer descrambling state, real-time signal-to-noise ratio, and physical layer chip link state of a target physical layer chip are obtained; the physical coding sublayer descrambling state, real-time signal-to-noise ratio, and physical layer chip link state are detected and configured according to a set single detection condition to obtain a first configuration condition for the real-time signal-to-noise ratio, a second configuration condition for the physical coding sublayer descrambling state, and a third configuration condition for the physical layer chip link state; based on the first configuration condition, the second configuration condition, and the third configuration condition, it is determined whether the link of the target physical layer chip is abnormal; if the link of the target physical layer chip is abnormal, the abnormality corresponding to the target configuration condition is determined as the cause of the link abnormality of the target physical layer chip, so as to determine whether the link of the target physical layer chip is abnormal based on the obtained physical coding sublayer descrambling state, real-time signal-to-noise ratio, and physical layer chip link state. After determining that the link of the target physical layer chip is abnormal, the abnormality corresponding to the target configuration condition used to determine the link abnormality of the target physical layer chip is accurately determined as the cause of the link abnormality of the target physical layer chip, thereby solving the problem of being unable to accurately locate the cause of the link abnormality of the physical layer chip.

[0011] According to one embodiment of the present application, the physical coding sublayer descrambling state, the real-time signal-to-noise ratio, and the physical layer chip link state are detected and configured according to a set single detection condition, and a first configuration condition for the real-time signal-to-noise ratio, a second configuration condition for the physical coding sublayer descrambling state, and a third configuration condition for the physical layer chip link state are obtained, including:

[0012] According to the set single detection condition, determining that the real-time signal-to-noise ratio is less than or equal to the first target standard value as the first configuration condition;

[0013] According to the single detection condition, determining that the physical coding sublayer descrambling state is equal to the second target standard value as the second configuration condition; the second target standard value indicates that the physical coding sublayer descrambling state of the target physical layer chip at the second target moment is normal;

[0014] According to the single detection condition, the physical layer chip link status being equal to the third target standard value is determined as the third configuration condition; the third target standard value indicates that the physical layer chip link status of the target physical layer chip is normal.

[0015] According to one embodiment of the present application, determining whether a link of a target physical layer chip is abnormal based on the first configuration condition, the second configuration condition, and the third configuration condition includes:

[0016] When the real-time signal-to-noise ratio reaches a first configuration condition, the physical coding sublayer descrambling state reaches a second configuration condition, or the physical layer chip link state reaches a third configuration condition, it is determined that a link of the target physical layer chip is abnormal.

[0017] According to one embodiment of the present application, when a link of a target physical layer chip is abnormal, determining the abnormality corresponding to the target configuration condition as a cause of the link abnormality of the target physical layer chip includes:

[0018] When the link of the target physical layer chip is abnormal and the real-time signal-to-noise ratio reaches the first configuration condition, determining the abnormality corresponding to the real-time signal-to-noise ratio as a cause of the link abnormality of the target physical layer chip;

[0019] or

[0020] When the link of the target physical layer chip is abnormal and the physical coding sublayer descrambling state meets the second configuration condition, the abnormality corresponding to the physical coding sublayer descrambling state is determined as the cause of the link abnormality of the target physical layer chip.

[0021] According to one embodiment of the present application, when a link of a target physical layer chip is abnormal, determining the abnormality corresponding to the target configuration condition as a cause of the link abnormality of the target physical layer chip includes:

[0022] When the link of the target physical layer chip is abnormal, the real-time signal-to-noise ratio does not meet the first configuration condition, and the physical coding sublayer descrambling state does not meet the second configuration condition, the abnormality corresponding to the third configuration condition is determined as the cause of the link abnormality of the target physical layer chip.

[0023] According to one embodiment of the present application, in the case of a link abnormality of a target physical layer chip, after determining the abnormality corresponding to the target configuration condition as the cause of the link abnormality of the target physical layer chip, the method includes:

[0024] Send the link abnormality reason of the target physical layer chip to the central processing unit;

[0025] The central processing unit modifies the circuit parameters based on the cause of the link abnormality to restore the link of the target physical layer chip to normal.

[0026] In a second aspect, the present application provides a physical layer chip link quality detection device, comprising:

[0027] The first acquisition module is used to obtain the physical coding sublayer descrambling status, real-time signal-to-noise ratio and physical layer chip link status of the target physical layer chip;

[0028] a second acquisition module, configured to detect and configure the physical coding sublayer descrambling state, the real-time signal-to-noise ratio, and the physical layer chip link state according to a set single detection condition, and obtain a first configuration condition for the real-time signal-to-noise ratio, a second configuration condition for the physical coding sublayer descrambling state, and a third configuration condition for the physical layer chip link state;

[0029] The first determining module is configured to determine whether the link of the target physical layer chip is abnormal based on the first configuration condition, the second configuration condition and the third configuration condition.

[0030] The second determining module is configured to determine, in a case where the link of the target physical layer chip is abnormal, that an abnormality corresponding to the target configuration condition is the reason for the abnormality of the link of the target physical layer chip, wherein the target configuration condition is one of the first configuration condition, the second configuration condition and the third configuration condition.

[0031] According to the physical layer chip link quality detection device provided in the application, the physical encoding sublayer descrambling state, the real-time signal-to-noise ratio and the physical layer chip link state of a target physical layer chip are acquired; the physical encoding sublayer descrambling state, the real-time signal-to-noise ratio and the physical layer chip link state are configured for detection according to a single detection condition, and the first configuration condition for the real-time signal-to-noise ratio, the second configuration condition for the physical encoding sublayer descrambling state and the third configuration condition for the physical layer chip link state are acquired; whether the link of the target physical layer chip is abnormal is determined based on the first configuration condition, the second configuration condition and the third configuration condition; in a case where the link of the target physical layer chip is abnormal, an abnormality corresponding to the target configuration condition is determined as the reason for the abnormality of the link of the target physical layer chip, so that whether the link of the target physical layer chip is abnormal is determined based on the acquired physical encoding sublayer descrambling state, real-time signal-to-noise ratio and physical layer chip link state, and after it is determined that the link of the target physical layer chip is abnormal, the abnormality corresponding to the target configuration condition used to determine that the link of the target physical layer chip is abnormal is accurately determined as the reason for the abnormality of the link of the target physical layer chip, thereby solving the problem that the reason for the abnormality of the physical layer chip link cannot be accurately located.

[0032] According to an embodiment of the application, the physical layer chip link quality detection device further comprises:

[0033] The sending module is configured to send the reason for the abnormality of the link of the target physical layer chip to a central processor.

[0034] The modifying module is configured to modify the circuit parameter based on the reason for the abnormality of the link, so as to restore the link of the target physical layer chip to normal.

[0035] In a third aspect, the application provides an electronic device, which comprises a memory, a processor and a computer program stored in the memory, and the processor executes the computer program to implement the physical layer chip link quality detection method in the first aspect.

[0036] In a fourth aspect, the application provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the physical layer chip link quality detection method in the first aspect.

[0037] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0039] Figure 1 This is a flowchart of the related technology provided by the embodiment of the present application for detecting whether the physical layer chip link is abnormal;

[0040] Figure 2 This is one of the flow charts of the physical layer chip link quality detection method provided in the embodiment of the present application;

[0041] Figure 3 This is the second flow chart of the physical layer chip link quality detection method provided in the embodiment of the present application;

[0042] Figure 4 This is a structural diagram of a physical layer chip link quality detection device provided in an embodiment of the present application;

[0043] Figure 5 It is a structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0044] The following will be combined with the accompanying drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this application.

[0045] The terms "first," "second," and the like in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of this application can be implemented in an order other than that illustrated or described herein, and that the objects distinguished by "first," "second," and the like are generally of the same type, and do not limit the number of objects; for example, the first object can be one or more. In addition, the term "and / or" in the specification and claims refers to at least one of the connected objects, and the character " / " generally indicates that the objects connected are in an "or" relationship.

[0046] like Figure 1As shown, for a physical layer chip, a failure in synchronization of the physical coding sublayer descrambling of the physical layer chip within a certain period of time (i.e., scr_status = 0) can cause a link anomaly in the physical layer chip, and / or a persistently low real-time signal-to-noise ratio (SNR) of the physical layer chip link within a certain period of time (e.g., every real-time SNR within a certain period of time is lower than the target real-time SNR, i.e., snr_drop_status = 1) can also cause a link anomaly in the physical layer chip. Because the factors that determine whether the physical layer chip link is normal are complex, after determining that the physical layer chip link is abnormal, it is difficult to accurately determine the specific cause of the physical layer chip link anomaly.

[0047] The following describes in detail the physical layer chip link quality detection method, device, and electronic device provided in the embodiments of the present application through specific embodiments and their application scenarios in conjunction with the accompanying drawings.

[0048] The physical layer chip link quality detection method may be applied to a terminal, and may be specifically executed by hardware or software in the terminal.

[0049] The terminal includes, but is not limited to, a portable communication device such as a mobile phone or tablet computer having a touch-sensitive surface (e.g., a touch screen display and / or a touch pad). It should also be understood that, in some embodiments, the terminal may not be a portable communication device, but a desktop computer having a touch-sensitive surface (e.g., a touch screen display and / or a touch pad).

[0050] In the following embodiments, a terminal including a display and a touch-sensitive surface is described. However, it should be understood that the terminal may include one or more other physical user interface devices such as a physical keyboard, a mouse, and a joystick.

[0051] The physical layer chip link quality detection method provided in the embodiment of the present application may be executed by an electronic device or a functional module or functional entity in the electronic device that can implement the physical layer chip link quality detection method. The electronic devices mentioned in the embodiment of the present application include but are not limited to mobile phones, tablet computers, computers, cameras, and wearable devices. The physical layer chip link quality detection method provided in the embodiment of the present application is described below using an electronic device as an example of the execution entity.

[0052] like Figure 2 As shown, the physical layer chip link quality detection method includes: step 210, step 220, step 230 and step 240.

[0053] Step 210: Obtain the physical coding sublayer descrambling status, real-time signal-to-noise ratio, and physical layer chip link status of the target physical layer chip.

[0054] In some embodiments, the physical layer chip link quality detection method can be applied to a target physical layer chip, or to a physical layer chip different from the target physical layer chip, and this application does not impose any specific restrictions on this.

[0055] In actual implementation, the target physical layer chip may be any physical layer chip, and the link of the target physical layer chip may be a receiving link of the target physical layer chip.

[0056] In some embodiments, the physical coding sublayer descrambling status, real-time signal-to-noise ratio, and physical layer chip link status can be obtained through the central processing unit.

[0057] Step 220: Detect and configure the physical coding sublayer descrambling state, the real-time signal-to-noise ratio, and the physical layer chip link state according to the set single detection condition, and obtain a first configuration condition for the real-time signal-to-noise ratio, a second configuration condition for the physical coding sublayer descrambling state, and a third configuration condition for the physical layer chip link state.

[0058] In actual implementation, the first configuration condition may include a target standard value corresponding to the real-time signal-to-noise ratio. In some embodiments, the target standard value corresponding to the real-time signal-to-noise ratio may be a set value, and the target standard value corresponding to the real-time signal-to-noise ratio may be set based on the real-time signal-to-noise ratio.

[0059] In some embodiments, the first configuration condition may include a time window length for detecting a real-time signal-to-noise ratio.

[0060] In some embodiments, the real-time signal-to-noise ratio may be detected and configured according to a set single detection condition to obtain a first configuration condition for the real-time signal-to-noise ratio.

[0061] In actual implementation, the second configuration condition may include a target standard value corresponding to the physical coding sublayer descrambling state. In some embodiments, the target standard value corresponding to the physical coding sublayer descrambling state may be a set value, and the target standard value corresponding to the physical coding sublayer descrambling state may be set based on the physical coding sublayer descrambling state.

[0062] In some embodiments, the physical coding sublayer descrambling state may be detected and configured according to a set single detection condition to obtain a second configuration condition for the physical coding sublayer descrambling state.

[0063] In actual implementation, the third configuration condition may include a target standard value corresponding to the physical layer chip link state. In some embodiments, the target standard value corresponding to the physical layer chip link state may be a set value, and the target standard value corresponding to the physical layer chip link state may be set based on the physical layer chip link state.

[0064] In some embodiments, the physical layer chip link state may be detected and configured according to a set single detection condition to obtain a third configuration condition for the physical layer chip link state.

[0065] Step 230: Determine whether the link of the target physical layer chip is abnormal based on the first configuration condition, the second configuration condition, and the third configuration condition.

[0066] In some embodiments, after obtaining the first configuration condition, the second configuration condition, and the third configuration condition, the real-time signal-to-noise ratio, the physical coding sublayer descrambling status, and the physical layer chip link status can be detected based on the first configuration condition, the second configuration condition, and the third configuration condition, respectively.

[0067] In some embodiments, whether a link of a target physical layer chip is abnormal can be determined based on a real-time signal-to-noise ratio and a first configuration condition corresponding to the real-time signal-to-noise ratio. Whether a link of a target physical layer chip is abnormal can be determined based on a physical coding sublayer descrambling state and a second configuration condition corresponding to the physical coding sublayer descrambling state. Whether a link of a target physical layer chip is abnormal can be determined based on a physical layer chip link state and a third configuration condition corresponding to the physical layer chip link state.

[0068] Step 240: When the link of the target physical layer chip is abnormal, determine the abnormality corresponding to the target configuration condition as the cause of the link abnormality of the target physical layer chip; the target configuration condition is one of the first configuration condition, the second configuration condition, and the third configuration condition.

[0069] In some embodiments, if a link anomaly of the target physical layer chip is detected based on any one of the first configuration condition, the second configuration condition, and the third configuration condition, that configuration condition may be determined as the target configuration condition, and the anomaly corresponding to the target configuration condition may be determined as the cause of the link anomaly of the target physical layer chip. For example, if it is detected that the real-time signal-to-noise ratio meets the corresponding first configuration condition, the real-time signal-to-noise ratio anomaly may be determined as the cause of the link anomaly of the target physical layer chip; if it is detected that the physical coding sublayer descrambling state meets the corresponding second configuration condition, the physical coding sublayer descrambling state anomaly may be determined as the cause of the link anomaly of the target physical layer chip.

[0070] In some embodiments, after determining the link abnormality cause of the target physical layer chip, the link abnormality cause can be sent to the central processor so that the central processor can repair the link of the target physical layer chip to restore the link of the target physical layer chip to normal.

[0071] According to the physical layer chip link quality detection method of the present application, the physical coding sublayer descrambling state, real-time signal-to-noise ratio, and physical layer chip link state of a target physical layer chip are obtained; the physical coding sublayer descrambling state, real-time signal-to-noise ratio, and physical layer chip link state are detected and configured according to a set single detection condition to obtain a first configuration condition for the real-time signal-to-noise ratio, a second configuration condition for the physical coding sublayer descrambling state, and a third configuration condition for the physical layer chip link state; based on the first configuration condition, the second configuration condition, and the third configuration condition, it is determined whether the link of the target physical layer chip is abnormal; if the link of the target physical layer chip is abnormal, the abnormality corresponding to the target configuration condition is determined as the cause of the link abnormality of the target physical layer chip, so as to determine whether the link of the target physical layer chip is abnormal based on the obtained physical coding sublayer descrambling state, real-time signal-to-noise ratio, and physical layer chip link state. After determining that the link of the target physical layer chip is abnormal, the abnormality corresponding to the target configuration condition used to determine the link abnormality of the target physical layer chip is accurately determined as the cause of the link abnormality of the target physical layer chip, thereby solving the problem of being unable to accurately locate the cause of the link abnormality of the physical layer chip.

[0072] In some embodiments, according to a set single detection condition, a real-time signal-to-noise ratio being less than or equal to a first target standard value is determined as the first target configuration condition.

[0073] In actual implementation, the first target standard value may be a set value. In some embodiments, the first target standard value may be a target standard value set for a real-time signal-to-noise ratio of a target physical layer chip.

[0074] In some embodiments, the time window length for detecting the real-time signal-to-noise ratio in the first configuration condition can be set to the first target time. Compared to the related art method of determining whether a physical layer chip link is abnormal based on all real-time signal-to-noise ratios calculated over a period of time, the present application shortens the time window length for detecting the real-time signal-to-noise ratio to the first target time, thereby increasing the sensitivity of detecting whether the target physical layer chip link is abnormal and determining the cause of the target physical layer chip link abnormality.

[0075] In some embodiments, a real-time signal-to-noise ratio (SNR) of a target physical layer chip at a first target time may be obtained, and based on the real-time SNR of the target physical layer chip at the first target time and a first target standard value, whether the real-time SNR of the target physical layer chip meets a first configuration condition may be determined. For example, whether the real-time SNR of the target physical layer chip meets the first configuration condition may be determined based on a magnitude relationship between the real-time SNR of the target physical layer chip at the first target time and the first target standard value.

[0076] In some embodiments, when the real-time signal-to-noise ratio at the first target moment is less than or equal to the first target standard value, it is determined that the real-time signal-to-noise ratio has reached the first target configuration condition. For example, if the real-time signal-to-noise ratio at the first target moment is 300, and the real-time signal-to-noise ratio at the first target moment (300) is less than the first target standard value 500, it is determined that the real-time signal-to-noise ratio has reached the first target configuration condition.

[0077] In some embodiments, the first target standard value may be obtained based on the target register.

[0078] In some embodiments, the first target standard value may be adjusted through the target register, for example, the first target standard value may be reduced through the target register.

[0079] In some embodiments, based on the target register, a first target standard value is obtained, so as to dynamically adjust the standard for judging whether the target detection parameter is abnormal by obtaining the updated first target standard value, thereby improving the sensitivity of sensing whether the link of the target physical layer chip is abnormal.

[0080] According to the physical layer chip link quality detection method of the embodiment of the present application, a first target detection indicator is obtained; when the first target detection indicator is a real-time signal-to-noise ratio, according to a set single detection condition, the real-time signal-to-noise ratio is less than or equal to a first target standard value is determined as a first target configuration condition; based on the first target configuration condition and the first target detection indicator, whether the link of the target physical layer chip is abnormal is determined; when the link of the target physical layer chip is abnormal, the abnormality corresponding to the first target detection indicator is determined as the cause of the link abnormality of the target physical layer chip, so as to determine whether the link of the target physical layer chip is abnormal based on the obtained first target detection indicator. After determining that the link of the target physical layer chip is abnormal, the abnormality corresponding to the first target detection indicator used to determine the link abnormality of the target physical layer chip is accurately determined as the cause of the link abnormality of the target physical layer chip, thereby solving the problem of not being able to accurately locate the cause of the link abnormality of the physical layer chip.

[0081] In some embodiments, according to a set single detection condition, the physical coding sublayer descrambling state is determined to be equal to a second target standard value as the second configuration condition; the second target standard value indicates that the physical coding sublayer descrambling state of the target physical layer chip is normal at the second target moment.

[0082] In actual implementation, the second target standard value may be a set value. In some embodiments, the second target standard value may be a target standard value set for a physical coding sublayer descrambling state of a target physical layer chip.

[0083] In some embodiments, the time window length for detecting the physical coding sublayer descrambling state in the second configuration condition can be set to the second target time. Compared to the related art method of determining whether a physical layer chip link is abnormal based on all physical coding sublayer descrambling states calculated over a period of time, the present application shortens the time window length for detecting the physical coding sublayer descrambling state to the second target time, thereby increasing the sensitivity of detecting whether the target physical layer chip link is abnormal and determining the cause of the target physical layer chip link abnormality.

[0084] In some embodiments, a physical coding sublayer descrambling state of a target physical layer chip at a second target time may be obtained, and based on the physical coding sublayer descrambling state of the target physical layer chip at the second target time and a second target standard value, whether the physical coding sublayer descrambling state of the target physical layer chip meets a second configuration condition may be determined. For example, whether the physical coding sublayer descrambling state of the target physical layer chip meets the second configuration condition may be determined based on a magnitude relationship between the physical coding sublayer descrambling state of the target physical layer chip at the second target time and the second target standard value.

[0085] In some embodiments, when the physical coding sublayer descrambling state at the second target time is not equal to the second target standard value, the physical coding sublayer descrambling state meets the second configuration condition. For example, when the physical coding sublayer descrambling state of the target physical layer chip at the second target time is 0 and not equal to the second target standard value 1, the physical coding sublayer descrambling is lost, and it is determined that the physical coding sublayer descrambling state meets the second configuration condition.

[0086] According to the physical layer chip link quality detection method of the embodiment of the present application, a first target detection indicator is obtained; when the first target detection indicator is the physical coding sublayer descrambling state, according to the set single detection condition, the physical coding sublayer descrambling state is determined to be equal to the second target standard value as the first target configuration condition; based on the first target configuration condition and the first target detection indicator, it is determined whether the link of the target physical layer chip is abnormal; when the link of the target physical layer chip is abnormal, the abnormality corresponding to the first target detection indicator is determined as the cause of the link abnormality of the target physical layer chip, so as to determine whether the link of the target physical layer chip is abnormal based on the obtained first target detection indicator; after determining that the link of the target physical layer chip is abnormal, the abnormality corresponding to the first target detection indicator used to determine the link abnormality of the target physical layer chip is accurately determined as the cause of the link abnormality of the target physical layer chip, thereby solving the problem of not being able to accurately locate the cause of the physical layer chip link abnormality.

[0087] In some embodiments, according to the set single detection condition, the physical layer chip link status being equal to a third target standard value is determined as the third configuration condition; the third target standard value indicates that the physical layer chip link status of the target physical layer chip is normal.

[0088] In actual implementation, the third target standard value may be a set value. In some embodiments, the third target standard value may be a target standard value set for the physical layer chip link status of the target physical layer chip.

[0089] In some embodiments, a physical layer chip link state of a target physical layer chip may be obtained, and based on the physical layer chip link state of the target physical layer chip and a third target standard value, it may be determined whether the physical layer chip link state meets a third configuration condition. For example, it may be determined whether the physical layer chip link state meets the third configuration condition based on a value between the physical layer chip link state of the target physical layer chip and the third target standard value.

[0090] In some embodiments, when the physical layer chip link state is not equal to the third target standard value, it is determined that the physical layer chip link state has met the third configuration condition. For example, if the physical layer chip link state of the target physical layer chip is 0 and the physical layer chip link state (0) is not equal to the third target standard value 1, it is determined that the physical layer chip link state has met the third configuration condition.

[0091] In some embodiments, when the real-time signal-to-noise ratio reaches a first configuration condition, the physical coding sublayer descrambling state reaches a second configuration condition, or the physical layer chip link state reaches a third configuration condition, it is determined that the link of the target physical layer chip is abnormal.

[0092] In some embodiments, a real-time signal-to-noise ratio (SNR) of a target physical layer chip at a first target time may be obtained, and based on the real-time SNR of the target physical layer chip at the first target time and a first target standard value, whether the real-time SNR of the target physical layer chip meets a first configuration condition may be determined. For example, whether the real-time SNR of the target physical layer chip meets the first configuration condition may be determined based on a magnitude relationship between the real-time SNR of the target physical layer chip at the first target time and the first target standard value.

[0093] In some embodiments, when the real-time signal-to-noise ratio at the first target moment is less than or equal to the first target standard value, it is determined that the real-time signal-to-noise ratio has reached the first target configuration condition. For example, if the real-time signal-to-noise ratio at the first target moment is 300, and the real-time signal-to-noise ratio at the first target moment (300) is less than the first target standard value 500, it is determined that the real-time signal-to-noise ratio has reached the first target configuration condition.

[0094] In some embodiments, a physical coding sublayer descrambling state of a target physical layer chip at a second target time may be obtained, and based on the physical coding sublayer descrambling state of the target physical layer chip at the second target time and a second target standard value, whether the physical coding sublayer descrambling state of the target physical layer chip meets a second configuration condition may be determined. For example, whether the physical coding sublayer descrambling state of the target physical layer chip meets the second configuration condition may be determined based on a magnitude relationship between the physical coding sublayer descrambling state of the target physical layer chip at the second target time and the second target standard value.

[0095] In some embodiments, when the physical coding sublayer descrambling state at the second target time is not equal to the second target standard value, the physical coding sublayer descrambling state meets the second configuration condition. For example, when the physical coding sublayer descrambling state of the target physical layer chip at the second target time is 0 and not equal to the second target standard value 1, the physical coding sublayer descrambling is lost, and it is determined that the physical coding sublayer descrambling state meets the second configuration condition.

[0096] In some embodiments, a physical layer chip link state of a target physical layer chip may be obtained, and based on the physical layer chip link state of the target physical layer chip and a third target standard value, it may be determined whether the physical layer chip link state meets a third configuration condition. For example, it may be determined whether the physical layer chip link state meets the third configuration condition based on a value between the physical layer chip link state of the target physical layer chip and the third target standard value.

[0097] In some embodiments, when the physical layer chip link state is not equal to the third target standard value, it is determined that the physical layer chip link state has met the third configuration condition. For example, if the physical layer chip link state of the target physical layer chip is 0 and the physical layer chip link state (0) is not equal to the third target standard value 1, it is determined that the physical layer chip link state has met the third configuration condition.

[0098] In some embodiments, detection indicators sent by a central processor are obtained; wherein the detection indicators are pre-set by the user based on the central processor, and the detection indicators may include a physical coding sublayer descrambling status, a real-time signal-to-noise ratio, and a physical layer chip link status.

[0099] In some embodiments, the central processing unit may obtain detection indicators preset by the user based on a visual interface.

[0100] In some embodiments, the central processing unit can display detection indicators to the user based on a visual interface, the detection indicators including the physical coding sublayer descrambling status, real-time signal-to-noise ratio and physical layer chip link status, and obtain the detection indicators selected by the user from the detection indicators.

[0101] In some embodiments, when the link of the target physical layer chip is abnormal and the real-time signal-to-noise ratio reaches a first configuration condition, the abnormality corresponding to the real-time signal-to-noise ratio is determined as the cause of the link abnormality of the target physical layer chip; or when the link of the target physical layer chip is abnormal and the physical coding sublayer descrambling state reaches a second configuration condition, the abnormality corresponding to the physical coding sublayer descrambling state is determined as the cause of the link abnormality of the target physical layer chip.

[0102] In some embodiments, when the link of the target physical layer chip is abnormal, the real-time signal-to-noise ratio does not meet the first configuration condition, and the physical coding sublayer descrambling state does not meet the second configuration condition, the abnormality corresponding to the third configuration condition is determined as the cause of the link abnormality of the target physical layer chip.

[0103] In actual implementation, the anomalies corresponding to the third configuration condition may include that the signal-to-noise ratio within the target time period is less than or equal to the fourth target standard value, and / or the physical coding sublayer descrambling state is not equal to the second target standard value, the fourth target standard value may be equal to the first target standard value, and the fourth target standard value may also not be equal to the first target standard value, and the target event end can be a time period of any length.

[0104] In some embodiments, when the link of the target physical layer chip is abnormal, the real-time signal-to-noise ratio does not meet the first configuration condition, and the physical coding sublayer descrambling state does not meet the second configuration condition, the physical coding sublayer descrambling state not being equal to the second target standard value can be excluded, and the signal-to-noise ratio within the target time period is less than or equal to the fourth target standard value as the cause of the link abnormality of the target physical layer chip.

[0105] In some embodiments, in the event of a link abnormality in the target physical layer chip, after the abnormality corresponding to the target configuration condition is determined as the cause of the link abnormality in the target physical layer chip, the cause of the link abnormality in the target physical layer chip is sent to the central processor; the central processor modifies the circuit parameters based on the cause of the link abnormality to restore the link of the target physical layer chip to normal.

[0106] In actual implementation, the circuit parameters may include coefficients of a clock recovery circuit or an equalization filter circuit of a target physical layer chip link.

[0107] In some embodiments, the central processor may modify the coefficients of the clock recovery circuit or the equalization filter circuit of the target physical layer chip link based on the cause of the link abnormality to improve the performance of the target physical layer chip link, thereby improving the quality of the received signal.

[0108] According to the physical layer chip link quality detection method of the present application, by obtaining a first target detection indicator for a target physical layer chip, the first target detection indicator is detected and configured according to a set single detection condition to obtain a first target configuration condition; based on the first target configuration condition and the first target detection indicator, it is determined whether the link of the target physical layer chip is abnormal; in the case that the link of the target physical layer chip is abnormal, the abnormality corresponding to the first target detection indicator is determined as the cause of the link abnormality of the target physical layer chip, so as to determine whether the link of the target physical layer chip is abnormal based on the obtained first target detection indicator. After determining that the link of the target physical layer chip is abnormal, the abnormality corresponding to the first target detection indicator used to determine the link abnormality of the target physical layer chip is accurately determined as the cause of the link abnormality of the target physical layer chip, and the cause of the link abnormality of the target physical layer chip is sent to a central processing unit; based on the cause of the link abnormality, the central processing unit modifies circuit parameters to restore the link of the target physical layer chip to normal, thereby improving the quality of the received signal.

[0109] In order to better understand the physical layer chip link quality detection method provided in the embodiment of the present application, further explanation is given below. It should be understood that the following discussion is only exemplary.

[0110] This application provides a physical layer chip link quality detection method, the specific steps can be as follows Figure 3 As shown:

[0111] Step 310: Obtain the detection indicators sent by the central processor; wherein the detection indicators are pre-set by the user based on the central processor for the link of the target physical layer chip, and the detection indicators include the physical coding sublayer descrambling status, real-time signal-to-noise ratio and physical layer chip link status of the target physical layer chip.

[0112] In some embodiments, the physical layer chip link quality detection method can be applied to a target physical layer chip, or to a physical layer chip different from the target physical layer chip, and this application does not impose any specific restrictions on this.

[0113] In actual implementation, the target physical layer chip may be any physical layer chip, and the link of the target physical layer chip may be a receiving link of the target physical layer chip.

[0114] In some embodiments, the central processing unit may obtain detection indicators preset by the user based on a visual interface.

[0115] In some embodiments, the central processing unit can display detection indicators to the user based on a visual interface, the detection indicators including the physical coding sublayer descrambling status, real-time signal-to-noise ratio and physical layer chip link status, and obtain the detection indicators selected by the user from the detection indicators.

[0116] Step 313: According to the set single detection condition, the real-time signal-to-noise ratio is determined to be less than or equal to the first target standard value as the first configuration condition.

[0117] In actual implementation, the first target standard value may be a set value. In some embodiments, the first target standard value may be a target standard value set for a real-time signal-to-noise ratio of a target physical layer chip.

[0118] In some embodiments, the time window length for detecting the real-time signal-to-noise ratio in the first configuration condition can be set to the first target time. Compared to the related art method of determining whether a physical layer chip link is abnormal based on all real-time signal-to-noise ratios calculated over a period of time, the present application shortens the time window length for detecting the real-time signal-to-noise ratio to the first target time, thereby increasing the sensitivity of detecting whether the target physical layer chip link is abnormal and determining the cause of the target physical layer chip link abnormality.

[0119] In some embodiments, the first target standard value may be obtained based on the target register.

[0120] In some embodiments, the first target standard value may be adjusted through the target register, for example, the first target standard value may be reduced through the target register.

[0121] In some embodiments, based on the target register, a first target standard value is obtained, so as to dynamically adjust the standard for judging whether the target detection parameter is abnormal by obtaining the updated first target standard value, thereby improving the sensitivity of sensing whether the link of the target physical layer chip is abnormal.

[0122] Step 316: According to the set single detection condition, the physical coding sublayer descrambling state is determined to be equal to the second target standard value as the second configuration condition; the second target standard value indicates that the physical coding sublayer descrambling state of the target physical layer chip is normal at the second target moment.

[0123] In actual implementation, the second target standard value may be a set value. In some embodiments, the second target standard value may be a target standard value set for a physical coding sublayer descrambling state of a target physical layer chip.

[0124] In some embodiments, the time window length for detecting the physical coding sublayer descrambling state in the second configuration condition can be set to the second target time. Compared to the related art method of determining whether a physical layer chip link is abnormal based on all physical coding sublayer descrambling states calculated over a period of time, the present application shortens the time window length for detecting the physical coding sublayer descrambling state to the second target time, thereby increasing the sensitivity of detecting whether the target physical layer chip link is abnormal and determining the cause of the target physical layer chip link abnormality.

[0125] Step 319: According to the set single detection condition, the physical layer chip link status being equal to the third target standard value is determined as the third configuration condition; the third target standard value indicates that the physical layer chip link status of the target physical layer chip is normal.

[0126] In actual implementation, the third target standard value may be a set value. In some embodiments, the third target standard value may be a target standard value set for the physical layer chip link status of the target physical layer chip.

[0127] Step 322: Detect whether the real-time signal-to-noise ratio meets the first configuration condition.

[0128] In some embodiments, a real-time signal-to-noise ratio (SNR) of a target physical layer chip at a first target time may be obtained, and based on the real-time SNR of the target physical layer chip at the first target time and a first target standard value, whether the real-time SNR of the target physical layer chip meets a first configuration condition may be determined. For example, whether the real-time SNR of the target physical layer chip meets the first configuration condition may be determined based on a magnitude relationship between the real-time SNR of the target physical layer chip at the first target time and the first target standard value.

[0129] In some embodiments, when the real-time signal-to-noise ratio at the first target moment is less than or equal to the first target standard value, it is determined that the real-time signal-to-noise ratio has reached the first target configuration condition. For example, if the real-time signal-to-noise ratio at the first target moment is 300, and the real-time signal-to-noise ratio at the first target moment (300) is less than the first target standard value 500, it is determined that the real-time signal-to-noise ratio has reached the first target configuration condition.

[0130] Step 325: Check whether the physical coding sublayer descrambling state meets the second configuration condition.

[0131] In some embodiments, a physical coding sublayer descrambling state of a target physical layer chip at a second target time may be obtained, and based on the physical coding sublayer descrambling state of the target physical layer chip at the second target time and a second target standard value, whether the physical coding sublayer descrambling state of the target physical layer chip meets a second configuration condition may be determined. For example, whether the physical coding sublayer descrambling state of the target physical layer chip meets the second configuration condition may be determined based on a magnitude relationship between the physical coding sublayer descrambling state of the target physical layer chip at the second target time and the second target standard value.

[0132] In some embodiments, when the physical coding sublayer descrambling state at the second target time is not equal to the second target standard value, the physical coding sublayer descrambling state meets the second configuration condition. For example, when the physical coding sublayer descrambling state of the target physical layer chip at the second target time is 0 and not equal to the second target standard value 1, the physical coding sublayer descrambling is lost, and it is determined that the physical coding sublayer descrambling state meets the second configuration condition.

[0133] Step 328: Check whether the physical layer chip link status meets the third configuration condition.

[0134] In some embodiments, a physical layer chip link state of a target physical layer chip may be obtained, and based on the physical layer chip link state of the target physical layer chip and a third target standard value, it may be determined whether the physical layer chip link state meets a third configuration condition. For example, it may be determined whether the physical layer chip link state meets the third configuration condition based on a value between the physical layer chip link state of the target physical layer chip and the third target standard value.

[0135] In some embodiments, when the physical layer chip link state is not equal to the third target standard value, it is determined that the physical layer chip link state has met the third configuration condition. For example, if the physical layer chip link state of the target physical layer chip is 0 and the physical layer chip link state (0) is not equal to the third target standard value 1, it is determined that the physical layer chip link state has met the third configuration condition.

[0136] Step 331: When the real-time signal-to-noise ratio reaches the first configuration condition, determine that a link of the target physical layer chip is abnormal, and determine the abnormal real-time signal-to-noise ratio as a cause of the link abnormality of the target physical layer chip.

[0137] Step 334: When the physical coding sublayer descrambling state reaches the second configuration condition, determine that the link of the target physical layer chip is abnormal, and determine the abnormal physical coding sublayer descrambling state as the cause of the link abnormality of the target physical layer chip.

[0138] Step 337: When the link of the target physical layer chip is abnormal, the real-time signal-to-noise ratio does not meet the first configuration condition, and the physical coding sublayer descrambling state does not meet the second configuration condition, the signal-to-noise ratio within the target time period is less than or equal to the fourth target standard value, which is determined as the cause of the link abnormality of the target physical layer chip.

[0139] In actual implementation, the anomalies corresponding to the third configuration condition may include that the signal-to-noise ratio within the target time period is less than or equal to the fourth target standard value, and / or the physical coding sublayer descrambling state is not equal to the second target standard value, the fourth target standard value may be equal to the first target standard value, and the fourth target standard value may also not be equal to the first target standard value, and the target event end can be a time period of any length.

[0140] In some embodiments, when the link of the target physical layer chip is abnormal, the real-time signal-to-noise ratio does not meet the first configuration condition, and the physical coding sublayer descrambling state does not meet the second configuration condition, the physical coding sublayer descrambling state not being equal to the second target standard value can be excluded, and the signal-to-noise ratio within the target time period is less than or equal to the fourth target standard value as the cause of the link abnormality of the target physical layer chip.

[0141] Step 340: Send the link abnormality cause of the target physical layer chip to the central processor; based on the link abnormality cause, the central processor modifies the circuit parameters to restore the link of the target physical layer chip to normal.

[0142] In actual implementation, the circuit parameters may include coefficients of a clock recovery circuit or an equalization filter circuit of a target physical layer chip link.

[0143] In some embodiments, the central processing unit can modify the coefficients of the clock recovery circuit or the equalization filter circuit of the target physical layer chip link based on the cause of the link abnormality to improve the performance of the target physical layer chip link, thereby improving the quality of the received signal and avoiding the phenomenon of large-scale packet loss that affects user use, thereby improving the stability of the target physical layer chip to a certain extent.

[0144] The embodiment of the present application also provides a physical layer chip link quality detection device.

[0145] like Figure 4 As shown, the physical layer chip link quality detection device 400 includes: a first acquisition module 410 , a second acquisition module 420 , a first determination module 430 and a second determination module 440 .

[0146] The first acquisition module 410 is configured to acquire the physical coding sublayer descrambling status, real-time signal-to-noise ratio, and physical layer chip link status of the target physical layer chip;

[0147] The second acquisition module 420 is configured to detect and configure the physical coding sublayer descrambling state, the real-time signal-to-noise ratio, and the physical layer chip link state according to a set single detection condition, and obtain a first configuration condition for the real-time signal-to-noise ratio, a second configuration condition for the physical coding sublayer descrambling state, and a third configuration condition for the physical layer chip link state;

[0148] A first determining module 430 is configured to determine whether a link of a target physical layer chip is abnormal based on the first configuration condition, the second configuration condition, and the third configuration condition;

[0149] The second determination module 440 is used to determine the abnormality corresponding to the target configuration condition as the cause of the link abnormality of the target physical layer chip when the link of the target physical layer chip is abnormal; the target configuration condition is one of the first configuration condition, the second configuration condition and the third configuration condition.

[0150] According to the physical layer chip link quality detection device of the present application, the physical coding sublayer descrambling state, real-time signal-to-noise ratio, and physical layer chip link state of the target physical layer chip are obtained; the physical coding sublayer descrambling state, real-time signal-to-noise ratio, and physical layer chip link state are detected and configured according to a set single detection condition to obtain a first configuration condition for the real-time signal-to-noise ratio, a second configuration condition for the physical coding sublayer descrambling state, and a third configuration condition for the physical layer chip link state; based on the first configuration condition, the second configuration condition, and the third configuration condition, it is determined whether the link of the target physical layer chip is abnormal; if the link of the target physical layer chip is abnormal, the abnormality corresponding to the target configuration condition is determined as the cause of the link abnormality of the target physical layer chip. Based on the obtained physical coding sublayer descrambling state, real-time signal-to-noise ratio, and physical layer chip link state, it is determined whether the link of the target physical layer chip is abnormal. After determining that the link of the target physical layer chip is abnormal, the abnormality corresponding to the target configuration condition used to determine the link abnormality of the target physical layer chip is accurately determined as the cause of the link abnormality of the target physical layer chip, thereby solving the problem of being unable to accurately locate the cause of the link abnormality of the physical layer chip.

[0151] In some embodiments, the second acquisition module 420 includes a first determining unit configured to determine, according to a set single detection condition, that the real-time signal-to-noise ratio is less than or equal to a first target standard value as the first configuration condition.

[0152] In some embodiments, the second acquisition module 420 includes a second determination unit, which is used to determine, according to a set single detection condition, that the physical coding sublayer descrambling state is equal to a second target standard value as a second configuration condition; the second target standard value indicates that the physical coding sublayer descrambling state of the target physical layer chip at the second target moment is normal.

[0153] In some embodiments, the second acquisition module 420 includes a third determination unit, which is used to determine, according to the set single detection condition, that the physical layer chip link state is equal to a third target standard value as a third configuration condition; the third target standard value indicates that the physical layer chip link state of the target physical layer chip is normal.

[0154] In some embodiments, the first determination module 430 is used to determine that the link of the target physical layer chip is abnormal when the real-time signal-to-noise ratio reaches the first configuration condition, the physical coding sublayer descrambling state reaches the second configuration condition, or the physical layer chip link state reaches the third configuration condition.

[0155] In some embodiments, the second determining module 440 includes a fourth determining unit configured to, when the link of the target physical layer chip is abnormal and the real-time signal-to-noise ratio meets the first configuration condition, determine the abnormality corresponding to the real-time signal-to-noise ratio as a cause of the link abnormality of the target physical layer chip;

[0156] or

[0157] In a case where the link of the target physical layer chip is abnormal, and the physical coding sublayer underrun state reaches the second configuration condition, the abnormality corresponding to the physical coding sublayer underrun state is determined as the link abnormality reason of the target physical layer chip.

[0158] In some embodiments, the second determining module 440 includes a fifth determining unit, configured to, in a case where the link of the target physical layer chip is abnormal, the real-time signal-to-noise ratio does not reach the first configuration condition, and the physical coding sublayer underrun state does not reach the second configuration condition, determine the abnormality corresponding to the third configuration condition as the link abnormality reason of the target physical layer chip.

[0159] In some embodiments, the physical layer chip link quality detection apparatus 400 further includes:

[0160] The sending module is configured to send the link abnormality reason of the target physical layer chip to a central processing unit.

[0161] The modifying module is configured to modify the circuit parameter based on the link abnormality reason, so as to make the link of the target physical layer chip normal.

[0162] The physical layer chip link quality detection apparatus in the embodiments of the present application can be an electronic device, or a component in an electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal, or other devices other than a terminal. For example, the electronic device can be a mobile phone, a tablet computer, a notebook computer, a palm computer, a vehicle-mounted electronic device, a Mobile Internet Device (MID), an augmented reality (AR) / virtual reality (VR) device, a robot, a wearable device, an ultra-mobile personal computer (UMPC), a netbook, or a personal digital assistant (PDA), etc., and can also be a server, a Network Attached Storage (NAS), a personal computer (PC), a television (TV), a teller machine, or a self-service machine, etc., and the embodiments of the present application are not limited thereto.

[0163] The physical layer chip link quality detection device in the embodiment of the present application can be a device having an operating system. The operating system can be a Microsoft (Windows) operating system, an Android operating system, an iOS operating system, or other possible operating systems, which are not specifically limited in the embodiment of the present application.

[0164] The physical layer chip link quality detection device 400 provided in the embodiment of the present application can achieve Figures 2 to 3 To avoid repetition, the various processes implemented in the method embodiment are not described here.

[0165] In some embodiments, as Figure 5 As shown, an embodiment of the present application also provides an electronic device 500, including a processor 501, a memory 502, and a computer program stored in the memory 502 and executable on the processor 501. When the program is executed by the processor 501, the various processes of the above-mentioned physical layer chip link quality detection method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0166] It should be noted that the computer devices in the embodiments of the present application include the mobile electronic devices and non-mobile electronic devices mentioned above.

[0167] An embodiment of the present application also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the various processes of the above-mentioned physical layer chip link quality detection method embodiment are implemented, and the same technical effects can be achieved. To avoid repetition, they are not repeated here.

[0168] The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0169] An embodiment of the present application also provides a computer program product, including a computer program, which implements the above-mentioned physical layer chip link quality detection method when executed by a processor.

[0170] The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0171] An embodiment of the present application further provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned physical layer chip link quality detection method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0172] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0173] It should be noted that, in this article, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element. In addition, it should be noted that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in the opposite order according to the functions involved. For example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0174] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), including a number of instructions for enabling a terminal (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0175] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

[0176] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0177] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and intent of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A physical layer chip link quality detection method, characterized in that: include: Obtain the physical coding sublayer descrambling status, real-time signal-to-noise ratio, and physical layer chip link status of the target physical layer chip; Detect and configure the physical coding sublayer descrambling state, the real-time signal-to-noise ratio, and the physical layer chip link state according to a set single detection condition, and obtain a first configuration condition for the real-time signal-to-noise ratio, a second configuration condition for the physical coding sublayer descrambling state, and a third configuration condition for the physical layer chip link state; Determining whether a link of a target physical layer chip is abnormal based on the first configuration condition, the second configuration condition, and the third configuration condition; In the case of a link abnormality of the target physical layer chip, the abnormality corresponding to the target configuration condition is determined as the cause of the link abnormality of the target physical layer chip; the target configuration condition is one of the first configuration condition, the second configuration condition and the third configuration condition.

2. The physical layer chip link quality detection method according to claim 1, characterized in that: The detecting and configuring the physical coding sublayer descrambling state, the real-time signal-to-noise ratio, and the physical layer chip link state according to the set single detection condition, and acquiring a first configuration condition for the real-time signal-to-noise ratio, a second configuration condition for the physical coding sublayer descrambling state, and a third configuration condition for the physical layer chip link state, includes: According to the set single detection condition, determining that the real-time signal-to-noise ratio is less than or equal to a first target standard value as a first configuration condition; According to the single detection condition, determining that the physical coding sublayer descrambling state is equal to a second target standard value as a second configuration condition; the second target standard value indicates that the physical coding sublayer descrambling state of the target physical layer chip is normal at a second target moment; According to the single detection condition, the physical layer chip link status being equal to a third target standard value is determined as a third configuration condition; the third target standard value indicates that the physical layer chip link status of the target physical layer chip is normal.

3. The physical layer chip link quality detection method according to claim 1, characterized in that: The determining whether a link of the target physical layer chip is abnormal based on the first configuration condition, the second configuration condition, and the third configuration condition includes: When the real-time signal-to-noise ratio reaches the first configuration condition, the physical coding sublayer descrambling state reaches the second configuration condition, or the physical layer chip link state reaches the third configuration condition, it is determined that a link of the target physical layer chip is abnormal.

4. The physical layer chip link quality detection method according to claim 1, characterized in that: When the link of the target physical layer chip is abnormal, determining the abnormality corresponding to the target configuration condition as the cause of the link abnormality of the target physical layer chip includes: If the link of the target physical layer chip is abnormal and the real-time signal-to-noise ratio reaches the first configuration condition, determining the abnormality corresponding to the real-time signal-to-noise ratio as a cause of the link abnormality of the target physical layer chip; or When the link of the target physical layer chip is abnormal and the physical coding sublayer descrambling state meets the second configuration condition, the abnormality corresponding to the physical coding sublayer descrambling state is determined as a cause of the link abnormality of the target physical layer chip.

5. The physical layer chip link quality detection method according to claim 1, characterized in that: When the link of the target physical layer chip is abnormal, determining the abnormality corresponding to the target configuration condition as the cause of the link abnormality of the target physical layer chip includes: When the link of the target physical layer chip is abnormal, the real-time signal-to-noise ratio does not meet the first configuration condition, and the physical coding sublayer descrambling state does not meet the second configuration condition, the abnormality corresponding to the third configuration condition is determined as the cause of the link abnormality of the target physical layer chip.

6. The physical layer chip link quality detection method according to any one of claims 1 to 5, characterized in that: In the case where the link of the target physical layer chip is abnormal, after determining the abnormality corresponding to the target configuration condition as the cause of the link abnormality of the target physical layer chip, the method includes: Sending the link abnormality reason of the target physical layer chip to the central processing unit; The central processor modifies circuit parameters based on the cause of the link abnormality so that the link of the target physical layer chip returns to normal.

7. A physical layer chip link quality detection device, characterized in that: include: The first acquisition module is used to obtain the physical coding sublayer descrambling status, real-time signal-to-noise ratio and physical layer chip link status of the target physical layer chip; a second acquisition module, configured to detect and configure the physical coding sublayer descrambling state, the real-time signal-to-noise ratio, and the physical layer chip link state according to a set single detection condition, and acquire a first configuration condition for the real-time signal-to-noise ratio, a second configuration condition for the physical coding sublayer descrambling state, and a third configuration condition for the physical layer chip link state; A first determining module, configured to determine whether a link of a target physical layer chip is abnormal based on the first configuration condition, the second configuration condition, and the third configuration condition; The second determination module is used to determine the abnormality corresponding to the target configuration condition as the cause of the link abnormality of the target physical layer chip when the link of the target physical layer chip is abnormal; the target configuration condition is one of the first configuration condition, the second configuration condition and the third configuration condition.

8. The physical layer chip link quality detection device according to claim 7, characterized in that: The device further comprises: A sending module, configured to send the link abnormality cause of the target physical layer chip to a central processing unit; The modification module is used to modify circuit parameters based on the cause of the link abnormality so that the link of the target physical layer chip returns to normal.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the physical layer chip link quality detection method according to any one of claims 1 to 6 is implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the physical layer chip link quality detection method according to any one of claims 1 to 6 is implemented.

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