Power device and preparation method thereof, and electronic equipment

Abstract

The invention relates to a power device and a preparation method thereof, and electronic equipment, and the device comprises the components of a substrate which comprises an epitaxial layer on a first surface; the epitaxial layer internally comprises a source region, a base region and a shielding region which are arranged along a first direction towards the substrate through the top surface; the grid electrodes are distributed at intervals along a second direction parallel to the first surface, penetrate through the source region and the base region along the first direction, and are partially embedded into the shielding region; the gate electrode comprises a gate conductive layer and a gate oxide layer which are arranged along a first direction; the interlayer dielectric layer is located on the top surface of the epitaxial layer and comprises an extension part which penetrates through the gate conductive layer in the first direction and is in contact with the gate oxide layer; the metal layer is positioned on the top surface of the interlayer dielectric layer and comprises a first source electrode which extends into the grid electrode through the top surface of the extension part; the width and depth of the first source are associated with the gate-source capacitance of the power device. The reliability of the gate oxide layer can be improved while the channel density is ensured.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a power device and a preparation method thereof, and an electronic device. Background Art

[0002] Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is a widely used power device with excellent performance. Silicon carbide (SiC) material, due to its excellent properties, is highly attractive in high-power applications, making it an ideal material for high-performance power MOSFETs. SiC MOSFET devices mainly have planar gate and trench gate structures.

[0003] Compared to planar gate structures, trench-gate silicon carbide (SiC) MOSFETs eliminate the JFET region effect due to their trench gate structure, allowing current to flow more vertically and directly from the source to the drift region. This allows for higher cell density, significantly reducing on-resistance per unit area. Thanks to higher cell density and shorter channels, input capacitance is lower, switching speeds are faster, and losses are lower, enabling more device units to be integrated on the same wafer area, effectively improving wafer utilization and chip density.

[0004] However, trench-gate SiC MOSFETs have certain manufacturing difficulties, and because the gate oxide layer is located inside the trench, its special structure makes the gate oxide layer susceptible to factors such as mechanical stress and electric field concentration, resulting in reduced breakdown voltage and reliability issues. Summary of the Invention

[0005] Based on this, it is necessary to provide a power device and a preparation method thereof, and an electronic device to address the technical problems in the prior art, which can at least improve the gate oxide reliability of the power device while improving its dynamic characteristics.

[0006] In a first aspect, the present application provides a power device, comprising: a substrate, wherein a first surface of the substrate includes an epitaxial layer; the epitaxial layer includes a source region, a base region, and a shielding region arranged along a first direction toward the substrate via a top surface;

[0007] A plurality of gates are spaced apart along a second direction parallel to the first surface, penetrate the source region and the base region along the first direction, and are partially embedded in the shielding region; the gates include a gate conductive layer and a gate oxide layer arranged along the first direction;

[0008] an interlayer dielectric layer, located on a top surface of the epitaxial layer, comprising an extension portion penetrating the gate conductive layer along a first direction and contacting the gate oxide layer;

[0009] The metal layer is located on the top surface of the interlayer dielectric layer, and includes: a first source extending into the gate through the top surface of the extension portion; the width and depth of the first source are related to the gate-source capacitance of the power device; wherein the width is used to characterize the dimension along the second direction; and the depth is used to characterize the dimension along the first direction.

[0010] In the power device of the above embodiment, the shielding region surrounds the bottom of the gate, and the gate oxide layer is separated from the high-voltage region by physical isolation, which can significantly reduce the electric field peak at the bottom of the gate, avoid the risk of gate oxide breakdown due to excessive local electric field, and enhance operational reliability. At the same time, the first source electrode and the interlayer dielectric layer extend into the gate to form a split-gate structure. By adjusting the depth and width of the first source electrode, the gate-source capacitance (C gs ) effectively reduces the power loss of the device during the switching process and optimizes the dynamic characteristics of the device.

[0011] In some embodiments, the gate comprises:

[0012] a first stage, wherein the bottom surface of the first stage is flush with the gate conductive layer;

[0013] The second stage has a top surface lower than the bottom surface of the base region and is partially embedded in the shielding region;

[0014] The bottom surface of the extension portion is located within the top surface of the second-level gate oxide layer;

[0015] The width of the second level is smaller than the width of the first level.

[0016] In some embodiments, the width of the shielding region is greater than the width of the second level and less than the width of the first level;

[0017] The depth of the first source electrode is no greater than the depth of the gate conductive layer.

[0018] In some embodiments, the width and depth of the first source electrode are related to the gate-source capacitance of the power device, including:

[0019] The depth of the first source is positively correlated with the gate-source capacitance of the power device;

[0020] The width of the first source electrode is negatively correlated with the gate-source capacitance of the power device.

[0021] In some embodiments, the gate and the interlayer dielectric layer are fabricated simultaneously in the same process step.

[0022] In some embodiments, the metal layer further includes: a second source electrode extending along the first direction through the top surface of the interlayer dielectric layer to partially embed into the base region.

[0023] In a second aspect, the present application further provides a method for preparing a power device, which is used to prepare the power device described in any of the above embodiments. The method for preparing the power device comprises:

[0024] Providing a substrate, wherein an epitaxial layer is formed on a first surface of the substrate; the epitaxial layer includes a source region, a base region, and a shielding region arranged along a first direction toward the substrate through a top surface;

[0025] After forming a plurality of gates in the epitaxial layer that are spaced apart along a second direction parallel to the first surface, penetrate the source region and the base region along the first direction, and are partially embedded in the shielding region, a stacked interlayer dielectric layer and a metal layer are formed on the top surface of the epitaxial layer;

[0026] Wherein, the gate includes a gate conductive layer and a gate oxide layer arranged along a first direction;

[0027] The interlayer dielectric layer includes an extension portion extending along a first direction through the gate conductive layer to contact the gate oxide layer;

[0028] The metal layer includes: a first source extending into the gate through the top surface of the extension portion; the width and depth of the first source are associated with the gate-source capacitance of the power device; the width is used to characterize the size along the second direction; the depth is used to characterize the size along the first direction.

[0029] In the above embodiment, a shielding region is formed at the bottom of the gate to reduce the electric field strength of the gate oxide layer at the bottom of the trench gate. An extension of the interlayer dielectric layer and a first source electrode are inserted between the gate conductive layer within the gate. The depth and width of the first source electrode inserted into the extension can be adjusted to flexibly adjust the gate-source capacitance. Compared to the traditional method of forming a shielding region solely through ion implantation at the bottom of the trench, the split-gate structure can improve the device's dynamic characteristics while improving the reliability of the device's gate oxide.

[0030] In some embodiments, forming a shielding region includes:

[0031] After forming a first-level trench in the epitaxial layer, a sacrificial layer is formed in the first-level trench;

[0032] removing a portion of the sacrificial layer to form a secondary trench penetrating the sacrificial layer along the first direction and extending to the epitaxial layer; the width of the secondary trench is smaller than the width of the primary trench;

[0033] An ion implantation process is performed on the epitaxial layer at the bottom of the secondary trench to form a shielding region.

[0034] In some embodiments, forming a gate, an interlayer dielectric layer, and a metal layer includes:

[0035] After removing the sacrificial layer, an initial gate is formed in the first-level trench;

[0036] Based on the same photomask as the secondary trench, a first groove is formed in the initial gate;

[0037] forming an interlayer dielectric layer in the first groove and on the top surface of the epitaxial layer;

[0038] forming a second groove and a third groove alternately arranged along the second direction in the interlayer dielectric layer; the third groove extends to the base region along the first direction;

[0039] A metal layer is formed to fill the second groove, the third groove, and cover the top surface of the interlayer dielectric layer; wherein the metal layer in the second groove is used to form the first source electrode, and the metal layer in the third groove is used to form the second source electrode.

[0040] In a third aspect, the present application further provides an electronic device, comprising a power device as described in any one of the above embodiments; or comprising a power device prepared by the preparation method as described in any one of the above embodiments.

[0041] In the above embodiments, electronic devices including the power devices can operate at higher switching frequencies, significantly reducing power losses during the switching process and improving operating efficiency. Furthermore, the improved gate oxide reliability can effectively reduce the probability of device damage, extend device life, and reduce equipment maintenance and replacement costs.

[0042] The power device and its manufacturing method, and electronic device provided in this application have the following unexpected technical effects:

[0043] The power device provided by this application forms physical isolation by designing a shielding region surrounding the bottom of the gate, effectively separating the gate oxide layer from the high-voltage region, alleviating the gate oxide breakdown problem caused by local electric field concentration, and significantly enhancing the reliability of the device under high-voltage working conditions. At the same time, the split-gate structure formed by the first source electrode and the extension of the interlayer dielectric layer can achieve gate-source capacitance (C) by adjusting the depth and width of the first source electrode embedded in the gate. gs ) through precise control, effectively reducing the gate-source capacitance-related losses of the device during the switching process, optimizing the switching dynamic characteristics, reducing switching power consumption, improving overall energy efficiency, and better adapting to the needs of various application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0045] Figure 1 A power device with a trench gate structure provided in the related art;

[0046] Figure 2 A power device with a trench gate structure provided in an embodiment of the present application;

[0047] Figure 3 is a flow chart of a preparation method provided in one embodiment;

[0048] Figure 4 Schematic cross-sectional view of the structure obtained after forming the buffer layer and the epitaxial layer in step S202 of the preparation method provided in one embodiment;

[0049] Figure 5 Schematic cross-sectional view of the structure obtained after the base region and the source region are formed in step S204 of the preparation method provided in one embodiment;

[0050] Figure 6a Schematic cross-sectional view of the structure obtained after forming the primary trench in step S206 of the preparation method provided in one embodiment;

[0051] Figure 6b for Figure 6a A schematic cross-sectional view of the structure obtained after forming a sacrificial layer;

[0052] Figure 7 Schematic diagram of a cross-section of a structure obtained by forming a secondary trench in step S208 of a preparation method provided in one embodiment;

[0053] Figure 8 Schematic cross-sectional view of a structure obtained after forming a shielding region in step S210 of a preparation method provided in one embodiment;

[0054] Figure 9 Schematic cross-sectional view of the structure obtained after the sacrificial layer is removed in step S402 of the preparation method provided in one embodiment;

[0055] Figure 10 Schematic cross-sectional view of a structure obtained after forming an initial gate in step S404 of a preparation method provided in one embodiment;

[0056] Figure 11 Schematic cross-sectional view of the structure obtained after forming the first groove in step S406 of the preparation method provided in one embodiment;

[0057] Figure 12 Schematic cross-sectional view of a structure obtained after forming an interlayer dielectric layer in step S408 of a preparation method provided in one embodiment;

[0058] Figure 13 Schematic cross-sectional view of a structure obtained after forming a contact hole in step S410 of a preparation method provided in one embodiment;

[0059] Figure 14 Schematic cross-sectional view of a structure obtained after forming a metal layer in step S412 of a preparation method provided in one embodiment;

[0060] Figure 15 for Figure 14 Schematic cross-sectional view of the resulting structure after forming the back metal layer.

[0061] Description of reference numerals:

[0062] 1. Initial substrate; 2. Buffer layer; 10. Substrate; 11. Epitaxial layer; 111. Source region; 112. Base region; 113. Shielding region; 20. Interlayer dielectric layer; 21. Extension portion; 30. Metal layer; 31. First source; 32. Second source; 401. Sacrificial layer; 402. Initial gate; 40. Gate; 411. Conductive material layer; 41. Gate conductive layer; 42. Gate oxide layer; 501. Primary trench; 502. Secondary trench; 503. First groove; 601. Second groove; 602. Third groove. DETAILED DESCRIPTION

[0063] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0064] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0065] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section; for example, a first dopant type could be termed a second dopant type, and, similarly, a second dopant type could be termed a first dopant type; a first dopant type and a second dopant type are different dopant types, for example, a first dopant type can be P-type and a second dopant type can be N-type, or a first dopant type can be N-type and a second dopant type can be P-type.

[0066] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It should also be understood that, when the term "comprising" is used in the present description and claims, it does not exclude the presence of other elements or steps than those listed. Likewise, the term "comprising" should not be interpreted as implying that the apparatus or method has to function only in the described way or that it has to function continuously. It should also be understood that the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0067] Embodiments of the application are described herein with reference to the drawings, which show idealized embodiments of the application (and intermediate structures thereof) in cross-section. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change between implanted and non-implanted regions. Similarly, a buried region formed by implantation can result in some implantation in a region between the buried region and the surface through which the implant was performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the application. It should also be understood that, wherever used, the terms "over", "under", "between", and "on" include wholly or in part by other intervening regions that are present.

[0068] Currently, there are two main types of trench gate structures in the industry: single trench structure and double trench structure. Figure 1 As shown in Figure (1), the structure has both source trenches and gate trenches, and a p-type shielding region is added to the bottom of the source trench; the single trench structure is as follows Figure 1 As shown in Figure (2), the gate has an asymmetric shielding area, and the gate trench is embedded in the shielding area at the bottom. Although the above two classic trench gate structures can solve the problem of excessively high gate oxide electric field at the bottom of the trench, they both have obvious limitations.

[0069] Specifically, when the single trench structure optimizes the electric field through the asymmetric shielding area, it needs to sacrifice about half of the number of channels, which directly leads to an increase in on-resistance; the double trench structure needs to increase the design intercept, which reduces the channel density in the overall dimension of the chip. At the same time, the gate-source capacitance C gs They are generally small, and the speed of opening and closing is extremely fast, which can easily produce oscillation and other characteristics that are unfavorable to the application, limiting the optimization of dynamic performance.

[0070] Based on this, the present application provides a power device. For ease of understanding, in an embodiment of the present application, the epitaxial layer may include a first surface located on the front side, and a back side opposite to the front side, i.e., a second surface. Ignoring the flatness of the first and second surfaces, the direction toward the substrate is defined to include a first direction perpendicular to the first surface of the substrate and a second direction parallel to the first surface. The first and second directions are perpendicular to each other. The first direction is defined as the Z-axis direction, and the second direction is defined as the Y-axis direction.

[0071] The power device provided by the present application is described in more detail below with reference to the accompanying drawings.

[0072] See also Figure 2 , Figure 2 A partial cross-sectional view of a power device provided in this application, such as Figure 2 As shown, the power device includes: a substrate 10 , an epitaxial layer 11 , a gate 40 , an interlayer dielectric layer 20 and a metal layer 30 .

[0073] The substrate 10 includes an initial substrate 1 and a buffer layer 2, with an epitaxial layer 11 located on top of the buffer layer 2. The epitaxial layer 11 includes a source region 111, a base region 112, and a shield region 113 arranged sequentially along the OZ direction. In the following embodiments, the source region 111, substrate 10, and epitaxial layer 11 are all N-type, while the base region 112 and shield region 113 are P-type. It will be appreciated that when the substrate 10 is P-type, the "P" and "N" in the above structure can be interchanged.

[0074] The power device includes a plurality of gates 40 spaced apart along the OY direction. The extension 21 of the interlayer dielectric layer 20 extends toward the bottom of the gate 40 along the OZ direction. The gate conductive layer 41 of the gate 40 is distributed on both sides of the extension 21 to form a split gate, thereby reducing the gate-drain capacitance C gd At the same time, the bottom of the gate 40 is surrounded by the shielding area 113, forming a PN junction with the epitaxial layer 11, attracting part of the electric lines, redistributing the electric lines in the epitaxial layer 11 to a certain extent, and alleviating the problem of electric field concentration at the bottom of the gate 40.

[0075] The gate 40 also includes a first source 31 extending into the gate 40 through the top surface of the extension portion 21, and a second source 32 extending into the base region 112; the width (dimension along the OY direction) and depth (dimension along the OZ direction) of the first source 31 are related to the gate-source capacitance C of the power device. gs ;

[0076] Specifically, the first source 31 extends into the gate 40, and the depth of the first source 31 is equal to the gate-source capacitance C of the power device. gs There is a positive correlation, that is, the deeper the depth, the larger the area facing the gate and source ends, and the gate-source capacitance C gs The larger the width of the first source 31 is, the greater the gate-source capacitance C of the power device gs is negatively correlated, that is, the smaller the width, the greater the thickness of the extension 21, and the gate-source capacitance C gs From the device's perspective, C gs / C gd It is greatly increased and has adjustment space, so that the device can optimize the switching speed, reduce oscillation, and optimize the switching loss during high-speed switching, thereby achieving the best device dynamic performance.

[0077] Please continue reading Figure 2 In some embodiments, the gate 40 is divided into a two-stage structure of a first stage and a second stage arranged along the OZ direction.

[0078] The first stage, wherein the bottom surface of the first stage is flush with the gate conductive layer 41;

[0079] The second level, wherein the top surface of the second level is lower than the bottom surface of the base region 112 and is partially embedded in the shielding region 113;

[0080] In the above embodiment, the second level is formed by secondary etching and has a width smaller than the first level. The gate conductive layer 41 is located in the first level, the bottom of the second level is embedded in the shielding area 113, and the extension portion 21 extends into the second level, and the bottom surface is surrounded by the gate oxide layer 42 of the second level. The specific structure is as follows: Figure 2 As shown, the thickness of the gate oxide layer at the bottom of the gate 40 is effectively increased, thereby improving the voltage resistance of the corner area at the bottom of the trench.

[0081] See also Figure 3-Figure 14On the other hand, the present application provides a method for preparing a power device, for preparing Figure 2 The power device shown in the method includes: steps S20 to S40.

[0082] Step S20 : ​​providing a substrate 10 , with an epitaxial layer 11 formed on a first surface 10 a of the substrate 10 ; the epitaxial layer 11 includes a source region 111 , a base region 112 , and a shield region 113 arranged along an OZ direction through a top surface.

[0083] Step S40: After forming a plurality of gates 40 spaced apart along the OY direction on the epitaxial layer 11 and penetrating the source region 111 and the base region 112 along the OZ direction and partially embedded in the shield region 113, a stacked interlayer dielectric layer 20 and a metal layer 30 are formed on the top surface of the epitaxial layer 11;

[0084] The gate 40 includes a gate conductive layer 41 and a gate oxide layer 42 arranged along the OZ direction;

[0085] The interlayer dielectric layer 20 includes an extension portion 21 extending along the OZ direction through the gate conductive layer 41 to contact the gate oxide layer 42;

[0086] The metal layer 30 includes: a first source electrode 31 extending from the top surface of the extension portion 21 to the gate electrode 40; the width and depth of the first source electrode 31 are related to the gate-source capacitance C of the power device. gs .

[0087] It should be understood that although Figure 3 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 3 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0088] Next, combine Figures 4 to 15 Describe an exemplary method of a power device according to the present application, Figures 3 to 15 It is a step-by-step cross-sectional view illustrating an exemplary method of manufacturing a power device according to the present application.

[0089] See also Figure 4-Figure 8 , step S20, further comprising:

[0090] Step S202: Using epitaxial process, a buffer layer 2 and an epitaxial layer 11 are sequentially formed on the top surface of the initial substrate 1. The buffer layer 2 and the initial substrate 1 are used to form a substrate 10. The specific structure is as follows: Figure 4 shown.

[0091] As an example, as mentioned above, the doping types of the epitaxial layer 11 , the buffer layer 2 and the initial substrate 1 are low-concentration N-type doping, medium-concentration N-type doping and high-concentration N-type doping, respectively.

[0092] Step S204: sequentially implanting a P-type base region 112 and a high-concentration N-type doped source region 111 on the epitaxial layer 11. The specific structure is as follows: Figure 5 shown.

[0093] Illustratively, the source region 111 has a depth ranging from 0.15 μm to 0.25 μm, such as 0.15 μm, 0.2 μm, or 0.25 μm.

[0094] Illustratively, the depth of the base region 112 ranges from 0.9 μm to 1.1 μm, such as 0.9 μm, 1 μm, or 1.1 μm.

[0095] In this embodiment, the depth of the base region 112 is 1 μm, and the depth of the source region 111 is 0.2 μm.

[0096] Step S206: After etching the first-level trench 501 in the epitaxial layer 11, a sacrificial layer 401 is formed in the first-level trench 501 and etched back to be flush with the top surface of the epitaxial layer 11. The specific structure is as follows: Figure 6a and Figure 6b shown.

[0097] By way of example, the material of the sacrificial layer 401 includes, but is not limited to, polysilicon.

[0098] For example, the depth of the primary trench 501 ranges from 1.1 μm to 1.3 μm, such as 1.1 μm, 1.2 μm, or 1.3 μm, and the width ranges from 2.5 μm to 3.5 μm, such as 2.5 μm, 3 μm, or 3.5 μm.

[0099] In this embodiment, the depth of the primary trench 501 is 1.2 μm.

[0100] Step S208: Etching the sacrificial layer 401 to form a secondary trench 502 that penetrates the sacrificial layer 401 along the OZ direction and extends to the epitaxial layer 11. The specific structure is as follows: Figure 7 shown.

[0101] In the above embodiment, the sacrificial layer 401 can be used as a mask layer for etching the secondary trench structure and a barrier layer for implantation in the shielding region, thereby improving process integration.

[0102] For example, the depth of the secondary trench 502 ranges from 1.4 μm to 1.6 μm, such as 1.4 μm, 1.5 μm or 1.6 μm, and the width ranges from 0.5 μm to 1.5 μm, such as 0.5 μm, 1 μm or 1.5 μm.

[0103] Step S210: perform ion implantation on the epitaxial layer 11 at the bottom of the secondary trench 502 to form a high-concentration P-type doped shielding region 113. The specific structure is as follows: Figure 8 shown.

[0104] See also Figures 9-15 In some embodiments, step S40 further includes:

[0105] Step S402: After removing the sacrificial layer 401, the epitaxial layer 11 is subjected to high temperature annealing to activate the impurities. The annealing temperature is 1650°C-1700°C. The specific structure is as follows: Figure 9 shown.

[0106] Step S404: using a gate oxide process, a gate oxide layer 42 is formed in the primary trench 501, and then backfilled to form a conductive material layer 411. Specifically, the initial gate 402 is as follows: Figure 10 Of course, in some embodiments, a sacrificial oxide layer (not shown) covering the inner surface of the multi-level trench structure (the primary trench 501 and the secondary trench 502 ) may be formed before the gate oxide growth is formally performed to generate a higher quality gate oxide layer.

[0107] By way of example, the material of the gate conductive layer 41 includes but is not limited to polysilicon.

[0108] For example, the thickness of the gate oxide layer 42 ranges from 45 nm to 55 nm, such as 45 nm, 47 nm, 50 nm, 53 nm, or 55 nm. In this embodiment, the thickness of the gate oxide layer 42 is 50 nm.

[0109] Step S406: Based on the same mask as the secondary trench 502, a first groove 503 extending along the OZ direction is formed in the gate conductive layer 41. Since the etching has the material selection characteristic, the etching will automatically stop on the gate oxide layer 42. The specific structure is as follows: Figure 11 shown.

[0110] Step S408: Using a deposition process, an interlayer dielectric layer 20 is formed in the first groove 503 and on the top surface of the epitaxial layer 11, and a reflow process or a chemical mechanical planarization process is used to make the top surface flat. The specific structure is as follows: Figure 12 shown.

[0111] For example, the material of the interlayer dielectric layer 20 includes, but is not limited to, a material with a high-k dielectric constant, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), or strontium titanium oxide (SrTiO3).

[0112] Step S410: Etching the interlayer dielectric layer 20 to form contact holes (second grooves 601 and third grooves 602) arranged alternately along the OY direction; the third groove 602 extends to the base region 112 along the OZ direction. The specific structure is as follows: Figure 13 shown.

[0113] Step S412: After making ohmic contacts on the power device structure obtained in step S410, a metal layer 30 is formed to fill the second groove and the third groove and cover the top surface of the interlayer dielectric layer 20. The specific structure is as follows: Figure 14 As shown; wherein, the metal layer 30 in the second groove is used to form a first source 31, and the metal layer 30 in the third groove is used to form a second source 32.

[0114] It should be understood that Figure 14 The illustration of the heavily doped P-type region forming an ohmic contact with the epitaxial layer 11 is omitted, which should not affect the normal understanding of those skilled in the art. In addition, after step S40, the power device structure prepared in step S412 is subjected to a backside thinning process and backside metallization. The specific structure is as follows Figure 15 As shown, since it is not the focus of the solution of this application, it will not be described in detail here.

[0115] In some embodiments, the present application also provides an electronic device, comprising a power device as described in any of the above embodiments; or comprising a power device prepared by the preparation method as described in any of the above embodiments.

[0116] Since the electronic device of the above embodiment and the power device and its preparation method provided by the present invention are based on the same inventive concept, the electronic device using this power device has all the advantages of the power device provided by the present invention, which will not be described in detail here.

[0117] In the above embodiments, the unexpected technical effects of the present application are:

[0118] Compared with trench gate transistors in other technologies, the power device provided in this application has a two-level structure (first level and second level), and cooperates with the shielding area at the bottom as an electric field shielding layer during reverse bias, ensuring that the channel density is basically not damaged, while protecting the bottom of the trench and shielding the high electric field, so that the gate oxide reliability of the device is significantly enhanced and the requirements for the gate oxide process are reduced.

[0119] At the same time, by designing the interlayer dielectric layer to split the gate, the area facing the gate and drain terminals is reduced, effectively reducing the gate-drain capacitance C of the device. gd , and insert a metal layer between the two gate conductive layers as the first source. By adjusting the depth of the first source inserted into the gate and the thickness in the extension, an adjustable gate-source capacitance C can be obtained. gs , thus obtaining C that meets application requirements gs / C gd , better adapt to the needs of various application scenarios.

[0120] In addition, the preparation method provided in this application has a process that is highly compatible with existing mainstream process platforms, has excellent process feasibility, and has outstanding engineering practical value.

[0121] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0122] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A power device, characterized in that: The method comprises: a substrate, wherein a first surface of the substrate comprises an epitaxial layer; the epitaxial layer comprises a source region, a base region, and a shielding region arranged along a first direction toward the substrate via a top surface; a plurality of gates, spaced apart along a second direction parallel to the first surface, penetrating the source region and the base region along the first direction, and partially embedded in the shielding region; the gates comprising a gate conductive layer and a gate oxide layer arranged along the first direction; an interlayer dielectric layer, located on a top surface of the epitaxial layer, comprising an extension portion penetrating the gate conductive layer along the first direction and contacting the gate oxide layer; A metal layer, located on the top surface of the interlayer dielectric layer, includes: a first source extending into the gate through the top surface of the extension portion; the width and depth of the first source are associated with the gate-source capacitance of the power device; wherein the width is used to characterize the dimension along the second direction; and the depth is used to characterize the dimension along the first direction.

2. The power device according to claim 1, wherein: The gate includes: a first stage, wherein a bottom surface of the first stage is flush with the gate conductive layer; a second stage, wherein a top surface of the second stage is lower than a bottom surface of the base region and is partially embedded in the shielding region; The bottom surface of the extension portion is located within the top surface of the second-level gate oxide layer; The width of the second stage is smaller than the width of the first stage.

3. The power device according to claim 2, characterized in that The width of the shielding area is greater than the width of the second level and smaller than the width of the first level; The depth of the first source electrode is no greater than the depth of the gate conductive layer.

4. The power device according to claim 1, wherein: The width and depth of the first source electrode are associated with the gate-source capacitance of the power device, including: The depth of the first source electrode is positively correlated with the gate-source capacitance of the power device; The width of the first source electrode is negatively correlated with the gate-source capacitance of the power device.

5. The power device according to claim 3, characterized in that: The gate and the interlayer dielectric layer are prepared at the same time in the same process step.

6. The power device according to any one of claims 2 to 5, characterized in that: The metal layer further includes a second source electrode extending along the first direction through the top surface of the interlayer dielectric layer to a portion embedded in the base region.

7. A method for preparing a power device, characterized in that: For preparing the power device according to any one of claims 1 to 6, the method for preparing the power device comprises: Providing a substrate, wherein an epitaxial layer is formed on a first surface of the substrate; the epitaxial layer includes a source region, a base region, and a shield region arranged along a first direction toward the substrate via a top surface; After forming a plurality of gates in the epitaxial layer that are spaced apart along a second direction parallel to the first surface, penetrate the source region and the base region along the first direction, and are partially embedded in the shielding region, a stacked interlayer dielectric layer and a metal layer are formed on the top surface of the epitaxial layer; Wherein, the gate includes a gate conductive layer and a gate oxide layer arranged along the first direction; The interlayer dielectric layer includes an extension portion extending along the first direction through the gate conductive layer to contact the gate oxide layer; The metal layer includes: a first source extending into the gate through the top surface of the extension portion; the width and depth of the first source are associated with the gate-source capacitance of the power device; the width is used to characterize the size along the second direction; and the depth is used to characterize the size along the first direction.

8. The preparation method according to claim 7, characterized in that Forming the shielding area includes: After forming a primary trench in the epitaxial layer, forming a sacrificial layer in the primary trench; removing a portion of the sacrificial layer to form a secondary trench penetrating the sacrificial layer along the first direction and extending to the epitaxial layer; the width of the secondary trench is smaller than the width of the primary trench; An ion implantation process is performed on the epitaxial layer at the bottom of the secondary trench to form the shielding region.

9. The preparation method according to claim 8, characterized in that Forming the gate, the interlayer dielectric layer, and the metal layer includes: After removing the sacrificial layer, forming an initial gate in the first-level trench; Based on the same photomask as the secondary trench, forming a first groove in the initial gate; forming the interlayer dielectric layer in the first groove and on the top surface of the epitaxial layer; forming a second groove and a third groove alternately arranged along the second direction in the interlayer dielectric layer; the third groove extends along the first direction to the base region; A metal layer is formed to fill the second groove, the third groove, and cover the top surface of the interlayer dielectric layer; wherein the metal layer in the second groove is used to form a first source electrode, and the metal layer in the third groove is used to form a second source electrode.

10. An electronic device, characterized in that: include: The power device according to any one of claims 1 to 6; or A power device prepared by the preparation method according to any one of claims 7 to 9.

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