SGPIO unified coding method, system and device

Abstract

The invention discloses an SGPIO (Serial General Purpose Input / Output) unified coding method, system and device, and the method is characterized in that the method comprises the steps: powering on a server host, and completing the initialization of a CPLD (Complex Programmable Logic Device) and an SATA / SAS controller; a register and a counter are established, and an SGPIO input Data buffer register, an output Data buffer register and a Clock counter of the SGPIO are established in the CPLD; data frame bit length calculation: the CPLD waits for receiving the SGPIO signal, and calculates the bit length of the input data frame after receiving the input SGPIO signal; whether the bit length of a data frame is equal to 12 bits or not is judged, if the length of the data frame is 12 bits, Clock, Load and Data signals of input SGPIO are directly transmitted to an output IO pin in a transparent mode, and the SGPIO signals of an output interface are completely equal to the SGPIO signals input by the CPLD; and if the data frame length is greater than 12 bits, the signal is processed, so that the SGPIO data of the output port is unified into 12-bit data. By unifying the SGPIO data of the output port into 12 bits, the problem that the bit lengths of SGPIO signals of different devices or interfaces are inconsistent is effectively solved, and the compatibility and standardization degree of the system are remarkably improved.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of servers and storage arrays, and relates to a method, system and device for unified encoding of SGPIO. BACKGROUND

[0002] In the current booming server industry, the demand for storage capacity of servers is increasing, and the number of hard disks is also increasing. In order to effectively manage and centrally place a large number of hard disks, servers generally use backplane design to centrally arrange hard disks on the front panel or other specific positions, and use RAID technology to improve the reliability and performance of data storage. At the same time, in order to enable maintenance personnel to quickly grasp the status of the hard disks, indicator lights are usually provided on the hard disk panel to visually display different states of the hard disks such as Present (in place), Active (active), rebuild (rebuild), Fault (fault) and the like through the on / off, blinking and other states of the indicator lights.

[0003] In the process of implementing the hard disk status indicator light display, SGPIO (Serial General Purpose Input / Output) communication bus is widely used as a common technical means. SGPIO complies with SFF-8485 specification, and its basic principle is to use SGPIO signals provided by SATA controllers, HBA / Raid cards or SAS expander chips. After these signals are parsed by CPLD (Complex Programmable Logic Device) on the backplane, corresponding status indication signals are output to drive the hard disk status indicator light to work. Under normal circumstances, every 3-bit data bit is used to represent the status identifier of 1 hard disk, for example, 12 bits can represent the status identifier of 4 hard disks, and 24 bits can represent the status identifier of 8 hard disks.

[0004] However, in actual application, due to differences in design schemes of SATA / SAS controllers or SAS Expander chips of different manufacturers, the length of SGPIO signal output encoding data presents the characteristics of diversification. Taking SATA controllers and HBA / Raid cards as examples, a single wide port provides an extension of 4 hard disks by default, but the length of SGPIO signal encoding data is commonly 12 bits or 24 bits. More complex is that in some cases, the SGPIO signals in two wide ports may be completely consistent, and each contains the status information of the hard disks in the other port, which undoubtedly increases the difficulty of signal parsing and processing. As for SAS Expander chips, the default length of SGPIO is closely related to the number of PHY ports of the chip. For example, when the number of ports is 36, although a single wide port only provides data signals of 4 hard disks, the default length of SGPIO data bits is as high as 108 bits.

[0005] In addition, in some specific application scenarios, the board storage device requirement must occupy the front 2 ports of the controller, and the signals in the remaining ports still need to be connected to the backplane for hard disk expansion, further exacerbating the complexity of SGPIO signal processing.

[0006] In the face of the above complex and variable situations, the existing backplane design usually adopts the way of equipping multiple different versions of firmware (FW) or reserving jumpers or DIP switches on the backplane to select the corresponding configuration according to different input signals when dealing with different input signals. Although these measures are relatively simple and easy to implement from the perspective of developers, they have brought many problems in the actual production and product maintenance process. On the one hand, there are multiple different versions of backplane firmware, and additional control measures are needed to ensure that different versions of firmware can be accurately applied to the corresponding products in the production process, which undoubtedly increases the complexity and cost of production management. On the other hand, due to the same hardware but different firmware, inventory management is difficult, and inventory costs rise. More seriously, in the after-sales maintenance process, if the firmware version of the spare parts does not match the actual demand, it will cause new problems, prolong the fault repair time, and affect customer satisfaction. At the same time, different DIP switches are used to configure the same backplane, and when there are multiple different configurations of the backplane, it will also bring great inconvenience to production and after-sales, increase the risk of operation errors, and reduce work efficiency.

[0007] In summary, the existing server backplane hard disk status indicator SGPIO signal processing method has many drawbacks when dealing with diversified input signals, which seriously affects production efficiency, product maintenance quality, and cost control. Therefore, there is an urgent need for a new technical solution to solve these problems to improve the universality, reliability, and production and maintenance efficiency of server backplane design. SUMMARY

[0008] The purpose of the present application is to solve the problem of the existing server backplane hard disk status indicator SGPIO signal processing method when dealing with diversified input signals, and to provide a SGPIO unified coding method, system and device.

[0009] To achieve the above purpose, the technical scheme is adopted as follows:

[0010] A SGPIO unified coding method, comprising the following steps:

[0011] The server host is powered on, and the CPLD and SATA / SAS controller initialization is completed;

[0012] The register is established with the counter, the CPLD establishes the SGPIO input Data buffer register, the output Data buffer register and the SGPIO Clock counter inside;

[0013] The data frame bit length is calculated, the CPLD waits to receive the SGPIO signal, and after receiving the input SGPIO signal, the bit length of the input data frame is calculated;

[0014] It is judged whether the bit length of the data frame is equal to 12 bits, if the length of the received data frame is 12 bits, the Clock, Load and Data signals of the input SGPIO are directly transmitted to the output IO pin, so that the SGPIO signals of the output interface are completely equal to the SGPIO signals input by the CPLD;

[0015] If the length of the data frame is greater than 12 bits, the signals are processed, and the SGPIO data of the output port is unified to 12-bit data.

[0016] The server host is powered on, and the CPLD and the SATA / SAS controller are initialized, specifically:

[0017] The system is initialized, after the server host is powered on, the CPLD and the SATA / SAS controller complete initialization and start working; wherein, the CPLD performs pin IO, power-on control initialization according to the conventional general server, and the SATA / SAS controller performs power-on, completes reset and FW ready work;

[0018] The signal is initialized, and all signals of the output SGPIO are initialized to high level by the CPLD.

[0019] When the data frame bit length is calculated, the CPLD waits to receive the SGPIO signal, and after receiving the input SGPIO signal, the bit length of the input data frame is calculated, the number of SGPIO clocks input in the period is counted based on the period length of the input SGPIO Load signal, specifically through the following steps:

[0020] Initialization, the CPLD enters a waiting state, continuously monitors the SGPIO_Load signal, initializes the counter to 0, and sets a flag to indicate that the data frame start has not been detected;

[0021] Frame start detection, when the rising edge of the SGPIO_Load signal is detected, the data frame start is marked, and the current time point or the Clock counter value is recorded as a reference;

[0022] Period length measurement, monitor the edge change of SGPIO_Clock signal during SGPIO_Load signal keeping high, count the rising edge or falling edge of each Clock signal according to the configuration, and continue counting until SGPIO_Load signal becomes low;

[0023] Bit length calculation, stop Clock counter when SGPIO_Load signal becomes low, and take the recorded Clock count as the bit length of input data frame;

[0024] Result output, store the calculated bit length in register, and use it to judge whether the input data frame is 12 bit.

[0025] When detecting that SGPIO_Load signal appears abnormal during counting, perform at least one of the following operations: set minimum / maximum bit length limit, set timeout mechanism to restart counting, or perform frame synchronization processing on continuous transmission mode.

[0026] If the data frame length is greater than 12 bits, process the signal to make the SGPIO data of the output port 12-bit data, and the specific steps are as follows:

[0027] Clock signal processing, process the output SGPIO clock, the frequency of Clock is configured according to requirements, and it is recommended to synchronize the input SGPIO clock, and output the Load signal according to 12 Clock periods; the frequency of SGPIO clock on the output port can be adjusted according to actual situation, or can follow the input SGPIO clock of CPLD;

[0028] Data temporary storage, temporarily store the input SGPIO signal Data in the input Data buffer register when the input SGPIO signal jumps to high;

[0029] Data grabbing, select the starting position of data according to the disk serial number corresponding to the output interface, grab the continuous 12-bit data from the input Data buffer register and store it into the output Data buffer register;

[0030] Data output, output the data of the output Data buffer register from the output SGPIO Data signal according to the SGPIO encoding requirement;

[0031] Data synchronization update, cyclically execute the data temporary storage-data output steps of data frame processing, synchronously update data, and ensure that the data in the input SGPIO is timely forwarded to the output SGPIO, so that the SGPIO data of the output port is unified as 12-bit data.

[0032] The data is captured, and the port used in the server supports four disks by default, and a set of SGPIO signals is provided in each port; when selecting the starting position of the data according to the disk serial number corresponding to the output interface, if the interface starts from the Nth disk, the starting position of the data is selected from bit (3x (N-1)), wherein N is an integer greater than or equal to 1;

[0033] When the starting position is not from the disk serial number that is a multiple of 4, the CPLD offsets the data according to the offset of the disk serial number accessed to the backplane, and re-encodes the data in a group of four disks, that is, 12 bits, to unify the data format.

[0034] An SGPIO unified encoding system, comprising the following modules:

[0035] A system initialization module, the server host is powered on, and the CPLD and the SATA / SAS controller are initialized;

[0036] A register and counter establishment module, the CPLD internally establishes an SGPIO input Data buffer register, an output Data buffer register, and an SGPIO Clock counter;

[0037] A data frame bit length calculation module, the CPLD waits to receive an SGPIO signal, and after receiving the input SGPIO signal, calculates the bit length of the input data frame;

[0038] A data frame bit length judgment and processing module, judges whether the bit length of the data frame is equal to 12 bits, if the received data frame length is 12 bits, the Clock, Load and Data signals of the input SGPIO are directly transmitted to the output IO pin, so that the SGPIO signals of the output interface are completely equivalent to the input SGPIO signals of the CPLD; if the data frame length is greater than 12 bits, the signals are processed, so that the SGPIO data of the output port is unified to 12-bit data.

[0039] The data frame bit length judgment and processing module comprises a data frame greater than 12-bit processing submodule, specifically comprising:

[0040] A Clock signal processing unit: for processing the output SGPIO Clock signal, the frequency is configured according to the requirement, the recommended synchronous input SGPIO Clock signal is output according to 12 Clock periods, and the SGPIO Clock frequency on the output port can be independently adjusted or followed by the input SGPIO Clock signal of the CPLD;

[0041] Data temporary storage unit: used for temporarily storing the input SGPIO_Data signal data into the input Data buffer register when the input SGPIO_Load signal jumps to high level;

[0042] Data grabbing unit: used for selecting the starting position of data according to the corresponding disk serial number of the output interface, grabbing the continuous 12-bit data from the input Data buffer register and storing into the output Data buffer register;

[0043] Data output unit: used for outputting the 12-bit data in the output Data buffer register through the output SGPIO Data signal line according to the SGPIO coding requirement;

[0044] Data synchronous updating unit: used for cyclically executing the data temporary storage, data grabbing and data output steps, realizing the real-time synchronous updating of data, ensuring that the data in the input SGPIO signal can be timely and accurately forwarded to the output SGPIO signal, and maintaining the SGPIO data format of the output port to be unified as 12 bits.

[0045] A kind of SGPIO unified coding device, the SGPIO of SATA / SAS controller is connected with CPLD, SATA / SAS high-speed signal is connected according to grouping and storage expansion interface, for the access of server backplane expansion hard disk, CPLD output SGPIO signal and storage expansion interface are connected;In normal system operation, SATA / SAS controller starts to work, and its SGPIO is outputted according to the data format of original design, wherein the data format of original design specifically refers to the data length defined by controller chip, and the data length is associated with the number of hard disks supported by the controller itself;CPLD is recoded according to the input signal data and the storage expansion interface port number in board, ensures that the hard disk status information contained in SGPIO and hard disk position correspond, guarantees the data format of SGPIO signal in hard disk backplane.

[0046] Compared with the prior art, the present application has the following beneficial effects:

[0047] The method for unified coding of SGPIO in the application effectively solves the problem of inconsistent SGPIO signal bit length of different devices or interfaces, significantly improves the system compatibility and standardization degree, ensures the accuracy and reliability of data transmission by accurately calculating the input data frame bit length and processing 12-bit direct transmission and more than 12-bit unified coding, enhances the flexibility and robustness of the system by supporting flexible configuration of output SGPIO Clock frequency, setting of abnormal processing mechanism and other measures, realizes real-time processing and timely forwarding of data through efficient processes such as data storage, grabbing, outputting and synchronous updating, and improves the system response speed and data processing efficiency, and in addition, the method steps are clear, the logic is clear, easy to implement and maintain, and through the selection of the data starting position based on the disk serial number, independent management and monitoring of multiple disks are supported, providing an efficient, reliable and flexible technical solution for the management and monitoring of server storage devices. BRIEF DESCRIPTION OF DRAWINGS

[0048] In order to more clearly illustrate the technical solutions of the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiments, and it should be understood that the following drawings only show some embodiments of the application, and therefore should not be regarded as a limitation on the scope, and for those skilled in the art, other related drawings can also be obtained without creative labor.

[0049] Figure 1 The figure is a schematic diagram of the hardware structure of the application. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solutions and advantages of the embodiments of the application more clear, the following will combine the drawings in the embodiments of the application to clearly and completely describe the technical solutions in the embodiments of the application, and obviously, the described embodiments are part of the embodiments of the application, not all the embodiments. The components of the embodiments of the application described and shown in the drawings here can be arranged and designed in various different configurations.

[0051] Therefore, the following detailed description of the embodiments of the application provided in the drawings is not intended to limit the scope of the claimed application, but only represents selected embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the application.

[0052] It should be noted that: similar numbers and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.

[0053] The application will be described in further detail below with reference to the drawings:

[0054] Referring to Figure 1 It is a schematic diagram of the hardware structure of the application, the SGPIO of the SATA / SAS controller is connected with the CPLD, the SATA / SAS high-speed signals are connected with the storage expansion interface according to the grouping, and the interface is used for the access of the server backboard expansion hard disk, the SGPIO signal of the CPLD is connected with the storage expansion interface; in the normal working state of the system, the SATA / SAS controller starts to work, the SGPIO outputs data according to the original design of the data format, the CPLD re-encodes according to the input signal data and the storage expansion interface port number in the board, ensures that the hard disk state information contained in the SGPIO corresponds to the hard disk position, and ensures that the data format in the SGPIO signal of the hard disk backboard is unified.

[0055] The SATA / SAS controller can also be a SAS expander and the like disk expansion chip, and the storage expansion interface is SFF-8643 or other forms of interface.

[0056] The SGPIO unified coding method in the application comprises the following steps:

[0057] The server host is powered on, and the CPLD and the SATA / SAS controller are initialized.

[0058] System initialization, after the server host is powered on, the CPLD and the SATA / SAS controller complete initialization and start to work; wherein the CPLD initializes the pin IO, power-on control according to the conventional general server, and the SATA / SAS controller works according to the power-on, completes reset, and is ready for FW;

[0059] Signal initialization, the CPLD initializes all signals of the output SGPIO to high level.

[0060] Register and counter establishment, the CPLD internally establishes the SGPIO input Data buffer register, the output Databuffer register and the Clock counter of the SGPIO.

[0061] Data frame bit length calculation, the CPLD waits to receive the SGPIO signal, and calculates the bit length of the input data frame after receiving the input SGPIO signal.

[0062] When the bit length of the input data frame is calculated, the number of SGPIO clocks input in the period is counted based on the period length of the input SGPIO Load signal, and the counting is specifically performed through the following steps:

[0063] Initialization, CPLD enters a waiting state, continuously monitors the SGPIO_Load signal, initializes the counter to 0, and sets a flag indicating that the start of the data frame has not been detected;

[0064] Frame start detection, when the rising edge of the SGPIO_Load signal is detected, the start of the data frame is marked, and the current time point or Clock counter value is recorded as a reference;

[0065] Period length measurement, during the period when the SGPIO_Load signal remains high, the edge changes of the SGPIO_Clock signal are monitored, the rising edge or falling edge of each Clock signal is counted according to the configuration, and the counting is continued until the SGPIO_Load signal becomes low;

[0066] Bit length calculation, when the SGPIO_Load signal becomes low, the Clock counter is stopped, and the recorded Clock count is taken as the bit length of the input data frame; to ensure the accuracy of the data frame length count, 2-3 consecutive data frames can be counted to confirm the bit length detection.

[0067] Result output, the calculated bit length is stored in the register, which is used to determine whether the input data frame is 12 bits.

[0068] Determine whether the bit length of the data frame is equal to 12 bits, if the length of the received data frame is 12 bits, the Clock, Load, and Data signals of the input SGPIO are directly transmitted to the output IO pin, so that the SGPIO signals of the output interface are completely equivalent to the SGPIO signals input by the CPLD; if the data frame length is greater than 12 bits, the signals are processed according to the corresponding relationship of the SATA / SAS physical signal channel of the output interface, so that the SGPIO data of the output port is unified to 12-bit data.

[0069] If the data frame length is greater than 12 bits, the signals are processed to unify the SGPIO data of the output port to 12-bit data, and the specific steps are as follows:

[0070] Clock signal processing, the output SGPIO clock is processed, the frequency of Clock is configured according to requirements, and the recommended synchronous input SGPIO clock is defined according to the output Load signal of 12 Clock periods; the frequency of the SGPIO clock on the output port can be adjusted according to actual conditions, or it can follow the SGPIO clock input by the CPLD.

[0071] Data temporary storage, according to the low level of SGPIO Load signal, the data is output to the data temporary storage register at each SGPIO Clock falling edge, and the input SGPIO signal Data is temporarily stored in the input Data buffer register when the input SGPIO Load signal jumps to high level.

[0072] Data grabbing, 4 disks are supported in the port used in the server by default, and a set of SGPIO signals are provided in each port; the starting position of data is selected according to the disk serial number corresponding to the output interface, and the continuous 12-bit data in the input Data buffer register is grabbed and stored in the output Data buffer register; when the starting position of data is selected according to the disk serial number corresponding to the output interface, if the interface starts from the Nth disk, the starting position of data is selected from bit (3*(N-1)), wherein N is an integer greater than or equal to 1.

[0073] When the starting position is not from the disk serial number which is a multiple of 4, the CPLD offsets the data according to the offset of the disk serial number accessed to the backboard, and re-encodes the data in a group of 4 disks, that is, 12 bits, to unify the data format.

[0074] Data output, the data in the output Data buffer register is output from the output SGPIO Data signal according to the SGPIO encoding requirement.

[0075] Data synchronization update, the data temporary storage-data output step of the data frame processing is executed cyclically, the data is updated synchronously, the data in the input SGPIO is forwarded to the output SGPIO in time, and the SGPIO data of the output port is unified to 12-bit data.

[0076] The SGPIO unified encoding system in the application comprises the following modules:

[0077] System initialization module, the server host is powered on, and the CPLD and the SATA / SAS controller are initialized.

[0078] Register and counter establishment module, the SGPIO input Data buffer register, the output Data buffer register and the SGPIO Clock counter are established in the CPLD.

[0079] Data frame bit length calculation module, the CPLD waits to receive the SGPIO signal, and the bit length of the input data frame is calculated after the input SGPIO signal is received.

[0080] The data frame bit length judgment and processing module judges whether the bit length of the data frame is equal to 12 bits. If the length of the received data frame is 12 bits, the Clock, Load and Data signals of the input SGPIO are directly transmitted to the output IO pin, so that the SGPIO signals of the output interface are completely equivalent to the SGPIO signals input by the CPLD. If the length of the data frame is greater than 12 bits, the signals are processed, so that the SGPIO data of the output port is unified as 12-bit data.

[0081] The more than 12-bit data frame processing submodule specifically comprises:

[0082] The Clock signal processing unit is used for processing the output SGPIO Clock signal. The frequency is configured according to the requirement. The recommended synchronous input SGPIO Clock signal is output according to the definition of the Load signal in 12 Clock cycles. The SGPIO Clock frequency on the output port can be independently adjusted or followed by the SGPIO Clock signal input by the CPLD.

[0083] The data temporary storage unit is used for temporarily storing the input SGPIO_Data signal data in the input Data buffer register when the input SGPIO Load signal jumps to high level.

[0084] The data grabbing unit is used for selecting the starting position of the data according to the corresponding disk serial number of the output interface, grabbing the continuous 12-bit data from the input Data buffer register and storing the data in the output Data buffer register.

[0085] The data output unit is used for outputting the 12-bit data in the output Data buffer register through the output SGPIO Data signal line according to the SGPIO coding requirement.

[0086] The data synchronization updating unit is used for cyclically executing the data temporary storage, data grabbing and data output steps, realizing the real-time synchronization updating of the data, ensuring that the data in the input SGPIO signal can be timely and accurately forwarded to the output SGPIO signal and maintaining the SGPIO data format of the output port to be unified as 12 bits.

[0087] An embodiment of the present application is a device for SGPIO unified coding, SGPIO of a SATA / SAS controller is connected with a CPLD, high-speed signals of the SATA / SAS are connected with a grouping and storage expansion interface, which is used for the access of a server backplane expansion hard disk, the CPLD output SGPIO signal is connected with the storage expansion interface; in normal system operation, the SATA / SAS controller starts to work, and its SGPIO outputs externally according to a data format originally designed, wherein the data format originally designed specifically refers to a data length defined by the controller chip, which is associated with the number of hard disks supported by the controller itself; the CPLD re-codes according to the input signal data and the storage expansion interface port number in the board, to ensure that the hard disk status information contained in the SGPIO corresponds to the hard disk position, and to ensure that the data format in the SGPIO signal of the hard disk backplane is unified.

[0088] Embodiment

[0089] The SGPIO of the SATA / SAS controller is connected with the CPLD, high-speed signals such as the SATA / SAS are connected with a grouping and storage expansion interface (SFF-8643 or other forms of interface), which is used for the access of a server backplane expansion hard disk. The CPLD output SGPIO signal is connected with the storage expansion interface. In normal system operation, the SATA / SAS controller starts to work, and the SGPIO of the SATA / SAS controller will output externally according to a data format originally designed by the manufacturer. The CPLD re-codes according to the input signal data of the SATA / SAS controller and the storage expansion interface port number in the board, to ensure that the hard disk status information contained in the SGPIO corresponds to the hard disk position. The data format in the SGPIO signal given to the hard disk backplane is unified.

[0090] The specific control process is as follows:

[0091] 1. The server host is powered on, the CPLD and the SATA / SAS controller are initialized and start to work.

[0092] The CPLD part initializes pin IO, power-on control, etc. according to a conventional general server

[0093] The SATA / SAS part performs power-on, completes reset, and is ready for FW, etc.

[0094] 2. All signals of the CPLD output SGPIO are initialized to high level.

[0095] 3. The CPLD internally establishes SGPIO input Data buffer register and output Data buffer register, and SGPIO Clock counter.

[0096] 4. The CPLD waits to receive the SGPIO signal. After receiving the input SGPIO signal, it calculates the bit length of the input data frame by counting the number of SGPIO clocks input within the period based on the period length of the input SGPIOLoad signal.

[0097] 5. The default number of conventional wide-port hard disks is 4. Therefore, if the received data frame length is 12 bits, the Clock, Load, and Data signals of the input SGPIO are directly transparently transmitted to the output IO pin. The SGPIO signal of the output interface is completely equivalent to the SGPIO signal of the CPLD input.

[0098] 6. If the data frame length is greater than 12 bits, further processing of the signal is required.

[0099] (1) For the output SGPIO clock processing, the clock frequency can be configured according to actual needs. At the same time, the load signal output is defined according to 12 clock cycles.

[0100] The SGPIO clock frequency on the output port can be adjusted according to the actual situation (for example, if the CPLD input SGPIO clock frequency is 1MHz, the output can be customized to 2MHz or 500KHz). It can also follow the CPLD input SGPIO clock.

[0101] (2) The SGPIO Load signal starts from a high-to-low level. Each falling edge of the SGPIO Clock outputs data to the data buffer register. When the input SGPIO Load signal jumps to a high level, the input SGPIO signal Data is temporarily stored in the input Data buffer register.

[0102] (3) Select the starting position of the data according to the disk serial number corresponding to the output interface (for example, if the interface starts from disk No. 4, then it starts from bit 12; if the interface starts from disk No. 16, then it starts from bit 48), and further capture continuous 12-bit data from the input data buffer register and store it in the output data buffer register.

[0103] (4) Refer to the SGPIO coding requirements to output the output Data buffer register data from the output SGPIO Data signal.

[0104] 7. Loop through steps 6, steps 2 to 4, and update the data synchronously to ensure that the data in the input SGPIO is forwarded to the output SGPIO in a timely manner.

[0105] 8. The SGPIO data of the output port is unified as 12-bit data after the above steps.

[0106] The SGPIO signal can be a group of input SGPIO signals corresponding to a group of SGPIO signal outputs, or a group of input SGPIO signals corresponding to multiple groups of SGPIO signal outputs.

[0107] The method unifies the SGPIO data of the output port as 12 bits, solves the problem of inconsistent bit lengths of SGPIO signals output by different storage controllers or expansion devices, and improves the compatibility and standardization of the system. Regardless of the bit length of the input SGPIO signal, the output can maintain a unified 12-bit format, simplifying the subsequent data processing and analysis process.

[0108] The above is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for unified SGPIO coding, characterized in that: The following steps are involved: The server host is powered on, and the CPLD and SATA / SAS controller are initialized; Registers and counters are established. The SGPIO input data buffer register, output data buffer register, and SGPIO clock counter are established inside the CPLD. Data frame bit length calculation: CPLD waits for the SGPIO signal to be received. After receiving the input SGPIO signal, it calculates the bit length of the input data frame. Determine whether the bit length of the data frame is equal to 12 bits. If the received data frame length is 12 bits, directly transparently transmit the Clock, Load, and Data signals of the input SGPIO to the output IO pin, so that the SGPIO signal of the output interface is completely equivalent to the SGPIO signal of the CPLD input; If the data frame length is greater than 12 bits, the signal is processed so that the SGPIO data of the output port is unified into 12-bit data.

2. A method for unified SGPIO coding as claimed in claim 1, characterized in that: The server host is powered on, and the CPLD and SATA / SAS controller are initialized, specifically: System initialization: After the server host is powered on, the CPLD and SATA / SAS controller complete initialization and begin working. The CPLD performs pin IO and power-on control initialization like a conventional general-purpose server, while the SATA / SAS controller performs power-on, completes reset, and becomes FW ready. Signal initialization: CPLD initializes all output SGPIO signals to high level.

3. A method for unified SGPIO coding as claimed in claim 1, characterized in that: The data frame bit length calculation is performed by the CPLD waiting to receive the SGPIO signal. After receiving the input SGPIO signal, the CPLD calculates the bit length of the input data frame by counting the number of SGPIO clocks input within the period based on the period length of the input SGPIO Load signal. Specifically, the calculation is performed by the following steps: Initialization: CPLD enters the waiting state, continuously monitors the SGPIO_Load signal, initializes the counter to 0, and sets the flag bit to indicate that the start of the data frame has not been detected; Frame start detection: When the rising edge of the SGPIO_Load signal is detected, the data frame starts and the current time point or the Clock counter value is recorded as a reference; Cycle length measurement: When the SGPIO_Load signal remains high, monitor the edge changes of the SGPIO_Clock signal. Count the rising or falling edges of each Clock signal according to the configuration, and continue counting until the SGPIO_Load signal becomes low. Bit length calculation, when the SGPIO_Load signal becomes low, the Clock counter is stopped and the recorded Clock count is used as the bit length of the input data frame; The result is output and the calculated bit length is stored in a register to determine whether the input data frame is 12 bits.

4. A method for unified SGPIO coding as claimed in claim 3, characterized in that: When an abnormality is detected in the SGPIO_Load signal during counting, at least one of the following operations is performed: setting minimum / maximum bit length limits, setting a timeout mechanism to restart counting, or performing frame synchronization processing for continuous transmission mode.

5. A method for unified SGPIO coding as claimed in claim 1, characterized in that: If the data frame length is greater than 12 bits, the signal is processed to unify the SGPIO data of the output port into 12-bit data. The specific steps are: Clock signal processing: Process the output SGPIO clock. The clock frequency is configured according to requirements. It is recommended to synchronize the input SGPIO clock and define the load signal output according to 12 clock cycles. The clock frequency of the SGPIO on the output port can be adjusted according to actual conditions or can follow the SGPIO clock input by the CPLD. Data temporary storage: when the input SGPIO signal jumps to a high level, the input SGPIO signal Data is temporarily stored in the input Data buffer register; Data capture: select the starting position of the data according to the disk serial number corresponding to the output interface, capture continuous 12-bit data from the input data buffer register and store it in the output data buffer register; For data output, refer to the SGPIO coding requirements to output the output Data buffer register data from the output SGPIO Data signal; The data is updated synchronously, and the data storage-data output steps of the data frame processing are executed cyclically to update the data synchronously, ensuring that the data in the input SGPIO is forwarded to the output SGPIO in time, so that the SGPIO data of the output port is unified into 12-bit data.

6. A method for unified SGPIO coding as claimed in claim 5, characterized in that: When capturing data, the ports used in the server support four disks by default, and each port provides a set of SGPIO signals. When selecting the starting position of the data based on the disk serial number corresponding to the output interface, if the interface starts from disk number N, the data starting position is selected starting from bit (3×(N-1)), where N is an integer greater than or equal to 1. When the starting position does not start from a disk serial number that is a multiple of 4, the CPLD offsets the data according to the offset of the disk serial number connected to the backplane and re-encodes it in groups of 4 disks, that is, 12 bits, to unify the data format.

7. A SGPIO unified coding system, characterized in that: Includes the following modules: System initialization module, server host is powered on, CPLD and SATA / SAS controller initialization is completed; Register and counter establishment module, the CPLD internally establishes the SGPIO input Data buffer register, output Databuffer register and SGPIO Clock counter; Data frame bit length calculation module, CPLD waits to receive SGPIO signal, and after receiving the input SGPIO signal, calculates the bit length of the input data frame; The data frame bit length judgment and processing module determines whether the bit length of the data frame is equal to 12 bits. If the received data frame length is 12 bits, the Clock, Load, and Data signals of the input SGPIO are directly transparently transmitted to the output IO pin, so that the SGPIO signal of the output interface is completely equivalent to the SGPIO signal of the CPLD input; if the data frame length is greater than 12 bits, the signal is processed to unify the SGPIO data of the output port into 12-bit data.

8. The SGPIO unified coding system according to claim 7, wherein: The data frame bit length judgment and processing module includes a data frame processing submodule greater than 12 bits, specifically including: Clock signal processing unit: used to process the output SGPIO Clock signal. The frequency is configured according to requirements. It is recommended to synchronize the input SGPIO Clock signal and define the Load signal output according to 12 clock cycles. The SGPIO Clock frequency on the output port can be adjusted independently or follow the SGPIO Clock signal input by the CPLD. Data temporary storage unit: used to temporarily store the input SGPIO_Data signal data into the input Data buffer register when the input SGPIO Load signal jumps to a high level; Data capture unit: used to select the starting position of the data according to the disk serial number corresponding to the output interface, capture continuous 12-bit data from the input data buffer register, and store it in the output data buffer register; Data output unit: refers to the SGPIO coding requirements and outputs the 12-bit data in the output data buffer register through the output SGPIO Data signal line; Data synchronization update unit: used to cyclically execute data temporary storage, data capture and data output steps to achieve real-time synchronous update of data, ensure that the data in the input SGPIO signal can be forwarded to the output SGPIO signal in a timely and accurate manner, and maintain the SGPIO data format of the output port to be unified as 12 bits.

9. A device for unified SGPIO coding, characterized in that: The SGPIO of the SATA / SAS controller is connected to the CPLD. The SATA / SAS high-speed signals are connected to the storage expansion interface in groups for accessing the server backplane expansion hard disk. The CPLD outputs the SGPIO signal and connects it to the storage expansion interface. During normal system operation, the SATA / SAS controller begins operating, and its SGPIO outputs data according to the originally designed data format. The originally designed data format specifically refers to the data length defined by the controller chip, which is related to the number of hard drives supported by the controller itself. The CPLD re-encodes the input signal data and the port number of the storage expansion interface on the board to ensure that the hard drive status information contained in the SGPIO corresponds to the hard drive location, ensuring that the data format of the SGPIO signal on the hard drive backplane is unified.

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