Paillier homomorphic encryption acceleration board card supporting multi-chip cooperative computing and scheduling method of Paillier homomorphic encryption acceleration board card

Abstract

The invention discloses a Paillier homomorphic encryption acceleration board card system supporting multi-chip cooperative computing. The Paillier homomorphic encryption acceleration board card system comprises a central scheduling control module, a plurality of isomorphic encryption computing chips, an inter-chip communication module, a host interface module and an auxiliary function module. And the central scheduling control module is used for analyzing a ciphertext structure and dynamically scheduling chip resources according to a task scale, and supports multiple cooperative computing modes such as ciphertext shunting, task fragmentation and pipeline processing. And the inter-chip communication module adopts AXI interconnection or an NoC structure to realize high-speed data exchange. Parallel calculation of modular exponent operation is completed among the slave chips in a master-slave cooperation mode, and dynamic modular basis configuration, chip activation control and a thermal management mechanism are supported. The system is suitable for being deployed on a cloud server, an edge device and a multi-card cluster platform, large-scale parallel acceleration processing of the Paillier encryption algorithm is achieved, and the system has high expansibility and high reliability.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of information security and integrated circuit technology, in particular to a multi-chip hardware acceleration board card system for Paillier homomorphic encryption calculation, specifically including a multi-chip cooperative scheduling method of ciphertext processing tasks, an inter-chip communication structure, a dynamic power consumption control mechanism, and integrated applications in cloud and edge computing environments, which belongs to the key supporting technology in the direction of privacy calculation and cryptography hardware acceleration. BACKGROUND

[0002] With the wide application of artificial intelligence, big data, and blockchain technologies in the fields of finance, medicine, government affairs, and military industry, the importance of data privacy protection is increasingly prominent. As a basic scheme of cryptography for realizing "data can be calculated but not visible", homomorphic encryption has become one of the core technical paths in the privacy calculation system. Paillier encryption algorithm has wide potential in applications such as federated learning, encrypted search, and secure audit due to its natural support for homomorphism of addition and limited multiplication. However, the homomorphic operations in Paillier algorithm, especially the homomorphic multiplication and modular exponentiation, usually involve large integer (thousands of bits) calculations, with high computational complexity and long execution delay, which seriously restricts its usability and deployment efficiency in practical engineering systems.

[0003] Currently, hardware acceleration for Paillier homomorphic operations mainly focuses on single-chip architecture, using methods such as Residue Number System (RNS) and Number Theoretic Transform (NTT) to optimize large number operations in parallel. Although the above methods can improve single-chip computing efficiency to some extent, they are limited by silicon area, power density, and interface bandwidth, as well as domestic process technology. A single chip often cannot meet the real-time processing needs of massive ciphertexts, and it is difficult to achieve performance breakthroughs in application scenarios that require large-scale privacy protection calculations, such as data fusion platforms, financial encryption engines, and edge node encryption processing. In addition, most existing hardware acceleration solutions are limited to chip-level design, lacking flexible and deployable system-level solutions, especially in the board card level, there is no Paillier homomorphic acceleration product form with standard interface, cluster deployment, and multi-scenario adaptation capability.

[0004] Therefore, there is an urgent need for a hardware acceleration system with scalability, schedulability, and industrial deployment capability, which can efficiently support large-scale ciphertext calculation tasks through multi-chip parallelism, cooperative scheduling, and dynamic energy management mechanisms while maintaining the correctness of Paillier homomorphic operations. At the same time, the system should have good packaging adaptability and deployment flexibility, and can be widely integrated into cloud servers, edge computing nodes, and multi-card cluster platforms, promoting the evolution of Paillier homomorphic encryption from academic research to industrial landing and acceleration. SUMMARY

[0005] The present application aims to solve the key bottlenecks of the existing Paillier homomorphic encryption acceleration system in system-level deployment, scalability, task scheduling capability and collaborative computing efficiency, and provides an acceleration board system with multi-chip parallel capability, structure-aware scheduling mechanism and high-performance communication interconnection architecture, which significantly improves the efficiency and energy efficiency of large-scale ciphertext processing in privacy computing.

[0006] Specifically, the present application aims to achieve the following technical objectives:

[0007] Providing a board system integrating multiple Paillier acceleration chips, supporting parallel computing and collaborative task execution.

[0008] Introducing a ciphertext structure-driven scheduling mechanism to dynamically adjust resource allocation based on ciphertext bit width, operation type, etc.

[0009] Designing a board-level inter-chip communication network structure to support intermediate result sharing and multi-chip collaborative CRT reconstruction.

[0010] Providing three collaborative operation modes to adapt to different homomorphic computing scene requirements, including ciphertext shunting, segmented reconstruction and master-slave collaboration.

[0011] Implementing power consumption regulation, interface compatibility and software driver support to meet the operability and practicality requirements of engineering deployment.

[0012] To achieve the above purpose, the present application proposes the following technical scheme: a multi-chip acceleration board system for accelerating Paillier homomorphic encryption of large integer operations, comprising:

[0013] Multiple Paillier homomorphic encryption acceleration chips, preferably 8, each chip is built based on the Residue Number System (RNS) and Number Theorem Transform (NTT) architecture, supporting high-concurrency large integer modular operations (including homomorphic addition, homomorphic multiplication, modular exponentiation, modular subtraction, modular inverse, etc.).

[0014] Central scheduling control module, used to analyze the required resources of the ciphertext to be processed according to its structural characteristics (such as bit density, operation type, task size, etc.), and to develop a task distribution strategy accordingly, dynamically activating part of the chips or configuring the number of module bases, NTT length, window width, etc.

[0015] Onboard chip interconnection communication module, constituting an on-chip high-speed interconnection network, supporting the exchange of intermediate frequency domain results, multi-module domain data, CRT sub-items and other information between chips, ensuring the continuity of multi-chip collaborative execution of Paillier encryption processes.

[0016] Host interface module, using PCIe Gen3 or above high-speed bus interface, realizing large bandwidth cipher text exchange with host system including x86 and domestic platform, supporting batch data transmission, task triggering and state feedback.

[0017] Auxiliary module, including DDR cache, thermal control unit, intermediate data cache, ROM lookup table module, power management, etc.

[0018] The system can run in the following three cooperative modes:

[0019] Cipher text shunting mode: different cipher text tasks are divided into multiple sub-flows, which are respectively assigned to multiple chips for independent and parallel execution, suitable for large batch small scale tasks.

[0020] Segmented reconstruction mode: a large cipher text is cut in the modulus dimension, each chip is responsible for part of the modulus processing, and then the CRT reconstruction is aggregated through the board communication network, suitable for super large cipher text tasks.

[0021] Master-slave cooperative mode: a certain chip is designated as the master, responsible for cipher text analysis, task decomposition and scheduling, and the slave chip focuses on executing core modular operation, suitable for scenarios sensitive to scheduling complexity and energy efficiency.

[0022] The board system also supports the following key mechanisms and characteristics:

[0023] Dynamic modulus base scheduling mechanism: the scheduler can dynamically increase or decrease the active modulus path according to the cipher text precision requirement, adjust the NTT point number and window size, and realize the adaptive balance of performance-power-precision.

[0024] Low power consumption control strategy: support for automatically reducing the working frequency of part of the chip or shutting down unnecessary cores based on the chip idle state or temperature threshold, optimize thermal design and energy consumption management.

[0025] Soft and hard cooperative interface: the system provides unified OpenCL driver and C / C++ API interface, which is convenient for integration with cloud scheduler, privacy computing platform or edge device software.

[0026] Pluggable structure and cluster expansion capability: support for deployment in standard PCIe slot, also support for multiple board cards interconnected horizontally to build a privacy computing cluster.

[0027] Compared with the prior art, the present application has the following significant technical advantages and engineering benefits:

[0028] Throughput capacity is greatly improved: through parallel processing of multiple acceleration chips and structure-aware scheduling, the cipher text processing throughput is improved by 5-10 times compared with the single chip solution.

[0029] Excellent energy efficiency: using dynamically adjustable module base and NTT configuration mechanism, avoiding excessive resource activation, maintaining low power consumption operation under high concurrency or low load.

[0030] Strong deployment flexibility: supports standard PCIe card structure, compatible with x86 and domestic platforms, can be deployed in cloud servers, AI edge gateways or security dedicated devices.

[0031] High system scalability: multi-chip architecture and inter-board communication protocol support horizontal expansion, which is beneficial to build privacy computing clusters and multi-tenant acceleration platforms.

[0032] Complete functions: fully supports main operation types in Paillier homomorphic encryption, and has scheduling, caching, controllable, interface and other system-level integrated functions.

[0033] In summary, the present application breaks through the limitations of existing Paillier acceleration chips in system deployment, task scheduling and scalability, has significant technical innovation and engineering practical value, and is suitable for multi-party secure computation, cloud privacy analysis, blockchain confidential contract, financial risk control and AI encryption inference and other fields. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 The figure is a schematic diagram of the overall structure and data flow of the present application.

[0035] Figure 2 The figure is a schematic diagram of the operation process under the ciphertext shunting mode. DETAILED DESCRIPTION

[0036] The embodiment provides a board card system integrating multiple Paillier homomorphic encryption acceleration chips, which is used to improve the parallel processing capability of ciphertext operation and the system-level deployment flexibility. The board card can adopt a standard PCIe expansion card form, has high-bandwidth data exchange capability, and is suitable for cloud servers, edge devices or security computing modules. As shown in the figure, the overall structure of the board card includes the following main modules: Figure 1

[0037] Multi-chip acceleration array: 8 Paillier homomorphic encryption acceleration chips are integrated on the board card, each chip adopts a customized circuit based on the residue number system (RNS) and number theory transform (NTT) architecture, and has the ability to support Paillier homomorphic addition, multiplication, modulus exponent, modulus inverse, modulus subtraction and other operations. The chips are arranged in equal intervals, connected to the scheduling control module through a high-speed local interconnection bus, and support independent operation or multi-chip cooperative operation.

[0038] ​Central scheduling control module: This module is composed of on-board FPGA or on-chip microcontroller, with functions of ciphertext structure analysis, task distribution, chip configuration, state monitoring and load balancing control. The scheduling control module establishes an independent control channel with each acceleration chip, which is used to issue configuration instructions, receive running state feedback, and decide whether to activate, close or reassign task paths in real time.

[0039] On-chip interconnection communication module: The board card realizes high-speed data interaction between multiple chips by building crossbar switch and network-on-chip structure. The communication module supports flexible transmission of intermediate frequency domain results (such as NTT domain output), CRT reconstruction sub-items, and modular multiplication intermediate values between chips, and has the ability of broadcast, multicast, and data multiplexing to support the running needs of segmented reconstruction mode and master-slave collaborative mode.

[0040] Host interface module: The board card is connected with the host system through a group of PCI Express (PCIe) physical channels, preferably PCIe Gen3 x8 or Gen4 x8 interface, supporting DMA mode data transfer and configuration register access. This module is responsible for receiving Paillier ciphertext and control commands sent by the host to the board card, and efficiently returning the operation results to the host memory, minimizing the call delay of the upper software system.

[0041] Shared intermediate cache module: A group of on-chip SRAM or external DDR is set in the central area of the board card as a shared buffer, which is used to cache intermediate data such as NTT results, modular products, modular inverses, or partial CRT intermediate items during collaborative computing of multiple chips, to improve the bandwidth utilization and data consistency during collaborative processing.

[0042] Power consumption and thermal control management module: The board card integrates an environmental monitoring circuit, including temperature sensors, current detectors, fan controllers, and dynamic frequency adjustment logic. When a chip is idle for a long time or the chip temperature exceeds the safety threshold, the scheduling module can trigger shutdown, frequency reduction or thermal scheduling operations to improve system stability and energy efficiency.

[0043] The multi-chip Paillier homomorphic encryption acceleration board provided by the embodiment is designed for large-scale ciphertext task processing needs, supporting end-to-end pipelining processing flow from ciphertext input, task scheduling, chip parallel execution on the host side to final result output. The operation process of each stage is as follows:

[0044] Ciphertext input stage: The host system (such as a server or edge gateway) transmits the ciphertext block to be processed to the board card in DMA mode through the PCIe interface. The transmission content includes: Paillier ciphertext original text (large integer representation); operation type identification (homomorphic addition, homomorphic multiplication, modulus exponent, etc.); optional operation parameters (such as constant multiplier, modulus exponent base, etc.); structure analysis instruction and scheduling flag (generated by the upper layer driver). After the data enters the board card through the host interface module, it is preferentially stored in the shared intermediate cache module, waiting for the central scheduler to process.

[0045] Task scheduling and configuration stage: The central scheduling control module (Central Scheduling Control) reads the task description from the intermediate cache and executes the following scheduling logic: bit width statistics and modulus base demand analysis of the ciphertext; according to the current system running load, select the appropriate number of acceleration chips to participate in processing; dynamically allocate tasks to idle chips; configure the modulus base number, NTT point number, window function window width and other parameters of the selected chip; the instruction on-chip interconnection communication network (On-Chip Interconnect) establishes the necessary data channel between chips. The scheduler issues running instructions to each chip in the form of microinstructions, and records the task-chip mapping relationship for subsequent tracking.

[0046] Acceleration operation execution stage: each chip allocated with a task starts the acceleration process, including: reading the ciphertext from the intermediate cache or communication channel; performing RNS conversion to convert the ciphertext into multiple small modulus domain representations; performing NTT forward transform to enter the frequency domain; performing homomorphic multiplication / multiplication / addition / exponent modulus operation; performing inverse NTT transform to restore the modulus domain result; returning the RNS component to the communication module. For tasks that require collaborative computation (such as segmented reconstruction mode or master-slave collaborative mode), part of the intermediate frequency domain result will be transmitted to other chips through the on-chip interconnection network to complete the subsequent stage (such as CRT reconstruction or exponent multiplication accumulation).

[0047] Result collection and output stage: after each chip completes the operation, it returns the output result to the communication module or shared intermediate cache module. According to the task type: if it is a shunt mode (multiple ciphertexts are processed independently), each chip directly writes the result to the cache; if it is a collaborative mode (the same ciphertext is processed by multiple chips), the communication module coordinates to combine the distributed results into a large integer output (such as completing CRT reconstruction); all results are packaged by the central scheduler into the format expected by the host. Finally, the processed result data is sent back to the host system through the PCIe bus, completing a complete Paillier homomorphic encryption calculation task.

[0048] Central Scheduling Control is the control center in the multi-chip Paillier acceleration board of the application, responsible for dynamically configuring chip resources, formulating task allocation strategies, monitoring running states, and coordinating data flow and energy consumption management in the board according to the task parameters and ciphertext structure transmitted by the host. The module is preferably implemented by a high-performance FPGA or a customized control SoC on board, and the internal control logic includes the following core functional units:

[0049] Ciphertext structure analysis unit: this unit is responsible for parsing the ciphertext task description transmitted by the host, and extracting the following information: ciphertext bit width (such as 2048 bits, 4096 bits); operation type (homomorphic addition, multiplication, modulus exponent, modulus subtraction, modulus inverse); number of participating data streams (ciphertext-ciphertext, ciphertext-constant, exponential multiplication base, etc.); required precision level (affects modulus number and window size). Structure analysis can be achieved by table lookup, bit width detection, operation flag analysis, etc. The output result is used as the parameter basis for task scheduling.

[0050] Resource scheduling and chip selection unit: this unit determines the following scheduling strategies according to the structure analysis results and the current running state of the system: the number of chips to be activated currently (1-8); the task range handled by each chip (independent ciphertext / modulus domain segmentation / exponential intermediate segment); the type of cooperative mode called (shunting / segmentation / master-slave); the data exchange relationship between chips (communication path, shared item); chip configuration parameters (modulus number, NTT point number, window width, etc.). Chip selection preferably adopts round robin method or lowest load priority strategy, and can also be dynamically adjusted according to chip temperature / idle state.

[0051] Micro-instruction issuing and configuration control unit: this unit is responsible for issuing the scheduling results to the target chip in the form of configuration instructions, and the control content includes: activation / sleeping instruction; task number and input address; operation type flag; modulus selection (selecting several from the predefined modulus base set); NTT core length and working mode (forward or reverse); CRT parameter and window lookup table address. Instruction issuing adopts a special inter-chip control channel, which is implemented in cooperation with the control protocol frame in the communication module.

[0052] Task tracking and state monitoring unit: this unit continuously records the information of all active tasks in the current board, including: the current task number and processing stage of each chip; whether the intermediate data has been synchronized to the target chip; the temperature, current, and running frequency state of each chip; whether there is an abnormal state (such as chip offline, verification failure, temperature exceeding standard, etc.). This unit provides a running state feedback interface to the host driver system, supporting OpenCL / C interface to read the task execution state.

[0053] Power management and temperature control strategy unit: This unit works with the power / thermal control module to perform the following control actions based on real-time sampling results: when the temperature exceeds the safety threshold (such as 85°C), issue a forced frequency reduction or load reduction instruction; when the idle time of a certain chip exceeds the set threshold (such as 100 ms), automatically enter the sleep state; support dynamic voltage adjustment (DVFS) to change the power supply voltage level according to the load. By dynamically starting and stopping the operation of the resource, the power consumption of the entire card can be effectively reduced, and the service life can be prolonged.

[0054] Task completion and data arrangement unit: This unit is responsible for the following tasks after the task is completed: notifying the communication module to collect, align and package the chip output data; notifying the host interface module to prepare DMA return; releasing chip resources and resetting the scheduling table item; writing logs into the soft reset buffer for debugging.

[0055] The on-chip interconnect communication module described in the embodiment is a data transmission channel, instruction issuing path and collaborative synchronization hub connecting the central scheduling control module and multiple Paillier homomorphic encryption acceleration chips, used to implement the following three types of communication tasks: transmission of configuration instructions and scheduling control information; inter-chip transfer of intermediate ciphertext data and calculation results; cross-chip data reorganization, broadcasting and synchronization in multi-chip collaborative processing.

[0056] The communication module can be implemented in any of the following structures, and the optimal architecture is selected according to the number of chips and system complexity.

[0057] AXI crossbar: suitable for the case where the number of chips is ≤8; all chips are connected with the central scheduler through a shared AXI bus; supports point-to-point communication between multiple master devices (schedulers) and multiple slave devices (chips); supports address mapping, multi-access arbitration and burst transmission, meeting the high-bandwidth task scheduling requirements.

[0058] Network-on-Chip (NoC): suitable for extended multi-chip boards (>8 chips or board cluster interconnection); uses Mesh, Torus or Ring topology, with chips as nodes, and data packets are routed according to the protocol; has the characteristics of strong scalability, good bandwidth isolation, and support for multicast / broadcast; typical NoC protocols support lightweight flow control and error detection.

[0059] The internal communication of the module is based on a unified protocol structure, which contains the following information fields: task number, source / destination address, data type identifier, data payload, and check code. The protocol supports multiple priority queues (such as control flow priority and data flow delay optimization) to meet real-time requirements.

[0060] Performance and interface parameters: bus width: 256 bits to 512 bits for AXI interface; maximum number of supported chips: 8-way for Crossbar structure, and NoC can be extended to more than 16 ways; single-channel delay: the typical delay of control command is less than 100 ns; upper limit of bandwidth: more than 16 GB / s, matched according to the number of PCIe channels; and DMA direct cache access is supported.

[0061] Each communication channel can integrate lightweight parity check or CRC redundancy check; the communication exception (such as timeout and back error) of the chip will trigger the retry mechanism of the scheduler; the inter-chip handshaking mechanism is supported, so as to ensure the consistency and safety of the tasks in the asynchronous scheduling process.

[0062] The host interface module of the application is mainly used for realizing the data interaction, instruction configuration and state feedback function between the board card and the host system, and is the core communication bridge of the whole acceleration board card facing the external system. The module is preferably integrated with a PCIExpress (PCIe) high-speed interconnection interface, and in combination with a direct memory access (DMA) mechanism, can receive the ciphertext task request from the host in a low-delay and high-throughput manner, and return the acceleration result to the host. The structure design and communication protocol configuration of the module are directly related to the bandwidth bottleneck and running efficiency of the whole system.

[0063] In specific implementation, the host interface module is internally provided with a PCIe controller, a DMA engine, a task buffer and a state register set. The host can access the configuration space of the module through the PCIe interface, so as to realize the task instruction issuing, parameter setting, chip control and reading of the running state of the board card. The PCIe controller supports multi-queue communication and scatter-gather transmission, and can effectively improve the concurrent processing capacity. In the task processing process, the host first writes the ciphertext input data into the shared memory area of the board card, and the host interface module automatically carries the ciphertext data to the central scheduling module or directly sends the ciphertext data to the specific Paillier acceleration chip through the DMA engine. After the operation is completed, the result data is also written back to the host memory through the DMA mode, so as to avoid frequent interruption and CPU intervention, and improve the overall processing efficiency of the system.

[0064] In addition, in order to support the dynamic perception of the host to the running state of the board card, the host interface module in the application is also provided with a plurality of state registers and an interrupt signal mechanism, which are used for feeding back the information such as the current task execution condition, the chip activation state, the temperature threshold early warning, the running error code and the like. The host can periodically or event-drivenly query the related registers, or receive the state change notification through the interrupt signal, so as to realize the task scheduling optimization and the thermal fault tolerance mechanism. The module is also linked with the system initialization and configuration storage module, supports the host to access the board card parameters stored in the EEPROM or ROM, and realizes the version management, parameter update and default configuration recovery and the like.

[0065] To ensure the long-term stable operation and efficient data support of the multi-chip Paillier acceleration board under high-intensity parallel tasks, the embodiment also integrates a plurality of auxiliary modules, including: on-chip cache system, temperature control and power consumption management mechanism, startup configuration storage system, etc. These modules are not the computing core, but play a key role in system-level stability and engineering feasibility.

[0066] To support multiple chips concurrent access to shared intermediate data, while reducing the host DMA bandwidth pressure, the board deploys on-chip DDR cache system, including the following components:

[0067] Data Buffer: Store host input ciphertext, constants, etc.; shared by multiple chips, support multi-port parallel access; support double buffering mechanism to realize data preloading and writeback separation; typical configuration: 4GB-8GB DDR4, bit width 64bit, bandwidth >10GB / s.

[0068] Coefficient Buffer (NTT / CRT Coefficient Buffer): Store the number theory transform (NTT) modulus, rotation root, modulus inverse constant, CRT weight coefficient, etc. in Paillier calculation; usually static ROM or initialized on-chip SRAM; with low-latency broadcast access capability for multiple chips to synchronize access.

[0069] Windowed Exponentiation LUT: Specialized for exponent pre-computation lookup in modular exponentiation (such as 2^k window method); each chip or multiple chips share a LUT module; initialized by ROM / EEPROM, also supports runtime refresh; cache can be configured to 128-1024 preset power values.

[0070] To prevent chips from performance degradation or damage due to overheating or continuous full-load operation, the board deploys active temperature control and power consumption dynamic adjustment system, including:

[0071] On-Chip Thermal Sensor: Each chip integrates an independent temperature detection module; supports 10ms periodic polling sampling or event-driven reading; temperature value is uploaded to the scheduler module and host configuration register.

[0072] Dynamic Frequency Scaling (DFS): The scheduler decides whether to dynamically reduce the working frequency according to the chip temperature and current load; supports 3-level voltage domain and 4-8 frequency steps; the frequency reduction strategy supports threshold triggering and predictive temperature rise model.

[0073] Fan control and onboard heat pipe support: The board has a fan control interface; the fan speed can be automatically adjusted according to the average chip temperature; and it supports physical cooling design with heat pipes or heat sinks.

[0074] To ensure that the board is ready for use immediately upon power-up without relying on the host to manually load the configuration file, the following non-volatile configuration storage and startup initialization mechanism is set up:

[0075] Onboard ROM (Boot ROM): Stores the basic initialization program (Bootloader) of the board. After power-on, the ROM contents are first loaded to initialize the clock tree, communication protocol stack, DMA configuration, etc. The ROM space is typically configured as 64KB to 256KB.

[0076] EEPROM configuration memory: stores chip quantity, address mapping table, frequency table, power consumption model, task scheduling strategy, etc.; supports the curing of user-defined configuration files and calibration parameters; accessed through the I2C or SPI interface, supports power-off saving and version switching.

[0077] Self-test and configuration echo mechanism: After each power-on, the board returns the initialization status code through the host interface. If a chip is abnormal, the ROM can be used to restore the default configuration or disable the problematic chip. Hot-swap detection and automatic host identification are supported.

[0078] Project feasibility and scalability support: All of the aforementioned auxiliary modules can be deployed in the FPGA preprocessing area or an external microcontroller (such as the STM32). Dynamic hot-update EEPROM configuration is supported without hardware reflashing. All modules are encapsulated as independent service units that can be called by the main control scheduling system.

[0079] The present invention supports three multi-chip cooperative operation modes.

[0080] Ciphertext Distribution Mode involves a central scheduling control module that evenly or dynamically distributes multiple pending homomorphic encryption tasks (or ciphertext data pairs) to multiple Paillier accelerator chips on the board. Each chip independently completes the entire computational process for the assigned task and returns the results to a shared intermediate cache for centralized collection by the host. This mode utilizes a parallel processing architecture with no dependencies between chips, focusing on improving throughput. It is suitable for the following typical application scenarios: large-scale Paillier ciphertext addition and multiplication operations in finance, healthcare, and government; batch processing tasks with a high density of homomorphic tasks but moderate computational complexity per data set; and service deployments in the cloud or edge servers with a large number of concurrent users and relatively uniform requests.

[0081] like Figure 2 ,The operation process in the ciphertext diversion mode mainly includes the following steps:

[0082] First, the host inputs multiple task data: such as N groups of Paillier ciphertext pairs (A i , B i ), i ∈ [1, N].

[0083] Second, the central scheduling controller performs load evaluation: queries the status of each chip; judges the number of idle chips and the allocation ratio.

[0084] Third, the task allocation strategy is executed: the task is divided into subtask packages; each chip is responsible for processing a subtask package; the allocation strategy supports polling, minimum load priority, temperature-aware shunting, etc.

[0085] Fourth, each chip independently completes the homomorphic operation: each chip completes the NTT transformation, modular multiplication, inverse transformation, and CRT reconstruction; the operation process is completed independently without relying on other chips.

[0086] Fifth, the results are written into the shared buffer area.

[0087] Sixth, the scheduler summarizes the task status and returns it to the host.

[0088] If a chip overheats, fails, or returns an error code, the scheduling module can immediately transfer its task to other chips for re-execution.

[0089] Supports "deadline-aware execution": if a chip is delayed by more than twice the average time, an interrupt and replacement can be triggered.

[0090] Supports the host reading the task completion time, processing rate, and idle ratio of each chip for system self-learning and optimization.

[0091] The parameter configuration under 8-chip is as follows: each chip processes an average of 500 Paillier ciphertext additions; the overall throughput (8 concurrent) ≥4000 times / sec (based on chip acceleration capability); the host once task submission package length 256 Byte×500 groups ≈128KB; processing time (8 tasks in parallel ≈10ms (ciphertext addition) or ≈30ms (modular exponent); bandwidth occupancy rate (including return) PCIe Gen3 x8, peak utilization rate about 60%.

[0092] Segmented CRT reconstruction mode is a running mode proposed by the present application for completing a single Paillier modular exponent task across chips, which is particularly suitable for ciphertext modular exponent (c rmod n²) operation. This mode splits the calculation task by RNS (Residue Number System) modulus dimension, distributes the segmented sub-tasks to multiple chips for parallel execution, and finally completes CRT reconstruction by the main chip or scheduling module to obtain the complete ciphertext result.

[0093] The core bottleneck of Paillier modular exponentiation is that the calculation complexity is much higher than that of addition and multiplication; the exponent is usually a large number (hundreds of bits of random r); and the exponentiation operation is difficult to directly parallelize.

[0094] This mode relies on the RNS parallelism in the modulus domain of the chip adapted by the application, and splits the entire exponentiation process horizontally according to the modulus domain, as follows:

[0095] First, the input ciphertext c and the exponent r are expanded into a plurality of modulus-based residue pairs in the RNS system.

[0096] Second, the scheduling module assigns different modulus components to multiple chips to complete the power operation in the modulus domain (i.e. i: c i r mod p i ).

[0097] Third, all chips return the results after completion.

[0098] Fourth, the scheduling module or a main chip uniformly performs CRT reconstruction to restore c r mod n².

[0099] In terms of scheduling and communication mechanism, a task tag mechanism is used, each modulus task has a task ID and a modulus ID; the communication module supports asynchronous broadcast and recycling mode, and the data returned by each chip can be spliced immediately; the scheduler uses a FIFO splicing buffer to manage the returned data to ensure the reconstruction order; if the task returned by a chip is overdue, the system can reschedule the remaining modulus and calculate it by other chips.

[0100] The parameter configuration under 4 modulus reconstruction is as follows: modulus number (Moduli) 4 (extensible to 8, 16); number of chips participating 4 chips (each chip processes one modulus); single task processing time 5-10 ms (depending on the number of exponent bits and modulus size); CRT reconstruction time ≤2 ms (supports pipeline and lookup table optimization); total throughput (concurrent execution) ≈100-150 times / s (modular exponent tasks).

[0101] Master-Slave Cooperative Mode is a mode in which one Paillier acceleration chip acts as a "master chip" (Master) responsible for task scheduling, instruction disassembly and partial core operation, and the rest of one or more chips act as "slave chips" (Slave) to execute sub-tasks assigned by the master chip, such as intermediate power calculation, multiplication chain expansion, preprocessing, etc. The master chip performs subsequent processing such as summarizing, inverse transformation and reconstruction after receiving the results from the slave chips, and finally generates the complete result and returns it to the host. This mode is suitable for Paillier tasks with extremely complex calculations or highly irregular data structures, such as nested exponentials, exponential multiplication chains, dynamic polynomial weighting, etc.

[0102] Unlike the "Ciphertext Shunting Mode" which focuses on task parallelism and the "Segment Reconstruction Mode" which focuses on modulus parallelism, the "Master-Slave Cooperative Mode" divides the entire operation process into multiple phased sub-processes and processes them in stages with the help of multi-chip cooperation. The master chip not only performs part of the calculation, but also takes on the role of logical control such as coordination, integration and transmission. This mode embodies a master control outsourcing mechanism under a heterogeneous computing architecture, with the following design ideas: the master chip performs non-parallel control logic, FFT expansion and exponential scheduling; the slave chips perform parallel low-level instructions such as modular_mul, NTT butterfly, r² mod n², etc.; the results of each slave chip calculation are used as subsequent input to the master chip, and intermediate results are not directly returned to the host; the overall structure is similar to a CPU-GPU or DSP-co-processor architecture.

[0103] The running process of the Master-Slave Cooperative Mode is as follows:

[0104] Step 1: The host submits a complex task, such as high-order power or exponential multiplication chain.

[0105] Step 2: The master chip identifies the task type and dynamically segments it into several sub-instructions.

[0106] Step 3: The sub-instructions are assigned to multiple slave chips according to priority or modulus correlation.

[0107] Step 4: The results of the slave chip processing are returned to the master chip's temporary buffer.

[0108] Step 5: The master chip concatenates the results and performs inverse transformation, reconstruction, formatting and other operations.

[0109] Step 6: The final result is written to the shared cache by the master chip, which is read by the host.

[0110] The example parameter configuration is as follows: the master-slave chip ratio is 1 master chip to 2-4 slave chips; the single task minimum fragmentation granularity is 32 bits x 4 components (exponential decomposition or multiplication chain segment); the single sub-task processing duration is 2-5 ms (slave chip); the master chip reconstruction time consumption is about 1-2 ms; the overall delay is 8-15 ms (depending on the task complexity); and the abnormal compensation response time is less than or equal to 2 ms (automatic retransmission, breakpoint continuation calculation).

[0111] The mode can be superimposed on mode two to form a hybrid collaborative computing framework, such as segmenting and reconstructing first, and then organizing intermediate exponential calculation in a master-slave manner to enhance the overall adaptability of the system.

[0112] The application further introduces "task-aware dynamic scheduling" and "thermal power consumption joint control mechanism" on the basis of multi-chip collaboration, realizes intelligent balance among calculation accuracy, power consumption and throughput, and the scheduling module no longer only distributes tasks based on a static chip state table, but dynamically selects operation module base, chip number and working frequency based on multi-dimensional indexes such as runtime load, chip temperature, power supply margin and operation accuracy, and flexibly reconstructs the task execution path accordingly.

[0113] The dynamic moduli set configuration strategy refers to that the scheduling module dynamically adjusts the number and type of RNS moduli bases used for Paillier modulus exponentiation according to task characteristics, chip state, power consumption budget and other factors, so as to achieve the optimal balance of performance-resource-energy consumption.

[0114] Paillier homomorphic operation needs to select a set of modulus base sets (RNS moduli base set) in the RNS system. The traditional scheme statically configures the number and value of the modulus base when designing, which leads to the following problems in different scenarios: excessive calculation, that is, all chips are still mobilized when the task is simple; resource waste, that is, some modulus bases are frequently idle; uneven energy consumption, that is, some chips are overheated and some have no task; and system inflexibility, that is, the system cannot be dynamically pruned when a sudden thermal failure occurs. Therefore, the application introduces a "configurable modulus base strategy" to realize accurate control and flexible arrangement by dynamically selecting the number, precision and distribution structure of the modulus base at runtime.

[0115] The strategy is realized by the scheduling module, and the core includes three aspects.

[0116] Modulus base number adaptive selection: for addition and multiplication tasks, 2-4 lightweight modulus bases can be selected; for exponential tasks, 6-8 complete modulus bases can be mobilized; the number of modulus bases N can be dynamically set according to the task complexity; and in the extreme case, "degradation" operation is allowed, and only the minimum modulus set is reserved to ensure low-power operation.

[0117] Dynamic reconstruction of module-base accuracy: supports reading multiple sets of module-base configuration files (such as "high-precision type / low power type / fault-tolerant type") from EEPROM; the scheduling module can select which set of module-base values ​​to activate based on host parameters and chip status; supports RNS module-base table hot update and erasable reconfiguration.

[0118] Module base allocation and chip mapping decoupling mechanism: Each chip is no longer fixed to a certain module base, but the module base mapping is dynamically configured according to task allocation; multiple chips are supported to cross-cover module base segments to improve fault tolerance; when a chip fails, hot switching to the backup module base mapping can be scheduled to ensure uninterrupted tasks.

[0119] The scheduling algorithm flow of the dynamic module-based configuration strategy is as follows:

[0120] In the first step, the scheduler parses the task type, accuracy requirements, and response time budget.

[0121] The second step is to query the current system load, power margin, chip temperature and other status parameters.

[0122] The third step is to select a matching module-based configuration solution (quantity + precision + mapping table) from the strategy library.

[0123] The fourth step is to dynamically generate the module-based mapping matrix and assign module-based tasks to idle chips.

[0124] The fifth step is to execute the task and monitor the calculation progress and power consumption of each module domain. If dynamic adjustment is required, interrupt and readjust the allocation.

[0125] In the sixth step, after all the results are summarized, CRT reconstruction or master control fusion is performed and the results are output.

[0126] To achieve low-power operation, long-term stability, and system-level robustness, the multi-chip accelerator board of this invention incorporates a task-driven chip activation strategy and a temperature-aware dynamic frequency reduction mechanism into the scheduling module. This mechanism, through sensing modules such as temperature sensors, load counters, and task completion cycle counters, enables on-demand activation of all chips, intelligent frequency reduction, hot zone rotation, and energy-efficient scheduling, while maintaining precise assurance of task correctness.

[0127] Power-Gated Activation: The scheduling module can decide whether to activate a certain chip according to the host task demand and the current chip state before each task scheduling: the default state is sleep or low-power listening state; each chip is controlled by an independent power gate to control the activation switch; support per-chip, batch or regional activation; the activation operation will synchronize the chip internal RNS module base mapping and cache preparation area; the activation threshold parameter can be configured by the host, such as "single task requires to enable ≥4 chips". For example, when only a light task arrives, the scheduling module can only activate 2 chips; if it is a high complexity exponential task, 8 chips are activated and the module base full configuration is started.

[0128] Thermal-Aware Dynamic Frequency Scaling (T-DFS): The scheduling module periodically reads the on-chip temperature sensor (such as a thermal diode, PTAT) and task completion period meter of each chip, judges its thermal load level and decides whether to reduce its working frequency.

[0129] If the chip temperature >80℃, its frequency will be reduced from 800MHz to 400MHz, and if it continues to rise, it will exit the operation.

[0130] If the chip load is continuously saturated for >5 periods, the frequency is actively reduced to reduce the instantaneous power consumption peak.

[0131] If the chip is continuously idle for >10 periods, it enters the automatic frequency reduction / standby state.

[0132] If the heat distribution is concentrated in the chip 3 / 4 / 5 area, the scheduling strategy is adjusted, and the task is transferred to the chip 1 / 2 / 6 / 7 to disperse the heat source.

[0133] This mechanism cooperates with the central scheduling module to realize the following behaviors.

[0134] Load-aware DFS: Set the target frequency of the chip according to the task size; light tasks run at low frequency, and exponential tasks automatically increase the frequency.

[0135] Temperature-aware Scheduling: Reduce or suspend the task of a hot chip; preferentially schedule a chip with low temperature to execute a high-intensity task.

[0136] Thermal Zone Round-Robin: The chip area is divided into thermal zones, and each round is scheduled to a neighboring chip to reduce thermal coupling.

[0137] Soft fault takeover: If the chip temperature frequently exceeds the limit, it will be automatically offline and taken over by a standby chip.

[0138] The running configuration parameters are as follows: the chip supports frequency levels 800MHz / 600MHz / 400MHz / 200MHz; the activation delay (including module base mapping) is less than or equal to 5ms (the chip is woken up before the task responds); the frequency reduction decision cycle is to perform temperature sampling and frequency evaluation once every 20ms; the frequency reduction energy saving effect (4-chip operation) can reduce the total power consumption of the board by 20-35%, and the peak working time is prolonged by more than 30%; the cooling rate (after active hibernation) is reduced to less than or equal to 65℃ in about 300ms (natural cooling, no fan).

[0139] To verify the engineering feasibility and commercial adaptability of the board card structure of the application, three types of implementation paths are planned in combination with the current mainstream private computing deployment environment: cloud server deployment, edge gateway deployment and customized security terminal embedded deployment. Each deployment mode provides complete interfaces, power supplies, heat dissipation, compatibility and integration framework to meet the full-scene adaptation from high-performance government clouds to low-power Internet of Things.

[0140] In cloud server deployment, the multi-chip Paillier homomorphic encryption acceleration board card proposed in the application has a standard PCIe interface and an industrial size specification, and can be easily deployed as a general plug-in card form inside various cloud servers to realize hardware acceleration support for homomorphic encryption computing tasks. In actual application, the acceleration card is connected to the mainboard through a PCIe x8 or x16 slot, and forms a hybrid collaborative computing architecture with the CPU or GPU. The host side software schedules the Paillier acceleration task and transmits the ciphertext data to the board card at high speed through the DMA channel. The central scheduling control module integrated in the acceleration card can automatically identify the task type, analyze the ciphertext structure, and dynamically schedule 8 Paillier computing chips to cooperatively execute homomorphic operation tasks such as modular exponentiation, modular multiplication or addition, thereby significantly reducing the CPU load of the host and improving the encryption computing throughput.

[0141] In the cloud computing environment, the deployment mode of the board card can be flexibly adapted to different server mainboard specifications, and it can be inserted into a high-performance AI server node as a single card, or it can be deployed in parallel on a standard 2U or 4U rack server to further expand the overall acceleration capability. By loading the matching driver program and scheduling SDK, the host can seamlessly migrate the existing data encryption processing flow to the hardware running path based on the Paillier algorithm API, while supporting batch ciphertext stream processing, task asynchronous scheduling, running state monitoring and dynamic energy management, and other high-performance running strategies. When facing a large number of user requests or multi-tenant computing load, the hardware board card can support the service invocation of data security computing through its low latency and high concurrency characteristics, providing stable, efficient and scalable homomorphic computing capability for the cloud platform.

[0142] In addition, considering the high requirements for energy density, heat dissipation performance and reliability in the cloud deployment process, the application has integrated complete power consumption perception scheduling logic and chip thermal management mechanism in the design, which can dynamically adjust the chip working frequency and the number of activated chips according to the temperature and computing load change in the server cabin, and guarantee the long-term operation stability of the acceleration system. Through the cloud deployment path of the acceleration board card, users can obtain orders of magnitude performance improvement of homomorphic encryption tasks without changing the underlying hardware platform, while ensuring data privacy and security, greatly improving the response speed and cost performance of secure computing services.

[0143] In terms of edge device integration (modular SoM), in order to meet the multiple requirements of homomorphic encryption performance, power consumption control and packaging integration in the edge computing environment, the application further proposes a board card cutting and packaging scheme based on the modular system-on-module (System on Module, SoM) method, which integrates core computing power and task scheduling control logic into an integrated small module to adapt to low-power, high-integration deployment scenarios in unmanned devices, embedded terminals, Internet of Things security gateways and other edge devices. In this implementation scheme, the Paillier acceleration chip array, central scheduling controller, host communication interface, power regulation circuit and part of the on-chip DDR cache in the core architecture of the board card are organically integrated into a highly integrated SoM module, leaving standardized connection interfaces (such as MXM, DIMM or custom gold fingers) to communicate with the mainboard, thereby realizing flexible and reliable embedded deployment.

[0144] The edge device master usually adopts ARM or RISC-V architecture processor, which has relatively limited performance and is difficult to perform large-scale Paillier modulus or modular multiplication ciphertext calculation. In the integrated mode described in the application, the edge master can send the ciphertext calculation task to the acceleration module via SPI, USB, PCIe mini or high-speed serial channel, and the internal scheduling controller of the module allocates 1 to 4 acceleration chips to participate in operation according to the task size, and the processing result is sent back to the master through the back channel. The SoM module has programmable power management logic and temperature detection unit, which can stably operate in complex external environments (such as vehicle-mounted, high temperature, outdoor nodes), and through dynamic frequency adjustment and chip sleep mechanism, the energy consumption is kept within an acceptable range, and the service life of the device is prolonged.

[0145] To improve the industrial adaptability of the module deployment, the SoM scheme of the application supports customization of the number of chips (1 / 2 / 4 / 8), the on-chip cache capacity and the interface type based on different target markets, has strong horizontal compatibility and expansion capability. At the same time, the module can be matched with a peripheral drive board (Carrier Board) or a standard interface bridge board, which is used to connect the device host, peripheral sensors or edge security units, to realize an integrated encryption link from edge data acquisition, homomorphic preprocessing to secure upload to the cloud. Through this scheme, the acceleration computing capability of the application can be sunk from the center node to the edge scene, providing low-latency, high-security and low-power local privacy computing support for smart cities, drones, border security, industrial gateways and other occasions, and expanding the application depth and actual deployment capability of homomorphic computing hardware.

[0146] In terms of multi-card cluster interconnection expansion, in the face of super-large-scale privacy computing scenarios, although the computing power of a single Paillier acceleration board can support high-concurrency task processing, it is still difficult to meet the deployment requirements of high-throughput and response time for tasks such as government data fusion, financial data desensitization computing, model training and encrypted reasoning. Therefore, the application further proposes a multi-card cluster expansion method, which supports interconnection and cooperation of multiple Paillier acceleration cards in the form of a cluster to build a distributed high-performance encryption computing platform. In this implementation structure, multiple acceleration cards can be inserted into multiple PCIe slots of the same server motherboard, or through PCIe expansion backplanes, distributed interconnection modules, switch backplanes and other methods, to realize horizontal connection between the cards and form an encryption acceleration cluster that shares the cryptographic scheduling resource pool.

[0147] The cluster uses a master-slave card architecture for management, one of the acceleration cards takes on the cluster scheduling and coordination function, responsible for global cryptographic task distribution, chip activation state synchronization, load balancing control and heat scheduling strategy issuance. Other acceleration cards act as slave nodes, receive task instructions and independently complete the encryption computing process. The cards interact with each other through high-speed PCIe exchange buses, AXI interconnection channels or custom NoC interconnection protocols to realize high-speed data interaction and instruction synchronization. When necessary, multiple acceleration cards can also be virtually connected into a unified logical acceleration resource pool for the host to call through SR-IOV or NVMe over PCIe virtual channel technology, significantly improving system manageability and scalability.

[0148] To guarantee the resource scheduling efficiency under the multi-card collaborative operation, the cluster interconnection scheme in the application further introduces a cluster-level state monitoring bus, which collects the chip running state, task queue length and thermal load information of each board card in real time, and feeds back to the main control board card scheduling module as the input condition of the chip distribution and frequency adjustment strategy. At the same time, during the system power-on stage, each board card completes automatic registration and collaborative domain division through the preset address recognition mechanism and link initialization protocol, realizes plug and play and dynamic expansion capability. In addition, considering the power consumption aggregation and heat accumulation problem caused by the multi-card cluster, the scheme supports centralized air duct design, group cooling strategy and distributed heat balance control logic, guarantees the long-term stable operation of the cluster system under high-density deployment.

[0149] In summary, the multi-card cluster interconnection expansion scheme proposed in the application not only has good horizontal scalability and deployment flexibility, but also takes into account the resource scheduling efficiency, thermal control safety and system maintainability, and can support the computing power evolution needs from small-scale application nodes to cloud large-scale privacy computing platforms, providing a system-level solution path for building scalable, controllable and commercial Paillier homomorphic computing infrastructure.

Claims

1. A multi-chip acceleration board system for accelerating Paillier homomorphic encryption operations, characterized in that: include: 1.1 At least two, preferably eight, homomorphic encryption accelerator chips based on the Residual Number System (RNS) and Number Theoretic Transform (NTT) architecture, used to perform homomorphic operations such as addition, multiplication, and modular exponentiation of ciphertext in parallel; 1.2 A central scheduling control module, which is used to dynamically allocate ciphertext tasks to different accelerator chips based on the bit density, operation type, or task load of the ciphertext data transmitted by the host; 1.3 An on-chip interconnect communication module, used to transmit intermediate computational data between multiple accelerator chips and support collaborative execution of operations such as modular convolution, modular inversion, and CRT reconstruction; 1.4 A host interface module, used to communicate with the host system through the PCIe bus to input ciphertext and output encryption results; The central scheduling control module supports module-based path activation, chip core number scheduling and dynamic power consumption control based on the ciphertext structure.

2. The system according to claim 1, wherein: Each of the acceleration chips supports NTT operations with a length of 1024 or 2048, the number of module bases can be configured from 4 to 16, and supports dynamic increase and decrease.

3. The system according to claim 1, wherein: The central dispatch control module includes a lightweight ciphertext feature recognition unit for analyzing the bit width distribution, encryption operation type and module base accuracy requirements of the input ciphertext to generate distribution strategy instructions.

4. The system according to claim 1, wherein: The interconnection communication module is an on-chip crossbar switch or a network interconnect structure (NoC), which supports multi-channel parallel communication and multicast data forwarding.

5. The system according to any one of claims 1 to 4, characterized in that The system further includes a shared intermediate result cache unit for temporarily storing frequency domain data or modular multiplication results generated when multiple chips execute the same ciphertext task, so as to realize multi-stage pipeline calculation.

6. The system according to any one of claims 1 to 5, characterized in that The host interface module is a PCIe Gen3 or higher speed version, and supports high-speed data exchange with domestic processor platforms including Feiteng or Kunpeng.

7. The system according to any one of claims 1 to 6, characterized in that The system supports the following three multi-chip collaborative working modes: (1) Ciphertext diversion mode: different ciphertext tasks are assigned to multiple acceleration chips for independent processing; (2) Segmented reconstruction mode: the same ciphertext is divided according to the module domain dimension and processed separately by different chips, and then the complete output is synthesized through the communication module; (3) Master-slave collaborative mode: the master chip completes the ciphertext structure recognition and scheduling, and the slave chip executes the assigned homomorphic encryption operation.

8. The system according to any one of claims 1 to 7, characterized in that When performing modular exponential operations, the acceleration chip can call a shared windowed exponentiation lookup table ROM to support fast modular multiplication with a window length of 4 to 8 bits.

9. The system according to any one of claims 1 to 8, characterized in that The central scheduling control module further supports dynamically reducing the number of activated chips or cores based on temperature thresholds or chip idle status to optimize power consumption and heat dissipation performance.

10. The system according to any one of claims 1 to 9, characterized in that The accelerator board is manufactured using 28nm to 12nm FinFET process nodes and integrates multiple acceleration chips in a pluggable or packaged manner, supporting deployment as a privacy computing acceleration module in a standard server motherboard PCIe slot.

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