Cholesteric liquid crystal display (LCD) multi-gray-scale display method and system

Abstract

The invention discloses a cholesteric phase LCD multi-gray-scale display method and system, and the method comprises the steps: decomposing each physical pixel in a cholesteric phase LCD into a plurality of sub-pixels which can be addressed independently, and distributing x gray-scale voltages to each sub-pixel, where x is greater than or equal to 1; controlling all sub-pixels in the cholesteric LCD to enter a P state; obtaining RGB pixel data corresponding to the to-be-displayed image and a target gray scale level n, and mapping the RGB pixel data to the corresponding target gray scale level n according to a pre-stored gray scale division strategy to obtain gray scale data corresponding to the RGB pixel data; and generating a control signal of the cholesteric LCD based on the gray-scale data to control the gray-scale state of each sub-pixel, acquiring a field synchronization signal, and generating a PWM signal according to the field synchronization signal to control a power circuit in the cholesteric LCD to output a gray-scale voltage matched with the gray-scale data so as to realize multi-gray-scale display of the cholesteric LCD. According to the method and the system, the gray scale level is remarkably improved under the condition of limited driving voltage.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a cholesteric LCD multi-gray scale display method and system. BACKGROUND

[0002] Cholesteric liquid crystal is widely used in electronic paper display due to its bistable characteristics. In the existing driving scheme, the panel is charged and discharged by alternately applying different voltage sequences to control the switching of liquid crystal molecules between H state (vertical alignment state), P state (planar state) or FC state (focal conic state). The traditional driving scheme controls the gray scale by a single voltage, which is limited by the response characteristics of the liquid crystal molecules. The actual achievable gray scale level is usually not more than 2 levels. The existing technology attempts to increase the number of voltage levels to improve the gray scale, but this will result in a dramatic increase in the complexity of the driving circuit and a decrease in the response speed. Therefore, how to realize high gray scale display under limited voltage levels has become a technical bottleneck in the industry. SUMMARY

[0003] To solve the technical problems in the background art, the present application provides a cholesteric LCD multi-gray scale display method and system.

[0004] The cholesteric LCD multi-gray scale display method provided by the present application comprises: Each physical pixel in the cholesteric LCD is divided into a plurality of independently addressable sub-pixels, and each sub-pixel is assigned x gray scale voltages, wherein x≥1; Control all sub-pixels in the cholesteric LCD to enter the P state; Obtain the RGB pixel data corresponding to the image to be displayed and the target gray scale level n, map the RGB pixel data to the corresponding target gray scale level n according to the pre-stored gray scale division strategy, to obtain the gray scale data corresponding to the RGB pixel data; Generate a control signal for the cholesteric LCD based on the gray scale data to control the gray scale state of each sub-pixel, obtain a field synchronization signal, and generate a PWM signal based on the field synchronization signal to control the power supply circuit in the cholesteric LCD to output a gray scale voltage matching the gray scale data, thereby realizing multi-gray scale display of the cholesteric LCD.

[0005] Preferably, the control of all sub-pixels in the cholesteric LCD to enter the P state comprises: Output the maximum driving voltage to drive the cholesteric LCD to enter the H state, and then lower the driving voltage to 0 to make all sub-pixels in the cholesteric LCD enter the P state.

[0006] Preferably, the pre-stored gray scale division strategy comprises: Divide the RGB value of 0-255 into n gray scale intervals according to the target gray scale level n, wherein n≥2.

[0007] Preferably, the mapping of the RGB pixel data to the corresponding target gray scale level n to obtain the gray scale data corresponding to the RGB pixel data specifically comprises: Comparing each RGB value in the RGB pixel data with the n gray scale intervals corresponding to the target gray scale level n one by one; Determining the gray scale interval to which each RGB value in the RGB pixel data belongs to obtain the corresponding gray scale data, wherein the gray scale data contains the gray scale interval corresponding to each RGB value in the RGB pixel data.

[0008] Preferably, when outputting the gray scale voltage corresponding to the i-th gray scale interval, the control signal corresponding to the sub-pixel matched with the gray scale interval is configured as high level, and the duration T of the gray scale voltage is configured, and the corresponding PWM signal is generated in combination with the field synchronization signal to control the power supply circuit to continuously output the gray scale voltage within the time T of scanning all the pixel points, wherein the duration T is the time of scanning all the pixel points on the screen from left to right and from top to bottom. And the process is iterated through all the gray scale intervals to complete the generation of the control signal and the PWM signal corresponding to the cholesteric LCD.

[0009] Preferably, it further comprises: Determining the gray scale voltage allocated to each sub-pixel according to the number of sub-pixels decomposed from each physical pixel and the target gray scale level n.

[0010] Preferably, when the target gray scale level n=8, the n gray scale intervals are: RGB<32 is the 1st gray scale interval, 32≤RGB<64 is the 2nd gray scale interval, 64≤RGB<96 is the 3rd gray scale interval, 96≤RGB<128 is the 4th gray scale interval, 128≤RGB<160 is the 5th gray scale interval, 160≤RGB<192 is the 6th gray scale interval, 192≤RGB<224 is the 7th gray scale interval, and 224≤RGB<256 is the 8th gray scale interval.

[0011] Preferably, when the control signal is high level, the corresponding pixel is applied with the current gray scale voltage; and when the control signal is low level, the corresponding pixel maintains the state at the last moment.

[0012] The present application provides a cholesteric LCD multi-gray scale display system, which comprises: A pixel decomposition module is configured to decompose each physical pixel in the cholesteric LCD into a plurality of independently addressable sub-pixels, and allocate x gray scale voltages to each sub-pixel, wherein x≥1. A control module is configured to control all the sub-pixels in the cholesteric LCD to enter the P state. The first processing module is configured to acquire RGB pixel data corresponding to a to-be-displayed image and a target gray scale level n, map the RGB pixel data to the corresponding target gray scale level n according to a pre-stored gray scale division strategy, and obtain gray scale data corresponding to the RGB pixel data. The signal generation module is configured to generate a control signal of the cholesteric LCD based on the gray scale data, control a gray scale state of each sub-pixel, acquire a field synchronization signal, and generate a PWM signal according to the field synchronization signal, so as to control a power supply circuit in the cholesteric LCD to output a gray scale voltage matched with the gray scale data, and realize multi-gray scale display of the cholesteric LCD.

[0013] Preferably, the system further comprises a second processing module configured to determine a gray scale voltage allocated to each sub-pixel according to a number of sub-pixels decomposed from each physical pixel and the target gray scale level n.

[0014] In the present application, the proposed cholesteric LCD multi-gray scale display method and system significantly improve the gray scale level under the condition of limited driving voltage by decomposing the pixel into multiple sub-pixels or increasing the number of gray scale voltages, and simultaneously realizing sub-pixel partition cooperative driving and dynamic gray scale mapping. In combination with the timing synchronization of the PWM signal, the stability and accuracy of the multi-gray scale display are ensured, and the level and clarity of the image display are improved. Taking a three-sub-pixel double-voltage configuration as an example, a highest 27-gray scale display can be realized, and the cost and power consumption problems caused by the need to increase voltage grading in the traditional scheme are overcome. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 FIG. 1 is a workflow schematic diagram of a cholesteric LCD multi-gray scale display method proposed in the present application; Figure 2 FIG. 2 is a voltage output structure schematic diagram of driving control signals corresponding to different gray scales of the cholesteric LCD multi-gray scale display method proposed in the present application; Figure 3 FIG. 3 is a driving control signal timing diagram of embodiment 1 of the cholesteric LCD multi-gray scale display method proposed in the present application; Figure 4 FIG. 4 is a physical pixel division schematic diagram of embodiment 2 of the cholesteric LCD multi-gray scale display method proposed in the present application; Figure 5 FIG. 5 is a driving control signal timing diagram of embodiment 2 of the cholesteric LCD multi-gray scale display method proposed in the present application; Figure 6 FIG. 6 is a system architecture schematic diagram of a cholesteric LCD multi-gray scale display system proposed in the present application. DETAILED DESCRIPTION

[0016] REFERENCE Figures 1-6The present invention proposes a cholesteric LCD multi-grayscale display method, comprising the following steps: S1. Decompose each physical pixel in the cholesteric LCD into a plurality of independently addressable sub-pixels, and assign x grayscale voltages to each sub-pixel, where x≥1.

[0017] S2. Control all sub-pixels in the cholesteric LCD to enter the P state.

[0018] In this embodiment, step S2 specifically includes: outputting the maximum driving voltage to drive the cholesteric LCD into the H state, and then reducing the driving voltage to 0 to make all sub-pixels in the cholesteric LCD enter the P state.

[0019] S3. Obtain RGB pixel data and a target grayscale level n corresponding to the image to be displayed, and map the RGB pixel data to the corresponding target grayscale level n according to a pre-stored grayscale division strategy to obtain grayscale data corresponding to the RGB pixel data.

[0020] In this embodiment, the pre-stored grayscale division strategy specifically includes: The RGB values ​​0-255 are divided into n grayscale intervals according to the target grayscale level n, where n≥2.

[0021] In this embodiment, mapping the RGB pixel data to the corresponding target grayscale level n to obtain grayscale data corresponding to the RGB pixel data specifically includes: Compare each RGB value in the RGB pixel data with the n grayscale intervals corresponding to the target grayscale level n one by one; The grayscale interval to which each RGB value in the RGB pixel data belongs is determined to obtain corresponding grayscale data, where the grayscale data includes the grayscale interval corresponding to each RGB value in the RGB pixel data.

[0022] like Figure 2 As shown in the figure, the image display sequence is to first output the maximum voltage, putting the liquid crystal in the H state, then quickly reduce the voltage, causing the H-state liquid crystal to enter the P state. After entering the P state, different voltages are output to obtain different reflectivities. In other words, after entering the P state, outputting different voltages to achieve multi-grayscale display. Because the liquid crystal is fully reflective after entering the P state, it can be used as one gray scale. Therefore, if the number of gray scales to be displayed is n, n-1 grayscale voltages are sufficient.

[0023] S4. Generate a control signal for the cholesteric LCD based on the grayscale data to control the grayscale state of each sub-pixel, and simultaneously obtain a field synchronization signal, and generate a PWM signal based on the field synchronization signal to control the power supply circuit in the cholesteric LCD to output a grayscale voltage that matches the grayscale data, thereby realizing multi-grayscale display of the cholesteric LCD.

[0024] In the embodiment, when outputting the gray scale voltage corresponding to the i-th gray scale interval, the control signal corresponding to the sub-pixel matched with the gray scale interval is configured as high level, and the duration T of the gray scale voltage is configured, and the corresponding PWM signal is generated in combination with the field synchronization signal to control the power supply circuit to continuously output the gray scale voltage within the time T of scanning all the pixel points, wherein the duration T is the time of scanning all the pixel points on the screen from left to right and from top to bottom. And traverse all the gray scale intervals in this process to complete the generation of the control signal and the PWM signal corresponding to the cholesteric LCD.

[0025] Specifically, when the control signal is high level, the current gray scale voltage is applied to the corresponding pixel; when the control signal is low level, the state at the last moment is maintained.

[0026] In the embodiment, further comprising: According to the number of sub-pixels decomposed from each physical pixel and the target gray scale level n, the value of the gray scale voltage allocated to each sub-pixel is determined.

[0027] Specifically, the sub-pixel in the P state can be regarded as one gray scale state, and after adding x gray scale voltages, the sub-pixel will have 1+x gray scales.

[0028] Specifically, the target gray scale level n is the product of the number of gray scale voltages corresponding to each sub-pixel plus one. For example, the number of sub-pixels is 3 (a\b\c), a corresponds to three gray scale voltages, b corresponds to two gray scale voltages, and c corresponds to one gray scale voltage, and the total number of gray scales is ; Specifically, when the target gray scale level n=8, the n gray scale intervals are: RGB<32 is the first gray scale interval, 32≤RGB<64 is the second gray scale interval, 64≤RGB<96 is the third gray scale interval, 96≤RGB<128 is the fourth gray scale interval, 128≤RGB<160 is the fifth gray scale interval, 160≤RGB<192 is the sixth gray scale interval, 192≤RGB<224 is the seventh gray scale interval, and 224≤RGB<256 is the eighth gray scale interval.

[0029] Embodiment 1:

[0030] Suppose the number of gray scales n to be displayed is 8, and the corresponding gray scale intervals are as follows: RGB<32 is gray scale 1; 32≤RGB<64 is gray scale 2, 64≤RGB<96 is gray scale 3, 96≤RGB<128 is gray scale 4, 128≤RGB<160 is gray scale 5, 160≤RGB<192 is gray scale 6, 192≤RGB<224 is gray scale 7, and 224≤RGB<256 is gray scale 8.

[0031] For the cholesteric LCD display, if the control signal is high, the corresponding pixel is applied with the current gray scale voltage, and if the control signal is low, the corresponding pixel keeps the state of the last moment.

[0032] As shown in Figure 3 , when the voltage output of the driving control signal is gray scale 1 voltage, the pixel point gray scale data of the RGB data less than 32 is output as high, and the rest of the pixel points are all low; similarly, when the voltage output of the driving control signal is gray scale 7 voltage, the pixel point gray scale data of the RGB data greater than or equal to 192 and less than 224 is output as high, and the rest of the pixel points are all low.

[0033] Embodiment 2:

[0034] Each physical pixel in the cholesteric LCD is composed of three sub-pixels, as shown in Figure 4 , when the gray scale voltage corresponding to the sub-pixel A is two voltages, and the gray scale voltage corresponding to the sub-pixels B and C is one voltage, 12 gray scale display can be realized; when the gray scale voltage corresponding to the sub-pixels A and B is two voltages, and the gray scale voltage corresponding to the sub-pixel C is one voltage, 18 gray scale display can be realized; when the gray scale voltage corresponding to the sub-pixels A, B and C are all two voltages, 27 gray scale display can be realized.

[0035] Taking 12 gray scale display as an example, the gray scale division and the corresponding gray scale coding are shown in the following table. Gray scale coding XXX corresponds to sub-pixels A, B and C from left to right; 100 means that sub-pixel A is black and sub-pixels B and C are white.

[0036]

[0037] Taking red data as an example, the timing circuit is shown in Figure 5 , similarly, the number of gray scale voltages can be increased to obtain more gray scales, and the number of sub-pixels can also be increased to obtain more gray scales.

[0038] Referring to Figures 1-6 , the present application provides a cholesteric LCD multi-gray scale display system, comprising: a pixel decomposition module, configured to decompose each physical pixel in the cholesteric LCD into a plurality of independently addressable sub-pixels, and assign x gray scale voltages to each sub-pixel, wherein x≥1; a control module, configured to control all sub-pixels in the cholesteric LCD to enter P state; a first processing module, configured to obtain RGB pixel data corresponding to a to-be-displayed image and a target gray scale level n, map the RGB pixel data to the corresponding target gray scale level n according to a pre-stored gray scale division strategy, to obtain gray scale data corresponding to the RGB pixel data; The signal generation module is configured to generate a control signal of the cholesteric LCD based on the gray scale data to control a gray scale state of each sub-pixel, to acquire a field synchronization signal, and to generate a PWM signal according to the field synchronization signal to control a power supply circuit in the cholesteric LCD to output a gray scale voltage matching the gray scale data, thereby realizing multi-gray scale display of the cholesteric LCD.

[0039] In the embodiment, the second processing module is further configured to determine a gray scale voltage allocated to each sub-pixel according to a number of sub-pixels decomposed from each physical pixel and a target gray scale level n.

[0040] The above merely describes a preferred embodiment of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can make equivalent replacements or changes to the technical solution and the inventive concept of the present application within the technical scope disclosed by the present application, which should be covered by the protection scope of the present application.

Claims

1. A cholesteric LCD multi-grayscale display method, characterized in that: include: Each physical pixel in the cholesteric LCD is decomposed into a plurality of independently addressable sub-pixels, and x grayscale voltages are assigned to each sub-pixel, where x ≥ 1; Control all sub-pixels in the cholesteric LCD to enter the P state; Obtaining RGB pixel data and a target grayscale level n corresponding to the image to be displayed, and mapping the RGB pixel data to the corresponding target grayscale level n according to a pre-stored grayscale division strategy to obtain grayscale data corresponding to the RGB pixel data; Based on the grayscale data, a control signal for the cholesteric LCD is generated to control the grayscale state of each sub-pixel. At the same time, a field synchronization signal is obtained and a PWM signal is generated based on the field synchronization signal to control the power supply circuit in the cholesteric LCD to output a grayscale voltage that matches the grayscale data, thereby realizing multi-grayscale display of the cholesteric LCD.

2. The cholesteric LCD multi-grayscale display method according to claim 1, wherein: The controlling all sub-pixels in the cholesteric LCD to enter the P state specifically includes: After outputting the maximum driving voltage to drive the cholesteric LCD into the H state, the driving voltage is then reduced to 0 to cause all sub-pixels in the cholesteric LCD to enter the P state.

3. The cholesteric LCD multi-grayscale display method according to claim 1, wherein: The pre-stored grayscale division strategy specifically includes: The RGB values ​​0-255 are divided into n grayscale intervals according to the target grayscale level n, where n≥2.

4. The cholesteric LCD multi-grayscale display method according to claim 3, wherein: Mapping the RGB pixel data to the corresponding target grayscale level n to obtain grayscale data corresponding to the RGB pixel data specifically includes: Compare each RGB value in the RGB pixel data with the n grayscale intervals corresponding to the target grayscale level n one by one; The grayscale interval to which each RGB value in the RGB pixel data belongs is determined to obtain corresponding grayscale data, where the grayscale data includes the grayscale interval corresponding to each RGB value in the RGB pixel data.

5. The cholesteric LCD multi-grayscale display method according to claim 1, wherein: When outputting the grayscale voltage corresponding to the i-th grayscale interval, the control signal corresponding to the sub-pixel matching the grayscale interval is configured to be high, and the duration T of the grayscale voltage is configured. In combination with the field synchronization signal, a corresponding PWM signal is generated to control the power supply circuit to continuously output the grayscale voltage within the time T after scanning all pixels, where the duration T is the time it takes to scan all pixels on the screen from left to right and from top to bottom; All grayscale intervals are traversed according to this process to complete the generation of control signals and PWM signals corresponding to the cholesteric LCD.

6. The cholesteric LCD multi-grayscale display method according to claim 1, wherein: Also includes: The value of the grayscale voltage allocated to each subpixel is determined according to the number of subpixels decomposed into each physical pixel and the target grayscale level n.

7. The cholesteric LCD multi-grayscale display method according to claim 4, wherein: When the target grayscale level n=8, the n grayscale intervals are: RGB<32 is the first grayscale interval, 32≤RGB<64 is the second grayscale interval, 64≤RGB<96 is the third grayscale interval, 96≤RGB<128 is the fourth grayscale interval, 128≤RGB<160 is the fifth grayscale interval, 160≤RGB<192 is the sixth grayscale interval, 192≤RGB<224 is the seventh grayscale interval, and 224≤RGB<256 is the eighth grayscale interval.

8. The cholesteric LCD multi-grayscale display method according to claim 5, wherein: When the control signal is at a high level, the current grayscale voltage is applied to the corresponding pixel; when the control signal is at a low level, the corresponding pixel maintains the state at the previous moment.

9. A cholesteric LCD multi-grayscale display system, characterized in that: include: A pixel decomposition module is used to decompose each physical pixel in the cholesteric LCD into a plurality of independently addressable sub-pixels and assign x grayscale voltages to each sub-pixel, where x ≥ 1; A control module controls all sub-pixels in the cholesteric LCD to enter the P state; A first processing module is configured to obtain RGB pixel data corresponding to an image to be displayed and a target grayscale level n, and map the RGB pixel data to the corresponding target grayscale level n according to a pre-stored grayscale division strategy to obtain grayscale data corresponding to the RGB pixel data; The signal generation module is used to generate a control signal for the cholesteric LCD based on the grayscale data to control the grayscale state of each sub-pixel, and at the same time obtain a field synchronization signal and generate a PWM signal based on the field synchronization signal to control the power supply circuit in the cholesteric LCD to output a grayscale voltage that matches the grayscale data, thereby realizing multi-grayscale display of the cholesteric LCD.

10. The cholesteric LCD multi-grayscale display system according to claim 9, wherein: Also includes: The second processing module is configured to determine a grayscale voltage allocated to each subpixel according to the number of subpixels decomposed from each physical pixel and a target grayscale level n.

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