Time delay circuit
By adjusting the capacitor connection mode and control voltage in the delay circuit and using MOS tubes to achieve transmission delay of different logic data, the problem of difficult circuit design in the existing technology is solved, and the stability and accuracy of logic data transmission delay are achieved.
Patent Information
- Application Number
- CN202510725623.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-30
- Publication Date
- 2025-10-17
AI Technical Summary
When existing delay circuits need to provide different transmission delays for different logic data, adjusting the inverter flip threshold increases the difficulty of circuit design and causes unstable simulation values.
By adjusting the connection mode and control voltage of the capacitor, the delay unit implemented by the MOS tube is used to change the capacitance of the capacitor to achieve the transmission delay of different logic data. The delay unit and the control voltage generation module connected in series are combined with the drive enhancement module to ensure the accuracy of signal transmission.
The transmission delay difference of different logic data can be achieved by adjusting the control voltage without changing the circuit structure, which simplifies the circuit design and improves the simulation stability and the accuracy of logic data transmission.
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Figure CN120811355A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of integrated circuits, and particularly relates to a delay circuit. BACKGROUND
[0002] The existing delay circuit is generally formed by connecting RC delay units in series, and each RC delay unit includes a standard inverter and a load capacitor. For a scenario in which different transmission delays need to be provided for different logic data, the flip threshold of the inverter is adjusted on the basis of the above scheme, the up-down pull ability is changed by changing the width-length ratio of the up-down pull transistors in the inverter, so as to change the flip threshold of the inverter.
[0003] In the actual circuit design process, it is often found that different transmission delays need to be provided for different logic data after the delay circuit formed by the standard inverter is simulated as a whole, at this time, the scheme of adjusting the flip threshold of the inverter will make the transmission speeds of the two kinds of logic data increase or decrease respectively, that is, the simulation values of the original delay circuit are all changed, if one kind is maintained unchanged and the other kind is reduced, it is necessary to continue to adjust the size of the capacitor or modify the number of RC delay units, which increases the difficulty of circuit design.
[0004] Therefore, a new delay circuit needs to be proposed to solve the above problems. SUMMARY
[0005] In view of the above problems, the purpose of the present application is to provide a delay circuit, so that different transmission delays can be generated for different logic data by adjusting the connection mode of the capacitor.
[0006] According to an aspect of the present application, a delay circuit is provided, including a delay module for transmission delay of input logic data, the delay module including at least two delay units connected in series, each delay unit including an inverter and a capacitor, the input end of the inverter receiving the input signal of the delay unit, the output end of the inverter providing the output signal of the delay unit, the first end of the capacitor being connected to the output end of the inverter, the second end of the capacitor receiving a control voltage, a control voltage generation module for adjusting the control voltage provided to each capacitor according to the value of the input logic data to adjust the capacitance of each capacitor.
[0007] Optionally, the capacitor is implemented by a MOS tube, the gate end of the MOS tube being connected to the output end of the inverter as the first end of the capacitor, and the source end and the drain end of the MOS tube being connected to receive the control voltage as the second end of the capacitor.
[0008] Optionally, the delay unit comprises a first type of delay unit in which the capacitor is implemented by an NMOS transistor, and a substrate of the NMOS transistor is connected to a ground terminal.
[0009] Optionally, the delay unit comprises a second type of delay unit in which the capacitor is implemented by a PMOS transistor, and a substrate of the PMOS transistor is connected to a power supply voltage.
[0010] Optionally, the delay module comprises a plurality of groups of delay units, each group of delay units comprises a first type of delay unit and a second type of delay unit connected in series, or a second type of delay unit and a first type of delay unit connected in series.
[0011] Optionally, the at least two delay units are both implemented by the first type of delay unit or both implemented by the second type of delay unit.
[0012] Optionally, the control voltage generation module comprises a first selection unit configured to select one of a power supply voltage and a ground voltage as a control voltage output to the first type of delay unit according to a value of the input logic data; and a second selection unit configured to select one of the power supply voltage and the ground voltage as a control voltage output to the second type of delay unit according to the value of the input logic data.
[0013] Optionally, the control voltage provided to the first type of delay unit and the control voltage provided to the second type of delay unit are different when any of the input logic data is transmitted.
[0014] Optionally, the delay circuit further comprises a drive enhancement module configured to enhance a driving capability of the delay circuit to ensure accuracy of signal transmission.
[0015] Optionally, the drive enhancement module is implemented by an even number of inverters connected in series.
[0016] The delay circuit provided by the application comprises a delay module and a control voltage generation module, the delay module is configured to perform transmission delay on input logic data, the delay module comprises at least two delay units, each delay unit comprises a capacitor and an inverter, a first end of the capacitor is connected to an output end of the inverter, and a second end of the capacitor receives a control voltage, and the control voltage generation module is configured to adjust the control voltage of each capacitor according to a value of the input logic data to adjust a capacitance of each capacitor, so that the delay circuit can perform different transmission delays on different logic data, and can make a time difference between two types of logic data be determined in proportion, thereby meeting specific synchronous or asynchronous requirements. When the circuit is designed, it can be applied to generate non-overlapping output stage control signals or used for aligning signals, etc. BRIEF DESCRIPTION OF DRAWINGS
[0017] The above and other objects, features and advantages of the present application will become more apparent from the following description when taken in conjunction with the accompanying drawings, in which:
[0018] Figures la-lb A circuit schematic diagram of a delay unit according to the prior art is shown;
[0019] Figure 2 A graph showing the equivalent capacitance of the NMOS transistor in Figure la as a function of its gate voltage is shown;
[0020] Figures 3a-3b A circuit schematic diagram of a delay unit according to an embodiment of the present application is shown;
[0021] Figure 4 A graph showing the equivalent capacitance of the NMOS transistor in Figure 3a as a function of its gate voltage under different control voltages is shown;
[0022] Figure 5 A graph showing the equivalent capacitance of the NMOS transistor in Figure 3a as a function of its gate voltage under a control voltage of 5V is shown;
[0023] Figure 6 A circuit schematic diagram of a delay circuit according to an embodiment of the present application is shown. DETAILED DESCRIPTION
[0024] Various embodiments of the present application will be described hereinafter with reference to the accompanying drawings. In the drawings, like reference numerals indicate identical or similar components. For the sake of clarity, each portion in the drawings is not drawn to scale.
[0025] It should be understood that, in the following description, "circuitry" can include a single or multiple components of hardware, programmable circuitry, state machine circuitry, and / or elements storing instructions for execution by programmable circuitry. When an element or circuitry is referred to as being "connected to" another element, or "connected between" two nodes, it can be directly coupled to the other element or directly connected between the two nodes, or intervening elements can be present. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it implies that no intervening element is present.
[0026] Also, certain terms have been used herein for the purpose of reference only and thus are not intended to be limiting. It should be understood that hardware manufacturers can use different terminology when referring to the same component. The present application is not intended to be limited to the specific components recited in the specification, but rather claims all components that are functionally equivalent.
[0027] In addition, it should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element.
[0028] Figures la-lb FIG. 1 shows a circuit diagram of a delay unit according to the prior art.
[0029] See also Figure la , which is a circuit diagram of a delay unit in the prior art. The delay unit includes an inverter INV1 and a capacitor C1, with capacitor C1 connected between the output terminal of inverter INV1 and the ground terminal. Capacitor C1 is implemented using an NMOS transistor, with its gate terminal serving as the first terminal of capacitor C1 connected to the output terminal of inverter INV1, and its source terminal and drain terminal connected as the second terminal of capacitor C1 connected to the ground terminal. Furthermore, the substrate of the NMOS transistor is connected to the ground terminal.
[0030] See also Figure lb , which is a circuit diagram of another delay unit in the prior art. The delay unit includes an inverter INV2 and a capacitor C2, wherein the capacitor C2 is connected between the power supply voltage VDD and the output terminal of the inverter INV2. Capacitor C2 is implemented using a PMOS transistor. The gate terminal of the PMOS transistor serves as the first terminal of capacitor C2, connected to the output terminal of the inverter INV2. The source and drain terminals are connected together, serving as the second terminal of capacitor C2, connected to the power supply voltage VDD. Furthermore, the substrate of the PMOS transistor is connected to the power supply voltage VDD.
[0031] by Figure la Taking the size of the NMOS tube in the figure as 10um*10um as an example, the equivalent capacitance of the NMOS tube changes with the gate voltage of the NMOS tube as shown in the figure. Figure 2 As shown. Figure 2It can be seen that in the process of the gate voltage of the NMOS transistor becoming high, the equivalent capacitance of the NMOS transistor first decreases and then gradually increases, and when the gate voltage of the NMOS transistor is greater than 1.5V, the equivalent capacitance of the NMOS transistor is basically unchanged; in the process of the gate voltage of the NMOS transistor becoming low, the equivalent capacitance of the NMOS transistor is first unchanged, and when the gate voltage of the NMOS transistor decreases to below 1.5V, the equivalent capacitance of the NMOS transistor significantly decreases, and then increases. If the change of the rate of change of the gate voltage of the NMOS transistor is not considered, the equivalent capacitance of the delay unit when transmitting data 0 and 1 is the same.
[0032] Figures 3a-3b A circuit schematic diagram of a delay unit according to an embodiment of the present application is shown.
[0033] The delay unit provided by the embodiment of the present application comprises an inverter INV and a capacitor C, an input end of the inverter INV receives an input signal of the delay unit, an output end of the inverter INV provides an output signal of the delay unit, a first end of the capacitor C is connected to the output end of the inverter INV, and a second end of the capacitor C receives a control voltage V_CTRL, and the voltage value of the control voltage V_CTRL affects the capacitance of the capacitor C. Wherein, the delay unit can adopt the first type delay unit 121, or can adopt the second type delay unit 122.
[0034] Referring to Figure 3a In the first type delay unit 121, the capacitor C is implemented by an NMOS transistor, the gate end of the NMOS transistor is connected to the first end of the capacitor C and connected to the output end of the inverter INV, and the source end and the drain end are connected to the second end of the capacitor C and receive the control voltage V_CTRL_N. Further, the substrate of the NMOS transistor is connected to the ground end.
[0035] Referring to Figure 3b In the second type delay unit 122, the capacitor C is implemented by a PMOS transistor, the gate end of the PMOS transistor is connected to the first end of the capacitor C and connected to the output end of the inverter INV, and the source end and the drain end are connected to the second end of the capacitor C and receive the control voltage V_CTRL_P. Further, the substrate of the PMOS transistor is connected to the power supply voltage VDD.
[0036] Similarly, taking the case that the capacitor C is implemented by an NMOS transistor and the size of the NMOS transistor is 10um*10um as an example, when the second end of the capacitor C receives different control voltages V_CTRL_N, the schematic diagram of the equivalent capacitance of the NMOS transistor changing with the gate voltage is as shown in Figure 4 Figure 4 It can be seen that, in the process of the gate voltage of the NMOS transistor increasing, when the control voltage V_CTRL_N is 0V-5V, the equivalent capacitance of the NMOS transistor decreases first and then increases with the change of the gate voltage, and the higher the control voltage V_CTRL_N, the higher the gate voltage corresponding to the minimum point of the equivalent capacitance of the NMOS transistor.
[0037] The schematic diagram of the equivalent capacitance of the NMOS transistor changing with the gate voltage when the control voltage V_CTRL_N is 5V is shown in FIG. 4. Figure 5 Figure 5 It can be seen that, in the process of the gate voltage of the NMOS transistor decreasing, the equivalent capacitance of the NMOS transistor first reaches a minimum value and then slowly increases. Comparing FIG. 3 and FIG. 4, it can be seen that, when the gate voltage of the NMOS transistor changes between -7V and 7V, the average value of the equivalent capacitance of the NMOS transistor when the control voltage V_CTRL_N of 5V is provided to the NMOS transistor is less than the average value of the equivalent capacitance of the NMOS transistor when the control voltage V_CTRL_N of 0V is provided to the NMOS transistor, and accordingly, providing the control voltage V_CTRL_N with different voltage values to the NMOS transistor when the delay unit transmits the logic data 0 and 1 can make the transmission delay of the logic data 0 and the transmission delay of the logic data 1 different. Figure 2 Figure 5 If the control voltage V_CTRL_N of 0V is provided to the second end of the capacitor C when the gate voltage of the NMOS transistor increases, and the control voltage V_CTRL_N of 5V is provided to the second end of the capacitor C when the gate voltage of the NMOS transistor decreases, the equivalent capacitance of the delay unit in the process of the gate voltage of the NMOS transistor increasing is the same as that of the prior art, and the equivalent capacitance of the delay unit in the process of the gate voltage of the NMOS transistor decreasing is less than that of the prior art, so that the delay time when the gate voltage of the NMOS transistor decreases is less than the delay time when the gate voltage of the NMOS transistor increases.
[0038] Therefore, providing the control voltage V_CTRL_N of 0V to the second end of the capacitor C when the NMOS transistor transmits the logic data 1 and providing the control voltage V_CTRL_N of 5V to the second end of the capacitor C when the NMOS transistor transmits the logic data 0 can make the equivalent capacitance of the NMOS transistor different when the delay unit transmits the logic data 0 and 1, and accordingly, the transmission delay of the delay unit when transmitting the logic data 0 and 1 is also different, so that without changing the circuit structure of the conventional delay unit, only by changing the control voltage V_CTRL_N provided to the capacitor C, the transmission delay of the logic data 1 can be unchanged and only the transmission delay of the logic data 0 can be reduced.
[0039] Therefore, providing the control voltage V_CTRL_N of 0V to the second end of the capacitor C when the NMOS transistor transmits the logic data 1 and providing the control voltage V_CTRL_N of 5V to the second end of the capacitor C when the NMOS transistor transmits the logic data 0 can make the equivalent capacitance of the NMOS transistor different when the delay unit transmits the logic data 0 and 1, and accordingly, the transmission delay of the delay unit when transmitting the logic data 0 and 1 is also different, so that without changing the circuit structure of the conventional delay unit, only by changing the control voltage V_CTRL_N provided to the capacitor C, the transmission delay of the logic data 1 can be unchanged and only the transmission delay of the logic data 0 can be reduced.
[0040] Further, if only the transmission delay of the logic data 1 needs to be reduced, only the control voltage V_CTRL_N of 5V is provided to the second end of the capacitor C when the voltage at the gate of the NMOS transistor is raised, and the control voltage V_CTRL_N of 0V is provided to the second end of the capacitor C when the voltage at the gate of the NMOS transistor is lowered. Thus, two different delay schemes can be realized by using the first type of delay unit 121.
[0041] It can be understood that the capacitor C has similar characteristics when implemented by the PMOS transistor as when implemented by the NMOS transistor, and thus the delay unit can have different transmission delays when transmitting the logic data 0 and 1 by changing the control voltage V_CTRL_P provided to the capacitor C, so as to realize two different delay schemes.
[0042] Figure 6 A circuit schematic diagram of a delay circuit according to an embodiment of the present application is shown.
[0043] Referring to Figure 6 The delay circuit 100 provided by the embodiment of the present application includes a control voltage generation module 110, a delay module 120, and a driving enhancement module 130.
[0044] The delay module 120 is configured to delay the input logic data. The delay module 120 includes at least one delay unit, and the at least two delay units are connected in series. The at least two delay units can all be the first type of delay unit 121, can all be the second type of delay unit 122, or can be both the first type of delay unit 121 and the second type of delay unit 122. The delay module 120 can obtain a power function of the number of delay units by the combination of the first type of delay unit 121 and the second type of delay unit 122 and the collocation of the four delay schemes.
[0045] The control voltage generation module 110 is configured to adjust the control voltage V_CTRL provided to each capacitor C according to the value of the input logic data, so as to adjust the capacitance of each capacitor C.
[0046] In actual application, in the circuit design stage, the control voltage V_CTRL provided to the capacitor C can be continuously adjusted according to the delay requirement of the logic data 1 and 0 until the preset delay effect is achieved, and then the switching logic of the control voltage generation module 110 is designed according to the working voltage V_CTRL of each capacitor C when the preset delay effect is achieved.
[0047] The drive enhancement module 130 is used to enhance the driving capability of the delay circuit 100 to ensure the accuracy of logical data transmission. The input of the drive enhancement module 130 is connected to the output of the delay module 120, and the output provides the output signal of the delay circuit 100. The drive enhancement module 130 is implemented using an even number of inverters of increasing size connected in series. For example, the drive enhancement module 130 is implemented using two inverters connected in series.
[0048] In one example, if Figure 6 As shown, the delay module 120 includes multiple groups of delay units, which are connected in series, and each group of delay units includes a first type of delay unit 121 and a second type of delay unit 122 connected in series. In other examples, the delay module 120 includes multiple groups of delay units, which are connected in series, and each group of delay units includes a second type of delay unit 122 and a first type of delay unit 121 connected in series.
[0049] It is understandable that the connection method of the first type delay unit 121 and the second type delay unit 122 in the above-mentioned delay module 120 is only exemplary. In actual applications, the first type delay unit 121 and the second type delay unit 122 can also be connected in series in other ways, and this application does not make specific limitations.
[0050] In one example, if Figure 6 As shown, the control voltage generating module 110 includes a selecting unit 111 and a selecting unit 112. The selecting unit 111 is used to select one of the power supply voltage VDD and the ground voltage GND according to the value of the input logic data as the control voltage V_CTRL_N to be output to the first type delay unit 121. The selecting unit 112 is used to select one of the power supply voltage VDD and the ground voltage GND according to the value of the input logic data as the control voltage V_CTRL_P to be output to the second type delay unit 122. When transmitting any input logic data, the control voltage V_CTRL_N provided to the first type delay unit 121 and the control voltage V_CTRL_P provided to the second type delay unit 122 have different voltage values. For example, when the input logic data is 1, the control voltage V_CTRL_N output by the selection unit 111 is the power supply voltage VDD, and the control voltage V_CTRL_P output by the selection unit 112 is the ground voltage GND; when the input logic data is 0, the control voltage V_CTRL_N output by the selection unit 111 is the ground voltage GND, and the control voltage V_CTRL_P output by the selection unit 112 is the power supply voltage VDD. At this time, if the delay module 120 adopts Figure 6 In the structure, the transmission delay of the delay module 120 for the logic data 1 is less than the transmission delay for the logic data 0, which only reduces the transmission delay of the logic data 1 compared to the prior art.
[0051] Further, Figure 6 The control voltage generation module 110 shown can only make the transmission delays of logic data 1 and 0 different as a whole, and make the transmission delays of logic data 0 and 1 have a preset ratio of transmission delay difference, but if alignment of two transmission delays of different logic data is needed, or more fine adjustment is needed, Figure 6 The control voltage generation module 110 shown cannot achieve this. Therefore, in actual application, the control voltage generation module 110 needs to set different control logics according to different values.
[0052] For example, when designing a circuit with the delay circuit 100, the inverters in the delay module 120 use standard inverters, and the capacitors also use capacitors of the same size. Since the time generated by input logic data 0 and 1 can be different, and the rise and fall times of the inverters can also be different, the transmission delay of the delay circuit 100 when transmitting logic data 0 is x, and the transmission delay when transmitting logic data 1 is y, and x < y. When the delay module 120 uses the structure shown, Figure 6 When the structure shown is used, if more fine adjustment of the transmission delays of logic data 0 and 1 is needed to obtain a smaller y equal to x, when the input logic data is 1, the control voltage V_CTRL_N of a capacitor C implemented by an NMOS transistor can be switched to the power supply voltage VDD first, and the transmission delay reduction time Δy1 of the input logic data 1 at this time is calculated, and then the number of capacitors C whose control voltage V_CTRL_N needs to be switched to the power supply voltage VDD is calculated by (y-x) / Δy1. If the number of capacitors C implemented by an NMOS transistor is insufficient, the control voltage V_CTRL_P of a capacitor C implemented by a PMOS transistor can be switched to the ground voltage, and the transmission delay reduction time Δy2 of the input logic data 1 at this time is calculated, and then how many capacitors C implemented by a PMOS transistor whose control voltage V_CTRL_P needs to be switched to the ground voltage is calculated, and then the control voltage generation circuit 110 provides the corresponding control voltage V_CTRL for each capacitor C, so that the transmission delays of the delay circuit 100 when transmitting logic data 1 and 0 are the same. This adjustment scheme does not need to repeatedly adjust the size of the standard inverter and the load capacitor, reduces the workload of circuit design, ensures the reusability of the delay unit, reduces the workload of layout design, and the ratio of the transmission delays of the two logic data is relatively stable through Monte Carlo simulation.
[0053] In summary, the delay circuit 100 of the present application can make the transmission delays of two kinds of logic data have a preset time difference by only changing the transmission delay of one kind of logic data, simplifying the iterative process of design, and obtaining a more stable ratio of the transmission delays of the two kinds of logic data.
[0054] In accordance with the practices of the present invention, these embodiments have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the present invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teachings. It is intended that the scope of the present invention be limited not with this detailed description, but rather by the claims appended hereto, with respect to the scope of the present invention.
Claims
1. A delay circuit comprising: A delay module is used to delay the transmission of input logic data. The delay module includes at least two delay units connected in series. Each delay unit includes an inverter and a capacitor. The input end of the inverter receives the input signal of the delay unit, and the output end of the inverter provides the output signal of the delay unit. The first end of the capacitor is connected to the output end of the inverter, and the second end of the capacitor receives the control voltage. The control voltage generating module is used to adjust the control voltage provided to each capacitor according to the value of the input logic data, so as to adjust the capacitance of each capacitor.
2. The delay circuit according to claim 1, wherein: The capacitor is implemented by a MOS transistor, the gate end of the MOS transistor serves as the first end of the capacitor connected to the output end of the inverter, and the source and drain ends of the MOS transistor are connected to serve as the second end of the capacitor to receive the control voltage.
3. The delay circuit according to claim 2, wherein: The delay unit includes a first type of delay unit in which the capacitor is implemented by an NMOS tube, and the substrate of the NMOS tube is connected to the ground end.
4. The delay circuit according to claim 3, wherein: The delay unit includes a second type of delay unit in which the capacitor is implemented by a PMOS tube, and the substrate of the PMOS tube is connected to the power supply voltage.
5. The delay circuit according to claim 4, wherein: The delay module includes multiple groups of delay units, and each group of delay units includes a first type of delay unit and a second type of delay unit connected in series, or a second type of delay unit and a first type of delay unit connected in series.
6. The delay circuit according to claim 4, wherein: The at least two delay units are both first-type delay units or are both second-type delay units.
7. The delay circuit according to claim 5 or 6, wherein: The control voltage generating module includes: a first selection unit, configured to select one of a power supply voltage and a ground voltage as a control voltage to be output to the first type delay unit according to a value of the input logic data; The second selection unit is configured to select one of the power supply voltage and the ground voltage as a control voltage to be output to the second-type delay unit according to the value of the input logic data.
8. The delay circuit according to claim 7, wherein: When transmitting any of the input logic data, the control voltages provided to the first type of delay unit and the control voltages provided to the second type of delay unit are different.
9. The delay circuit according to claim 1, further comprising: The driving enhancement module is used to enhance the driving capability of the delay circuit to ensure the accuracy of signal transmission.
10. The delay circuit according to claim 9, wherein: The driving enhancement module is implemented by an even number of inverters connected in series.