Method of forming metal liner for interconnect structure

Abstract

A method of forming a device includes forming a dielectric layer on a substrate, the dielectric layer including at least one feature defining a gap, the gap including sidewalls and a bottom. The method includes selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap. The SAM comprises a hydrocarbon having the formula H-C = C-R, where R is an alkyl linear or aryl group comprising from 1 to 20 carbon atoms, or having the formula R 'C = CR ", where R' and R" independently comprise an alkyl linear or aryl group comprising from 1 to 20 carbon atoms. A barrier layer is formed on the SAM and then a metal liner is selectively deposited on the barrier layer. After selectively depositing a metal liner on the barrier layer, the SAM is removed.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to methods of forming a metal liner for an interconnect structure. More specifically, embodiments of the present disclosure are directed to methods of selectively depositing a metal liner layer. BACKGROUND

[0002] As transistors and interconnects are scaled to 3 nm nodes and below, a variety of challenges impede power and performance improvements. Interconnects include metal lines that transport current within the same device layer and metal vias that transport current between layers. Reduction in pitch narrows the width of both and increases resistance, and also increases voltage drop across the entire circuit, throttling circuit speed and increasing power dissipation.

[0003] While transistor performance improves with scaling, interconnect metal does not. As size shrinks, interconnect via resistance can increase by 10x. The increase in interconnect via resistance can result in resistive-capacitive (RC) delay, degrading performance and increasing power consumption. Conventional copper interconnect structures include a barrier layer and / or a metal liner deposited on the gap sidewalls, which provide a via with sidewalls made of a dielectric material, providing good adhesion and preventing copper diffusion into the dielectric layer. The barrier layer can often be the largest contributor to via resistance due to high resistivity. Previous methods have focused on reducing the thickness of the barrier layer or finding a barrier layer with lower resistivity to reduce via resistance. Increased via resistance remains a problem, particularly in smaller features where the percentage of via volume formed by the barrier layer on the sidewalls is increasing.

[0004] A metal liner deposited on the barrier layer adheres to the barrier layer and facilitates subsequent filling of copper (Cu) in the gap between the sidewalls. Current methods have focused on selectively growing the metal liner on the via sidewalls with high selectivity relative to the via bottom in an attempt to reduce via resistance and copper corrosion, although selective growth remains a challenge.

[0005] Accordingly, there is a need for methods for depositing layers of material that improve interconnect performance, e.g., reduce via resistance and improve deposition selectivity. SUMMARY

[0006] Embodiments of the present disclosure are directed to methods for forming microelectronic devices. In one or more embodiments, the method includes forming a dielectric layer on a substrate, the dielectric layer including at least one feature defining a gap, the gap including sidewalls and a bottom; selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap, the SAM including or consisting essentially of a hydrocarbon having the chemical formula HC≡CR, where R is an alkyl linear or aryl group containing 1 to 20 carbon atoms, or having the chemical formula R'C=CR", where R' and R" independently include alkyl linear or aryl groups containing 1 to 20 carbon atoms; forming a barrier layer on the SAM; selectively depositing a metal liner on the barrier layer on the sidewalls, the metal liner being deposited to a thickness greater than the thickness of the metal liner deposited on the sidewalls; removing the SAM after selectively depositing the metal liner on the barrier layer; and performing a gap fill process on the metal liner. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to understand in detail the manner in which the above-described features of the present disclosure are achieved, reference may be made to a more particular description of the disclosure, briefly summarized above, with reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only typical embodiments of the disclosure and are therefore not to be considered limiting of its scope, as the disclosure may admit to other equally effective embodiments.

[0008] FIG. 1A shows a portion of a microelectronic device during a manufacturing stage, one or more embodiments of the present disclosure having a passivation layer formed on the bottom of the gap;

[0009] FIG. 1B Shown in the formation FIG. 1A a barrier layer formed after the passivation layer shown;

[0010] FIG. 1C Shown in FIG. 1B a liner layer formed on the barrier layer formed in the step of:

[0011] FIG. 1D Shown in FIG. 1C a second liner layer formed on the liner layer formed in the step of:

[0012] FIG. 1E Shown in the formation FIG. 1D The optional second liner layer is removed after FIG. 1A A passivation layer formed in

[0013] FIG. 2AA portion of a microelectronic device during fabrication stages having a first passivation layer formed on a gap bottom according to one or more embodiments of the present disclosure is shown;

[0014] FIG. 2B A barrier layer formed on the gap of FIG. 2A is shown;

[0015] FIG. 2C Removal of the passivation layer formed in FIG. 2A is shown;

[0016] FIG. 2D A second passivation layer formed on the barrier layer formed in FIG. 2B is shown;

[0017] FIG. 2E A liner layer on the barrier layer formed in FIG. 2B is shown;

[0018] FIG. 2F A second liner layer formed on the liner layer formed in FIG. 2E is shown;

[0019] FIG. 2G The structure after removal of the second passivation layer in FIG. 2F is shown;

[0020] FIG. 3 A process flow diagram of a method of fabricating a microelectronic device according to one or more embodiments of the present disclosure is shown; and

[0021] FIG. 4 A process flow diagram of a method of fabricating a microelectronic device according to one or more embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0022] Before several exemplary embodiments of the present disclosure are described, it is to be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description. The present disclosure is capable of other embodiments and is practiced or carried out in various ways.

[0023] As used in this specification and the appended claims, the terms "substrate" and "wafer" are used interchangeably, and both refer to a surface upon which a process acts or to a portion of a surface upon which a process acts. Those skilled in the art will further appreciate that a reference to a substrate can also refer to only a portion of the substrate unless the context clearly indicates otherwise. Additionally, reference to depositing on a substrate can mean both a bare substrate and a substrate with one or more film or features deposited or formed thereon.

[0024] As used herein, "substrate" refers to any substrate or material surface formed of material on which film processing is performed during a fabrication process. For example, depending on the application, the substrate surface on which processing is performed can include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon doped silicon oxides, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other material such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, without limitation, semiconductor wafers. Substrates can be exposed to pre-processing treatments for polishing, etching, reducing, oxidizing, hydroxylating (or otherwise producing or grafting target chemical moieties to impart chemical functionality), annealing, and / or baking the substrate surface. In addition to film processing directly on the substrate's own surface, in the present disclosure, any of the film processing steps disclosed can be performed on an underlayer formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such underlayer as the context indicates. Thus, for example, where a film / layer or partial film / layer has been deposited onto a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface. The contents of a given substrate surface will depend on what films are to be deposited and the particular chemistry used.

[0025] As used in the present specification and in the appended claims, the terms "reactive gas," "precursor," "reactant," and the like are used interchangeably to mean a gas comprising a species that reacts with a substrate surface. For example, a first "reactive gas" can simply adsorb onto the surface of a substrate, and can be used in further chemical reactions with a second reactive gas.

[0026] Some embodiments of the present disclosure provide methods for improving interconnect performance. Interconnects include metal lines that transport current within the same device layer and metal vias that transport current between layers. These lines and vias are formed in gaps within a device with a conductive metal such as copper or cobalt. In one or more embodiments, a dielectric layer includes at least one feature that defines a gap, the gap including a sidewall and a bottom. In one or more embodiments, the gap includes a metal line and a metal via. In one or more embodiments, the metal line has a sidewall and a bottom. In one or more embodiments, the metal via has a sidewall and a bottom. As used in the present specification and in the appended claims, a reference to "gap bottom" is intended to mean the metal via bottom closest to the substrate, unless otherwise indicated.

[0027] Embodiments of the present disclosure provide methods of forming interconnect structures in microelectronic device fabrication. In one or more embodiments, the microelectronic devices described herein include at least one top interconnect structure that is interconnected with at least one bottom interconnect structure. Embodiments of the present disclosure provide microelectronic devices and methods of fabricating microelectronic devices that improve the performance of the interconnects, for example, by reducing via resistance.

[0028] Reference is made herein to FIGS. 1A-1E and FIGS. 2A-2G Methods of forming microelectronic devices are described. FIG. 3 is a flowchart of an exemplary method of forming a microelectronic device. FIGS. 1A-1E is a flowchart of an exemplary method of forming a microelectronic device. FIG. 4 is a flowchart of an exemplary method of forming a microelectronic device. FIGS. 2A-2G is a flowchart of an exemplary method of forming a microelectronic device.

[0029] Reference is made to FIGS. 1A-1D , a portion of a microelectronic device 100 during fabrication stages is illustrated. In FIG. 1A , the microelectronic device 100 includes a substrate 110, a barrier layer 120 on the substrate 110, a metal layer 130 on the barrier layer 120, a conductive fill gap 140, an aluminum oxide etch stop layer 142, a dielectric layer 145 on the aluminum oxide etch stop layer 142, the dielectric layer 145 including at least one feature defining a gap 146, the gap 146 including sidewalls 148 and a bottom 149. According to one or more embodiments, a passivation layer (e.g., a self-assembled monolayer (SAM)) 150 is formed on the bottom 149 of the gap. It should be appreciated that, in one or more embodiments, the conductive fill gap 140 forms a metal line that transports current within the same device layer.

[0030] In one or more embodiments, the substrate 110 is a wafer, such as a semiconductor substrate. In one or more embodiments, the substrate 110 is an etch stop layer on a wafer. In one or more embodiments, the substrate 110 is an aluminum oxide etch stop layer on a wafer. In one or more embodiments, the barrier layer 120 includes tantalum nitride (TaN). In one or more embodiments, the barrier layer 120 includes tantalum nitride (TaN) formed by ALD. In one or more embodiments, the metal layer 130 includes one or more of ruthenium (Ru), cobalt (Co), molybdenum (Mo), or tantalum (Ta). In one or more embodiments, the metal layer 130 includes one or more of a single layer of ruthenium (Ru) or a single layer of cobalt (Co). In one or more embodiments, a portion of the metal layer 130 is etched. In one or more embodiments, the SAM 150 is deposited on the portion of the metal layer 130 that is etched. In one or more embodiments, the electrically conductive gap fill 140 includes one or more of copper (Cu) or cobalt (Co). In one or more embodiments, the etch stop layer 142 includes one or more of aluminum oxide, silicon nitride, and aluminum nitride.

[0031] In one or more embodiments, the dielectric layer 145 is a low dielectric constant (k) dielectric layer. In certain embodiments, the dielectric layer 145 includes silicon oxide (SiO x ) with a k value of less than about 5. In one or more embodiments, the dielectric layer 145 includes SiO x H y (CH z ) with a k value of less than about 5. Further embodiments provide that the dielectric layer 145 includes porous or carbon-doped SiO x . In some embodiments, the dielectric layer 145 is a porous or carbon-doped SiO x layer with a k value of less than about 5. In other embodiments, the dielectric layer 145 is a multi-layer structure. For example, in one or more embodiments, the dielectric layer 145 includes a multi-layer structure having one or more of a dielectric layer, an etch stop layer, and a hard mask layer.

[0032] In one or more embodiments, the dielectric layer 145 includes at least one feature defining a gap 146 including sidewalls 148 and a bottom 149. The figures illustrate a substrate with a single feature for illustrative purposes; however, one of skill in the art will appreciate that there can be more than one feature. The shape of the feature can be any suitable shape including, but not limited to, a trench, a cylindrical via (which when filled with metal transports current between layers), and a line that transports current within the same device layer. In some embodiments, the feature defines a gap 146 in the dielectric layer 145. In some embodiments, the gap 146 defines a via portion 146V and a line portion 146L, although the illustrated embodiments are not intended to be limiting. As used herein, the term "feature" means any intentional surface irregularity. Suitable examples of features include, but are not limited to, a trench having a top, two sidewalls, and a bottom, a peak having a top and two sidewalls. The feature can have any suitable aspect ratio (ratio of the depth of the feature to the width of the feature). In some embodiments, the aspect ratio is greater than or equal to about 5: 1, 10: 1, 15: 1, 20: 1, 25: 1, 30: 1, 35: 1, or 40: 1.

[0033] In one or more embodiments, the SAM 150 is formed on the metal layer 130. In one or more embodiments, the SAM 150 is deposited by exposing the bottom 149 of the gap to a hydrocarbon carried by argon (Ar) gas. In one or more embodiments, the SAM 150 includes an unsaturated hydrocarbon.

[0034] It has been found that using an unsaturated hydrocarbon SAM 150 can improve Cu interconnect via resistance by selectively depositing a metal liner on the via sidewalls rather than the via bottom to minimize via bottom metal liner growth. Embodiments of the present disclosure provide a method of selectively growing a metal liner (such as a Ru liner) on the via sidewalls relative to the via bottom with high selectivity (e.g., a ratio of sidewall liner thickness to bottom liner thickness greater than 3, greater than 4, greater than 5, greater than 6, greater than 7, greater than 8, greater than 9, or greater than 10). The choice of SAM chemistry and process enables the metal (e.g., Ru) to only nucleate and grow at the via sidewalls and not on the via bottom. Growing a thin metal (e.g., Ru) or no metal on the via bottom reduces via resistance and Cu corrosion. Other liner materials include cobalt (Co), molybdenum (Mo), and tantalum (Ta). In particular embodiments, the SAM chemistry / process can inhibit metal liner growth at the via bottom (e.g., less than 10 Angstroms, less than 5 Angstroms, less than 4 Angstroms, less than 3 Angstroms, less than 2 Angstroms, or less than 1 Angstrom) and maintain metal liner growth at the via sidewalls (e.g., 5 Angstroms or more, or 10 Angstroms or more). The SAM chemistry helps achieve selectivity on the via bottom (e.g., Cu, Co, W) relative to the via sidewall (e.g., TaN).

[0035] According to one or more embodiments, selectively depositing the SAM includes exposing the bottom 149 of the gap 146 to a hydrocarbon having a chemical formula H-C≡C-R, where R is an alkyl straight chain or aryl group comprising 1 to 20 carbon atoms, or having a chemical formula R’C=CR”, where R’ and R” independently comprise an alkyl straight chain or aryl group comprising 1 to 20 carbon atoms.

[0036] In some embodiments, the substrate is immersed in a vapor of the unsaturated hydrocarbon. In some embodiments, the process conditions for exposing the substrate to the unsaturated hydrocarbon are controllable.

[0037] In some embodiments, the pressure of the processing chamber is controlled. The pressure of the processing chamber can be any suitable pressure for forming the barrier layer. In some embodiments, the pressure of the processing chamber is maintained at less than or equal to about 80 Torr, less than or equal to about 70 Torr, less than or equal to about 60 Torr, less than or equal to about 50 Torr, less than or equal to about 40 Torr, less than or equal to about 30 Torr, less than or equal to about 20 Torr, less than or equal to about 15 Torr, less than or equal to about 10 Torr, or less than or equal to about 5 Torr. In some embodiments, the pressure of the processing chamber is maintained at about 10 Torr, about 20 Torr, about 30 Torr, about 40 Torr, or about 50 Torr.

[0038] In one or more embodiments, an argon (Ar) gas flow is configured to carry the unsaturated hydrocarbon from the container to the processing chamber. In some embodiments, the flow rate of the argon (Ar) gas configured to carry the unsaturated hydrocarbon to the processing chamber is controlled. The flow rate of the argon (Ar) gas can be any suitable flow rate for forming the passivation layer. In some embodiments, the flow rate of the argon (Ar) gas is in a range from about 50 seem to about 100 seem, or in a range from about 75 seem to about 100 seem. In one or more embodiments, the flow rate of the argon (Ar) gas is about 600 seem. In some embodiments, the flow rate of the argon (Ar) gas is less than or equal to about 600 seem, less than or equal to about 500 seem, less than or equal to about 400 seem, less than or equal to about 300 seem, less than or equal to about 250 seem, less than or equal to about 200 seem, less than or equal to about 150 seem, less than or equal to about 100 seem, less than or equal to about 75 seem, or less than or equal to 50 seem.

[0039] In some embodiments, the immersion time period of the unsaturated hydrocarbon exposure to the substrate is controlled. The immersion time period can be any suitable time period for forming the barrier layer. In some embodiments, the immersion time period is 1 to 200 seconds, such as 1 to 10 seconds, greater than or equal to about 10 seconds, greater than or equal to about 20 seconds, greater than or equal to about 30 seconds, greater than or equal to about 45 seconds, greater than or equal to about 60 seconds, greater than or equal to about 80 seconds, greater than or equal to about 120 seconds, greater than or equal to about 150 seconds, or greater than or equal to about 200 seconds. In some embodiments, the immersion time period is about 60 seconds. In some embodiments, the immersion time period is about 200 seconds.

[0040] In one or more embodiments, when the unsaturated hydrocarbon is in a container, such as an ampoule or a cylinder, the unsaturated hydrocarbon is in a liquid phase, the unsaturated hydrocarbon is transported from the container to the chamber in a carrier gas. In some embodiments, the unsaturated hydrocarbon is in a saturated gas phase in the container when the container has a pressure of about 0.1 Torr. In one or more embodiments, the temperature of the container is lower than the temperature in the processing chamber. In one or more embodiments, a carrier gas, such as argon (Ar) gas, carries the saturated gas phase unsaturated hydrocarbon from the container to the processing chamber. In some embodiments, the temperature of the processing chamber is controlled during the exposure to the unsaturated hydrocarbon. The temperature of the processing chamber can also be referred to as the operating temperature. In some embodiments, the temperature of the processing chamber is in a range from about 150 °C to about 400 °C, such as 200 °C to about 300 °C. In some embodiments, the temperature of the processing chamber is less than or equal to about 300 °C, less than or equal to about 275 °C, less than or equal to about 250 °C, less than or equal to about 225 °C, or less than or equal to about 200 °C.

[0041] Referring to FIG. 1B , a barrier layer 160 is illustrated on the SAM 150, i.e., over the sidewall 148. In one or more embodiments, the barrier layer 160 has the same characteristics as the barrier layer 120. In one or more embodiments, the barrier layer 160 is not formed on the bottom 149 of the gap 146. In one or more embodiments, the deposition of the barrier layer 160 is substantially conformal when the SAM 150 is not present. In one or more embodiments where the SAM 150 is not present, the barrier layer 160 is formed on the sidewall 148 and the bottom 149 of the gap 146. As used herein, a layer that is “substantially conformal” refers to a layer that has a thickness that is approximately the same everywhere, e.g., on the top, middle, and bottom of the sidewall 148 and on the bottom 149 of the gap 146. A layer that is substantially conformal has a thickness that varies by less than or equal to about 5%, 2%, 1%, or 0.5%. In one or more embodiments, the barrier layer 160 is selectively deposited on at least a portion of the sidewall 148. In one or more embodiments not shown, the barrier layer 160 is selectively deposited on at least a portion of the bottom 149. In one or more embodiments, the barrier layer 160 can cover the entire sidewall 148.

[0042] In one or more embodiments, the barrier layer 160 is selectively deposited by atomic layer deposition (ALD) and has a thickness in a range from about 2 Angstroms to about 10 Angstroms. In some embodiments, the barrier layer 160 is deposited in a single ALD cycle. In other embodiments, the barrier layer 160 is deposited in 1 to 20 ALD cycles. In one or more embodiments, each cycle of the 1 to 20 ALD cycles is configured to deposit the barrier layer 160 having a thickness of about 0.5 Angstroms.

[0043] In one or more embodiments, when the barrier layer 160 is formed on the bottom 149 and the sidewall 148, a ratio of a thickness of the barrier layer 160 thickness on the sidewall 148 to a thickness of the barrier layer 160 thickness on the bottom 149 is greater than 6. In one or more cases, the ratio is greater than 5, greater than 4, greater than 3, greater than 2, or greater than 1. In one or more embodiments, the thickness of the barrier layer 160 on the sidewall 148 is in a range from 5 Angstroms to 20 Angstroms when the SAM 150 is present. In one or more embodiments, the thickness of the barrier layer 160 on the bottom 149 is less than or equal to 5 Angstroms. In one or more embodiments, the thickness of the barrier layer 160 on the bottom 149 is less than or equal to 4 Angstroms, less than or equal to 3 Angstroms, less than or equal to 2 Angstroms, or less than or equal to 1 Angstrom. In one or more embodiments, the barrier layer 160 is not formed on the bottom 149.

[0044] Referring to FIG. 1C , a first metal liner 170 is illustrated FIG. 1B on the barrier layer 160 shown. In one or more embodiments, the first metal liner 170 has the same properties as the metal layer 130. In one or more embodiments, the metal liner 170 is selectively deposited on the sidewall 148 of the microelectronic device. In one or more embodiments, the first metal liner 170 includes one or more of ruthenium (Ru), cobalt (Co), molybdenum (Mo), or tantalum (Ta). In one or more embodiments, the first metal liner 170 includes one or more of a single layer of ruthenium (Ru) or a single layer of cobalt (Co). In one or more embodiments, the first metal liner 170 includes a single layer of ruthenium (Ru). In one or more embodiments, the first metal liner 170 includes a single layer of ruthenium (Ru) selectively deposited on the sidewall. In one or more embodiments, the first metal liner 170 includes a multi-layer film having a first liner film composed of a first metal M1 and a second liner film composed of a second metal M2. In one or more embodiments, the first metal liner 170 includes a first metal M1 including ruthenium (Ru) and a second metal M2 including cobalt (Co).

[0045] Embodiments of the present disclosure advantageously provide methods of forming microelectronic devices that reduce via resistance by at least 20% as compared to via resistance in microelectronic devices that do not selectively deposit a metal liner. In one or more embodiments, the via resistance of the microelectronic devices described herein is reduced by at least 15%, at least 10%, or at least 5% as compared to via resistance in microelectronic devices that do not selectively deposit a metal liner.

[0046] By using a typical deposition process, ruthenium (Ru) is deposited on the sidewalls and the bottom. It has been found that when using a known deposition process for a period of 40 seconds, the layer of ruthenium (Ru) deposited on the sidewalls has a thickness of 10 Angstroms, while the layer of ruthenium (Ru) deposited on the bottom has a thickness of about 3.87 Angstroms. In one or more embodiments, the ratio of the thickness of the layer of ruthenium (Ru) on the sidewalls to the thickness of the layer of ruthenium (Ru) on the bottom is about 2.6.

[0047] It has been found that selectively depositing a monolayer of ruthenium (Ru) according to embodiments of the methods described herein increases the ratio of the thickness of the metal liner thickness on the sidewalls to the thickness of the metal liner thickness on the bottom. In one or more embodiments, the thickness of the metal liner thickness on the sidewalls is greater than the thickness of the metal liner on the bottom.

[0048] In one or more embodiments, when the metal liner 170 includes a selectively deposited monolayer of ruthenium (Ru) on the sidewalls 148, the ratio of the thickness of the metal liner thickness on the sidewalls 148 to the thickness of the metal liner 170 thickness on the bottom 149 is greater than 3. In one or more embodiments, the ratio of the thickness of the metal liner thickness on the sidewalls 148 to the thickness of the metal liner thickness on the bottom 149 is greater than 4, greater than 5, greater than 6, or greater than 7. In one or more embodiments, the metal liner 170 is not formed on the bottom 149.

[0049] In one or more embodiments, when the metal liner 170 includes a selectively deposited monolayer of ruthenium (Ru), the thickness of the metal liner 170 on the sidewalls 148 ranges from 5 Angstroms to 20 Angstroms. In one or more embodiments, when the metal liner 170 includes a selectively deposited monolayer of ruthenium (Ru), the thickness of the metal liner 170 on the bottom 149 is less than or equal to 5 Angstroms. In one or more embodiments, when the metal liner 170 includes a selectively deposited monolayer of ruthenium (Ru), the thickness of the metal liner 170 on the bottom 149 is less than or equal to 4 Angstroms, less than or equal to 3 Angstroms, less than or equal to 2 Angstroms, or less than or equal to 1 Angstrom.

[0050] In one or more embodiments, the metal liner 170 comprising ruthenium (Ru) is selectively deposited by a selective ruthenium (Ru) deposition process. The selective ruthenium (Ru) deposition on the sidewalls includes a cyclical deposition process that includes a ruthenium deposition step using a ruthenium (Ru) precursor carried by a carrier gas such as argon (Ar) gas. In one or more embodiments, the selective ruthenium (Ru) deposition further includes an anneal or treatment step that is performed while flowing hydrogen (H2) and optionally a second gas such as argon (Ar). In one or more embodiments, the selective ruthenium (Ru) deposition is performed in a substrate processing chamber where the deposition step is performed while the chamber is at a first pressure and the anneal step is performed while the substrate processing chamber is at a second pressure that is greater than the first pressure. In one or more embodiments, the first pressure is in a range from 1 Torr to 5 Torr. In some embodiments, the first pressure is in a range from 1 Torr to 4 Torr, or in a range from 1 Torr to 3 Torr. In one or more embodiments, the second pressure is in a range from 10 Torr to 150 Torr. In some embodiments, the second pressure is in a range from 10 Torr to 40 Torr, or in a range from 10 Torr to 30 Torr. Thus, according to one or more embodiments, the cyclical deposition process includes a deposition step and an anneal / treatment step. In the deposition step, a ruthenium precursor (e.g., any suitable metal organic precursor such as tricarbonyl cyclohexadienyl ruthenium Ru3(Co)9) is flowed in a carrier gas and a reactive gas (e.g., Ar and / or H2) for 2 to 10 seconds, such as 3 to 6 seconds, to form a deposited ruthenium layer. In the anneal or treatment step, the deposited ruthenium layer is annealed or treated in the presence of a flowing gas (e.g., greater than 90% H2and a second gas such as Ar) for 30 to 90 seconds, such as 40 to 70 seconds. This cycle of a deposition step and an anneal or treatment step is repeated multiple times to obtain a desired film thickness.

[0051] Referring to FIG. 1DIn one or more embodiments, an optional second metal liner 180 is illustrated on the first metal liner 170. In one or more embodiments, the second metal liner 180 includes one or more of ruthenium (Ru), cobalt (Co), molybdenum (Mo), or tantalum (Ta). In one or more embodiments, the second metal liner 180 includes one or more of a single layer of ruthenium (Ru) or a single layer of cobalt (Co). In one or more embodiments, the metal liner 180 includes a single layer of cobalt (Co) deposited on the sidewall. In one or more embodiments, when the metal liner 180 includes a single layer of deposited cobalt (Co), the thickness of the metal liner 180 on the sidewall 148 is in a range from 5 Angstroms to 20 Angstroms. In one or more embodiments, when the metal liner 180 includes a single layer of deposited cobalt (Co), the thickness of the metal liner 180 on the bottom 149 is less than or equal to 5 Angstroms. In one or more embodiments, when the metal liner 180 includes a single layer of deposited cobalt (Co), the thickness of the metal liner 180 on the bottom 149 is in a range from 5 Angstroms to 20 Angstroms. In one or more embodiments, the second metal liner 180 is not formed on the bottom 149.

[0052] In one or more embodiments, the second metal liner 180 includes a multi-layer film having a first liner film composed of a first metal Ml and a second liner film composed of a second metal M2. In one or more embodiments, the second metal liner 180 includes a first metal Ml including ruthenium (Ru) and a second metal M2 including cobalt (Co). In one or more embodiments, when the second metal liner 180 includes a first metal Ml including ruthenium (Ru) and a second metal M2 including cobalt (Co), the combined thickness of the multi-layer film on the sidewall 148 is in a range from 10 Angstroms to 20 Angstroms. In one or more embodiments, when the second metal liner 180 includes a first metal Ml including ruthenium (Ru) and a second metal M2 including cobalt (Co), the combined thickness of the multi-layer film on the bottom 149 is in a range from 5 Angstroms to 20 Angstroms.

[0053] In one or more embodiments, the microelectronic device 100 includes one or more of the first metal liner 170 and the second metal liner 180. In one or more embodiments, the first metal liner 170 is the same as the second metal liner 180. In one or more embodiments, the first metal liner 170 is different than the second metal liner 180.

[0054] In some embodiments, the dual metal liner film comprises an alloy of the two metals in a single layer. In some embodiments, the dual metal liner film comprises alternating layers of two metals M1 and M2, or alternating layers of a first metal liner film and a second metal liner film. In one or more embodiments, the two metals comprise two metals selected from the group consisting of: (M1) Co and (M2) tantalum (Ta); (M1) Co and (M2) molybdenum (Mo); (M1) Ru and (M2) Ta; (M1) Ru and (M2) W; (M1) Ru and (M2) Mo; (M1) Co and (M2) Ru; and (M1) Ru and (M2) Co. In one or more embodiments, the dual metal liner film has a thickness of less than 20 Angstroms.

[0055] According to one or more embodiments, the dual metal liner film can be formed by various deposition methods, including by ALD / CVD / PE-ALD alternating and / or co-flow precursors (precursors with multi-metal ligands), dopant implantation, and or thermal diffusion. The dual metal liner film can be formed in a single processing chamber or multiple processing chambers. In one or more embodiments, the dual metal liner film can be processed by various methods, including thermal processing, plasma processing, and / or chemical processing.

[0056] Advantageously, the ultra-thin (e.g., thickness of 20 Angstroms or less) dual metal liner film according to one or more embodiments provides better interfacial adhesion and mobility between two metals, such as barrier and gap fill metals. The dual metal liner film and method described according to one or more embodiments can be used for metal contact, interconnect, and capping applications. The dual metal liner film according to one or more embodiments is thinner than current liners, which are typically greater than 20 Angstroms and up to 30 Angstroms. In some embodiments, the liner film composed of two metals has a thickness in the range of 10 Angstroms to 20 Angstroms, 10 Angstroms to 19 Angstroms, 10 Angstroms to 18 Angstroms, 10 Angstroms to 17 Angstroms, 10 Angstroms to 16 Angstroms, 10 Angstroms to 15 Angstroms, 10 Angstroms to 14 Angstroms, 10 Angstroms to 13 Angstroms, or 10 Angstroms to 12 Angstroms. The dual metal liner film described herein can extend metal fill and capping to develop nodes, such as enabling copper reflow in 3nm / 2nm nodes, low resistivity in middle of the line (MOL) and back end of line (BEOL), and memory. The methods described herein can also simplify current complex integration systems to one chamber or multiple chamber processes involving CVD / ALD / PVD / PEALD / ion implantation.

[0057] In one or more embodiments, the barrier layer and / or metal film can be deposited via ALD. In a typical ALD process, a film can be deposited using alternating pulses or flows of "A" and "B" precursors. The surface is continually exposed to the reactants "A" and "B" until a film of the desired thickness is obtained. However, as an alternative to pulsing the reactants, the gases can be flowed simultaneously from one or more gas delivery heads or nozzles, and the substrate and / or gas delivery heads can be moved so that the substrate is sequentially exposed to each reactive gas. Of course, the foregoing ALD cycle is merely an example of a variety of ALD process cycles in which a layer is formed from alternating layers of a precursor and a co-reactant.

[0058] In one or more embodiments, the co-reactant is in the form of a vapor or gas. The reactants can be delivered with a carrier gas. The carrier gas, purge gas, deposition gas, or other process gas can contain nitrogen, hydrogen, argon, neon, helium, or a combination of each of the foregoing. Various plasmas described herein, such as a nitrogen plasma or an inert gas plasma, can be ignited from and / or contain a plasma co-reactant gas.

[0059] In one or more embodiments, the various gases used in the process can be pulsed through a gas channel from various apertures or outlets into an inlet, and into a central channel. In one or more embodiments, the deposition gases can be pulsed sequentially to and through a showerhead. Alternatively, as described above, the gases can be flowed simultaneously through a gas supply nozzle or head, and the substrate and / or gas supply head can be moved so that the substrate is sequentially exposed to the gases.

[0060] In one or more embodiments, the barrier layer material and liner film are deposited using a multi-chamber process and the barrier layer material (e.g., tantalum nitride (TaN)) and metal liner film are separated. In other embodiments, a single chamber method is used, all processes occur in one chamber, and the different layers / films are separated in the process by gas purging.

[0061] Some embodiments of the present disclosure are directed to barrier applications, such as copper barrier applications. Barrier layers formed by one or more embodiments can be used as copper barriers. Suitable barrier layers for copper barrier applications include, but are not limited to, TaN and MnN. Suitable dopants for copper barrier applications include, but are not limited to, ruthenium, copper, cobalt, manganese, aluminum, tantalum, molybdenum, niobium, vanadium, or combinations thereof. A plasma treatment can be used after doping to promote intermetallic compound formation between the matrix and the dopant, as well as to remove film impurities and improve the density of the barrier layer. In other embodiments, post-treatment can include, but is not limited to, physical vapor deposition (PVD) treatment, thermal annealing, chemical enhancement, and the like. In some copper barrier applications, a high frequency plasma (defined as greater than about 14 MHz or about 40 MHz or higher) can be used with any inert gas, including, but not limited to, one or more of neon (Ne), hydrogen (H2), and argon (Ar) gas. In one or more embodiments, to prevent low dielectric constant damage, a higher plasma frequency (higher than 13.56 MHz) can be used. In some embodiments, the barrier layer is a copper barrier and includes TaN doped with Ru.

[0062] Suitable precursors for depositing the liner layer include metal-containing precursors, such as carbonyl-containing and cyclopentadiene-containing precursors. In a non-limiting example, if the liner layer is RuCo, the Ru-containing precursor can be triruthenium dodecacarbonyl Ru3(CO) 12 and the Co-containing precursor can be dicobalthexacarbonyl third butyl acetylene (CCTBA). If the liner layer is TaRu, the Ta-containing precursor can be pentakis(dimethylamino)tantalum (PDMAT). Other suitable precursors are known to those skilled in the art. The organic species portion of the organic-containing precursors used for the liner layer binds into the underlying layer (such as the barrier layer or the dielectric layer), which can increase adhesion at the interface of the liner layer and the underlying layer.

[0063] As used herein, "chemical vapor deposition" refers to a process in which a substrate surface is exposed to a precursor and / or co-reagent simultaneously or substantially simultaneously. As used herein, "substantially simultaneously" refers to concurrent flow of precursors or a majority of the precursor exposure with overlap.

[0064] The metal liner film can be formed by CVD, PVD, or ALD deposition of alternating layers of the two metals or co-reaction of two metal precursors. Depending on the liner metal used, co-reactants or co-precursors can be used to deposit the liner film. In one or more embodiments, ion implantation can be used to incorporate a second metal into a liner film comprised of a first metal. In other embodiments, physical vapor deposition (PVD) co-processing can be used to add a second metal to a doped liner film formed over a barrier layer. In further embodiments, the liner film can be annealed inside an atmosphere containing the second metal to thermally diffuse the second metal into the liner film of the first metal to form a liner film on the barrier layer.

[0065] In one or more embodiments, a PVD process employing sputtering can be used to incorporate an optional second metal into a liner film comprising a first metal. For example, a PVD process employing cobalt (Co) can implant Co into a ruthenium film to form a liner film comprising ruthenium and cobalt.

[0066] In some embodiments, a post-plasma treatment step can be used after exposing the liner film comprising a first metal to an optional second metal precursor, either instead of or in addition to using a co-reactant. According to one or more embodiments, the plasma comprises any suitable inert gas known to the skilled artisan. In one or more embodiments, the plasma comprises one or more of helium (He), argon (Ar), ammonia (NH3), hydrogen (H2), and nitrogen (N2). In some embodiments, the plasma can comprise a mixture of Ar and H2, such as a mixture having an Ar:H2 molar ratio in the range of 1 : 1 to 1 : 15. The plasma power can be in the range of about 200 Watts to about 1000 Watts. The plasma frequency can be in the range of 350 KHz to 40 MHz. The plasma treatment time can vary from 5 seconds to 60 seconds, such as in the range of 10 seconds to 30 seconds. In some embodiments, the pressure during plasma treatment can be in the range of 0.5 Torr to 50 Torr, such as 1 to 10 Torr. In some embodiments, the wafer spacing can be in the range of 100 mils to 600 mils.

[0067] In one or more embodiments, the liner film comprising a first metal can be exposed to a second metal precursor during deposition, i.e., the second metal precursor can be used sequentially in the ALD cycles to provide a liner film comprised of two metals on the barrier layer. In various embodiments, the duration of exposure to the second metal-containing precursor can be in the range of 1 second to 60 seconds, such as in the range of 3 seconds to 30 seconds or 5 seconds to 10 seconds. Exposure to the second metal precursor for longer times will increase the amount of the second metal in the dual metal liner film. In one or more embodiments, the dual metal liner film is formed by a cyclic deposition process.

[0068] Referring to FIG. 1EIn one or more embodiments, the microelectronic device has been removed from the structure shown in FIG. 1D In one or more embodiments, removing the SAM 150 includes a plasma treatment process that includes flowing one or more of hydrogen (H2) or argon (Ar). In one or more embodiments, the plasma treatment process includes increasing the density of the barrier layer 160. In one or more embodiments, the gap fill process includes filling the gap 146 with one or more of copper (Cu) or cobalt (Co). FIG. 1E In one or more embodiments, the gap 146 is filled with one or more of copper (Cu) or cobalt (Co).

[0069] Referring to FIG. 2A and FIG. 2B , according to alternative embodiments of the disclosure, a portion of a microelectronic device 200 is illustrated during various stages of manufacture. In one or more embodiments, the microelectronic device 200 includes a substrate 210, a barrier layer 220 on the substrate 210, a metal liner 230 on the barrier layer 220, a conductive fill gap 240, an aluminum oxide etch stop layer 242, a dielectric layer 245 on the aluminum oxide etch stop layer 242, the dielectric layer 245 including at least one feature defining a gap 246, the gap 246 including a sidewall 248 and a bottom 249. In one or more embodiments, a first passivation layer (e.g., a first self-assembled monolayer (SAM)) 250 is formed on the bottom 249 of the gap.

[0070] In one or more embodiments, FIGS. 1A-1E and FIGS. 2A-2G The features of the microelectronic device shown have the same characteristics, including materials, methods of manufacture, dimensions, etc. In one or more embodiments, the substrate 210, the barrier layer 220 on the substrate, the metal liner 230 on the barrier layer 220, the conductive fill gap 240, the aluminum oxide etch stop layer 242, and the dielectric layer 245 on the aluminum oxide etch stop layer 242 including at least one feature defining a gap 246, the gap 246 including a sidewall 248 and a bottom 249. The first SAM 250 is formed by flowing a hydrocarbon carried in an argon (Ar) gas. In one or more embodiments, the first SAM 250 includes an unsaturated hydrocarbon. In one or more embodiments, the first SAM 250 is deposited on the dielectric layer 245.

[0071] Referring to FIG. 2B , a barrier layer 260 is illustrated as formed on the first SAM 250 and the sidewall 248. In FIG. 2C , the first SAM 250 has been removed. In one or more embodiments, removing the first SAM 250 includes a plasma treatment process that includes flowing one or more of hydrogen (H2) or argon (Ar). In one or more embodiments, the plasma treatment process increases the density of the barrier layer 260.

[0072] See now FIG. 2D , after removing the first SAM 250, a second passivation layer (e.g., a second self-assembled monolayer (SAM)) 255 is shown formed on the bottom 249 of the gap, the barrier layer 260, and the bottom 249 of the gap. In one or more embodiments, the first SAM 250 and the second SAM 255 are the same. In one or more embodiments, the first SAM 250 and the second SAM 255 are different. See FIG. 2E , a first metal liner 270 is shown as being deposited on the barrier layer 260. FIG. 2F In one or more embodiments, an optional second metal liner 280 is illustrated as being formed on the first metal liner 270 .

[0073] See FIG. 2G , the second SAM 255 has been removed. In one or more embodiments, the first SAM 250 and the second SAM 255 can be removed by the same process. In one or more embodiments, removing one or more of the first SAM and the second SAM includes a plasma treatment process comprising flowing one or more of hydrogen (H2) or argon (Ar). In one or more embodiments, the plasma treatment process increases the density of the barrier layer 260.

[0074] FIG. 3 A process flow diagram of a method 300 for forming a microelectronic device is shown. FIG. 3 Shows the formation FIGS. 1A-1E Methods for any microelectronic device of one or more embodiments shown. FIG. 3 Method 300 includes, at operation 310, forming a dielectric layer on a substrate. The dielectric layer includes at least one feature defining a gap, the gap including sidewalls and a bottom. At operation 320, method 300 includes selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap. At operation 330, method 300 includes forming a barrier layer on the SAM. At operation 340, method 300 includes selectively depositing a metal liner on the barrier layer. At operation 340, in some embodiments, the metal liner is deposited to a greater thickness on the sidewalls than on the bottom. In one or more embodiments, at operation 340, the metal liner is selectively deposited on the sidewalls rather than on the bottom. At operation 350, method 300 includes removing the SAM after selectively depositing the metal liner on the barrier layer. At operation 360, method 300 includes performing a gap-fill process on the metal liner. The gap-fill process may include forming one or more of vias and lines to form interconnects in the device.

[0075] FIG. 4A process flow diagram for a method 400 of forming a microelectronic device is shown. FIG. 4 A process flow diagram for a method 400 of forming a microelectronic device is shown. FIGS. 2A-2G A process flow diagram for a method 400 of forming a microelectronic device is shown. Referring to FIG. 4, the method 400 includes forming a dielectric layer on a substrate at operation 410. The dielectric layer includes at least one feature defining a gap, the gap including sidewalls and a bottom. At operation 420, the method 400 includes selectively depositing a first self-assembled monolayer (SAM) on the gap bottom. At operation 430, the method 400 includes forming a barrier layer on the first SAM. At operation 440, the method 400 includes removing the first SAM after forming the barrier layer. At operation 450, the method 400 includes selectively depositing a second self-assembled monolayer (SAM) on the barrier layer after removing the first SAM. FIG. 4 A process flow diagram for a method 400 of forming a microelectronic device is shown. Referring to FIG. 4, the method 400 includes forming a dielectric layer on a substrate at operation 410. The dielectric layer includes at least one feature defining a gap, the gap including sidewalls and a bottom. At operation 420, the method 400 includes selectively depositing a first self-assembled monolayer (SAM) on the gap bottom. At operation 430, the method 400 includes forming a barrier layer on the first SAM. At operation 440, the method 400 includes removing the first SAM after forming the barrier layer. At operation 450, the method 400 includes selectively depositing a second self-assembled monolayer (SAM) on the barrier layer after removing the first SAM.

[0076] At operation 460, the method 400 includes selectively depositing a metal liner on the barrier layer. At operation 460, in some embodiments, the metal liner is deposited to a greater thickness on the sidewalls than on the bottom. In one or more embodiments, at operation 460, the metal liner is selectively deposited on the sidewalls and not on the bottom. At operation 470, the method 400 includes removing the second SAM after selectively depositing the metal liner on the barrier layer. At operation 480, the method 400 includes performing a gap fill process on the metal liner. The gap fill process can include forming one or more of vias and lines to form interconnects in the device.

[0077] In one or more embodiments, the methods described herein include optional post-processing operations. The optional post-processing operations can be, for example, a process to modify the properties of the film (e.g., annealing) or a further film deposition process (e.g., an additional ALD or CVD process) to grow an additional film. In some embodiments, the optional post-processing operation can be a process to modify the properties of the deposited film. In some embodiments, the optional post-processing operation includes annealing the deposited film. In some embodiments, the annealing is done at a temperature in a range of about 300 °C, 400 °C, 500 °C, 600 °C, 700 °C, 800 °C, 900 °C, or 1000 °C. The annealing environment of some embodiments includes one or more of: an inert gas (e.g., molecular nitrogen (N2), argon (Ar)) or a reducing gas (e.g., molecular hydrogen (H2) or ammonia (NH3)) or an oxidizing agent such as, but not limited to, oxygen (O2), ozone (O3), or a peroxide. The annealing can be performed for any suitable length of time. In some embodiments, the film is annealed for a predetermined time in a range of about 15 seconds to about 90 minutes, or in a range of about 1 minute to about 60 minutes. In some embodiments, annealing the deposited film increases the density, decreases the resistivity, and / or increases the purity of the metal liner layer.

[0078] In some embodiments, the substrate is moved from the first chamber to a separate next chamber for further processing. The substrate can be moved directly from the first chamber to a separate processing chamber, or the substrate can be moved from the first chamber to one or more transfer chambers and then to a separate processing chamber. In some embodiments, deposition of the barrier layer and dopant film can be performed in a single chamber, and then post processing can be performed in a separate chamber. Thus, a processing apparatus can include a plurality of chambers in communication with a transfer station. Such an apparatus can be referred to as a "cluster tool" or "cluster system," among others.

[0079] Generally, a cluster tool is a modular system that includes a plurality of chambers that perform various functions, including substrate center finding and orientation, degassing, annealing, deposition, and / or etching. According to one or more embodiments, a cluster tool includes at least a first chamber and a central transfer chamber. The central transfer chamber can house a robot that can transfer substrates back and forth between and among processing chambers and load lock chambers. The transfer chamber is typically maintained under vacuum conditions and provides an intermediate stage for transferring substrates from one chamber to another and / or to a load lock chamber positioned at the front end of the cluster tool. However, the exact arrangement and combination of chambers can be varied in order to perform the particular steps of the processes described herein. Other processing chambers that can be used include, but are not limited to, cyclic deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etching, pre-cleaning, chemical cleaning, plasma nitridation, degassing, orientation, hydroxylation, and other substrate processes including deposition steps and anneal or treatment steps. By performing processes in chambers on a cluster tool, surface contamination of the substrate by atmospheric impurities can be avoided without oxidation prior to deposition of subsequent films.

[0080] According to one or more embodiments, the substrate is continuously under vacuum or "load lock" conditions and is not exposed to ambient air when moved from one chamber to the next. Thus, the transfer chamber is under vacuum and is "pumped down" under vacuum pressure. An inert gas can be present in the processing chamber or the transfer chamber. In some embodiments, the inert gas is used as a purge gas to remove some or all of the reactants (e.g., reactants). According to one or more embodiments, a purge gas is injected at the outlet of the deposition chamber to prevent reactants (e.g., reactants) from moving from the deposition chamber to the transfer chamber and / or additional processing chambers. Thus, an inert gas flow forms a gas curtain at the outlet of the chamber.

[0081] A substrate can be processed in a single substrate deposition chamber, in which a single substrate is loaded, processed, and unloaded, followed by processing another substrate. Substrates can also be processed in a continuous fashion similar to a conveyor system, in which multiple substrates are individually loaded into a first portion of the chamber, moved through the chamber, and unloaded from a second portion of the chamber. The shape of the chamber and associated conveyor system can form a straight path or a curved path. Further, the processing chamber can be a carousel, in which multiple substrates are moved around a central axis and exposed to deposition, etching, annealing, cleaning, etc. processes throughout the carousel path.

[0082] During processing, the substrate can be heated or cooled. Such heating or cooling can be accomplished by any suitable means, including but not limited to changing the temperature of the substrate support and flowing heated or cooled gas to the substrate surface. In some embodiments, the substrate support includes a heater / cooler that can be controlled to change the substrate temperature in a conductive fashion. In one or more embodiments, the gas being employed (reactive or inert) is heated or cooled to locally change the substrate temperature. In some embodiments, a heater / cooler is located within the chamber proximate to the substrate surface to change the substrate temperature in a convective fashion.

[0083] The substrate can also be stationary or rotated during processing. A rotating substrate can be continuously rotated (about the substrate axis) or rotated in discrete steps. For example, the substrate can be rotated throughout the process, or the substrate can be rotated by a small amount between exposures to different reactive or purge gases. Rotating the substrate during processing (continuously or in steps) can help produce more uniform deposition or etching by minimizing the effects of, for example, local variability in gas flow geometry.

[0084] Another aspect of the disclosure relates to a non-transitory computer readable medium comprising instructions that, when executed by a controller of a processing system, cause the processing system to perform operations of the methods described herein. In one embodiment, the non-transitory computer readable medium comprising instructions that, when executed by a controller of a processing system, cause the processing system to perform operations of the methods described herein with respect to FIGS. 1A-1E , FIGS. 2A-2G , FIG. 3 and FIG. 4 .

[0085] References in the specification to "one embodiment", "certain embodiments", "one or more embodiments", or "an embodiment" mean that a particular feature, structure, material, or characteristic being described is included in at least one embodiment of the disclosure. Thus, the appearances of such phrases in various places in the specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments.

[0086] While the disclosure has been described herein with reference to specific embodiments thereof, it should be understood that these embodiments are merely illustrative of the principles and applications of the disclosure. It will thus be apparent that various modifications and adaptations can be made within the scope of the disclosure and the scope of the appended claims without departing from the true spirit and scope of the disclosure.

Claims

1. A method of forming a microelectronic device, the method comprising: forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap, the gap comprising sidewalls and a bottom; selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap, the SAM comprising a hydrocarbon having the chemical formula HC≡CR, wherein R is an alkyl linear or aryl group containing 1 to 20 carbon atoms, or having the chemical formula R'C=CR", wherein R' and R" independently comprise an alkyl linear or aryl group containing 1 to 20 carbon atoms; forming a barrier layer on the SAM; selectively depositing a metal liner on the barrier layer on the sidewall, wherein the thickness of the metal liner deposited on the sidewall is greater than the thickness of the metal liner deposited on the bottom; removing the SAM after selectively depositing the metal liner on the barrier layer; and A gap-fill process is performed on the metal liner. 2 . The method of claim 1 , wherein selectively depositing the SAM comprises exposing the bottom of the gap to hydrocarbons carried in argon (Ar) gas.

3. The method of claim 1, wherein the SAM comprises a first SAM deposited on the dielectric layer. 4 . The method of claim 3 , further comprising removing the first SAM after forming the barrier layer on the SAM.

5. The method of claim 4 , further comprising selectively depositing a second SAM on the barrier layer after removing the first SAM, the second SAM comprising a hydrocarbon having a chemical formula HC≡CR, wherein R is an alkyl linear or aryl group containing 1 to 20 carbon atoms, or having a chemical formula R′C═CR″, wherein R′ and R″ independently comprise an alkyl linear or aryl group containing 1 to 20 carbon atoms. The method of claim 5 , wherein the first SAM and the second SAM are different. The method of claim 5 , wherein the first SAM and the second SAM are identical.

8. The method of claim 1, wherein the metal liner is selectively deposited on sidewalls of the microelectronic device.

9. The method of claim 8, wherein the metal liner comprises one or more of ruthenium (Ru), cobalt (Co), molybdenum (Mo), and tantalum (Ta).

10. The method of claim 9, wherein when the metal liner comprises a single layer of ruthenium (Ru) selectively deposited on the sidewalls, the thickness of the metal liner on the bottom is less than 10 angstroms.

11. The method of claim 10, wherein the selective ruthenium (Ru) deposition on the sidewalls comprises a cyclic deposition process using a ruthenium (Ru) precursor carried by argon (Ar) gas to form the deposited Ru layer.

12. The method of claim 11, wherein the cyclic deposition process further comprises annealing the deposited ruthenium layer while flowing hydrogen (H2) gas, and annealing the deposited ruthenium layer.

13. The method of claim 12, wherein the cyclic deposition process is performed in a substrate processing chamber at a first pressure to form the deposited ruthenium layer, and annealing the deposited ruthenium layer is performed while the substrate processing chamber is at a second pressure greater than the first pressure.

14. The method of claim 1, wherein the hydrocarbon has the formula HC≡CR, wherein R is an alkyl linear or aryl group containing 1 to 20 carbon atoms.

15. The method of claim 14, wherein R is a linear alkyl group.

16. The method of claim 1, wherein the hydrocarbon has the formula R'C=CR", wherein R' and R" independently comprise an alkyl linear or aryl group containing from 1 to 20 carbon atoms.

17. The method of claim 16, wherein R' and R" independently comprise a linear alkyl group.

18. The method of claim 17, wherein removing the SAM comprises a plasma treatment process comprising flowing one or more of hydrogen (H2) or argon (Ar), and the plasma treatment process comprises increasing the density of the barrier layer.

19. The method of claim 1, wherein the gap filling process comprises filling the gap with one or more of copper (Cu) or cobalt (Co).

20. The method of claim 1, wherein forming the microelectronic device reduces the resistance of the via by at least 20% compared to the resistance of the via in a microelectronic device without the selectively deposited metal liner.

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