Anti-radiation circuit of three-node reinforced latch based on enhanced interlocking feedback

Abstract

The invention relates to an anti-radiation circuit of a three-node reinforced latch based on enhanced interlocking feedback, and the anti-radiation circuit forms an enhanced interlocking feedback loop through the cooperation of a double-input C unit and a three-input C unit, and can achieve the self-recovery of a logic state under the condition that any three sensitive nodes are disturbed at the same time. And meanwhile, a transmission gate and inverter series connection structure is introduced into a key signal channel, so that the data transmission delay in a transparent mode is reduced, and the influence of transient interference on the circuit stability is inhibited through a filtering effect. In addition, the complementary design of the feedback path ensures the balance of the driving relationship between the nodes, thereby further improving the robustness and reliability of the circuit in a high-radiation environment. Compared with the prior art, the circuit not only breaks through the reliability bottleneck of a traditional latch in a three-node flipping scene, but also achieves good balance between structural redundancy and performance overhead, and has the outstanding advantages of high stability, high anti-interference capability and wide application range.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits and relates to an anti-radiation circuit of a three-node reinforced latch based on enhanced interlock feedback. Background Art

[0002] With the continuous reduction in the process size of integrated circuits, the further increase in device density and the further complexity of circuit structures, tiny erroneous charges can cause changes in the logical state of nodes. Due to the charge sharing effect, a single particle impact will not only cause a single node upset (SNU), but may also cause a double node upset (DNU) or even a triple node upset (TNU). These multi-node upset phenomena seriously threaten the reliability of integrated circuits in high radiation environments. At the same time, traditional radiation-resistant latches are difficult to meet the requirements of modern circuits for low power consumption, high performance and high reliability, especially in terms of achieving a balanced optimization between power consumption, delay and area. As the process nodes continue to shrink, the probability of multi-node upsets increases significantly, which places higher demands on the radiation-resistant design of latches. The schematic diagram of the radiation-resistant circuit is shown in the figure. Figure 1 shown.

[0003] An existing radiation-hardened circuit for a dual-node hardened latch based on enhanced interlocked feedback primarily consists of eight C-cells, six inverters, and four transmission gates. In this structure, CE1 and CE3 are dual-input C-cells driven by a clock signal, while the remaining C-cells operate independently of the clock signal. The system clock is denoted as CLK, the input signal is D, the output signal is Q, and the remaining symbols correspond to internal nodes of the circuit. The radiation-hardening properties of this circuit primarily rely on the C-cells' tolerance to single-node upsets (SNUs). Specifically, C-cells CE1, CE2, CE3, and CE4 are connected end-to-end to form a feedback loop, which somewhat suppresses abnormal upsets caused by radiation. However, when encountering a double-node upset (DNU), the feedback mechanism of these four C-cells alone is insufficient to ensure full circuit recovery. Therefore, four additional C-cells, CE5, CE6, CE7, and CE8, are introduced to further harden critical nodes. With these eight C-cells forming an enhanced interlocked feedback loop, the circuit effectively resists any double-node upset and achieves self-recovery.

[0004] While this circuit exhibits strong anti-interference capabilities under single-node upset (SNU) and double-node upset (DNU) conditions, it exhibits significant shortcomings under triple-node upset (TNU) scenarios. When multiple nodes (such as I, a, and Q) are simultaneously subjected to charge injection, the output Q and other related nodes experience an erroneous flip and are unable to recover, reflecting design flaws in its internal structure under multi-node perturbations. Therefore, improving the fault-tolerance performance of radiation-hardened circuits under triple-node upset (TNU) scenarios requires the introduction of higher redundancy or innovative structures to enhance their reliability and applicability under harsh radiation conditions. Summary of the Invention

[0005] In response to the problems existing in the above-mentioned traditional methods, the present invention proposes an anti-radiation circuit of a three-node reinforced latch based on enhanced interlocking feedback, which can overcome the defects of the existing anti-radiation circuit of a two-node reinforced latch based on enhanced interlocking feedback, such as insufficient anti-interference ability and limited reliability in multi-node flipping scenarios.

[0006] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: In one aspect, a radiation-resistant circuit of a three-node reinforced latch based on enhanced interlocked feedback is provided, comprising: The clock-controlled signal transmission module is used to receive the input signal D and control the conduction and cutoff of multiple transmission gates through the clock signal CLK. Two inverters connected in series after each transmission gate drive nodes N1 to N5 and the output node Q.

[0007] An enhanced interlocking feedback loop is used to form a closed main feedback loop by connecting six dual-input C units CE_1 to CE_6 end to end, and introduce six three-input C units CE_7 to CE_12 to form an enhanced interlocking feedback loop together with the main feedback loop; one input end of CE_1 to CE_6 is respectively connected to nodes N1 to N5 and output node Q, the other input end of CE_1 to CE_6 is respectively connected to the output end of CE_7 to CE_12, and the three input ends of each three-input C in CE_7 to CE_12 are respectively connected to the output node Q and three adjacent nodes among nodes N5, N4, N3, N2, and N1.

[0008] In one embodiment, the clock-controlled signal transmission module includes six transmission gates TG_1 to TG_6 and 13 inverters INV1 to INV13 .

[0009] The input terminals of TG_1 to TG_3 all receive the input signal D, which is then transmitted to the input terminals of TG_4 to TG_6 after passing through INV1. The clock control terminals of TG_1 to TG_6 are linked to the input terminals of the clock signals, and INV2 to INV13 are divided into six inverter groups in groups of two. Two inverters in an inverter group are connected in series, and one inverter group is connected in series behind each of TG_1 to TG_6. The output terminals of the six inverter groups are connected to nodes N1 to N5 and the output node Q, respectively.

[0010] In one embodiment, in the enhanced interlocking feedback loop: an input terminal of CE_1 and an output terminal of CE_6 are both connected to node N1, the output terminal of CE_1 and an input terminal of CE_2 are both connected to node N2, the output terminal of CE_2 and an input terminal of CE_3 are both connected to node N3, the output terminal of CE_3 and an input terminal of CE_4 are both connected to node N4, the output terminal of CE_4 and an input terminal of CE_5 are both connected to node N5, the output terminal of CE_5 and an input terminal of CE_6 are both connected to output node Q, and the other input terminal of CE_1 to CE_6 are respectively connected to the output terminals of CE_7 to CE_12.

[0011] The output node Q and three adjacent nodes N5, N4, N3, N2, and N1 are taken as a node group, and 6 node groups are obtained. The first node group includes: output node Q, node N5, and node N4; the second node group includes: node N1, output node Q, and node N5; the third node group includes: nodes N2 and N1, and output node Q; the fourth node group includes: nodes N3, N2, and N1; the fifth node group includes: nodes N4, N3, and N2; and the sixth node group includes: nodes N5, N4, and N3.

[0012] The six node groups correspond one-to-one to CE_7 to CE_12. One node is selected from each node group and connected to one input end of CE_7 to CE_12 through an inverter. The other two nodes in each node group are respectively connected to the other two nodes of CE_7 to CE_12. The nodes connected to the input ends of CE_7 to CE_12 through inverters are: node N5, output node Q, and nodes N1 to N4.

[0013] In one embodiment, when the clock signal CLK is high, the circuit is in transparent mode; transmission gates TG_1 to TG_6 are all turned on, and all C units are in operation; nodes N1 to N5 and output node Q are driven by input signal D after being processed by transmission gates and inverters; in transparent mode, each node completes pre-charging related to input signal D to achieve data writing.

[0014] In one embodiment, when the clock signal CLK is at a low level, the circuit enters a hold mode; transmission gates TG_1 to TG_6 are all closed, and nodes N1 to N5 and output node Q are no longer directly driven by the current input signal D; CE_1 to CE_12 are in an operating state, and the enhanced interlocking feedback loop maintains the circuit's self-stability.

[0015] One of the above technical solutions has the following advantages and beneficial effects: The above-mentioned radiation-resistant circuit of the three-node reinforced latch based on enhanced interlocked feedback, which is composed of dual-input and three-input C units to form an enhanced interlocked feedback loop, can achieve self-recovery of the logic state when any three sensitive nodes are disturbed at the same time; at the same time, the introduction of a transmission gate and inverter series structure in the key signal path not only reduces the data transmission delay in transparent mode, but also suppresses the impact of transient interference on circuit stability through filtering. In addition, the complementary design of the feedback path ensures the balance of the driving relationship between nodes, thereby further improving the robustness and reliability of the circuit in high-radiation environments. Compared with the existing technology, this circuit not only breaks through the reliability bottleneck of traditional latches in three-node flip scenarios, but also achieves a good balance between structural redundancy and performance overhead, showing outstanding advantages of strong stability, high anti-interference ability and wide application range. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 This is a radiation-resistant circuit diagram of a dual-node reinforced latch based on enhanced interlock feedback in the prior art; Figure 2 FIG1 is a schematic diagram of a radiation-resistant circuit of a three-node reinforced latch based on enhanced interlock feedback in one embodiment; Figure 3 1 is a diagram illustrating simulation waveforms of six typical interference situations of a radiation-resistant circuit of a three-node reinforced latch based on enhanced interlocked feedback in one embodiment. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used in this specification are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0020] It should be noted that, when referred to in this document as an "embodiment", it means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The presentation of this phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be understood by those skilled in the art that the embodiments described herein may be combined with other embodiments. The term "and / or" used in this document refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0021] The following describes the implementation of the present invention in detail with reference to the accompanying drawings in the embodiments of the present invention.

[0022] In one embodiment, Figure 2 As shown, a radiation-resistant circuit of a three-node reinforced latch based on enhanced interlock feedback is provided, comprising: The clock-controlled signal transmission module is used to receive the input signal D and control the conduction and cutoff of multiple transmission gates through the clock signal CLK. Two inverters connected in series after each transmission gate drive nodes N1 to N5 and the output node Q.

[0023] An enhanced interlocking feedback loop is used to form a closed main feedback loop by connecting six dual-input C units CE_1 to CE_6 end to end, and introduce six three-input C units CE_7 to CE_12 to form an enhanced interlocking feedback loop together with the main feedback loop; one input end of CE_1 to CE_6 is respectively connected to nodes N1 to N5 and output node Q, the other input end of CE_1 to CE_6 is respectively connected to the output end of CE_7 to CE_12, and the three input ends of each three-input C in CE_7 to CE_12 are respectively connected to the output node Q and three adjacent nodes among nodes N5, N4, N3, N2, and N1.

[0024] Specifically, existing radiation-hardened circuits based on dual-node reinforced latches with enhanced interlocked feedback fail to adequately address the logic interference caused by simultaneous flipping of three nodes, resulting in significant deficiencies in their radiation resistance. When multiple critical nodes are simultaneously subject to charge disturbances, the interference signal propagates through the feedback loop to the output, causing logic errors. Furthermore, there is a lack of effective self-recovery mechanisms to suppress the spread of interference. This lack of structural redundancy significantly reduces the circuit's reliability in triple-node flip (TNU) scenarios, limiting its application in deep submicron processes and high-radiation intensity environments. To improve the circuit's practicality and robustness, it is necessary to introduce more comprehensive redundancy mechanisms and an enhanced interlocked feedback structure into the circuit design to further enhance its fault tolerance to multi-node flip disturbances.

[0025] To address these issues, the proposed radiation-hardened three-node latch circuit based on enhanced interlocked feedback achieves improved performance through structural optimization. The circuit's dual-input and triple-input C-units form an enhanced interlocked feedback loop, enabling self-recovery of the logic state even when any three sensitive nodes are simultaneously perturbed. Furthermore, the introduction of a series transmission gate and inverter structure in the critical signal path not only reduces data transmission latency in transparent mode but also suppresses the impact of transient interference on circuit stability through filtering. Furthermore, the complementary design of the feedback paths ensures balanced driving relationships between nodes, further enhancing the circuit's robustness and reliability in high-radiation environments.

[0026] While maintaining low latency, the three-node radiation-resistant circuit significantly enhances the fault tolerance and self-recovery capabilities to multi-node flip interference, and has better radiation resistance performance.

[0027] The radiation-resistant circuit of the three-node reinforced latch based on enhanced interlocked feedback proposed in this application is composed of 12 C units, 19 inverters and 6 transmission gates TG1 to TG6. Among them, CE_1 to CE_6 are dual-input C units, and CE_7 to CE_12 are triple-input C units. The six dual-input C units CE_1 to CE_6 are connected end to end to form a closed feedback loop. This loop can effectively suppress abnormal logic flips caused by radiation, thereby improving the stability and robustness of the circuit. To further improve the anti-interference ability of the circuit, six three-input C units (CE_7 to CE_12) are also introduced in the design, which together with the original two-input C units form an enhanced interlocked feedback loop. This loop can achieve self-recovery when disturbances occur simultaneously on any three sensitive nodes, thereby significantly enhancing the reliability and robustness of the circuit.

[0028] The above-mentioned radiation-resistant circuit of the three-node reinforced latch based on enhanced interlocked feedback, which is composed of dual-input and three-input C units to form an enhanced interlocked feedback loop, can achieve self-recovery of the logic state when any three sensitive nodes are disturbed at the same time; at the same time, the introduction of a transmission gate and inverter series structure in the key signal path not only reduces the data transmission delay in transparent mode, but also suppresses the impact of transient interference on circuit stability through filtering. In addition, the complementary design of the feedback path ensures the balance of the driving relationship between nodes, thereby further improving the robustness and reliability of the circuit in high-radiation environments. Compared with the existing technology, this circuit not only breaks through the reliability bottleneck of traditional latches in three-node flip scenarios, but also achieves a good balance between structural redundancy and performance overhead, showing outstanding advantages of strong stability, high anti-interference ability and wide application range.

[0029] In one embodiment, the clock-controlled signal transmission module includes six transmission gates TG_1 to TG_6 and 13 inverters INV1 to INV13 .

[0030] The input terminals of TG_1 to TG_3 all receive the input signal D, which is then transmitted to the input terminals of TG_4 to TG_6 after passing through INV1. The clock control terminals of TG_1 to TG_6 are linked to the input terminals of the clock signals, and INV2 to INV13 are divided into six inverter groups in groups of two. Two inverters in an inverter group are connected in series, and one inverter group is connected in series behind each of TG_1 to TG_6. The output terminals of the six inverter groups are connected to nodes N1 to N5 and the output node Q, respectively.

[0031] In one embodiment, in the enhanced interlocking feedback loop: an input terminal of CE_1 and an output terminal of CE_6 are both connected to node N1, the output terminal of CE_1 and an input terminal of CE_2 are both connected to node N2, the output terminal of CE_2 and an input terminal of CE_3 are both connected to node N3, the output terminal of CE_3 and an input terminal of CE_4 are both connected to node N4, the output terminal of CE_4 and an input terminal of CE_5 are both connected to node N5, the output terminal of CE_5 and an input terminal of CE_6 are both connected to output node Q, and the other input terminal of CE_1 to CE_6 are respectively connected to the output terminals of CE_7 to CE_12.

[0032] The output node Q and three adjacent nodes N5, N4, N3, N2, and N1 are taken as a node group, and 6 node groups are obtained. The first node group includes: output node Q, node N5, and node N4; the second node group includes: node N1, output node Q, and node N5; the third node group includes: nodes N2 and N1, and output node Q; the fourth node group includes: nodes N3, N2, and N1; the fifth node group includes: nodes N4, N3, and N2; and the sixth node group includes: nodes N5, N4, and N3.

[0033] The six node groups correspond one-to-one to CE_7 to CE_12. One node is selected from each node group and connected to one input end of CE_7 to CE_12 through an inverter. The other two nodes in each node group are respectively connected to the other two nodes of CE_7 to CE_12. The nodes connected to the input ends of CE_7 to CE_12 through inverters are: node N5, output node Q, and nodes N1 to N4.

[0034] The clock control terminals CE_7 to CE_12 receive the clock signal CLK.

[0035] In one embodiment, when the clock signal CLK is high, the circuit is in transparent mode; transmission gates TG_1 to TG_6 are all turned on, and all C units except the three-input C unit are in an operating state; nodes N1 to N5 and output node Q are driven by the input signal D after being processed by the transmission gate and inverter; in transparent mode, each node completes the pre-charge related to the input signal D to achieve data writing.

[0036] Specifically, in this anti-radiation circuit, the operating mode of the anti-radiation circuit can be switched simply by changing the clock signal CLK level. When the clock signal CLK level is high (1) and the clock signal CLKB is low (0), the circuit is in transparent mode. At this time, the transmission gates TG_1 to TG_6 are all turned on, and all C units are in working state. Nodes N1 to N5 and the output node Q are all driven by a single transmission gate or a transmission gate plus an inverter, thereby ensuring a low circuit propagation delay. In particular, two inverters are set in series at the output end of the transmission gate to form a filtering effect, which can effectively suppress high-frequency glitches and transient interference caused by radiation or noise, thereby enhancing the stability and accuracy of the signal. In this transparent mode, nodes N1 to N5 and output node Q are driven by input signal D. Output node Q, nodes N5, and N4 jointly drive node a; node N1, output node Q, and node N5 jointly drive node b; nodes N2, N1, and output node Q jointly drive node c; node N3, node N2, and node N1 jointly drive node d; node N4, node N3, and node N2 jointly drive node e; and node N5, node N4, and node N3 jointly drive node f. In transparent mode, each node is precharged in response to input signal D to enable data writing. The transmission gate and inverter work together to ensure smooth and stable transmission of input data.

[0037] In one embodiment, when the clock signal CLK is at a low level, the circuit enters a hold mode; transmission gates TG_1 to TG_6 are all closed, and nodes N1 to N5 and output node Q are no longer directly driven by the current input signal D; CE_1 to CE_12 are in an operating state, and the enhanced interlocking feedback loop maintains the circuit's self-stability.

[0038] Specifically, in this anti-radiation circuit, when the clock signal CLK level is low (0) and the clock signal CLKB is high (1), the anti-radiation circuit enters the hold mode, TG_1 to TG_6 are turned off, and nodes N1 to N5 and the output node Q are no longer directly driven by the input signal D. In this mode, the three-input C unit is turned on under clock control, wherein node f and the output node Q jointly drive node N1, node a and node N1 jointly drive node N2, node N2 and b jointly drive node N3, node N3 and c jointly drive node N4, node N4 and d jointly drive node N5, and node N5 and e jointly drive the output node Q. The driving relationship of the remaining nodes a to f is consistent with the transparent mode. The feedback interlock loop formed by the twelve C units maintains the self-stability and robustness of the circuit, effectively ensuring the stability of the data in the hold mode.

[0039] The circuit contains 12 sensitive nodes (N1 to N5, Q, and a to f). For the triple-node upset (TNU) scenario, there are 220 possible triple-node upset combinations. Due to the circuit's high symmetry, these can be further categorized into six typical scenarios. These six typical scenarios will be discussed further below.

[0040] In T1, when the inputs of two adjacent C cells flip, the flipped sensitive nodes are N1, a, and b, meaning the inputs of CE_1 and CE_2 flip. CE_1's output node N2 also flips, causing CE_2 to affect sensitive node N3, and CE_10 to affect node d. At the input of CE_3, only one node flips, leaving sensitive nodes N4, N5, Q, e, and f unaffected. Node a then returns to its original logic value via CE_7, sensitive node N1 to its original value via CE_6, and node b to its original value via CE_2. Simultaneously, CE_1, CE_2, and CE_10 flip sensitive nodes N2, N3, and d back to their original logic levels. This demonstrates that a three-node flip is self-recoverable.

[0041] In T2, when the two C-cells with input flips are not adjacent but separated by a C-cell, the flipped sensitive nodes are N1, a, and N3. This means that the inputs of CE_1 and CE_3 are flipped. CE_1's output node N2 flips, while CE_10 affects node d. At the input of CE_3, only one node flips, leaving sensitive nodes N4, N5, Q, e, and f unaffected. Node a then recovers via CE_7, and node N1 recovers via CE_6. Meanwhile, CE_1, CE_2, and CE_10 flip sensitive nodes N2, N3, and d back to their original state. This demonstrates that a three-node flip is self-recoverable.

[0042] In T3, when two C-cell inputs flip, separated by two C-cells, the flipped sensitive nodes are N1, a, and N4. This means that the inputs of CE_1 and CE_4 flip. CE_1's output node N2 flips, while only one node on the input of CE_4 flips. Subsequent sensitive nodes N5, output node Q, and nodes e and f are unaffected. Node N4 then recovers via CE_3, node a recovers via CE_7, and sensitive node N1 recovers via CE_6. Simultaneously, CE_1 flips node N2 back. This demonstrates that a three-node flip is self-recoverable.

[0043] In T4, when the inputs of three adjacent C cells flip simultaneously, the flipped sensitive nodes are N1, N2, and N3, meaning the inputs of CE_1, CE_2, and CE_3 flip. The self-recovery principle is the same as in T2 and will not be further explained. This shows that a three-node flip can self-recover.

[0044] In T5, when the inputs of two adjacent C-cells and a non-adjacent C-cell flip, the flipped sensitive nodes are N1, N2, and N4. That is, the inputs of CE_1, CE_2, and CE_4 flip. The remaining nodes are unaffected. CE_1, CE_2, and CE_10 flip sensitive nodes N2, N3, and d back, while CE_6, CE_1, and CE_3 flip sensitive nodes N1, N2, and N4 back. This shows that a three-node flip is self-recoverable.

[0045] In T6, when the inputs of three non-adjacent C cells flip, the sensitive nodes flipped are N1, N3, and N5. This means the inputs of CE_1, CE_3, and CE_5 flip. Other nodes are unaffected, and CE_6, CE_2, and CE_4 flip the sensitive nodes N1, N3, and N5 back to their original logic levels. This demonstrates that a three-node flip is self-recoverable.

[0046] Based on the circuit's symmetrical structure and enhanced interlocking feedback characteristics, it can ensure that different types of three-node disturbances can achieve stable recovery of the logic state through the self-recovery mechanism, and the inverter connected in series after the transmission gate further improves the circuit's filtering ability for transient interference, thereby significantly enhancing the circuit's robustness and anti-interference ability.

[0047] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0048] The above embodiments merely illustrate several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of protection of the present application. It should be noted that a person skilled in the art may make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application.

Claims

1. A radiation-resistant circuit based on a three-node reinforced latch with enhanced interlocked feedback, characterized in that: include: A clock-controlled signal transmission module receives an input signal D and controls the on / off state of multiple transmission gates via a clock signal CLK. Two inverters connected in series behind each transmission gate drive nodes N1 to N5 and the output node Q. An enhanced interlocking feedback loop is used to form a closed main feedback loop by connecting six dual-input C units CE_1 to CE_6 end to end, and introduce six three-input C units CE_7 to CE_12 to form an enhanced interlocking feedback loop together with the main feedback loop; one input end of CE_1 to CE_6 is respectively connected to nodes N1 to N5 and output node Q, the other input end of CE_1 to CE_6 is respectively connected to the output end of CE_7 to CE_12, and the three input ends of each three-input C in CE_7 to CE_12 are respectively connected to the output node Q and three adjacent nodes among nodes N5, N4, N3, N2, and N1.

2. The radiation-resistant circuit of the three-node reinforced latch based on enhanced interlocked feedback according to claim 1, characterized in that: The clock-controlled signal transmission module includes 6 transmission gates TG_1 to TG_6 and 13 inverters INV1 to INV13; The input terminals of TG_1 to TG_3 all receive the input signal D, which is then transmitted to the input terminals of TG_4 to TG_6 after passing through INV1. The clock control terminals of TG_1 to TG_6 are linked to the input terminals of the clock signals, and INV2 to INV13 are divided into six inverter groups in groups of two. Two inverters in an inverter group are connected in series, and one inverter group is connected in series behind each of TG_1 to TG_6. The output terminals of the six inverter groups are connected to nodes N1 to N5 and the output node Q, respectively.

3. The radiation-resistant circuit of the three-node reinforced latch based on enhanced interlocked feedback according to claim 1, characterized in that: In the enhanced interlock feedback loop: An input terminal of CE_1 and an output terminal of CE_6 are both connected to node N1, an output terminal of CE_1 and an input terminal of CE_2 are both connected to node N2, an output terminal of CE_2 and an input terminal of CE_3 are both connected to node N3, an output terminal of CE_3 and an input terminal of CE_4 are both connected to node N4, an output terminal of CE_4 and an input terminal of CE_5 are both connected to node N5, an output terminal of CE_5 and an input terminal of CE_6 are both connected to output node Q, and the other input terminals of CE_1 to CE_6 are respectively connected to the output terminals of CE_7 to CE_12; The output node Q and three adjacent nodes N5, N4, N3, N2, and N1 are grouped as a node, resulting in six node groups. The first node group includes: output node Q, node N5, and node N4; the second node group includes: node N1, output node Q, and node N5; the third node group includes: nodes N2 and N1, and output node Q; the fourth node group includes: nodes N3, N2, and N1; the fifth node group includes: nodes N4, N3, and N2; and the sixth node group includes: nodes N5, N4, and N3; The six node groups correspond one-to-one to CE_7 to CE_12. One node is selected from each node group and connected to one input end of CE_7 to CE_12 through an inverter. The other two nodes in each node group are respectively connected to the other two nodes of CE_7 to CE_12. The nodes connected to the input ends of CE_7 to CE_12 through inverters are: node N5, output node Q, and nodes N1 to N4.

4. The radiation-resistant circuit of the three-node reinforced latch based on enhanced interlocked feedback according to claim 1, characterized in that: When the clock signal CLK is at a high level, the radiation-resistant circuit is in transparent mode; transmission gates TG_1 to TG_6 are all turned on, and all C units are in an operating state; nodes N1 to N5 and output node Q are driven by the input signal D after being processed by the transmission gate and inverter; in transparent mode, each node completes the pre-charge related to the input signal D to achieve data writing.

5. The radiation-resistant circuit of the three-node reinforced latch based on enhanced interlocked feedback according to claim 1, characterized in that: When the clock signal CLK is low, the anti-radiation circuit enters hold mode; transmission gates TG_1–TG_6 are all closed, and nodes N1 to N5 and output node Q are no longer directly driven by the current input signal D; CE_1 to CE_12 are in operation, and the enhanced interlocking feedback loop maintains the circuit's self-stability.

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