Semiconductor stack structure and preparation method thereof, high-bandwidth memory and electronic equipment

Abstract

The invention provides a semiconductor stacking structure and a preparation method thereof, a high-bandwidth memory and electronic equipment, and relates to the technical field of semiconductor chips. The semiconductor stacked structure comprises a plurality of stacked semiconductor structures, each semiconductor structure comprises a storage unit layer and a bonding layer, the bonding layer is arranged on the surface, facing the adjacent semiconductor structure, of the storage unit layer, and the bonding layer is coupled to the storage unit layer. Wherein two adjacent semiconductor structures are in bonding connection through a bonding layer. The semiconductor structure is applied to the dynamic random access memory so as to realize data reading and writing operation.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor chip, and particularly relates to a semiconductor stack structure and a preparation method thereof, a high-bandwidth memory and an electronic device. BACKGROUND

[0002] With the improvement of process technology, circuit design and manufacturing process, dynamic random access memory (DRAM) is scaled to a smaller size. However, as the feature size of the semiconductor structure in the DRAM approaches the lower limit, the planar process and manufacturing technology become challenging and costly, causing the density of the semiconductor structure to approach the upper limit, which in turn makes it difficult to further miniaturize the semiconductor stack structure obtained by stacking multiple semiconductor structures.

[0003] Therefore, how to realize the miniaturization of the semiconductor stack structure has become a technical problem to be solved by the current technical personnel. SUMMARY

[0004] Embodiments of the present disclosure provide a semiconductor stack structure and a preparation method thereof, a high-bandwidth memory and an electronic device.

[0005] Embodiments of the present disclosure adopt the following technical solutions:

[0006] In one aspect, a semiconductor stack structure is provided. The semiconductor stack structure includes a plurality of stacked semiconductor structures, each semiconductor structure including a memory cell layer and a bonding layer, the memory cell layer being provided with the bonding layer on a surface facing an adjacent semiconductor structure, and the bonding layer being coupled to the memory cell layer. The adjacent two semiconductor structures are bonded and connected by the bonding layer.

[0007] In some embodiments, the bonding layer includes a plurality of bonding portions. The semiconductor structure further includes a plurality of connecting portions, the connecting portions penetrating the memory cell layer and being connected to the bonding portions. The number of the connecting portions is less than or equal to the number of the bonding portions.

[0008] In some embodiments, at least one side of the plurality of stacked semiconductor structures in the stacking direction is provided with a substrate, and the connecting portions of the semiconductor structure close to the substrate extend into the substrate.

[0009] In some embodiments, the memory cell layer includes a plurality of arrayed memory cells.

[0010] In some embodiments, the connecting portions and the bonding portions have a size in a first direction less than or equal to 1 μm. The first direction is perpendicular to the stacking direction.

[0011] In another aspect, a high bandwidth memory is also provided. The high bandwidth memory includes a semiconductor stack structure, a logic chip, and a controller. The semiconductor stack structure is as described above. The logic chip is stacked on one side of the semiconductor stack structure and coupled to the semiconductor stack structure. The controller is coupled to the logic chip to control the semiconductor stack structure to store data by controlling the logic chip.

[0012] In yet another aspect, a method for fabricating a semiconductor stack structure is provided. The method includes forming a plurality of semiconductor structures and stacking and bonding the plurality of semiconductor structures. Each semiconductor structure includes a memory cell layer and a bonding layer, and the memory cell layer has the bonding layer formed on a surface thereof facing a surface of an adjacent semiconductor structure, and the memory cell layer is coupled to the bonding layer. The adjacent two semiconductor structures are bonded by the bonding layer.

[0013] In some embodiments, the forming and stacking and bonding the plurality of semiconductor structures includes forming a plurality of semiconductor devices, each semiconductor device including a memory cell layer and a bonding layer formed on a surface of the memory cell layer facing away from the bonding layer. The plurality of semiconductor devices includes two first semiconductor devices and a plurality of second semiconductor devices. Another bonding layer is formed on a surface of the memory cell layer of each second semiconductor device facing away from the bonding layer, and the plurality of second semiconductor devices are sequentially bonded by the bonding layer in a stacking direction. The two first semiconductor devices are bonded by the bonding layer to two second semiconductor devices at two ends of the stacking direction, respectively.

[0014] In some embodiments, the semiconductor device further includes a substrate, and the memory cell layer is disposed between the substrate and the bonding layer. Before the forming another bonding layer on the surface of the memory cell layer of each second semiconductor device facing away from the bonding layer and the sequentially bonding the plurality of second semiconductor devices by the bonding layer in the stacking direction, the method includes removing the substrate of each second semiconductor device to expose the surface of the memory cell layer of each second semiconductor device facing away from the bonding layer.

[0015] In some embodiments, the forming the plurality of semiconductor devices includes forming the memory cell layer on one side of a substrate. A plurality of connection portions are formed, each connection portion extending through the memory cell layer and to the substrate. A bonding layer is formed on a side of the memory cell layer facing away from the substrate, and the bonding layer includes a plurality of bonding portions, each bonding portion being connected to a connection portion.

[0016] In yet another aspect, a method for fabricating a high bandwidth memory is provided. The method includes forming a first interconnection layer on one side of a semiconductor stack structure. A second interconnection layer is formed on one side of a logic chip. The semiconductor stack structure and the logic chip are stacked and bonded by the first interconnection layer and the second interconnection layer.

[0017] In yet another aspect, an electronic device is provided, the electronic device including a high bandwidth memory as described above. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings described in the following description are only some drawings of the embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual timing of signals, etc. of the products involved in the embodiments of the present disclosure.

[0019] Figure 1 A structural block diagram of an electronic device provided by some embodiments of the present disclosure is shown in FIG. 1.

[0020] Figure 2 A structural block diagram of a memory provided by some embodiments of the present disclosure is shown in FIG. 2.

[0021] Figure 3 A structural schematic diagram of a high bandwidth memory provided by some embodiments of the present disclosure is shown in FIG. 3.

[0022] Figure 4 A structural schematic diagram of a semiconductor stack structure provided by some embodiments of the present disclosure is shown in FIG. 4.

[0023] Figure 5 A structural schematic diagram of a memory cell layer provided by some embodiments of the present disclosure is shown in FIG. 5.

[0024] Figure 6 A flowchart of a preparation method of a semiconductor stack structure provided by some embodiments of the present disclosure is shown in FIG. 6.

[0025] Figure 7 A structural schematic diagram of a second semiconductor device corresponding to the preparation method in FIG. 6 is shown in FIG. 7. Figure 6

[0026] A structural schematic diagram of a first semiconductor device corresponding to the preparation method in FIG. 6 is shown in FIG. 8. Figure 8 Figure 6 A structural schematic diagram of a semiconductor stack structure corresponding to the preparation method in FIG. 6 is shown in FIG. 9.

[0027] Figure 9 Figure 6 A structural schematic diagram of another semiconductor stack structure provided by some embodiments of the present disclosure is shown in FIG. 10.

[0028] Figure 10 A structural schematic diagram of another semiconductor stack structure provided by some embodiments of the present disclosure is shown in FIG. 10.

[0029] Figure 11 ​​A schematic structural diagram of another semiconductor stack structure provided in some embodiments of the present disclosure;

[0030] Figure 12 A flowchart of a method for manufacturing a semiconductor device provided in some embodiments of the present disclosure;

[0031] Figure 13 For Figure 12 A schematic structural diagram of a semiconductor device corresponding to the provided preparation method;

[0032] Figure 14 For Figure 12 A schematic structural diagram of a semiconductor stack structure corresponding to the provided preparation method;

[0033] Figure 15 A flowchart of a method for preparing a high-bandwidth memory provided in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0034] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0035] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary," or "some examples" are intended to indicate that specific features, structures, materials, or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0036] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0037] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0038] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0039] As used herein, the term "substrate" refers to a material onto which subsequent layers of material may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0040] Figure 1 The block diagram of the structure of an electronic device 9000 provided in some embodiments of the present disclosure. The electronic device 9000 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device (such as a smart watch, a smart bracelet, smart glasses, etc.), a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0041] like Figure 1As shown, the electronic device 9000 can include a high-bandwidth memory 910 and a host 920. Among others, the high-bandwidth memory 910 can be integrated into various types of memory devices, such as a memory card. Among others, the memory card includes any one of a PC card (PCMCIA, Personal Computer Memory Card International Association), a compact flash (CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC), a secure digital memory card (SD), and a universal flash storage (UFS). That is, the high-bandwidth memory 910 can be applied to and packaged into different types of electronic products.

[0042] The host 920 can include a processor of the electronic device 9000, such as a central processing unit (CPU) or a system-on-chip (SoC), such as an application processor (AP). The host 920 can be configured to transmit or receive data to or from the memory.

[0043] In some embodiments, the high-bandwidth memory 910 can have one or more memories 911 and a controller 912. For example, the controller 912 can be configured to operate in a low duty cycle environment, such as an SD card, a CF card, a universal serial bus (USB) flash drive, or other media used in electronic devices for personal computers, digital cameras, mobile phones, etc. Alternatively, in other examples, the controller 912 is configured to operate in a high duty cycle environment, such as an SSD or eMMC used for data storage of mobile devices such as smartphones, tablets, laptops, etc., and enterprise storage arrays. Alternatively, in some examples, the controller 912 is coupled to the memory 911 and the host 920 and configured to control data in the memory 911 while being able to communicate with an external device, such as a host.

[0044] The number of memories 911 in the high-bandwidth memory 910 can be one or more, Figure 1911 as an example. The controller 912 can manage the data stored in each memory 911 and communicate with the host 920. The controller 912 can be configured to control the operations of each memory 911, such as read, write and refresh operations. The controller 912 can also be configured to manage various functions related to the data stored or to be stored in each memory 911, including but not limited to refresh and timing control, command / request translation, buffering and scheduling, and power management. In some embodiments, the controller 912 is also configured to determine the maximum memory capacity that can be used by the computer system, the number of memory banks, memory type and speed, memory granule data depth and data width, and other important parameters. Any other suitable function can also be performed by the controller 912. The controller 912 can communicate with an external device (e.g., the host 920) according to a specific communication protocol. For example, the controller 912 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, peripheral component interconnection (PCI) protocol, PCI Express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer small interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, FireWire protocol, etc.

[0045] Figure 2 This is a structural block diagram of the memory 911 provided in some embodiments of the present disclosure. Figure 2 As shown, the memory 911 includes a memory cell array 913 and a peripheral circuit 914 for controlling the memory cell array 913. The peripheral circuit 914 (also referred to as a control and sensing circuit) may include any suitable digital, analog, and / or mixed signal circuit for facilitating the operation of the memory cell array 913. For example, the peripheral circuit 914 may include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), an input / output (I / O) circuit, a charge pump, a voltage source or generator, a current or voltage reference, any portion (e.g., a sub-circuit) of the aforementioned functional circuits, or any active or passive component of the circuit (e.g., a transistor, a diode, a resistor, or a capacitor).

[0046] Exemplarily, the peripheral circuit 914 can use complementary metal-oxide-semiconductor (CMOS) technology, for example, it can be implemented with a logic process (e.g., a technology node of 90 nm, 65 nm, 60 nm, 45 nm, 32 nm, 28 nm, 22 nm, 20 nm, 16 nm, 14 nm, 10 nm, 7 nm, 5 nm, 3 nm, 2 nm, etc.).

[0047] The memory cell array 913 and the peripheral circuit 914 can be arranged side by side in the same plane, for example, on the same wafer, that is, the memory cell array 913 and the peripheral circuit 914 can be located in the same semiconductor structure. The memory cell array 913 and the peripheral circuit 914 can also be formed on different wafers and bonded together in a face-to-face manner. Figure 2 As shown, when the memory cell array 913 and the peripheral circuit 914 are formed on different wafers and bonded together in a face-to-face manner, the memory 911 can include a first semiconductor structure 901 and a second semiconductor structure 902, and a bonding interface 903 between the first semiconductor structure 901 and the second semiconductor structure 902. Among them, the first semiconductor structure 901 can include the memory cell array 913, and the second semiconductor structure 902 can include the peripheral circuit 914.

[0048] Among them, the memory cell array 913 can be an array of memory cells using vertical transistors as switching and selection devices. In some embodiments, the memory cell array 913 can be a dynamic random access memory cell array. For ease of description, a DRAM cell array can be used to describe an example of the memory cell array 913 in the present disclosure. However, it should be understood that the memory cell array 913 is not limited to a DRAM cell array, for example, it can also include any other suitable type of memory cell array 913 that can use vertical transistors as switching and selection devices, such as a PCM cell array, a static random access memory (SRAM) cell array, a FRAM cell array, a resistive memory cell array, a magnetic memory cell array, a spin transfer torque (STT) memory cell array, etc.

[0049] When the memory cell array 913 is a DRAM cell array, the memory cells therein are DRAM cells. A DRAM cell includes a capacitor for storing a data bit as a positive or negative charge and one or more transistors (also known as pass transistors) for controlling (e.g., switching and selecting) access to the DRAM cell. In some embodiments, each DRAM cell is a transistor and capacitor (1T1C) cell. According to some embodiments, the DRAM cell can be refreshed by the peripheral circuit 914 to retain data.

[0050] Figure 3 A schematic diagram of the structure of a high bandwidth memory 910 provided in some embodiments of the present disclosure.

[0051] like Figure 3 As shown, in some embodiments, a high bandwidth memory (HBM) 910 includes a semiconductor stack structure 100, a logic chip 915, and a controller 912. The logic chip 915 is stacked on one side of the semiconductor stack structure 100 and coupled to the semiconductor stack structure 100. The controller 912 is coupled to the logic chip 915 to control the semiconductor stack structure 100 to store data by controlling the logic chip 915. The semiconductor stack structure 100 will be described in detail in subsequent embodiments and will not be described in detail here.

[0052] In this embodiment, the semiconductor stacked structure 100 includes one or more memories 911 , wherein the multiple memories 911 are stacked sequentially along a stacking direction Z. By stacking multiple memories 911 , the high-bandwidth memory 910 can have high bandwidth and excellent storage performance.

[0053] The logic chip 915 stacked on one side of the semiconductor stack structure 100 can control one or more memories 911 in the semiconductor stack structure 100 , thereby enabling the high bandwidth memory 910 to write, read or clear data.

[0054] In addition, the logic chip 915 can be connected to the controller 912 through a silicon chip with an interconnection function, so that the controller 912 controls the logic chip 915 to control one or more memories 911 in the semiconductor stack structure 100.

[0055] In some examples, the controller 912 may include a CPU, a graphics processing unit (GPU), a SOC, or the like.

[0056] Figure 4 A schematic structural diagram of a semiconductor stack structure 100 provided in some embodiments of the present disclosure.

[0057] like Figure 4 As shown, in some embodiments, the semiconductor stacked structure 100 includes: a plurality of stacked semiconductor structures 110. The semiconductor structure 110 includes a memory cell layer 111 and a bonding layer 112. The bonding layer 112 is provided on the surface of the memory cell layer 111 facing the adjacent semiconductor structure 110, and the bonding layer 112 is coupled to the memory cell layer 111. The adjacent semiconductor structures 110 are bonded to each other via the bonding layer 112.

[0058] In this embodiment, two adjacent semiconductor structures 110 are connected to each other through hybrid bonding technology, so a bonding layer 112 is provided on the surface of the storage unit layer 111 facing the adjacent semiconductor structure 110, and the bonding layer 112 is used to realize the bonding connection while also realizing signal transmission between the two adjacent storage unit layers 111.

[0059] In some examples, hybrid bonding is a direct bonding technique, that is, a bond is formed between surfaces without an intermediate layer (such as solder or adhesive) and can achieve both metal-to-metal bonding and dielectric-to-dielectric bonding.

[0060] In this embodiment, two adjacent semiconductor structures 110 are bonded together via the bonding layer 112 , so that the height of the semiconductor stack structure 100 formed by stack bonding can be reduced, thereby facilitating miniaturization of the semiconductor stack structure 100 .

[0061] Furthermore, the introduction of the bonding layer enables the independent fabrication of multiple semiconductor structures 110. That is, two adjacent semiconductor structures 110 can be independently fabricated on different production lines. By fabricating multiple semiconductor structures 110 simultaneously, the fabrication efficiency of the semiconductor structures 110 can be improved, thereby further improving the fabrication efficiency of the semiconductor stacked structure 100.

[0062] Please continue reading Figure 4 In some embodiments, the bonding layer 112 includes a plurality of bonding portions 1121. The semiconductor structure 110 further includes a plurality of connecting portions 113, which penetrate the memory cell layer 111 and are connected to the bonding portions 1121. The number of the connecting portions 113 is less than or equal to the number of the bonding portions 1121.

[0063] Based on the hybrid bonding technology, the connection between two adjacent semiconductor structures 110 can be achieved through a plurality of bonding portions 1121 provided in the bonding layer 112. For example, the bonding portions 1121 can include metal contacts, such as copper contacts.

[0064] In some examples, the storage unit layer 111 is provided with a connection part 113 extending along the stacking direction Z. The connection part 113 can be used for signal transmission within a single storage unit layer 111, and the connection between the connection part 113 and the bonding part 1121 can be used for signal transmission between two adjacent storage unit layers 111. Based on this, the embodiment can realize signal transmission between a plurality of storage unit layers 111 stacked in the stacking direction Z.

[0065] The number of connection parts 113 is less than or equal to the number of bonding parts 1121, which can avoid too many connection parts 113. For example, the number of connection parts 113 is greater than the number of bonding parts 1121. The connection part 113 is used to realize signal transmission within a single storage unit layer 111 and signal transmission between two adjacent storage unit layers 111. In actual application, the number of connection parts 113 can be reasonably set according to design requirements, which can avoid too many connection parts 113 occupying the layout area of the storage unit layer 111, thereby avoiding resource waste and reducing production cost.

[0066] The bonding part 1121 is used to bond two adjacent storage unit layers 111, thereby realizing signal transmission between two adjacent storage unit layers 111. Since the bonding connection is the connection between the surfaces of two storage unit layers 111, the number and position of the bonding part 1121 are related to the size of the bonding surface. On the basis of the unchanged size of the bonding surface, increasing the number of bonding parts 1121 can improve the stability and reliability of the bonding connection between the two storage unit layers 111. In addition, increasing the number of bonding parts 1121 is conducive to the uniformity of subsequent dry etching process or chemical mechanical polishing (CMP) process, thereby improving the flatness and cleanliness of the bonding interface, so that the resistivity is more uniform, thereby further improving the stability and reliability of the semiconductor structure 110. Based on this, the number of connection parts 113 in the embodiment can be less than or equal to the number of bonding parts 1121.

[0067] Please continue to refer to Figure 4 In some embodiments, at least one side of the plurality of stacked semiconductor structures 110 in the stacking direction Z is provided with a substrate 114, and the connection part 113 of the semiconductor structure 110 close to the substrate 114 extends into the substrate 114.

[0068] In the embodiment, by providing the substrate 114 on one side of the semiconductor structure 110, support force can be provided for a single semiconductor structure 110 or a plurality of semiconductor structures 110 after stacking, thereby ensuring that the semiconductor structure 110 has sufficient strength during preparation, testing and transportation, and thereby improving the stability and reliability of the semiconductor structure.

[0069] In addition, by extending the connecting portion 113 of the semiconductor structure 110 close to the substrate 114 into the substrate 114, the electrical connection between the semiconductor stack structure 100 and other external devices can be achieved while the substrate 114 is reserved. For example, the semiconductor stack structure 100 obtained by stacking multiple semiconductor structures 110 can be electrically connected to a logic chip 915 through the connecting portion 113 in the substrate 114 (see Figure 3 ), and then the control of one or more semiconductor structures 110 in the semiconductor stack structure 100 can be realized by using the logic chip 915, so as to realize the data writing, reading or clearing operation of the semiconductor structure 110.

[0070] Figure 5 A structure schematic diagram of a memory cell layer 111 provided by some embodiments of the present disclosure is shown.

[0071] As shown in Figure 5 , in some embodiments, the memory cell layer 111 includes a plurality of arrayed memory cells 1111.

[0072] In some examples, the semiconductor structure 110 can be a wafer, and in this case, the plurality of memory cells 1111 included in the memory cell layer 111 can be a plurality of dies. In this embodiment, the adjacent two wafer-level memory cell layers 111 can be directly bonded and connected by using the bonding layer 112, so as to realize the signal transmission between the two memory cell layers 111. In other examples, the semiconductor structure 110 can also be other devices with storage function, which is not limited by the present disclosure.

[0073] For example, in actual application, the semiconductor stack structure 100 formed by stacking a plurality of wafer-level memory cell layers 111 can be cut as needed, so as to realize the splitting of the dies (i.e., the memory cells 1111) on the multiple semiconductor structures 110 in the same process.

[0074] In this way, the process of splitting the plurality of dies on each memory cell layer 111 can be simplified, so as to simplify the preparation process flow, improve the preparation efficiency, and reduce the production cost. In addition, since the bonding operation is performed on the wafer-level memory cell layer 111, the process window is large, so the difficulty of the bonding process can be reduced, and then the reliability and stability of the semiconductor stack structure 100 formed after bonding can be improved.

[0075] Please continue to refer to Figure 4 In some embodiments, the size of the connecting portion 113 and the bonding portion 1121 in the first direction X is less than or equal to 1 μm. The first direction X is perpendicular to the stacking direction Z.

[0076] In the embodiment, the size of the connection part 113 in the first direction X is less than or equal to 1 μm, which can reduce the layout area occupied by the connection part 113 on the memory cell layer 111, thereby reducing the size of the memory cell layer 111 and even the semiconductor stack structure 100, and further realizing further miniaturization of the semiconductor stack structure 100.

[0077] In some examples, in the preparation process of the memory cell layer 111, due to different preparation procedures, the layout position for the preparation of the connection part 113 can be reserved in advance before the preparation of the connection part 113, thereby providing sufficient process window for the subsequent preparation of the connection part 113. In the embodiment, the size of the connection part 113 in the first direction X is less than or equal to 1 μm, which can reduce the layout area reserved for the preparation of the connection part 113, thereby improving the device density of the memory cell layer 111, and further realizing further miniaturization of the memory cell layer 111 in structure.

[0078] In other examples, since the size of the connection part 113 in the first direction X is less than or equal to 1 μm, the layout area occupied by the connection part 113 is small, and thus the requirement for the layout position can be reduced, that is, the position can be flexibly selected. For example, in the preparation procedure of other devices, based on the size advantage of the connection part 113, the layout position for the connection part 113 can not be reserved, and thus in the preparation process of the connection part 113, the layout position can be selected in combination with the layout positions of other devices on the current memory cell layer 111, that is, the layout position can be selected by "filling the gap", thereby improving the layout utilization rate of the memory cell layer 111.

[0079] In addition, by flexibly selecting the layout position of the connection part 113, the distance between the connection part 113 and the device electrically connected thereto can be shortened, thereby shortening the line length, improving the signal transmission efficiency, reducing the transmission delay and loss.

[0080] In the embodiment, the size of the bonding part 1121 in the first direction X is less than or equal to 1 μm, which can reduce the layout area occupied by a single bonding part 1121 on the basis of realizing signal transmission between two adjacent memory cell layers 111, thereby increasing the number of bonding parts 1121 under the premise that the size of the semiconductor structure 110 remains unchanged, thereby improving the flatness and cleanliness of the bonding interface, thereby making the resistivity more uniform, and improving the stability and reliability of the semiconductor structure 110. In addition, the size advantage of the bonding part 1121 can improve the bonding density between a plurality of semiconductor structures 110, thereby increasing the number of stacked semiconductor structures 110 under the condition that the height of the semiconductor stack structure 100 is limited, and further increasing the stacking density of the semiconductor stack structure 100.

[0081] Based on the semiconductor stacked structure 100 provided in some of the above embodiments, an embodiment of the present disclosure further provides a method for preparing the semiconductor stacked structure 100 . The above-mentioned semiconductor stacked structure 100 can be prepared by the method for preparing the semiconductor stacked structure 100 .

[0082] In some embodiments, the method for preparing the semiconductor stacked structure 100 includes the following step S1 .

[0083] S1. Form multiple semiconductor structures 110, and stack and bond the multiple semiconductor structures 110. The semiconductor structure 110 includes a memory cell layer 111 and a bonding layer 112. The bonding layer 112 is formed on the surface of the memory cell layer 111 facing the adjacent semiconductor structure 110. The memory cell layer 111 is coupled to the bonding layer 112. Two adjacent semiconductor structures 110 are bonded to each other via the bonding layer 112.

[0084] In step S1 , the plurality of semiconductor structures 110 are bonded together via the bonding layer 112 , which can reduce the height of the semiconductor stack structure 100 formed after bonding, thereby increasing the stacking density of the semiconductor stack structure 100 and facilitating further miniaturization of the semiconductor stack structure 100 .

[0085] In some examples, in this embodiment, multiple semiconductor structures 110 can be pre-fabricated and then stacked, thereby enabling simultaneous fabrication of multiple semiconductor structures 110, thereby improving the fabrication efficiency of the semiconductor structures 110, and further improving the fabrication efficiency of the semiconductor stacked structure 100. In addition, the fabrication method of forming the semiconductor stacked structure 100 by stacking multiple pre-fabricated semiconductor structures 110 can reduce the process difficulty of fabricating the semiconductor stacked structure 100.

[0086] In other examples, the preparation process of multiple semiconductor structures 110 can also be interspersed with the stacking process, that is, after stacking any two semiconductor structures 110, the next semiconductor structure 110 is prepared, and then the next semiconductor structure 110 is stacked with the previous two semiconductor structures 110, and the preparation is repeated in this way.

[0087] In some other examples, the preparation process may also be implemented in other reasonable preparation orders, and the embodiments of the present disclosure are not limited to this.

[0088] Figure 6 A flowchart of a method for preparing a semiconductor stacked structure 100 provided in some embodiments of the present disclosure is provided. Figure 7 For Figure 6 A schematic structural diagram of the second semiconductor device 122 corresponding to the preparation method in FIG. Figure 8 For Figure 6a structure diagram of a first semiconductor device 121 corresponding to the preparation method in the above step S1, Figure 9 as shown in the above step S1, Figure 6 a structure diagram of a semiconductor stack structure 100 corresponding to the preparation method in the above step S1.

[0089] as shown in the above step S1, Figure 6 In some embodiments, the above step S1 can further include the following steps S11-S13:

[0090] S11, forming a plurality of semiconductor devices, the semiconductor device including a memory cell layer 111 and a bonding layer 112 disposed on one side surface of the memory cell layer 111. Among the plurality of semiconductor devices, two first semiconductor devices 121 and a plurality of second semiconductor devices 122 are included.

[0091] In this step S11, by forming a bonding layer 112 on one side surface of the semiconductor device, the bonding connection between the adjacent two semiconductor devices can be realized, so as to realize the signal transmission between the adjacent two semiconductor devices. In this way, the stacking density of the semiconductor stack structure 100 after bonding can be improved through hybrid bonding process, thereby facilitating the further miniaturization of the semiconductor stack structure 100 in structure after bonding.

[0092] S12, forming another bonding layer 112 on the surface of the memory cell layer 111 of the second semiconductor device 122 away from the bonding layer 112, and making the plurality of second semiconductor devices 122 sequentially pass through the bonding layer 112 for bonding connection in the stacking direction Z.

[0093] as shown in the above step S1, Figures 7-9 In some examples, when the number of semiconductor devices stacked and bonded is greater than 2, the semiconductor devices are divided into first semiconductor devices 121 and second semiconductor devices 122 according to the positions of the semiconductor devices in the semiconductor stack structure 100 and the structures of the semiconductor devices after bonding. Among them, the semiconductor devices located at both ends of the semiconductor stack structure 100 in the stacking direction Z are the first semiconductor devices 121, and the other semiconductor devices located between the two first semiconductor devices 121 are the second semiconductor devices 122.

[0094] For example, in the bonding process, since the second semiconductor device 122 is bonded with semiconductor devices on both sides in the stacking direction Z, the memory cell layer 111 of the second semiconductor device 122 is formed with a bonding layer 112 on both sides in the stacking direction Z, so as to realize the bonding of the second semiconductor device 122 with the semiconductor devices 120 on both sides.

[0095] In some examples, when the number of second semiconductor devices 122 is greater than or equal to 2, each second semiconductor device 122 is bonded to other semiconductor devices by repeating the method of step S12.

[0096] S13, bonding two first semiconductor devices 121 to two second semiconductor devices 122 at both ends of the stacking direction Z through the bonding layer 112.

[0097] Please continue to refer to Figure 9 After the above step S12 is completed, another bonding layer 112 is formed on the side of the two second semiconductor devices 122 at the top and bottom ends away from the adjacent second semiconductor device 122, and is bonded to one first semiconductor device 121, respectively, to complete the preparation of the semiconductor stack structure 100.

[0098] In this embodiment, by arranging the first semiconductor device 121 on both sides of the semiconductor stack structure 100, the process of preparing the bonding layer 112 on both sides of the semiconductor stack structure 100 can be omitted, thereby simplifying the preparation process difficulty and reducing the production cost.

[0099] In some embodiments, the semiconductor device further comprises a substrate 114, and the storage unit layer 111 is arranged between the substrate 114 and the bonding layer 112.

[0100] In this embodiment, the semiconductor device can be divided into a first semiconductor device 121 and a second semiconductor device 122, wherein the second semiconductor device 122 is further prepared on the basis of the first semiconductor device 121. Therefore, before the second semiconductor device 122 is prepared, the semiconductor device is the first semiconductor device 121.

[0101] Based on this, please continue to refer to Figure 8 The side of the semiconductor device is provided with a substrate 114, so that the substrate 114 can be used to provide support for the semiconductor device, so as to ensure that the semiconductor device has sufficient strength during preparation, testing and bonding, thereby improving the reliability of the semiconductor device.

[0102] In this case, before the above step S12, the following step S110 is further included:

[0103] S110, removing the substrate 114 of the second semiconductor device 122 to expose the surface of the storage unit layer 111 of the second semiconductor device 122 away from the bonding layer 112.

[0104] Figure 10 Another structural schematic diagram of a semiconductor stack structure 100 provided by some embodiments of the present disclosure is shown in the following figure: Figure 11A schematic structural diagram of another semiconductor stacked structure 100 provided in some embodiments of the present disclosure.

[0105] like Figure 10 and Figure 11 As shown, in the process of stacking the second semiconductor device 122, the substrate 114 on one side thereof can be removed by an etching process or a chemical mechanical polishing process, thereby exposing the surface of the storage unit layer 111 and the connecting portion 113, and another bonding layer 112 is prepared based on the surface to achieve subsequent bonding connection with other semiconductor devices.

[0106] This arrangement can reduce the height of the stacked second semiconductor devices 122, thereby reducing the height of the semiconductor stack structure 100 formed by stacking multiple second semiconductor devices 122, thereby increasing the stacking density of the semiconductor stack structure 100. Furthermore, the increased stacking density of the semiconductor stack structure 100 is beneficial for increasing the speed of data transmission and processing, thereby reducing transmission delay.

[0107] Figure 12 A flowchart of a method for manufacturing a semiconductor device 120 provided in some embodiments of the present disclosure is provided. Figure 13 For Figure 12 A schematic structural diagram of a semiconductor device 120 corresponding to the provided preparation method, Figure 14 For Figure 12 A schematic structural diagram of a semiconductor stacked structure 100 corresponding to the provided preparation method is provided.

[0108] like Figure 12 As shown, in some embodiments, the above step S11 may further include the following steps S111 to S113.

[0109] S111 , forming a memory cell layer 111 on one side of a substrate 114 .

[0110] In this step S111, the term "substrate" refers to a material onto which subsequent material layers may be added. Substrate 114 itself may be patterned. The material added to substrate 114 may be patterned or may remain unpatterned. Furthermore, substrate 114 may comprise a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or a sapphire wafer.

[0111] In some examples, the semiconductor device 120 may be a wafer. In other examples, the semiconductor device 120 may be other devices with storage functions, which is not limited in this disclosure. The following embodiment describes the preparation process of the memory cell layer 111 using the semiconductor device 120 being a wafer as an example.

[0112] In this step S111, after the substrate 114 is subjected to a proper cleaning operation, an oxidation operation is performed on one side of the substrate 114 to form an oxide film. The oxidation operation can be performed by, for example, a thermal oxidation method, an electrochemical anodic oxidation method, a plasma enhanced chemical vapor deposition (PECVD) method, or the like. The oxidation operation forms a protective film on the surface of the substrate 114, thereby protecting subsequent manufacturing processes from chemical impurities, preventing ion diffusion during subsequent ion implantation, and preventing problems such as slipping during subsequent etching.

[0113] After the oxidation operation is completed, photoresist is applied to the side of the oxide film that is away from the substrate 114 to form a photoresist pattern. The oxide film is then etched using the photoresist pattern to form a semiconductor circuit pattern. The oxide film is doped according to the semiconductor circuit pattern by, for example, ion implantation or thermal diffusion, thereby forming a doped region for subsequent transistor manufacturing. In addition, after the foregoing operation is completed, multiple film formation operations are performed on the basis of the foregoing operation. The film formation operations can include, for example, depositing a thin film of a desired molecular or atomic unit, and performing photolithography, etching, cleaning, or the like on the thin film, thereby achieving isolation, connection, and protection between single-layer or multi-layer semiconductor circuits. The deposition process can include, for example, a chemical vapor deposition (CVD) method, a physical vapor deposition (PVD) method, an atomic layer deposition (ALD) method, or the like.

[0114] At this point, the manufacturing of the memory cell layer 111 is completed in this step S111.

[0115] In the foregoing description, the manufacturing process of the memory cell layer 111 is described and analyzed by taking the semiconductor device 120 as a wafer as an example. In some other examples, when the semiconductor device 120 is another device having a memory function, the manufacturing process of the memory cell layer 111 can be different from the manufacturing process of the step S111.

[0116] S112, a plurality of connection portions 113 are formed, wherein the connection portions 113 pass through the memory cell layer 111 and extend to the substrate 114.

[0117] In step S111, a large number of semiconductor circuits can be fabricated on one side of substrate 114. Since the normal operation of the semiconductor circuits requires external electrical signals (or electrical pulses), the semiconductor circuits need to be electrically connected according to the semiconductor circuit diagram. This process requires the preparation of a large number of connecting portions 113. Exemplarily, connecting portions 113 can include metal wiring or any other conductive lines or contacts that can achieve electrical connections.

[0118] Please continue reading Figure 13 Exemplarily, the preparation process of the connection portion 113 may include forming a photoresist layer on a surface of the memory cell layer 111 away from the substrate 114, and patterning the photoresist layer to obtain a first mask layer having a first opening. The memory cell layer 111 is etched based on the first mask layer to form a hole. Exemplarily, the memory cell layer 111 may be etched using a dry etching method to obtain the hole.

[0119] A conductive material is filled into the hole to form the connection portion 113. For example, the conductive material may be a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, or other suitable materials. The conductive material may be filled using CVD, PVD, ALD, or any other thin film deposition process.

[0120] In this step S112, the holes obtained by etching can pass through the memory cell layer 111 and extend into the substrate 114, thereby preparing the memory cell layer 111 and the connection portion 113 extending into the substrate 114. Figure 14 As shown, such a configuration is advantageous in that, in the subsequent preparation process, a portion of the substrate 114 is removed to expose the connection portion 113 , and the connection portion 113 is used to realize the connection between the semiconductor stack structure 100 (or a single semiconductor device 120 ) carrying the substrate 114 and other external devices.

[0121] Furthermore, the connection portion 113 can ensure signal transmission between semiconductor circuits within the memory cell layer 111. Furthermore, the presence of the substrate 114 can also provide support for the memory cell layer 111, thereby ensuring the reliability and stability of the memory cell layer 111 during preparation, testing, or transportation.

[0122] As an option, chemical mechanical polishing may be used to remove excess material remaining after the holes are filled, thereby achieving a planarization process on the surface of the memory cell layer 111 .

[0123] S113 , forming a bonding layer 112 on a side of the memory cell layer 111 away from the substrate 114 , wherein the bonding layer 112 includes a plurality of bonding portions 1121 , and the bonding portions 1121 are connected to the connecting portions 113 .

[0124] A first dielectric layer 1122 is formed on the side of the memory cell layer 111 away from the substrate 114. Exemplarily, the material of the first dielectric layer 1122 can include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. A plurality of bonding portions 1121 are formed in the first dielectric layer 1122. The first dielectric layer 1122 and the bonding portions 1121 constitute a bonding layer 112, so that the semiconductor device is obtained as shown in FIG. 12. Figure 8 Exemplarily, the material of the bonding portions 1121 can include metal, such as copper.

[0125] In some examples, when the semiconductor device 120 is bonded to another semiconductor device 120 adjacent thereto, the number of bonding portions on the memory cell layer 111 of the other semiconductor device 120 can be the same as that of the semiconductor device 120 in the embodiment, and the bonding portions of the other semiconductor device 120 are connected to the bonding portions of the semiconductor device 120 in one-to-one correspondence when bonding.

[0126] In other examples, the bonding portions of one semiconductor device 120 and the bonding portions of the other semiconductor device 120 can not be connected in one-to-one correspondence in the two semiconductor devices 120 bonded to each other. That is, the bonding portions of one semiconductor device 120 can be in contact with the dielectric layer of the other semiconductor device 120. In addition, the distribution of the plurality of bonding portions 1121 of the semiconductor device 120 on the first dielectric layer 1122 can be uniform or non-uniform.

[0127] In this way, hybrid bonding between the two semiconductor devices 120 adjacent to each other can be achieved through the bonding layer 112, the device density can be improved, the speed of data transmission and processing can be improved, and the process difficulty and production cost can be reduced.

[0128] In addition, in some examples, before the bonding layer 112 is formed on the side surface of the memory cell layer 111, some processing procedures can be performed on the surface of the memory cell layer 111, such as plasma treatment, wet treatment, and / or heat treatment, etc.

[0129] Based on the high-bandwidth memory 910 provided in some embodiments above, the embodiment of the disclosure further provides a preparation method of the high-bandwidth memory 910. The high-bandwidth memory 910 described above can be prepared by the preparation method of the high-bandwidth memory 910.

[0130] Figure 15 A flowchart of a preparation method of a high-bandwidth memory 910 provided in some embodiments of the disclosure.

[0131] As shown in FIG. 12, in some embodiments, the preparation method of the high-bandwidth memory 910 described above can include the following steps S10-S30: Figure 15 Exemplarily, the material of the bonding portions 1121 can include metal, such as copper.

[0125] In some examples, when the semiconductor device 120 is bonded to another semiconductor device 120 adjacent thereto, the number of bonding portions on the memory cell layer 111 of the other semiconductor device 120 can be the same as that of the semiconductor device 120 in the embodiment, and the bonding portions of the other semiconductor device 120 are connected to the bonding portions of the semiconductor device 120 in one-to-one correspondence when bonding.

[0126] In other examples, the bonding portions of one semiconductor device 120 and the bonding portions of the other semiconductor device 120 can not be connected in one-to-one correspondence in the two semiconductor devices 120 bonded to each other. That is, the bonding portions of one semiconductor device 120 can be in contact with the dielectric layer of the other semiconductor device 120. In addition, the distribution of the plurality of bonding portions 1121 of the semiconductor device 120 on the first dielectric layer 1122 can be uniform or non-uniform.

[0127] In this way, hybrid bonding between the two semiconductor devices 120 adjacent to each other can be achieved through the bonding layer 112, the device density can be improved, the speed of data transmission and processing can be improved, and the process difficulty and production cost can be reduced.

[0128] In addition, in some examples, before the bonding layer 112 is formed on the side surface of the memory cell layer 111, some processing procedures can be performed on the surface of the memory cell layer 111, such as plasma treatment, wet treatment, and / or heat treatment, etc.

[0129] Based on the high-bandwidth memory 910 provided in some embodiments above, the embodiment of the disclosure further provides a preparation method of the high-bandwidth memory 910. The high-bandwidth memory 910 described above can be prepared by the preparation method of the high-bandwidth memory 910.

[0130] Figure 15 A flowchart of a preparation method of a high-bandwidth memory 910 provided in some embodiments of the disclosure.

[0131] As shown in FIG. 12, in some embodiments, the preparation method of the high-bandwidth memory 910 described above can include the following steps S10-S30:

[0132] S10, forming a first interconnection layer 130 on one side of the semiconductor stack structure 100.

[0133] Please continue to see Figure 3 A second dielectric layer 150 is formed on the side of the semiconductor stack structure 100 close to the substrate 114. Exemplarily, the material of the second dielectric layer 150 can include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric or any combination thereof. A plurality of first interconnection contacts 131 are formed in the second dielectric layer 150, wherein the second dielectric layer 150 and the first interconnection contacts 131 constitute the first interconnection layer 130. Exemplarily, the material of the first interconnection contacts 131 can include metal, such as copper.

[0134] S20, forming a second interconnection layer 140 on one side of the logic chip 915.

[0135] Please continue to see Figure 3 A third dielectric layer 160 is formed on the side of the logic chip 915. Exemplarily, the material of the third dielectric layer 160 can include silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric or any combination thereof. A plurality of second interconnection contacts 141 are formed in the third dielectric layer 160, wherein the third dielectric layer 160 and the second interconnection contacts 141 constitute the second interconnection layer 140. Exemplarily, the material of the second interconnection contacts 141 can include metal, such as copper.

[0136] In some examples, the number of the second interconnection contacts 141 can be the same as the number of the first interconnection contacts 131 in the above step S10, and the second interconnection contacts 141 are connected to the first interconnection contacts 131 in the above step S10 one by one when bonding.

[0137] In other examples, the second interconnection contacts 141 can also not be connected to the first interconnection contacts 131 in the above step S10 one by one. That is, there can be second interconnection contacts 141 in contact with the second dielectric layer 150, or first interconnection contacts 131 in contact with the third dielectric layer 160.

[0138] In addition, the distribution of the first interconnection contacts 131 on the second dielectric layer 150 can be uniform or non-uniform. The distribution of the second interconnection contacts 141 on the third dielectric layer 160 can be uniform or non-uniform.

[0139] S30, stacking the semiconductor stack structure 100 and the logic chip 915, and bonding the first interconnection layer 130 and the second interconnection layer 140.

[0140] Please continue to see Figure 3In step S30, by bonding the first interconnect layer 130 and the second interconnect layer 140, the device density of the high bandwidth memory 910 after bonding can be improved, thereby increasing the speed of data transmission and data processing of the high bandwidth memory 910.

[0141] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A semiconductor stack structure, characterized by, Comprising: a plurality of stacked semiconductor structures, the semiconductor structure comprising a memory cell layer and a bonding layer, the memory cell layer being provided with the bonding layer towards a surface of an adjacent semiconductor structure, and the bonding layer being coupled to the memory cell layer; wherein two adjacent semiconductor structures are bonded together by the bonding layer.

2. The semiconductor stack structure of claim 1, wherein: the bonding layer comprises a plurality of bonding portions; the semiconductor structure further comprises a plurality of connecting portions, the connecting portions penetrating the memory cell layer and being connected to the bonding portions; the number of the connecting portions is less than or equal to the number of the bonding portions.

3. The semiconductor stack structure of claim 2, wherein: at least one side of the plurality of stacked semiconductor structures in a stacking direction is provided with a substrate, and the connecting portions of the semiconductor structure close to the substrate extend into the substrate.

4. The semiconductor stack structure of any one of claims 1-3, wherein: the memory cell layer comprises a plurality of arrayed memory cells.

5. The semiconductor stack structure of claim 2, wherein: the connecting portions and the bonding portions each have a size in a first direction less than or equal to 1 μm; wherein the first direction is perpendicular to the stacking direction.

6. A high bandwidth memory, comprising: Comprising: a semiconductor stack structure as claimed in any one of claims 1-5; a logic chip stacked on one side of the semiconductor stack structure and coupled to the semiconductor stack structure; a controller coupled to the logic chip to control the semiconductor stack structure to store data by controlling the logic chip.

7. A method for preparing a semiconductor stacked structure, characterized in that: Comprising: forming a plurality of semiconductor structures, and stacking and bonding the plurality of semiconductor structures together; wherein the semiconductor structure comprises a memory cell layer and a bonding layer, the memory cell layer being formed with the bonding layer towards a surface of an adjacent semiconductor structure, and the memory cell layer being coupled to the bonding layer, and wherein two adjacent semiconductor structures are bonded together by the bonding layer.

8. The manufacturing method of claim 7, wherein: the forming a plurality of semiconductor structures, and stacking and bonding the plurality of semiconductor structures together comprises: forming a plurality of semiconductor devices, the semiconductor device comprising a memory cell layer and a bonding layer provided on a side surface of the memory cell layer; wherein the plurality of semiconductor devices comprises two first semiconductor devices and a plurality of second semiconductor devices; forming another bonding layer on a surface of the memory cell layer of the second semiconductor device away from the bonding layer, and bonding the plurality of second semiconductor devices together in a stacking direction by the bonding layer; bonding the two first semiconductor devices to two second semiconductor devices at two ends in the stacking direction by the bonding layer, respectively.

9. The manufacturing method of claim 8, wherein: the semiconductor device further comprises a substrate, and the memory cell layer is provided between the substrate and the bonding layer. Before the forming another bonding layer on a surface of a memory cell layer of the second semiconductor device facing away from the bonding layer and causing a plurality of second semiconductor devices to be sequentially bonded by the bonding layer in a stacking direction, the method comprises: removing the substrate of the second semiconductor device to expose the surface of the memory cell layer of the second semiconductor device facing away from the bonding layer.

10. The manufacturing method of claim 9, wherein The forming a plurality of semiconductor devices comprises: forming a memory cell layer on one side of the substrate; forming a plurality of connection portions, wherein the connection portions pass through the memory cell layer and extend to the substrate; forming the bonding layer on a side of the memory cell layer distal to the substrate, wherein the bonding layer comprises a plurality of bonding portions connected with the connection portions.

11. A method of making a high bandwidth memory, comprising: comprising: forming a first interconnection layer on one side of a semiconductor stack structure; forming a second interconnection layer on one side of a logic chip; stacking the semiconductor stack structure and the logic chip and causing the first interconnection layer to be bonded with the second interconnection layer.

12. An electronic device, comprising: comprising the high bandwidth memory of claim 6.

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