Memory device, memory system and operating method thereof

Abstract

A method of operating a memory system includes performing a first read operation with a first read voltage of a first single read stage; determining an actual mode of bit count at the first read voltage of the first single read stage; and in response to a difference between an expected pattern of bit count at the first read voltage of the first single read stage and an actual pattern of the bit count being equal to or below a first threshold, determining that the first read voltage is a first optimal read voltage. The first single read stage of a first page is under a multi-stage architecture.

Description

BACKGROUND

[0001] The disclosure relates to a memory device, a memory system, and an operating method thereof.

[0002] In a non-volatile memory device, as a multiple bit per cell storage architecture emerges and becomes more popular within the industry, a read margin becomes narrower, thus the memory device is more susceptible to noise, program / read disturbance, coupling issues, charge loss, etc. Accordingly, more read errors occur during a read operation. Therefore, several solutions are introduced to minimize the raw bit error rate (RBER) of a memory cell. SUMMARY

[0003] In one aspect, a method of operating a memory system includes performing a first read operation with a first read voltage of a first single read level, determining an actual pattern of bit counts at the first read voltage of the first single read level, and determining that the first read voltage is a first optimal read voltage in response to a difference between an expected pattern of bit counts and the actual pattern of bit counts at the first read voltage of the first single read level being equal to or below a first threshold. The first single read level of a first page is under a multi-level architecture.

[0004] In some embodiments, the first read voltage is determined not to be the first optimal read voltage in response to the difference between the expected pattern of bit counts and the actual pattern of bit counts at the first read voltage of the first single read level being above the first threshold.

[0005] In some embodiments, the expected pattern includes an expected ratio of bit counts and the actual pattern includes an actual ratio of bit counts.

[0006] In some embodiments, in response to determining that the first read voltage is not the first optimal read voltage, the method further includes performing a first shifted read operation with a first shifted read voltage of the first single read level. The first shifted read voltage is determined based on a comparison between the expected ratio of bit counts and the actual ratio of bit counts at the first read voltage of the first single read level.

[0007] In some embodiments, determining the first shifted read voltage based on the comparison between the expected ratio of bit counts and the actual ratio of bit counts at the first read voltage of the first single read level further includes determining that the first shifted read voltage is higher than the first read voltage in response to the expected ratio of bit counts being higher than the actual ratio of bit counts, and determining that the first shifted read voltage is lower than the first read voltage in response to the expected ratio of bit counts being lower than the actual ratio of bit counts.

[0008] In some embodiments, in response to an expected ratio of the bit counts being higher than an actual ratio of the bit counts, determining the first shifted read voltage as the first read voltage plus a first offset voltage; and in response to the expected ratio of the bit counts being lower than the actual ratio of the bit counts, determining the first shifted read voltage as the first read voltage minus a first offset voltage.

[0009] In some embodiments, after performing the first read operation with the first read voltage of the first single read level, the method further comprises counting bit counts at the first read voltage of the first single read level.

[0010] In some embodiments, counting bit counts at the first read voltage of the first single read level further comprises counting bit counts of a target memory cell, all memory cells in a target page, memory cells in one or more pages including the target page, or all memory cells in all pages.

[0011] In some embodiments, determining an actual pattern of bit counts at the first read voltage of the first single read level further comprises calculating a ratio of a first actual bit count to a second actual bit count to determine an actual ratio of the bit counts. Determining an expected ratio of bit counts for each read level of the first page comprises calculating a ratio of a first expected bit count to a second expected bit count to determine an expected ratio of the bit counts.

[0012] In some embodiments, in response to determining that the first read voltage is the first optimal read voltage, the method further comprises determining a second voltage of a second single read level.

[0013] In some embodiments, in response to determining all optimal read voltages, the method further comprises performing a normal read operation based on all optimal read voltages. The normal read operation is not the first read operation.

[0014] In some embodiments, the method further comprises performing a first pre-read operation with a first pre-read voltage; determining a first read offset based on a first bit count in the first pre-read operation and a first relationship between bit counts in the first single read level and a read offset; and determining the first read voltage based on the first pre-read voltage and the first read offset.

[0015] In some embodiments, the method further comprises determining each relationship for each read level using the first relationship of the first single read level.

[0016] In some embodiments, determining each relationship of each read level further includes determining each relationship between a first voltage offset of the first single read level and each of other voltage offsets of other read levels.

[0017] In some embodiments, after determining that the first read voltage is a first best read voltage and in response to a number of error correction code (ECC) errors being greater than an ECC threshold, the method further includes performing a second read operation with the first best read voltage of the first single read level, performing a first shifted read operation with the first best read voltage plus a first offset voltage, performing a second shifted read operation with the first best read voltage minus the first offset voltage, and in response to a difference between first bit flip information of the first shifted read operation and second bit flip information of the second shifted read operation being equal to or below a second threshold, determining that the first best read voltage is a second best read voltage.

[0018] In some embodiments, the method further includes, in response to the difference between the first bit flip information of the first shifted read operation and the second bit flip information of the second shifted read operation being above the second threshold, determining that the first best read voltage is not the second best read voltage, and performing a third read operation with a third read voltage. The third read voltage is determined based on the difference between the first bit flip information of the first shifted read operation and the second bit flip information of the second shifted read operation.

[0019] In another aspect, a method of operating a memory system includes determining all best read voltages, and performing a normal read operation based on all best read voltages to read out data. Determining all best read voltages includes performing a first read operation with a first read voltage of a first single read level, determining an actual pattern of bit counts at the first read voltage of the first single read level, and in response to a difference between an expected pattern of bit counts at the first read voltage of the first single read level and the actual pattern of bit counts being equal to or below a first threshold, determining that the first read voltage is a first best read voltage. The first single read level is in a first page under a multi-cell architecture.

[0020] In some embodiments, the method further includes correcting any errors in the data with an error correction code (ECC).

[0021] In yet another aspect, a memory device includes an array of memory cells and a peripheral circuit coupled to the array of memory cells. The array of memory cells includes a memory cell. The peripheral circuit is configured to: apply a first read voltage of a first single read level to a target memory cell in a first read operation; and apply a first shift read voltage of the first single read level to the target memory cell in a first shift read operation. The first shift read voltage is determined based on a bit count at the first read voltage of the first single read level.

[0022] In some implementations, the peripheral circuit is further configured to: store the bit count into a page buffer of the peripheral circuit or into the array of memory cells.

[0023] In yet another aspect, a memory system includes a memory device and a memory controller coupled to the memory device. The memory device includes: an array of memory cells including a memory cell; and a peripheral circuit coupled to the array of memory cells. The memory controller is configured to: perform a first read operation with a first read voltage of a first single read level; determine an actual pattern of bit counts at the first read voltage of the first single read level; and determine that the first read voltage is a first optimal read voltage in response to a difference between an expected pattern of bit counts at the first read voltage of the first single read level and the actual pattern of bit counts being equal to or below a first threshold. The first single read level of a first page is under a multi-level architecture.

[0024] In yet another aspect, a non-transitory computer readable medium storing instructions that, when executed by a processor, cause the processor to perform a method including: performing a first read operation with a first read voltage of a first single read level; determining an actual pattern of bit counts at the first read voltage of the first single read level; and determining that the first read voltage is a first optimal read voltage in response to a difference between an expected pattern of bit counts at the first read voltage of the first single read level and the actual pattern of bit counts being equal to or below a first threshold. The first single read level of a first page is under a multi-level architecture. BRIEF DESCRIPTION OF DRAWINGS

[0025] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate various aspects of the present disclosure and, together with the specification, further serve to explain the principles of the present disclosure.

[0026] Figure 1 A schematic circuit diagram of an exemplary memory device including a peripheral circuit is shown in accordance with some implementations of the present disclosure.

[0027] Figure 2 A block diagram illustrating an exemplary memory device including an array of memory cells and peripheral circuitry is shown, in accordance with some embodiments of the present disclosure.

[0028] Figure 3 A block diagram illustrating an exemplary memory system including a host, a memory controller, and a memory device is shown, in accordance with some embodiments of the present disclosure.

[0029] Figure 4 A flow diagram of a read recovery procedure during operation of an exemplary memory system is shown, in accordance with some embodiments of the present disclosure.

[0030] Figure 5A A voltage distribution and corresponding read levels illustrating an exemplary method for determining an optimal read voltage is shown, in accordance with some embodiments of the present disclosure.

[0031] Figure 5B A bit count chart with corresponding read levels illustrating an exemplary method for determining an optimal read voltage is shown, in accordance with some embodiments of the present disclosure.

[0032] Figure 6A A voltage distribution illustrating an exemplary method for determining an optimal read voltage is shown, in accordance with some embodiments of the present disclosure.

[0033] Figure 6B A voltage distribution during a read operation illustrating an exemplary method for determining an optimal read voltage is shown, in accordance with some embodiments of the present disclosure.

[0034] Figure 6C A voltage distribution illustrating an exemplary method for determining an optimal read voltage is shown, in accordance with some embodiments of the present disclosure.

[0035] Figure 6D A table including bit count information in each read level illustrating an exemplary method for determining an optimal read voltage is shown, in accordance with some embodiments of the present disclosure.

[0036] Figure 6E A table including bit count information in each read level illustrating an exemplary method for determining an optimal read voltage is shown, in accordance with some embodiments of the present disclosure.

[0037] Figure 7A A flow diagram for determining an optimal read voltage is shown, in accordance with some embodiments of the present disclosure.

[0038] Figure 7B A flow diagram for determining an optimal read voltage is shown, in accordance with some embodiments of the present disclosure.

[0039] Figure 8AVoltage distributions during read operations and a correspondence between read offsets and number of bit counts are shown in accordance with some embodiments of the present disclosure.

[0040] Figure 8B Relationships in different optimal read voltage levels are shown in accordance with some embodiments of the present disclosure.

[0041] Figure 9A A flowchart for determining an optimal read voltage is shown in accordance with some embodiments of the present disclosure.

[0042] Figure 9B A flowchart for determining an optimal read voltage is shown in accordance with some embodiments of the present disclosure.

[0043] Figure 9C A flowchart for determining an optimal read voltage is shown in accordance with some embodiments of the present disclosure.

[0044] Figure 10 A block diagram of an exemplary system with a memory device is shown in accordance with some embodiments of the present disclosure.

[0045] Figure 11A A diagram of an exemplary memory card with a memory device is shown in accordance with some embodiments of the present disclosure.

[0046] Figure 11B A diagram of an exemplary solid state drive (SSD) with a memory device is shown in accordance with some embodiments of the present disclosure.

[0047] The present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0048] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Other configurations and arrangements can be employed without departing from the scope of the present disclosure. Moreover, the present disclosure can also be employed in a variety of other applications. The described features can be combined in order to produce additional desirable attributes, and in an manner that is not specifically discussed, but nevertheless is within the scope of the present disclosure.

[0049] In general, terms should be understood, at least in part, by their use in the context. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in the singular, or may be used to describe a combination of features, structures, or characteristics in the plural, depending, at least in part, on the context. Similarly, terms such as "a," "an," or "the" may also be understood to convey singular usage or plural usage, depending, at least in part, on the context. Furthermore, the term "based on" may be understood to not necessarily be intended to convey an exclusive set of factors, but rather to allow for the presence of other factors that may not be explicitly stated, again depending, at least in part, on the context.

[0050] In non-volatile memory devices, storage architectures with multiple bits per memory cell are emerging and becoming more prevalent in the industry. Read margins are becoming narrower, making memory devices more susceptible to noise, program / read disturb, coupling issues, charge loss, and the like. For example, multi-level cell (MLC) technology significantly reduces the read margin between different threshold voltage (Vth) levels used to store multiple bits in a single memory cell. However, the Vth level of a memory cell may shift beyond the read reference voltage (Vref) (i.e., the voltage used to distinguish the cell's Vth level), resulting in more read errors.

[0051] One of the solutions is to apply a read retry operation. The read retry operation can be used to determine the optimal read voltage of the memory device. However, a large number of read retry operations may cause significant performance degradation due to read latency by introducing multiple read retry steps of rereading the target page using an adjusted read reference voltage (Vref). Another solution is to apply an error correction code (ECC) that can detect and correct raw bit errors. However, ECC may only detect and correct a limited number of errors. Accordingly, more solutions can be applied in combination with these solutions to reduce the read bit error rate while maintaining the performance of the memory system.

[0052] To address one or more of the issues described above, the present disclosure introduces solutions to determine the optimal read voltage for each read level using several methods. In particular, the present disclosure introduces solutions that can utilize single-level reading to determine the optimal read voltage, thereby reducing the computation time and improving overall performance. Further, the present disclosure also provides solutions that implement various methods for data recovery to correct data and reduce RBER. It is noted that single-level reading is a type of read operation that reads at least one bit (as a first order bit "0" or "1") of data stored in a memory cell using a single reference voltage level (e.g., a single read reference voltage level). The data stored in the memory cell can include multiple bits (e.g., 110, 001, or 011). The single reference voltage level can be, for example, a first single read level (RV1) that distinguishes between adjacent program states (e.g., L0 and LI). For example, the first single read level (RV1) voltage (V RV1 ) can be applied to a word line connected to a target memory cell, and other word lines are applied with a voltage. Then, at least one bit of data stored in the target memory cell can be determined as "0" or "1" depending on whether a current is detected in a bit line connected to the target memory cell at the first single read level voltage V RV1 . It is noted that, in some embodiments, the bit count disclosed herein is the number of bits that are either bit=l or bit=0 under a single-level read operation.

[0053] Figure 1 A schematic circuit diagram of a memory device 100 including a peripheral circuit is shown in accordance with some aspects of the present disclosure. The memory device 100 can include a memory cell array 101 and a peripheral circuit 102 coupled to the memory cell array 101. In some embodiments, the memory cell array 101 can be a NAND flash memory cell array in which the memory cells 106 are provided in the form of an array of three-dimensional (3D) NAND memory strings 108 each extending vertically above a substrate (not shown). In some embodiments, each 3D NAND memory string 108 includes a plurality of memory cells 106 coupled in series and disposed vertically stacked. Each memory cell 106 is capable of holding a continuous analog value, e.g., a voltage or charge, that depends on the number of electrons trapped within a region of the memory cell 106. Each memory cell 106 can be a "floating gate" type of memory cell that includes a floating gate transistor, or can be a "charge trap" type of memory cell that includes a charge-trapping transistor. Each array made up of 3D NAND memory strings 108 can include one or more 3D memory devices.

[0054] In some embodiments, each memory cell 106 is a single-level cell (SLC) that has two possible memory states and thus is capable of storing one bit of data. For example, a first memory state "0" can correspond to a first range of voltages, and a second memory state "1" can correspond to a second range of voltages. In some embodiments, each memory cell 106 is a multi-level cell (MLC) that is capable of storing more than one bit of data in four or more memory states. For example, an MLC can store two bits per cell, three bits per cell (also referred to as a triple-level cell (TLC)), or four bits per cell (also referred to as a quad-level cell (QLC)). Each MLC can be programmed to exhibit a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed from an erased state to exhibit one of three possible programmed levels by writing one of three possible nominal storage values to the cell. A fourth nominal storage value can be used as an erased state. It is noted that the multi-level architecture in this disclosure includes MLC architecture, TLC architecture, or QLC architecture, etc., or combinations thereof.

[0055] As shown in Figure 1 Each 3D NAND memory string 108 can include a source select transistor 110 at its source end and a drain select transistor 112 at its drain end, as shown in FIG. 1. The source select transistors 110 and the drain select transistors 112 can be configured to activate a selected 3D NAND memory string 108 (column of the array) during read and program operations. In some embodiments, the sources of the source select transistors 110 of the 3D NAND memory strings 108 in the same block 104 are coupled to, for example, ground, by the same source line (SL) 114 (e.g., a common SL). According to some embodiments, the drain select transistors 112 of each 3D NAND memory string 108 are coupled to a respective bit line 116 from which data can be read or to which data can be programmed via an output bus (not shown). In some embodiments, each 3D NAND memory string 108 is configured to be selected or deselected by applying a select signal (e.g., a select voltage that exceeds a threshold voltage of the drain select transistor 112) or a deselect signal (e.g., a deselect voltage such as 0V) to the respective drain select transistor 112 via one or more drain select lines 113 and / or by applying a select voltage (e.g., exceeds a threshold voltage of the source select transistor 110) or a deselect voltage (e.g., 0V) to the respective source select transistor 110 via one or more source select lines 115.

[0056] As shown in Figure 1As shown in FIG. 1, the 3D NAND memory string 108 can be organized into a plurality of blocks 104, each of which can have a common source line 114. In some embodiments, each block 104 is the basic unit of data for an erase operation, i.e., all memory cells 106 on the same block 104 are erased at the same time. The memory cells 106 can be coupled by word lines 118, which select which row of memory cells 106 is affected by read and program operations. In some embodiments, each word line 118 is coupled to a row of memory cells 106, which is the basic unit of data for program and read operations. Each word line 118 can be coupled to a plurality of control gates (gate electrodes) at each memory cell 106 in the corresponding row and to gate lines that couple the control gates.

[0057] The peripheral circuitry 102 can be coupled to the memory cell array 101 by the bit lines 116, the word lines 118, the source lines 114, the source select lines 115, and the drain select lines 113. As described above, the peripheral circuitry 102 can include any suitable circuitry for facilitating the operation of the memory cell array 101, which facilitates the operation by applying voltage and / or current signals to and sensing voltage and / or current signals from each target memory cell 106 via the bit lines 116 through the word lines 118, the source lines 114, the source select lines 115, and the drain select lines 113. The peripheral circuitry 102 can include various types of peripheral circuitry formed using complementary metal-oxide-semiconductor (CMOS) technology. For example, Figure 2 An exemplary peripheral circuitry 102 is shown, which includes a page buffer 204, a column decoder / bit line driver 206, a row decoder / word line driver 208, a voltage generator 210, control logic 212, registers 214, an interface (I / F) 216, and a data bus 218. It should be understood that other peripheral circuitry 102 can also be included in some examples.

[0058] The page buffer 204 can be configured to buffer data read from or written to the memory cell array 101 according to control signals of the control logic 212. In one example, the page buffer 204 can store a page or pages of program data (write data) to be programmed into a row or rows of the memory cell array 101. In another example, the page buffer 204 also performs program verify operations to ensure that the data has been correctly programmed into the memory cells 106 coupled to the selected word lines 118. In yet another example, the page buffer 204 can also store bit information, bit flip information, bit counts, bit count information, offset information, intermediate calculation data, data tables, or other information used to implement the methods in the present disclosure.

[0059] Row decoders / word line drivers 208 can be configured to be controlled by control logic 212 and to select or not select blocks 104 of memory cell array 101 and to select or not select word lines 118 of blocks 104. Row decoders / word line drivers 208 can be further configured to drive memory cell array 101. For example, row decoders / word line drivers 208 can use word line voltages generated by voltage generator 210 to drive memory cells 106 coupled to selected word lines 118. In some embodiments, row decoders / word line drivers 208 can include decoders and string drivers (drive transistors) coupled to local word lines and word lines 118.

[0060] Voltage generator 210 can be configured to be controlled by control logic 212 and to generate word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, verify voltages, etc.) to be provided to memory cell array 101. In some embodiments, voltage generator 210 is part of a voltage source that provides various levels of voltages for different peripheral circuits 102, as described in detail below. In some embodiments, voltage generator 210 provides voltages to row decoders / word line drivers 208 and page buffer 204 that are higher than certain levels sufficient to perform memory operations, in accordance with the scope of the present disclosure. For example, the voltage provided to page buffer 204 can be between 2V and 3.3V, such as 3.3V, and the voltage provided to row decoders / word line drivers 208 can be greater than 3.3V, such as between 3.3V and 30V.

[0061] Column decoders / bit line drivers 206 can be configured to be controlled by control logic 212 and to select one or more 3D NAND memory strings 108 by applying bit line voltages generated by voltage generator 210. For example, column decoders / bit line drivers 206 can apply column signals to select a set of N-bit data from page buffer 204 to be output in a read operation.

[0062] Control logic 212 can be coupled to each peripheral circuit 102 and configured to control the operation of peripheral circuits 102. Registers 214 can be coupled to control logic 212 and include status registers, command registers, and address registers to store status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit 102. Control logic 212 is configured to control the operation in embodiments of the present disclosure.

[0063] The interface 216 can be coupled to the control logic 212 and configured to interface the memory cell array 101 with a memory controller (not shown). In some embodiments, the interface 216 acts as a control buffer to buffer and forward control commands received from the memory controller and / or a host (not shown) to the control logic 212, and to buffer and forward status information received from the control logic 212 to the memory controller and / or the host. The interface 216 can also be coupled to the page buffer 204 and the column decoder / bit line driver 206 via a data bus 218 and act as an input / output (I / O) interface and data buffer to buffer and forward program data received from the memory controller and / or the host to the page buffer 204, and to buffer and forward read data from the page buffer 204 to the memory controller and / or the host. In some embodiments, the interface 216 and the data bus 218 are part of the I / O circuitry of the peripheral circuitry 102.

[0064] Figure 3 An exemplary memory system 350 including a host 357, a memory controller 300, and a memory device 100 is shown in accordance with some embodiments of the present disclosure. The memory controller 300 includes a microprocessor 351, a controller / host interface (I / F) 355 coupled between the microprocessor 351 and the host 357, and a controller / memory device interface 359 coupled between the microprocessor 351 and the memory device 100. The controller / host interface 355 is configured to implement standard communication protocols, including embedded multimedia card (EMMC), universal serial bus (USB), universal flash storage (UFS), parallel advanced technology attachment (parallel ATA or PATA), serial advanced technology attachment (SATA), etc., to communicate with the host 357. The controller / memory device interface 359 is configured to translate commands into corresponding control signals to control the memory device 100.

[0065] The memory controller 300 can manage data stored in the memory device 100 and communicate with the host 357. The memory controller 300 can be configured to control operations of the memory device 100, such as read, erase, program operations, data recovery operations, or other operations according to some embodiments of the present disclosure. The memory controller 300 can be configured to control the operations by sending a command (e.g., a read command) or a command with a data address. In some embodiments, the memory controller 300 can also include a controller memory 353 (e.g., a volatile cache memory and / or a non-volatile memory) that stores data tables, intermediate calculation information, offset information, verification information, failure bit count information, bit information, bit flip information, bit counts, bit count information, or other information of embodiments of the present disclosure. The memory controller 300 can also be configured to manage various functions related to data stored in or to be stored in the memory device 100, including, but not limited to, bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 300 is also configured to process error correction codes (ECC) related to data read from or written to the memory device 100. In some embodiments, the memory controller 300 is also configured to execute or issue instructions to perform operations including optimal read voltage determination operations, read retry operations, or other operations of embodiments of the present disclosure. The memory controller 300 can also perform any other suitable functions, such as causing the memory device 100 to format. The memory controller 300 can communicate with external devices (e.g., the host 357) according to a particular communication protocol. The host 357 can be a processor of an electronic device, such as a central processing unit (CPU) or a system on chip (SoC) (e.g., an application processor (AP)). The host 357 can be configured to send or receive data to or from the memory device 100 through the memory controller 300.

[0066] Figure 4 A read recovery flow diagram during operation of an exemplary memory system according to some embodiments of the present disclosure is shown. First, the firmware can instruct the memory controller 300 to read with an initial threshold voltage and attempt a hard decode of the read information. If the initial threshold voltage is selected well such that the initial read passes, then the hard decode will succeed and the decoded read information is sent to the host 357. Otherwise, if the hard decode fails, then the initial read also fails, and the firmware can instruct the memory controller 300 to perform a read retry operation, an optimal read voltage determination operation, or a combination thereof.

[0067] In some embodiments, the best read voltage determination operation can be performed upon a failure of the initial read operation. Thereafter, the best read voltage determination operation can start the implementation of the best read voltage determination operation using the default read voltage of the initial read operation as the first read voltage (i.e., as the initial read voltage of the best read voltage determination operation). It is noted that the first read voltage in the first read operation in the present disclosure can be the single read level voltage in the single read level operation.

[0068] In some embodiments, the best read voltage determination operation can be performed within the read retry operation. For example, during the read retry operation, a read offset voltage can be obtained by checking a read retry table (RRT). The RRT can include a plurality of offset voltage values or include corresponding values from which the offset voltage values can be obtained by calculation. The offset voltage obtained by the RRT during the read retry operation can be used directly or can be used to determine the read retry voltage by calculation.

[0069] In some embodiments, the read retry voltage can be used directly as the first read voltage of the best read voltage determination operation, thereby starting the implementation of the best read voltage determination operation.

[0070] In some embodiments, a normal read operation can be performed with the read retry voltage. If the normal read operation passes, the best read voltage determination operation is not needed. Otherwise, if the normal read operation fails, the read retry voltage is used as the first read voltage of the best read voltage determination operation, thereby starting the implementation of the best read voltage determination operation.

[0071] In some embodiments, the best read voltage determination operation can be performed upon a failure of the read retry operation.

[0072] As shown in Figure 4 The read retry operation can include a read operation and a hard decode operation for each read retry operation, as shown in the above. However, the best read voltage determination operation can only require a plurality of read operations along with a best hard decode or soft decode operation. Accordingly, the best read voltage determination operation reduces the cost and latency compared to the read retry operation and improves the efficiency of obtaining the best read voltage for each read level.

[0073] To further improve error correction capability, the memory controller 300 can examine a log likelihood ratio (LLR) table generated during characterization of the memory device. The input of the LLRs provides statistical information of the memory device about the most likely correct value of each data bit. For example, the LLRs can provide probabilities of determining how likely it is that a received bit ("0" or "1") has flipped or not. These probabilities are taken from the LLR table in a look-up table that has been generated and stored into the memory controller 300. This can be implemented before, during, or after the read retry operation or the best read voltage determination operation.

[0074] In some embodiments, the ECC mechanism can also be implemented before, during, or after the read retry operation or the best read voltage determination operation.

[0075] If all read retry operations and best read voltage determination operations fail, then it is determined that there can be a defective memory cell (e.g., a stuck cell) and thus an uncorrectable ECC failure (or UECC) exists. The redundant array of independent disks (RAID) and corresponding components (i.e., dies / planes / blocks / pages) can be reconstructed accordingly. For example, the RAID operation can recover a failed component in a RAID stripe by using the remaining successful components in the RAID stripe.

[0076] Figure 5A-5B An exemplary method for determining a best read voltage is shown in accordance with some embodiments of the present disclosure. As shown in Figure 5A This example utilizes QLC NAND as one embodiment. It is noted that embodiments in the present disclosure can not be limited to QLC architecture. It can also include MLC or TLC architecture. Since the read operation in this embodiment is not a single level read operation, the randomness of the bit counts of all types of pages (i.e., lower page (LP), middle page (MP), upper page (UP), and extra page (XP)) for each read level is needed to find the best read voltage for one of the read levels. For example, the randomness of the bit counts of program state L0 and program state L1 of page XP should be obtained before determining the best read voltage for read level 1 (RV1).

[0077] In Figure 5BIn implementations of the optimal read voltage determination operation, the actual bit counts (e.g., by reading a target memory cell, a subset of memory cells in a target page (e.g., memory cells of a target page in at least one program state), all memory cells in a target page, memory cells in one or more pages including the target page, all memory cells in all pages, and counting the bit counts thereof) and the expected bit counts (which are equally distributed among all read levels of all pages and can be predetermined or calculated) are compared, and thus the shift of the read voltage in the next iteration of the optimal read voltage determination operation can be determined. It should be noted that the collected actual bit count data can include bit counts of a target group of memory cells or a target group of pages, and the target optimal read voltage is the optimal read voltage of the target group of memory cells or pages. Thus, the addresses of the read operations used to determine the actual bit counts can be the addresses of the corresponding target group of memory cells or pages.

[0078] Figure 6A A voltage distribution illustrating an exemplary method for determining an optimal read voltage is shown in accordance with some embodiments of the present disclosure. To find the optimal read voltage, the bit counts in a certain Vth are close to a certain amount of the total bit counts based on the randomness characteristic of the program data, where from this can be relied upon, the shift of the read voltage in the next iteration during the optimal read voltage determination operation can be determined using the expected bit count information and the actual bit count information. For example, as shown in Figure 6A In the first read level (RV1) during the read voltage Vrd, the actual bit counts at bit = 0 should be close to 3 / 4 * total bit counts (i.e., the expected bit counts), and the actual bit counts at bit = 1 should be close to 1 / 4 * total bit counts, as shown in

[0079] For example, as shown in Figure 6B To determine a single level cell (i.e., two program states), there can be bit counts at bit = 1 and bit = 0, both of which should be 1 / 2 of the total bit counts, as shown in

[0080] In the next iteration, the second read voltage V1 is applied, the actual bit count (bit = 1) is still greater than the expected bit count (bit = 1), and the difference between the actual bit count and the expected bit count is still greater than the threshold, then it is determined that the next read voltage in the next iteration should be shifted left to a third read voltage V2.

[0081] In the next iteration, the third read voltage V2 is applied, at this time the actual bit count (bit = 1) is less than the expected bit count (bit = 1), and the difference between the actual bit count and the expected bit count is greater than the threshold, then it is determined that the next read voltage in the next iteration should be shifted right to a fourth read voltage V3.

[0082] In some embodiments, the shift value of the fourth read voltage V3 can be, for example, half of the last shift value when the shift direction changes.

[0083] In the next iteration, the fourth read voltage V3 is applied, the actual bit count (bit = 1) is less than or greater than the expected bit count (bit = 1), but the difference between the actual bit count and the expected bit count is equal to or less than the threshold, then it is determined that the fourth read voltage V3 is the first optimal read voltage of the first read level of the current page.

[0084] Figure 7A A flowchart of a method 700 of determining an optimal read voltage in an example of Figure 6A-6E according to some embodiments of the present disclosure is shown. It is pointed out that this embodiment can be performed under an MLC architecture, a TLC architecture, or a QLC architecture.

[0085] First, reference is made to operation 702, in which the expected pattern of bit count information of each read level of the current page is determined. For example, all expected patterns of bit count information of each read level of each page are determined (e.g., the expected ratio of bit counts as shown in Figure 6D or the scaled ratio of bit counts as shown in Figure 6E of the bit count information or the bit count information being processed or biased.

[0086] In some embodiments, the threshold or so-called ratio buffer, for example, ratio buffer 1 to ratio buffer 15, is determined according to the randomness feature of the programming data. The randomness feature of the programming data can be determined through big data analysis. That is, the actual bit count information and the expected bit count information can be compared to determine whether they are within the corresponding ratio buffer. If the difference between the actual bit count information and the expected bit count information is equal to or less than the corresponding ratio buffer, then the current read voltage can be determined as the optimal read voltage.

[0087] Next, referring to operation 704, a first read operation is performed on the current page data (i.e., the target page). The read level of the current page, for example, as shown in the embodiment of FIG6 , applies the first read operation to the read level Vrd_P3 of the page MP and performs reading using a first read voltage V0.

[0088] Next, referring to operation 706 , actual bit count information is obtained and stored after the first read operation. In some embodiments, the actual bit count information may be stored in the controller memory 353 of the memory controller 300 or the page buffer 204 of the memory device 100 .

[0089] The expected pattern of the bit count information may be predetermined based on the randomness characteristics of the programming data. For example, the expected pattern of the bit count information includes the expected bit count when bit=0 / the expected bit count when bit=1, such as Figure 6D As shown in the embodiment of the present invention. In another example, the expected pattern of the bit count information includes (expected bit count when bit=0-expected bit count when bit=1) / total bit count. In another example, the expected pattern of the bit count information includes a scaling ratio of (expected bit count when bit=0-expected bit count when bit=1). For example, for a read operation including a read voltage Vrd_P2 of a read level P2 in a page LP, the expected bit count when bit=1 / total bit count is 1 / 8 (e.g., 2 / 16), the expected bit count when bit=0 / total bit count is 7 / 8 (e.g., 14 / 16), and the expected bit count when bit=0-expected bit count when bit=1) / total bit count is 3 / 4 (e.g., 12 / 16). If a scaling ratio is used as the bit count information pattern, the scaling ratio of (expected bit count when bit=0-expected bit count when bit=1) is 1 / 12 (e.g., 1 / (14-2)).

[0090] In some embodiments, the expected pattern of the bit count information may include comparison value 1 (e.g., 1 / 16 total comparison value - count buffer), comparison value 2 (e.g., 1 / 16 total comparison value + count buffer), comparison value 3 (e.g., -count buffer), and comparison value 4 (e.g., count buffer), all of which may be predetermined and programmed and stored in the memory controller 300 or the memory device 100. The count buffer may also be predetermined based on randomness characteristics of the programming data.

[0091] Next, referring to operation 708, the actual pattern of the bit count information is calculated. For example, the actual pattern of the bit count information includes the actual bit count when bit=0 / the actual bit count when bit=1, as shown in FIG. Figure 6DIn another example, the actual pattern of bit count information includes a scaled ratio of (actual bit count at bit = 0 - actual bit count at bit = 1). In another example, the actual pattern of bit count information includes (actual bit count at bit = 0 - actual bit count at bit = 1) / total bit count.

[0092] The actual pattern of bit count information (for example) can be a scaled ratio of (actual bit count at bit = 0 - actual bit count at bit = 1). Thereafter, the value can be compared to comparison value 1, comparison value 2, comparison value 3, and comparison value 4. The actual pattern of bit count information can be compared to the expected pattern of bit count information.

[0093] Next, reference is made to operation 710, in which it is determined whether the expected pattern of bit count information and the actual pattern of bit count information are comparable. One of the embodiments is shown below.

[0094] If the scaled ratio > 0, then at scaled ratio * (actual bit count at bit = 0 - actual bit count at bit = 1) > comparison value 2, the first read voltage V0 should be shifted right, the second read voltage V1 is determined as first read voltage V0 + shift value for this iteration; at scaled ratio * (actual bit count at bit = 0 - actual bit count at bit = 1) < comparison value 1, the first read voltage V0 should be shifted left, the second read voltage V1 is determined as first read voltage V0 - shift value for this iteration; at comparison value 1 <= scaled ratio * (actual bit count at bit = 0 - actual bit count at bit = 1) <= comparison value 2, the first read voltage V0 is determined as the best read voltage for the current level of the current page.

[0095] If the scaled ratio < 0, then at scaled ratio * (actual bit count at bit = 0 - actual bit count at bit = 1) > comparison value 2, the first read voltage V0 should be shifted left, the second read voltage V1 is determined as first read voltage V0 - shift value for this iteration; at scaled ratio * (actual bit count at bit = 0 - actual bit count at bit = 1) < comparison value 1, the first read voltage V0 should be shifted right, the second read voltage V1 is determined as first read voltage V0 + shift value for this iteration; at comparison value 1 <= scaled ratio * (actual bit count at bit = 0 - actual bit count at bit = 1) <= comparison value 2, the first read voltage V0 is determined as the best read voltage for the current level of the current page.

[0096] If the scaling ratio = 0, then if (actual bit count at bit = 0 - actual bit count at bit = 1) > comparison value 4, the first read voltage V0 should be right shifted, and the second read voltage V1 is determined as the first read voltage V0 + shift value for this iteration; if (actual bit count at bit = 0 - actual bit count at bit = 1) < comparison value 3, the first read voltage V0 should be left shifted, and the second read voltage V1 is determined as the first read voltage V0 - shift value for this iteration; if comparison value 3 <= actual bit count at bit = 0 - actual bit count at bit = 1 <= comparison value 4, the first read voltage V0 is determined as the best read voltage for the current level of the current page.

[0097] Thus, by applying the above calculations, the second read voltage V1 can be determined and the next iteration can be repeated, as shown in operation 716.

[0098] Conversely, if the expected pattern of bit count information and the actual pattern of bit count information are not comparable, i.e., the difference between the expected pattern of bit count information and the actual pattern of bit count information is less than a threshold value (e.g., corresponding to a count buffer), then the first read voltage V0 (or other read voltage during the iteration) is determined as the best read voltage (e.g., the first best read voltage) for the current level of the current page, as shown in operation 712.

[0099] Upon determining one of the best read voltages for the current read level of the current page, as shown in operation 712, the method 700 further proceeds to operation 714, in which it is determined whether all of the best read voltages for all of the read levels of the current page have been determined. If all of the best read voltages for all of the read levels of the current page have not been determined, then the method 700 further proceeds to operation 718, in which the next read voltage for the next read level of the current page is determined, and the next iteration can be repeated.

[0100] This iteration process is repeated until all of the SLR levels on the current page have found their respective best read voltages.

[0101] Finally, the method 700 proceeds to operation 720, in which the iteration reaches an end once all of the SLR levels of the current page have found their respective best read voltages. Also, it is determined that all of the best read voltages for the current page have been found.

[0102] Figure 7BA flowchart of a method 740 of determining an optimal read voltage is shown, in accordance with some embodiments of the present disclosure. It can begin with a coarse optimal read voltage operation, for example, in operation 742. Based on the programmed data randomness characteristics, and by using the actual pattern of bit count information and the expected pattern of bit count information, as discussed above, the coarse optimal read voltage determination operation can find a coarse optimal read voltage. Then, the coarse optimal read voltage can be utilized as a default read voltage or a first read voltage to start a fine optimal read voltage process, as in operation 744.

[0103] The fine optimal read voltage determination operation can start, for example, with determining an initial SLR level for the current page.

[0104] Next, a third read operation is performed with a third read voltage of the first read level. In some embodiments, as mentioned above, the initial single-level read voltage includes a read retry voltage during a previous read retry operation, a default read voltage, or any optimal read voltage obtained in the present disclosure.

[0105] Next, a first shift read operation is performed with the third read voltage plus a first offset voltage. In some embodiments, the first offset voltage can be determined according to a threshold voltage overall distribution characteristic or a read margin of the memory device. It is noted that the first offset voltage can be between 0.01 V and 1.0 V. It is noted that the lower the first offset voltage (i.e., the smaller the bit shift step), the more iterations the optimal read voltage determination operation needs.

[0106] Next, a second shift read operation is performed with the third read voltage minus the first offset voltage.

[0107] Next, in response to a difference between the first bit flip information of the first shift read operation and the second bit flip information of the second shift read operation being equal to or lower than a threshold value, the third read voltage is determined to be an optimal read voltage of a current read level of the current page.

[0108] On the contrary, in response to the difference between the first bit flip information of the first shift read operation and the second bit flip information of the second shift read operation being higher than the threshold value, the third read voltage is determined not to be the optimal read voltage of the current read level of the current page.

[0109] After determining that the third read voltage is not the optimal read voltage, a fourth read operation is performed with a fourth read voltage, wherein the fourth read voltage is determined based on the difference between the first bit flip information of the first shift read operation and the second bit flip information of the second shift read operation.

[0110] In particular, the fourth read voltage is determined to be higher than the third read voltage in response to the first bit flip information of the first shift read operation being higher than the second bit flip information of the second shift read operation, and the fourth read voltage is determined to be lower than the third read voltage in response to the first bit flip information of the first shift read operation being lower than the second bit flip information of the second shift read operation. In some embodiments, the fourth read voltage is determined to be the third read voltage minus half of the first offset voltage in response to the first bit flip information of the first shift read operation being higher than the second bit flip information of the second shift read operation, and the fourth read voltage is determined to be the third read voltage plus half of the first offset voltage in response to the first bit flip information of the first shift read operation being lower than the second bit flip information of the second shift read operation. By utilizing multiple iterations to approach the optimal read voltage, the optimal read voltage for the current page can be found.

[0111] Figure 9A A flowchart of a method 900 for determining an optimal read voltage is shown in accordance with some embodiments of the present disclosure.

[0112] The method 900 begins at operation 902, in which an expected pattern of bit count information for each read level of a first page of a memory cell array is determined. For example, a program level PI in the current page LP can be determined as the first read level in the current page LP. All of the above-mentioned expected patterns of bit count information are determined, for example, Figure 6D and / or Figure 6E among the embodiments in the present disclosure.

[0113] With reference to operation 904, a first read operation is performed with a first read voltage of the first read level. In some embodiments, as mentioned above, the initial single-level read voltage includes a read retry voltage during a previous read retry operation, a default read voltage, or any optimal read voltage obtained in the present disclosure.

[0114] With reference to operation 906, an actual pattern of bit count information at the first read voltage of the first read level is determined. For example, once the expected pattern of bit count information for the program level PI in the current page LP is determined, the actual pattern of bit count information mentioned above is calculated and determined, for example, Figure 6D and / or Figure 6E among the embodiments in the present disclosure.

[0115] With reference to operation 908, whether the first read voltage is a first optimal read voltage is determined based on a comparison between the expected pattern of bit count information and the actual pattern of bit count information at the first read voltage of the first read level.

[0116] Referring to operation 910, in this operation, a first shifted read operation is performed with a first shifted read voltage of the first read level in response to determining that the first read voltage is not the first optimal read voltage. By approaching the optimal read voltage with multiple iterations, the optimal read voltage for the current page can be found.

[0117] In some embodiments, the method 900 can further include determining a second single-level read level for the current page in response to determining that the first read voltage is the first optimal read voltage for the first page. Once all optimal read voltages for all corresponding read levels of the current page are determined, the same operations can be performed for the next page.

[0118] In some embodiments, after all optimal read voltages for all corresponding read levels of the current page are determined, the method 900 can further include performing a normal read operation based on the optimal read voltages for the current page. It is noted that the normal read operation is not a single-level read operation.

[0119] Figure 9B A flowchart of a method 920 for determining optimal read voltages according to some embodiments of the present disclosure is shown.

[0120] The method 920 starts with operation 922, in which a relationship between bit count information and corresponding offsets for each read level of a current page is determined. As Figure 8A As shown in the middle, a voltage distribution for read levels (e.g., read level P3 and read level P7) and a corresponding relationship between read offsets and bit count numbers in each read level are obtained and calculated or determined based on a big data analysis of the memory device.

[0121] In some embodiments, the big data analysis is done by: (1) reading all bit count information for all corresponding Vths of the NAND; (2) defining an estimated range for each read level; (3) calculating delta values, which include a difference between two bit count information using two corresponding Vths; (4) calculating a relationship between the delta values and offsets of optimal read voltages for each read level; and (5) storing the relationship into firmware. When checking with the relationship, at least one single-level read operation is performed to obtain the delta values. Thus, by using the relationship and the obtained delta values, the optimal read voltages can be determined.

[0122] Referring to operation 924, in which at least one read operation of each read level of the current page is performed to determine an optimal read voltage for each read level using the corresponding relationship of each read level. In some embodiments, the method 920 includes performing a first pre-read operation with a first pre-read voltage Vo to determine first pre-read bit count information. A first read offset is determined based on the first pre-read bit count information in the first read level and a first relationship (e.g., a linear relationship) between bit count information and read offset. Thereafter, a first optimal read voltage is determined using the first read offset and the first pre-read voltage Vo. It is noted that the first read offset is an estimated voltage offset (e.g., a left or right shift of the read voltage) toward the optimal read voltage to be determined. The first optimal read voltage can be utilized as the first read voltage in other embodiments of the optimal read voltage determination operation mentioned above. This will significantly reduce the number of iterations in other optimal read voltage determination operations.

[0123] Once one of the read levels (e.g., the first read level of the first page) is determined, as shown in operation 924, the mapping of the relationship in the current read level of the current page to other read levels of the current page can be further used. For example, the relationship of other read levels of the first page can be determined by using the first relationship of the first read level of the first page. Figure 8B

[0124] Figure 9C A flowchart of a method 940 for read recovery according to some embodiments of the present disclosure is shown. The method 940 starts at operation 942, in which a firmware initial read operation is performed. If the firmware initial read operation fails, the method 940 proceeds to operation 944, in which a read retry operation is performed. Next, if the read retry operation fails, the method 940 proceeds to operation 946, in which all optimal read voltages of a first page of the memory cell array are determined. It is noted that the optimal read voltage determination operation can be performed before, within, or after the read retry operation, as mentioned above. The optimal read voltage found in the read retry operation can be utilized as the initial read voltage in the optimal read voltage determination operation, or vice versa. Accordingly, the optimal read voltage can be determined as accurately as possible without degrading the overall performance of the memory device. Next, the method 940 proceeds to operation 948, in which a normal read operation is performed based on all optimal read voltages of the first page of the memory cell array to read out data. Next, the method 940 proceeds to operation 950, in which any errors in the data are detected and corrected using an error correction code (ECC). It is noted that the ECC can also be performed before, within, or after the read retry operation.

[0125] Figure 10 ​A block diagram illustrating a system 1000 having a memory device in accordance with some aspects of the present disclosure is shown. The system 1000 can be a mobile phone, a desktop computer, a laptop, a tablet, a vehicle-mounted computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other electronic device having a storage component located therein. As Figure 10 As shown in the middle, the system 1000 can include a host 1008 and a memory system 1002 having one or more memory devices 1004 and a memory controller 1006. The host 1008 can be a processor of an electronic device, such as a central processing unit (CPU), or can be a system on chip (SoC), such as an application processor (AP). The host 1008 can be configured to send or receive data to or from the memory device 1004.

[0126] The memory device 1004 can be any memory device disclosed herein, such as the memory device 100. In some implementations, each memory device 1004 includes a memory device as described in detail above.

[0127] According to some embodiments, the memory controller 1006 is coupled to the memory devices 1004 and the host 1008 and is configured to control the memory devices 1004. The memory controller 1006 can be any of the memory controllers disclosed herein, e.g., the memory controller 300. In some embodiments, each memory controller 1006 includes a memory controller as described in detail above. The memory controller 1006 can manage data stored in the memory devices 1004 and communicate with the host 1008. In some embodiments, the memory controller 1006 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 1006 is designed to operate in a high duty cycle environment, such as an SSD or embedded multimedia card (eMMC), which is used as a data storage device for mobile devices such as smartphones, tablets, laptops, etc., and enterprise storage arrays. The memory controller 1006 can be configured to control operations of the memory devices 1004, such as read, erase, and program operations. The memory controller 1006 can also be configured to manage various functions related to data stored in or to be stored in the memory devices 1004, including but not limited to bad block management, garbage collection, logical to physical address translations, wear leveling, etc. In some embodiments, the memory controller 1006 is further configured to process error correction codes (ECCs) related to data read from or written to the memory devices 1004. Any other suitable functions can also be performed by the memory controller 1006, e.g., formatting the memory devices 1004. The memory controller 1006 can communicate with external devices (e.g., the host 1008) according to a particular communication protocol. For example, the memory controller 1006 can communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0128] The memory controller 1006 and the one or more memory devices 1004 can be integrated into various types of memory devices, e.g., contained in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 1002 can be implemented and packaged into different types of end electronic products. In some embodiments, the memory system 1002 is implemented and packaged into a memory card, a memory stick, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, a memory module, aFigure 11A In one example shown, the memory controller 1006 and the single memory device 1004 can be integrated into a memory card 1102. The memory card 1102 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 1102 can further include a memory card connector 1104 that couples the memory card 1102 with a host (e.g., the host 1008 in Figure 10 In another example shown, the memory controller 1006 and the multiple memory devices 1004 can be integrated into an SSD 1106. The SSD 1106 can further include an SSD connector 1108 that couples the SSD 1106 with a host (e.g., the host 1008 in Figure 11B Figure 10 In some implementations, the storage capacity and / or operating speed of the SSD 1106 is higher than that of the memory card 1102.

[0129] The foregoing description of specific implementations has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the implementations to the precise forms disclosed. Many modifications and variations are possible in light of the teaching and

[0130] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations, but should be defined in accordance with the following claims and their equivalents.​

Claims

1. A method of operating a memory system, comprising: performing a first read operation with a first read voltage of a first single read level; determining an actual pattern of bit counts at the first read voltage of the first single read level; and in response to a difference between an expected pattern of bit counts at the first read voltage of the first single read level and the actual pattern of bit counts being at or below a first threshold, determining that the first read voltage is a first optimal read voltage, wherein the first single read level of a first page is under a multi-level architecture.

2. The method of claim 1, wherein, in response to the difference between the expected pattern of bit counts at the first read voltage of the first single read level and the actual pattern of bit counts being above the first threshold, determining that the first read voltage is not the first optimal read voltage.

3. The method of claim 1, wherein, the expected pattern comprises an expected ratio of bit counts and the actual pattern comprises an actual ratio of bit counts.

4. The method of claim 2, wherein, in response to determining that the first read voltage is not the first optimal read voltage, the method further comprising: performing a first shifted read operation with a first shifted read voltage of the first single read level, wherein the first shifted read voltage is determined based on a comparison between the expected ratio of bit counts at the first read voltage of the first single read level and the actual ratio of bit counts.

5. The method of claim 4, wherein, determining the first shifted read voltage based on a comparison between an expected ratio of bit counts at the first read voltage of the first single read level and an actual ratio of bit counts further comprises: in response to the expected ratio of bit counts being above the actual ratio of bit counts, determining that the first shifted read voltage is above the first read voltage; and in response to the expected ratio of bit counts being below the actual ratio of bit counts, determining that the first shifted read voltage is below the first read voltage.

6. The method of claim 5, wherein: in response to the expected ratio of bit counts being above the actual ratio of bit counts, determining that the first shifted read voltage is the first read voltage plus a first offset voltage; and in response to the expected ratio of bit counts being below the actual ratio of bit counts, determining that the first shifted read voltage is the first read voltage minus a first offset voltage.

7. The method of claim 3, wherein, after performing the first read operation with the first read voltage of the first single read level, the method further comprising: counting bit counts at the first read voltage of the first single read level.

8. The method of claim 7, wherein, counting bit counts at the first read voltage of the first single read level further comprises: counting bit counts of a target memory cell, all memory cells in a target page, memory cells in one or more pages including the target page, or all memory cells in all pages.

9. The method of claim 3, wherein, determining an actual pattern of bit counts at the first read voltage of the first single read level further comprises: calculating a ratio of a first actual bit count to a second actual bit count to determine an actual ratio of bit counts, and wherein determining an expected ratio of bit counts for each read level of the first page comprises: computing a ratio of the first expected bit count and the second expected bit count to determine an expected ratio of the bit counts.

10. The method of claim 1, wherein, In response to determining that the first read voltage is the first optimal read voltage, the method further comprises: determining a second voltage of a second single read level.

11. The method of claim 10, wherein, In response to determining all optimal read voltages, the method further comprises: performing a normal read operation based on all optimal read voltages, wherein the normal read operation is not the first read operation.

12. The method of claim 1, further comprising: performing a first pre-read operation with a first pre-read voltage; determining a first read offset based on a first bit count in the first pre-read operation and a first relationship between bit counts and read offsets in the first single read level; and determining the first read voltage based on the first pre-read voltage and the first read offset.

13. The method of claim 12, further comprising: determining each relationship of each read level using the first relationship of the first single read level.

14. The method of claim 13, wherein, Determining each relationship of each read level further comprises: determining each relationship between a first voltage offset of the first single read level and each of other voltage offsets of other read levels.

15. The method of claim 14, wherein, after determining that the first read voltage is a first optimal read voltage and in response to a number of error correction code (ECC) errors being greater than an ECC threshold, the method further comprises: performing a second read operation with the first optimal read voltage of the first single read level; performing a first shifted read operation with the first optimal read voltage plus a first offset voltage; performing a second shifted read operation with the first optimal read voltage minus the first offset voltage; and in response to a difference between first bit flip information of the first shifted read operation and second bit flip information of the second shifted read operation being equal to or below a second threshold, determining that the first optimal read voltage is a second optimal read voltage.

16. The method of claim 15, further comprising: in response to the difference between the first bit flip information of the first shifted read operation and the second bit flip information of the second shifted read operation being above the second threshold, determining that the first optimal read voltage is not the second optimal read voltage; and performing a third read operation with a third read voltage, wherein the third read voltage is determined based on the difference between the first bit flip information of the first shifted read operation and the second bit flip information of the second shifted read operation.

17. A method of operating a memory system, comprising: determining all optimal read voltages, wherein determining all optimal read voltages comprises: performing a first read operation with a first read voltage of a first single read level; determining an actual pattern of bit counts at the first read voltage of the first single read level; and determining that the first read voltage is a first optimal read voltage in response to a difference between an expected pattern of bit counts at the first read voltage of the first single read level and an actual pattern of bit counts being at or below a first threshold, wherein the first single read level is in a first page under a multi-cell architecture; and performing a normal read operation based on all optimal read voltages to read out data.

18. The method of claim 17, further comprising: correcting any errors in the data using an error correction code (ECC).

19. A memory device, comprising: a memory cell array comprising memory cells; and a peripheral circuit coupled to the memory cell array, wherein the peripheral circuit is configured to: apply a first read voltage of a first single read level to a target memory cell in a first read operation; and apply a first shift read voltage of the first single read level to the target memory cell in a first shift read operation, wherein the first shift read voltage is determined based on a bit count at the first read voltage of the first single read level.

20. The memory device of claim 19, wherein, the peripheral circuit is further configured to: store the bit count into a page buffer of the peripheral circuit or into the memory cell array.

21. A memory system, comprising: a memory device; and a memory controller coupled to the memory device, wherein the memory device comprises: a memory cell array comprising memory cells; and a peripheral circuit coupled to the memory cell array, wherein the memory controller is configured to: perform a first read operation with a first read voltage of a first single read level; determine an actual pattern of bit counts at the first read voltage of the first single read level; and determine that the first read voltage is a first optimal read voltage in response to a difference between an expected pattern of bit counts at the first read voltage of the first single read level and an actual pattern of bit counts being at or below a first threshold, wherein the first single read level of a first page is under a multi-level architecture.

22. A non-transitory computer-readable medium storing instructions that, when executed by a processor, cause the processor to perform a method comprising: performing a first read operation with a first read voltage of a first single read level; determining an actual pattern of bit counts at the first read voltage of the first single read level; and in response to a difference between an expected pattern of bit counts at the first read voltage of the first single read level and an actual pattern of the bit counts being equal to or below a first threshold, determining that the first read voltage is a first optimal read voltage, wherein, the first single read level of a first page is under a multi-level architecture.

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