JTAG (Joint Test Action Group) link topology control device and method and server

Abstract

The invention relates to the technical field of servers, and discloses a JTAG (Joint Test Action Group) link topology control device and method and a server, the device comprises a first switching module and a second switching module, during single-path control, the first switching module is used for establishing a JTAG link between a first master device and a first slave device, and the second switching module is used for establishing a JTAG link between a second master device and a second slave device; the second switching module is used for establishing a JTAG link between the second master device and the second slave device; during two-way control, the first switching module is used for establishing a JTAG link between the first master device and the first slave device, and the second switching module is used for establishing a JTAG link between the first master device and the second slave device; or, during two-way control, the first switching module is used for establishing a JTAG link between the second master device and the first slave device, and the second switching module is used for establishing a JTAG link between the second master device and the second slave device, so that the debugging and control requirements in different scenes are met, and the flexibility of the system topology is improved.

Description

Technical Field

[0001] This invention relates to the field of server technology, specifically to a JTAG link topology control device and method, and a server. Background Technology

[0002] In the field of server system technology, existing server systems are typically configured in a fixed manner, mainly divided into dual-socket servers and single-socket servers. In a dual-socket server, the JTAG interfaces of the two CPUs are usually connected in series to form a daisy-chain structure. This connection method allows for unified debugging during the debugging process, offering a certain degree of convenience. In contrast, the JTAG interfaces of each CPU in a single-socket server are independent, a design that prevents it from supporting multi-CPU collaborative debugging.

[0003] However, the aforementioned fixed-configuration server design has significant drawbacks. On the one hand, because dual-socket and single-socket servers require independent design and development, the hardware resource reuse rate is low, greatly increasing the enterprise's R&D costs. On the other hand, the fixed JTAG interface design makes the debugging mode inflexible, unable to dynamically switch according to actual application scenarios and debugging needs, thus limiting debugging efficiency and effectiveness. Summary of the Invention

[0004] In view of this, the present invention provides a JTAG link topology control device and method, and a server, to solve the problem of how to achieve rapid adaptation and efficient utilization of hardware resources.

[0005] In a first aspect, the present invention provides a JTAG link topology control device, comprising: a first switching module and a second switching module, wherein the first switching module is connected to a first master device, a first slave device, and the second switching module; the second switching module is connected to a second master device and a second slave device; in single-channel control, the first switching module is used to establish a JTAG link between the first master device and the first slave device, and the second switching module is used to establish a JTAG link between the second master device and the second slave device; in dual-channel control, the first switching module is used to establish a JTAG link between the first master device and the first slave device, and the second switching module is used to establish a JTAG link between the first master device and the second slave device; or, in dual-channel control, the first switching module is used to establish a JTAG link between the second master device and the first slave device, and the second switching module is used to establish a JTAG link between the second master device and the second slave device.

[0006] In this invention, through the collaborative work of the first switching module and the second switching module, an independent link (first master device → first slave device, second master device → second slave device) can be realized in single-channel control, and cross-module links (such as the first master device controlling the first slave device and the second slave device at the same time) can be supported in dual-channel control, meeting the debugging and control needs in different scenarios and improving the flexibility of the system topology.

[0007] In one alternative implementation, the first switching module is disposed on the first motherboard, and the second switching module is disposed on the second motherboard.

[0008] In this invention, the first switching module and the second switching module are respectively set on different motherboards (such as the first motherboard and the second motherboard), which can realize hardware decoupling, facilitate system upgrades or maintenance, and reduce signal interference between motherboards, thereby improving stability.

[0009] In one optional embodiment, the first switching module includes: a first programmable logic device and a first connector, wherein the first JTAG interface of the first programmable logic device is connected to the JTAG interface of the first master device, the second JTAG interface of the first programmable logic device is connected to the JTAG interface of the first connector, the third JTAG interface of the first programmable logic device is connected to the JTAG interface of the first slave device, and the control terminal of the first programmable logic device is connected to the first master device; the JTAG interface of the first connector is connected to the second switching module.

[0010] In one optional embodiment, the second switching module includes: a second programmable logic device and a second connector, wherein the first JTAG interface of the second programmable logic device is connected to the JTAG interface of the second master device, the second JTAG interface of the second programmable logic device is connected to the JTAG interface of the second connector, the third JTAG interface of the second programmable logic device is connected to the JTAG interface of the second slave device, the control terminal of the second programmable logic device is connected to the second master device, and the JTAG interface of the second connector is connected to the first connector.

[0011] In one alternative implementation, the control terminal of the first programmable logic device is connected to the first master device via an I2C bus; the control terminal of the second programmable logic device is connected to the second master device via an I2C bus.

[0012] In this invention, the control terminal of the programmable logic device is connected to the master device via the I2C bus, which has bidirectional synchronous communication capability, can accurately transmit control commands (such as single-channel / dual-channel mode switching), reduce signal delay and bit error rate, and ensure the real-time and accuracy of link establishment.

[0013] In one alternative implementation, the JTAG interface includes a TDI pin and a TDO pin.

[0014] Secondly, the present invention provides a server comprising a JTAG link topology control device according to any optional embodiment of the first aspect, a first master device, a second master device, a first slave device, and a second slave device. The JTAG link topology control device includes: a first switching module and a second switching module, wherein the first switching module is connected to the first master device, the first slave device, and the second switching module; the second switching module is connected to the second master device and the second slave device. In single-path control, the first switching module is used to establish a JTAG link between the first master device and the first slave device, and the second switching module is used to establish a JTAG link between the second master device and the second slave device. In dual-path control, the first switching module is used to establish a JTAG link between the first master device and the first slave device, and the second switching module is used to establish a JTAG link between the first master device and the second slave device; or, in dual-path control, the first switching module is used to establish a JTAG link between the second master device and the first slave device, and the second switching module is used to establish a JTAG link between the second master device and the second slave device.

[0015] In this invention, the server integrates a JTAG link topology control device, which supports the independent or collaborative control of slave devices (first slave device and second slave device) by the first master device and the second master device. It is suitable for complex systems that require parallel debugging of multiple nodes (such as multi-motherboard server clusters) and improves debugging efficiency.

[0016] In one alternative implementation, the first slave device is disposed on the first motherboard; the second slave device is disposed on the second motherboard.

[0017] In one alternative implementation, the first master device is disposed on the first control motherboard, and the second master device is disposed on the second control motherboard.

[0018] Thirdly, the present invention provides a JTAG link topology control method, characterized in that the control method is applied to a server according to the second aspect and any optional embodiment thereof, the method comprising: when single-path control is used, a first master device sends a single-path control command to a first switching module, and a second master device sends a single-path control command to a second switching module; the first switching module establishes a JTAG link between the first master device and the first slave device based on the single-path control command, and the second switching module establishes a JTAG link between the second master device and the second slave device based on the single-path control command; when dual-path control is used, the first master device sends a dual-path control command to the first switching module; the first switching... The module establishes a JTAG link between the first master device and the first slave device based on dual-channel control commands. The first switching module sends the dual-channel control commands to the second switching module, and the second switching module establishes a JTAG link between the first master device and the second slave device based on the dual-channel control commands. Alternatively, when dual-channel control is in operation, the second master device sends dual-channel control commands to the second switching module; the second switching module establishes a JTAG link between the second master device and the second slave device based on the dual-channel control commands; the second switching module sends the dual-channel control commands to the first switching module, and the first switching module establishes a JTAG link between the second master device and the first slave device based on the dual-channel control commands. Attached Figure Description

[0019] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0020] Figure 1 This is a diagram illustrating the composition of a JTAG link topology control device according to an embodiment of the present invention;

[0021] Figure 2 This is a composition diagram of another JTAG link topology control device according to an embodiment of the present invention;

[0022] Figure 3 This is a composition diagram of another JTAG link topology control device according to an embodiment of the present invention;

[0023] Figure 4 This is a composition diagram of another JTAG link topology control device according to an embodiment of the present invention;

[0024] Figure 5 This is a flowchart illustrating the composition of another JTAG link topology control device according to an embodiment of the present invention;

[0025] Figures 6(a) and 6(b) are TAG link topologies under single-path control according to an embodiment of the present invention;

[0026] Figures 7(a) and 7(b) show the TAG link topology under dual-path control according to an embodiment of the present invention. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] In the field of modern electronic system development and testing, JTAG (Joint Test Action Group) technology, as a standardized test interface, is widely used for chip-level and system-level debugging and verification. To meet diverse testing and control needs, this embodiment provides a JTAG link topology control device, such as... Figure 1 As shown, the core architecture of this device consists of a first switching module and a second switching module, which work together to achieve flexible and adaptable JTAG link topology control. The first switching module is connected to the first master device, the first slave device, and the second switching module; the second switching module is connected to the second master device and the second slave device.

[0029] The device supports both single-channel and dual-channel control operating modes, as detailed below:

[0030] (1) When single-channel control is used, the first switching module is used to establish a JTAG link between the first master device and the first slave device, and the second switching module is used to establish a JTAG link between the second master device and the second slave device.

[0031] In single-channel control mode, the first switching module performs its signal switching function, establishing a stable and reliable JTAG link between the first master device and the first slave device through precise configuration of its internal switching circuit. This allows the first master device to independently program, debug, and test the first slave device. Simultaneously, the second switching module, operating on the same mechanism, establishes a dedicated JTAG link between the second master device and the second slave device. The second master device can then execute corresponding control tasks on the second slave device. The two links are independent and do not interfere with each other, making this suitable for scenarios where devices are tested independently.

[0032] (2) When dual-channel control is used, the first switching module is used to establish a JTAG link between the first master device and the first slave device, and the second switching module is used to establish a JTAG link between the first master device and the second slave device; or, when dual-channel control is used, the first switching module is used to establish a JTAG link between the second master device and the first slave device, and the second switching module is used to establish a JTAG link between the second master device and the second slave device.

[0033] In dual-path control mode, the system's flexibility is further enhanced. In the first scenario, the first switching module remains responsible for establishing the JTAG link between the first master device and the first slave device, ensuring normal control of the slave device. The second switching module, however, breaks with convention and establishes a JTAG link between the first master device and the second slave device. In this case, the first master device can simultaneously coordinate control of both slave devices, meeting the needs of joint debugging and testing of multiple devices. In the second scenario, the first switching module establishes a JTAG link between the second master device and the first slave device, and the second switching module establishes a JTAG link between the second master device and the second slave device. In this case, the second master device becomes the control core, achieving unified scheduling and management of the two slave devices, providing diverse solutions for complex system testing scenarios.

[0034] In some alternative implementations, such as Figure 2 As shown, the first switching module is located on the first motherboard, and the second switching module is located on the second motherboard.

[0035] Specifically, the first switching module and the second switching module can be precisely soldered onto the first motherboard and the second motherboard using surface mount packaging technology. This area has reserved dedicated gold-plated pads and signal transmission channels.

[0036] In some alternative implementations, such as Figure 3 As shown, the first switching module includes: a first programmable logic device and a first connector.

[0037] like Figure 3 As shown, the first JTAG interface of the first programmable logic device is connected to the JTAG interface of the first master device; the second JTAG interface of the first programmable logic device is connected to the JTAG interface of the first connector; the third JTAG interface of the first programmable logic device is connected to the JTAG interface of the first slave device; and the control terminal of the first programmable logic device is connected to the first master device. The JTAG interface of the first connector is connected to the second switching module. Optionally, the JTAG interface includes a TDI pin and a TDO pin.

[0038] Specifically, in single-channel control, the first JTAG interface of the first programmable logic device is connected to its third JTAG interface, thereby connecting the first master device to the first slave device.

[0039] Specifically, in dual-channel control, if the first master device is the target master device and the second master device is not working, then the first JTAG interface of the first programmable logic device is connected to its third JTAG interface, and the first connector is connected to the second switching module, thereby enabling the first master device to connect to the first slave device, and at the same time, the first master device is connected to the second slave device through the second switching module.

[0040] Specifically, in dual-channel control, if the second master device is the target master device and the first master device is not working, the third JTAG interface of the first programmable logic device is connected to its second JTAG interface, and the first connector is connected to the second switching module, thereby enabling the second master device to connect with the first slave device and the second slave device.

[0041] In some alternative implementations, such as Figure 3 As shown, the second switching module includes: a second programmable logic device and a second connector.

[0042] like Figure 3 As shown, the first JTAG interface of the second programmable logic device is connected to the JTAG interface of the second master device; the second JTAG interface of the second programmable logic device is connected to the JTAG interface of the second connector; the third JTAG interface of the second programmable logic device is connected to the JTAG interface of the second slave device; and the control terminal of the second programmable logic device is connected to the second master device. The JTAG interface of the second connector is connected to the first connector. Optionally, the JTAG interface includes a TDI pin and a TDO pin.

[0043] Specifically, in single-channel control mode, the first JTAG interface of the second programmable logic device is connected to its third JTAG interface, thereby enabling the second master device to connect with the second slave device.

[0044] Specifically, in dual-channel control, if the first master device is the target master device and the second master device is not working, the third JTAG interface of the second programmable logic device is connected to its second JTAG interface, and the second connector is connected to the first switching module, thereby enabling the second master device to connect with the first slave device and the second slave device.

[0045] Specifically, in dual-channel control, if the second master device is the target master device and the first master device is not working, the first JTAG interface of the second programmable logic device is connected to its third JTAG interface, and the second connector is connected to the first switching module, thereby enabling the second master device to connect with the first slave device and the second slave device.

[0046] In some alternative implementations, the control terminal of the first programmable logic device is connected to the first master device via an I2C bus; the control terminal of the second programmable logic device is connected to the second master device via an I2C bus.

[0047] This embodiment provides a server, such as Figure 1 As shown, the device includes: a JTAG link topology control device according to any optional implementation of the above embodiments, a first master device, a second master device, a first slave device, and a second slave device. The JTAG link topology control device includes: a first switching module and a second switching module. The first switching module is connected to the first master device, the first slave device, and the second switching module; the second switching module is connected to the second master device and the second slave device.

[0048] Specifically, during single-channel control, the first master device sends a single-channel control command to the first switching module, and the second master device sends a single-channel control command to the second switching module. The first switching module is used to establish a JTAG link between the first master device and the first slave device, and the second switching module is used to establish a JTAG link between the second master device and the second slave device.

[0049] Specifically, during dual-channel control, the first master device sends a dual-channel control command to the first switching module, which is used to establish a JTAG link between the first master device and the first slave device, and the second switching module is used to establish a JTAG link between the first master device and the second slave device; or, during dual-channel control, the second master device sends a dual-channel control command to the second switching module, which is used to establish a JTAG link between the second master device and the first slave device, and the second switching module is used to establish a JTAG link between the second master device and the second slave device.

[0050] In some alternative implementations, such as Figure 2 As shown, the first slave device is mounted on the first motherboard; the second slave device is mounted on the second motherboard.

[0051] In some alternative implementations, such as Figure 4 As shown, the first master device is mounted on the first control motherboard, and the second master device is mounted on the second control motherboard.

[0052] This embodiment provides a JTAG link topology control method, which is applied to the server in the above embodiments and any of their optional implementations, such as... Figure 5 As shown, the method includes:

[0053] Step S1: When single-channel control is in operation, the first master device sends a single-channel control command to the first switching module, and the second master device sends a single-channel control command to the second switching module. The first switching module establishes a JTAG link between the first master device and the first slave device based on the single-channel control command, and the second switching module establishes a JTAG link between the second master device and the second slave device based on the single-channel control command.

[0054] Step S2: When dual-channel control is in operation, the first master device sends a dual-channel control command to the first switching module; the first switching module establishes a JTAG link between the first master device and the first slave device based on the dual-channel control command, and then sends the dual-channel control command to the second switching module, which establishes a JTAG link between the first master device and the second slave device based on the dual-channel control command; or, when dual-channel control is in operation, the second master device sends a dual-channel control command to the second switching module; the second switching module establishes a JTAG link between the second master device and the second slave device based on the dual-channel control command, and then sends the dual-channel control command to the first switching module, which establishes a JTAG link between the second master device and the first slave device based on the dual-channel control command.

[0055] For example, taking the master device as a BMC, the slave device as a CPU, and the programmable device as a CPLD as an example, as shown in Figures 6(a) and 6(b), when the system is configured as two single-processor servers, the JTAG interfaces of the BMCs on the two DC-SCMs (i.e., the first control motherboard and the second control motherboard) are respectively connected to CPLD1 on the first motherboard and CPLD2 on the second motherboard. BMC1 controls CPLD1 via the I2C bus, causing CPLD1's CPLD_JTAG1 to be routed to CPLD_JTAG3. BMC2 controls CPLD2 via the I2C bus, causing CPLD2's CPLD_JTAG1 to be routed to CPLD_JTAG3. At this time, since the CPLD internally routes CPLD_JTAG1 to CPLD_JTAG3, each BMC can access the CPU JTAG interface on one motherboard.

[0056] For example, taking the BMC as the master device, the CPU as the slave device, and the CPLD as the programmable device as an example, as shown in Figures 7(a) and 7(b), when the system is configured as a dual-processor system, only one DC-SCM is needed to manage the two motherboards. For example, BMC1 commands CPLD1 and CPLD2 to switch their internal JTAG routing via the I2C bus, thereby forming a daisy chain of JTAGs on the two motherboards. The specific implementation method is as follows:

[0057] (1) The JTAG interface of BMC1 is connected to the CPLD_JTAG1 interface on the CPLD1 of the first motherboard.

[0058] (2) BMC1 commands CPLD1 on the first motherboard via the I2C bus, causing the TDI pin at CPLD_JTAG1 of CPLD1 to be routed to the TDI pin at CPLD_JTAG2. The TDI pin at CPLD_JTAG2 is connected to the TDI pin of the connector on the motherboard, and then connected to the TDI pin of the connector on the second motherboard via a cable. It is then connected to the TDI pin at CPLD_JTAG2 on the second motherboard via a trace on the second motherboard. BMC1 commands CPLD2 on the second motherboard, causing the TDI pin at CPLD_JTAG2 inside to be routed to the TDI pin at CPLD_JTAG3. The TDI pin at CPLD_JTAG3 is connected to the TDI pin of the CPU on the second motherboard. The TDO pin at CPLD_JTAG3 is connected to the TDO pin of the CPU on the second motherboard. The TDO pin at CPLD_JTAG3 is routed inside the CPLD to the TDO pin at CPLD_JTAG2. The TDO pin at CPLD_JTAG2 is connected to the TDO pin of the second connector on the second motherboard, and then connected via a cable to the TDO pin of the first connector on the first motherboard. On the first motherboard, the TDO pin at the first connector is connected to the TDO pin at CPLD_JTAG2 on the first motherboard.

[0059] (3) Inside CPLD1 on the first motherboard, the TDO pin at CPLD_JTAG2 is routed to the TDI pin at CPLD_JTAG3. The TDI pin at CPLD_JTAG3 is connected to the TDI pin at the CPU on the motherboard. The TDO pin at CPU1 is connected to the TDO pin at CPLD_JTAG3 of CPLD1 on the first motherboard. Inside CPLD1 on the first motherboard, the TDO pin at CPLD_JTAG3 is routed to the TDO pin at CPLD_JTAG1. The TDO pin at CPLD_JTAG1 is connected to the DC_SCM connector on the motherboard and finally to the TDO pin at BMC1, thus forming a daisy-chain access mode for JTAG.

[0060] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A JTAG link topology control device, characterized in that, include: The first switching module and the second switching module, wherein... The first switching module is connected to the first master device, the first slave device, and the second switching module; The second switching module is connected to the second master device and the second slave device; When single-channel control is used, the first switching module is used to establish a JTAG link between the first master device and the first slave device, and the second switching module is used to establish a JTAG link between the second master device and the second slave device. When dual-channel control is used, the first switching module is used to establish a JTAG link between the first master device and the first slave device, and the second switching module is used to establish a JTAG link between the first master device and the second slave device; or, when dual-channel control is used, the first switching module is used to establish a JTAG link between the second master device and the first slave device, and the second switching module is used to establish a JTAG link between the second master device and the second slave device.

2. The JTAG link topology control device according to claim 1, characterized in that, The first switching module is located on the first motherboard, and the second switching module is located on the second motherboard.

3. The JTAG link topology control device according to claim 1, characterized in that, The first switching module includes: a first programmable logic device and a first connector, wherein, The first JTAG interface of the first programmable logic device is connected to the JTAG interface of the first master device, the second JTAG interface of the first programmable logic device is connected to the JTAG interface of the first connector, the third JTAG interface of the first programmable logic device is connected to the JTAG interface of the first slave device, and the control terminal of the first programmable logic device is connected to the first master device. The JTAG interface of the first connector is connected to the second switching module.

4. The JTAG link topology control device according to claim 3, characterized in that, The second switching module includes: a second programmable logic device and a second connector, wherein, The first JTAG interface of the second programmable logic device is connected to the JTAG interface of the second master device, the second JTAG interface of the second programmable logic device is connected to the JTAG interface of the second connector, the third JTAG interface of the second programmable logic device is connected to the JTAG interface of the second slave device, and the control terminal of the second programmable logic device is connected to the second master device. The JTAG interface of the second connector is connected to the first connector.

5. The JTAG link topology control device according to claim 4, characterized in that, The control terminal of the first programmable logic device is connected to the first master device via an I2C bus; the control terminal of the second programmable logic device is connected to the second master device via an I2C bus.

6. The JTAG link topology control device according to any one of claims 2-4, characterized in that, The JTAG interface includes: TDI pin and TDO pin.

7. A server, characterized in that, include: The JTAG link topology control device, first master device, second master device, first slave device, and second slave device according to any one of claims 2-6, wherein the JTAG link topology control device comprises: a first switching module and a second switching module, wherein, The first switching module is connected to the first master device, the first slave device, and the second switching module; The second switching module is connected to the second master device and the second slave device; When single-channel control is used, the first switching module is used to establish a JTAG link between the first master device and the first slave device, and the second switching module is used to establish a JTAG link between the second master device and the second slave device. When dual-channel control is used, the first switching module is used to establish a JTAG link between the first master device and the first slave device, and the second switching module is used to establish a JTAG link between the first master device and the second slave device; or, when dual-channel control is used, the first switching module is used to establish a JTAG link between the second master device and the first slave device, and the second switching module is used to establish a JTAG link between the second master device and the second slave device.

8. The server according to claim 7, characterized in that, The first slave device is mounted on the first motherboard; the second slave device is mounted on the second motherboard.

9. The server according to claim 7, characterized in that, The first master device is mounted on the first control motherboard, and the second master device is mounted on the second control motherboard.

10. A JTAG link topology control method, characterized in that, The control method is applied to the server according to any one of claims 7-9, the method comprising: When single-channel control is enabled, the first master device sends a single-channel control command to the first switching module, and the second master device sends a single-channel control command to the second switching module. The first switching module establishes a JTAG link between the first master device and the first slave device based on the single-channel control command, and the second switching module establishes a JTAG link between the second master device and the second slave device based on the single-channel control command. When dual-channel control is in operation, the first master device sends a dual-channel control command to the first switching module; the first switching module establishes a JTAG link between the first master device and the first slave device based on the dual-channel control command; the first switching module sends the dual-channel control command to the second switching module; and the second switching module establishes a JTAG link between the first master device and the second slave device based on the dual-channel control command. Alternatively, in dual-channel control mode, the second master device sends a dual-channel control command to the second switching module; the second switching module establishes a JTAG link between the second master device and the second slave device based on the dual-channel control command, and the second switching module sends the dual-channel control command to the first switching module, and the first switching module establishes a JTAG link between the second master device and the first slave device based on the dual-channel control command.

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