Ultra-wide RISC-V long vector processor

Abstract

The invention relates to the technical field of processor hardware design, and discloses an ultra-wide RISC-V long vector processor, which comprises a 64-bit scalar RISC-V core and a plurality of vector clusters, wherein each vector cluster comprises an instruction dispatcher and an instruction scheduler, the instruction dispatcher receives vector instructions sent from the scalar core and distributes the instructions to idle processing channels, and the instruction scheduler controls the execution sequence of the instructions in time; each channel is connected with the mask unit, the sliding unit and the vector read-write unit through the full-interconnection crossbar switch, and the full-interconnection crossbar switch and the mask unit carry out conditional execution on elements in a vector instruction based on the mask register. According to the method, the long vector can be quickly and efficiently calculated, the expandability problem of a full interconnection structure is solved by adopting a special layered pipeline interconnection structure, and then long vector support can be carried out on an extended vector processor architecture.

Description

Technical Field

[0001] This application relates to the field of processor hardware design technology, such as an ultrawide RISC-V long vector processor. Background Art

[0002] With the surge in data volume and computational demands of applications today, the power wall is increasingly constraining design. Even in high-performance computing (HPC), energy efficiency must be a top priority. One effective solution to this challenge is to leverage data-level parallelism in applications, encoding multiple operations into a single instruction, thereby reducing the cost of instruction fetching and decoding. In HPC and complex machine learning (ML) applications, computations on extremely long vectors are often required.

[0003] Single Instruction Multiple Data (SIMD) architectures can leverage these very long vectors by processing multiple vector elements simultaneously. However, these architectures are typically limited by the width of the Vector Register File (VRF), which limits the number of vector elements that can be buffered within the architecture. Furthermore, the width of the data path is usually equal to the width of the VRF, further restricting data reuse capabilities and preventing further reductions in instruction fetching and decoding costs.

[0004] Furthermore, supporting longer vector lengths can lead to significant performance improvements. Using vectors closer to the floating-point unit (FPU) increases data reuse and reduces pressure on data memory. Additionally, they are more tolerant of pauses and memory access latency during execution.

[0005] The vector register file (VRF) and the number of parallel floating-point units (FPUs) in extended vector processor architectures face numerous challenges, making it impossible to support long vectors at the architecture level.

[0006] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application. Summary of the Invention

[0007] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0008] The ultrawide RISC-V long vector processor provided in this disclosure solves the technical problem that existing extended vector processor architectures cannot support long vectors.

[0009] The ultrawide RISC-V long vector processor in this embodiment includes a 64-bit scalar RISC-V core and multiple vector clusters;

[0010] Each vector cluster contains its own instruction dispatcher and instruction scheduler. The instruction dispatcher receives vector instructions from the scalar RISC-V core and distributes these instructions to idle processing channels. The instruction scheduler controls the execution order of instructions in time to ensure that instructions are executed in full parallel while ensuring that the dependencies are correct.

[0011] Each channel is connected to the mask unit, sliding unit, and vector read / write unit via a fully interconnected cross switch. The fully interconnected cross switch and the mask unit perform conditional execution on elements in the vector instruction based on the mask register. The sliding unit is connected to other vector clusters to perform vector sliding operations, including sliding left / right to insert and extract elements. The vector read / write unit is responsible for handling reading or writing vector data to memory.

[0012] Each vector cluster contains four processing channels to achieve a balance between energy consumption and performance; each processing channel contains processing units and vector register file blocks.

[0013] In some embodiments, the vector cluster includes three scalable interfaces: a request interface for connecting the vector cluster to the scalar RISC-V core; a global load memory interface for connecting the vector cluster to L2 memory; and a cluster interconnect interface for performing direct data exchange operations between different clusters.

[0014] In some embodiments, the entire ultrawide RISC-V vector processor is a vector cluster that is started and synchronized via a request interface. A global loading storage interface realizes the mapping of data from storage to vector register files in the processing channel. The actual operation is then performed by the processing unit, and data is efficiently transferred between different clusters using the cluster interconnect interface without having to send data down to storage for data exchange.

[0015] In some embodiments, the scalar RISC-V core described above broadcasts vector instructions to be processed to all clusters through a request interface via its L1 instruction cache.

[0016] When a cluster receives a request, each cluster synchronously decodes and executes each instruction, and only cluster 0 sends a response to the scalar RISC-V core, returning an ACK, including possible exception information and other information including scalar results.

[0017] In some embodiments, in the byte mapping from memory to vector register file, the i-th element is always mapped to the i(mod)L-th processing channel of the i / L(mod)C-th cluster, where L is the total number of processing channels and C is the number of vector clusters.

[0018] In some embodiments, data is first distributed from storage to the corresponding cluster via a global loading storage interface, and then distributed to the corresponding channel by the vector read / write unit within the cluster.

[0019] In some embodiments, the global load storage interface receives requests from the vector read / write units of each cluster and converts them into bus requests with a wider width to access memory. The byte alignment and rearrangement logic is implemented through multi-stage pipelines and is completed by the global memory access module to transfer memory bytes to the correct cluster in multiple cycles.

[0020] In some embodiments, the vector read / write unit of the above-mentioned vector cluster first sends a bus request signal to the bus interface, and then configures the alignment and rearrangement registers based on the decoded instruction result;

[0021] The request splitting module in the address generation phase is responsible for splitting the corresponding request into multiple aligned and valid sub-requests;

[0022] The alignment phase performs power-of-2 shifts on unaligned data to adapt to the storage bus or vector cluster; the address generation phase performs request splitting and bandwidth conversion; and the rearrangement phase distributes the aligned data to different clusters according to the element width configuration.

[0023] The alignment and rearrangement stages are both guaranteed by registers to ensure logical correctness. The corresponding control signals are determined by the address, vector length, and element width. This information is recorded in the alignment table and the rearrangement table, both of which are maintained in the global memory access module. The vector read / write unit inside the cluster only needs to complete the rearrangement operation of data bytes to each channel. The alignment process has been completed by the global load storage interface.

[0024] In some embodiments, the cluster interconnect interface adopts a ring interconnect mechanism, and the sliding unit in each cluster is also extended to utilize data from the cluster interconnect interface when needed.

[0025] In some embodiments, each cluster supports a data link between two clusters with a bidirectional 64-bit bandwidth, connecting the previous cluster and the next cluster respectively.

[0026] For operations with a sliding distance greater than 1, the single-step sliding operation will be repeated.

[0027] The cluster interconnection interface supports physical links for cross-cluster protocol operations. Registers used to ensure correct timing are located in each sliding unit. There is no direct data interaction link between each vector channel. During sliding, vector elements need to be popped into the sliding unit and the sliding unit needs to re-execute the injection operation.

[0028] The ultrawide RISC-V long vector processor provided in this disclosure can achieve the following technical effects:

[0029] This disclosure enables fast and efficient computation of long vectors. It employs a dedicated hierarchical pipelined interconnect architecture to solve the scalability problem of the full interconnect architecture, allowing it to be extended to 64 vector channels supporting double-precision floating-point operations and supporting up to 8192 double-precision vector elements, which is the longest vector length allowed in the RISC-V vector extension specification. This enables long vector support on extended vector processor architectures.

[0030] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0031] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein:

[0032] Figure 1 This is a schematic diagram of the structure of an ultrawide RISC-V long vector processor provided in an embodiment of this disclosure;

[0033] Figure 2 This is a functional diagram of a global memory access module provided in an embodiment of this disclosure;

[0034] Figure 3 This is a schematic diagram illustrating the sliding working principle of a CI interface according to an embodiment of the present disclosure;

[0035] Figure 4 This is a schematic diagram of the structure of an ultrawide RISC-V long vector processing device provided in an embodiment of this disclosure. DETAILED DESCRIPTION

[0036] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0037] The terms "first," "second," etc., used in the embodiments of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0038] Unless otherwise stated, the term "multiple" means two or more.

[0039] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0040] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0041] The term "correspondence" can refer to an association or binding relationship. The correspondence between A and B means that there is an association or binding relationship between A and B.

[0042] The ultrawide RISC-V long vector processor provided in the embodiments of this disclosure will now be described with reference to the accompanying drawings.

[0043] Figure 1 This is a schematic diagram of the structure of an ultrawide RISC-V long vector processor provided in an embodiment of this disclosure.

[0044] like Figure 1 As shown, an ultrawide RISC-V long vector processor can include a 64-bit scalar RISC-V core and multiple vector clusters;

[0045] Each vector cluster contains its own instruction dispatcher and instruction scheduler. The instruction dispatcher receives vector instructions from the scalar RISC-V core and distributes these instructions to idle processing channels. The instruction scheduler controls the execution order of instructions in time to ensure that instructions are executed in full parallel while ensuring that the dependencies are correct.

[0046] Each channel is connected to the mask unit, sliding unit, and vector read / write unit via a fully interconnected cross switch. The fully interconnected cross switch and the mask unit perform conditional execution on elements in the vector instruction based on the mask register. The sliding unit is connected to other vector clusters to perform vector sliding operations, including sliding left / right to insert and extract elements. The vector read / write unit is responsible for handling reading or writing vector data to memory.

[0047] Each vector cluster contains four processing channels to achieve a balance between energy consumption and performance; each processing channel contains processing units and vector register file blocks.

[0048] In some embodiments, the vector cluster includes three scalable interfaces: a request interface for connecting the vector cluster to the scalar RISC-V core; a global load memory interface for connecting the vector cluster to L2 memory; and a cluster interconnect interface for performing direct data exchange operations between different clusters.

[0049] In some embodiments, the entire ultrawide RISC-V vector processor is a vector cluster that is started and synchronized via a request interface. A global loading storage interface realizes the mapping of data from storage to vector register files in the processing channel. The actual operation is then performed by the processing unit, and data is efficiently transferred between different clusters using the cluster interconnect interface without having to send data down to storage for data exchange.

[0050] In some embodiments, the scalar RISC-V core broadcasts vector instructions to be processed to all clusters via a request interface through its L1 instruction cache.

[0051] When a cluster receives a request, each cluster synchronously decodes and executes each instruction, and only cluster 0 sends a response to the scalar RISC-V core, returning an ACK, including possible exception information and other information including scalar results.

[0052] In some embodiments, in the byte mapping from memory to vector register file, the i-th element is always mapped to the i(mod)L-th processing channel of the i / L(mod)C-th cluster, where L is the total number of processing channels, C is the number of vector clusters, and mod is the modulo operation.

[0053] In some embodiments, data is first distributed from storage to the corresponding cluster via a global loading storage interface, and then distributed to the corresponding channel by the vector read / write unit within the cluster.

[0054] In some embodiments, the global load storage interface receives requests from the vector read / write units of each cluster and converts them into bus requests with a wider width to access memory. Byte alignment and rearrangement logic is implemented through multi-stage pipelines and is completed by the global memory access module to transfer memory bytes to the correct cluster over multiple cycles.

[0055] In some embodiments, the vector read / write unit of the vector cluster first sends a bus request signal to the bus interface, and then configures the alignment and rearrangement registers based on the decoded instruction result;

[0056] The request splitting module in the address generation phase is responsible for splitting the corresponding request into multiple aligned and valid sub-requests;

[0057] The alignment phase performs power-of-2 shifts on unaligned data to adapt to the storage bus or vector cluster; the address generation phase performs request splitting and bandwidth conversion; and the rearrangement phase distributes the aligned data to different clusters according to the element width configuration.

[0058] The alignment and rearrangement stages are both guaranteed by registers to ensure logical correctness. The corresponding control signals are determined by the address, vector length, and element width. This information is recorded in the alignment table and the rearrangement table, both of which are maintained in the global memory access module. The vector read / write unit inside the cluster only needs to complete the rearrangement operation of data bytes to each channel. The alignment process has been completed by the global load storage interface.

[0059] In some embodiments, the cluster interconnect interface employs a ring interconnect mechanism, and the sliding units in each cluster are also extended to utilize data from the cluster interconnect interface when needed.

[0060] In some embodiments, each cluster supports a data link between two clusters with a bidirectional 64-bit bandwidth, connecting the previous cluster and the next cluster respectively.

[0061] For operations with a sliding distance greater than 1, the single-step sliding operation will be repeated.

[0062] The cluster interconnection interface supports physical links for cross-cluster protocol operations. Registers used to ensure correct timing are located in each sliding unit. There is no direct data interaction link between each vector channel. During sliding, vector elements need to be popped into the sliding unit and the sliding unit needs to re-execute the injection operation.

[0063] Figure 2 This is a functional diagram of a global memory access module provided in an embodiment of this disclosure. Figure 3 This is a schematic diagram of the sliding working principle of a CI interface provided in an embodiment of this disclosure, combined with... Figure 2 and Figure 3 ,right Figure 1 The ultra-wide RISC-V long vector processor will be described in further detail.

[0064] Specifically, the ultrawide RISC-V vector processor proposed in this disclosure adopts a decoupled overall architecture: it consists of a 64-bit scalar RISC-V core and multiple vector clusters, which work together to operate as a unified RISC-V vector accelerator. For example... Figure 1As shown, each vector cluster is equipped with its own instruction dispatcher (DISP) and instruction scheduler (SEQ). The former receives vector instructions from the scalar core and distributes them to idle processing channels, while the latter controls the execution order of instructions in time, ensuring that instructions are executed in full parallelism while maintaining correct dependencies. Each channel is connected to the Mask Unit (MASKU), Sliding Unit (SLDU), and Vector Read / Write Unit (VLSU) via a fully interconnected crossbar switch. The MASKU performs conditional execution on elements in the vector instructions based on the mask register; the SLDU is connected to other vector clusters to perform vector sliding operations, including sliding left / right to achieve element insertion and extraction at the vector granularity; the VLSU is responsible for handling reading or writing vector data to memory. Each vector cluster contains four processing channels to achieve a balance between power consumption and performance. Each processing channel contains a processing unit and a VRF block.

[0065] The vector cluster includes three extensible interfaces: a request interface (REQ) for connecting the vector cluster to the scalar core, such as... Figure 1 As shown in ①; the global load-memory interface (LS) used to connect the vector cluster and the L2 memory, as shown in ①. Figure 1 As shown in ②; and the Cluster Interconnect Interface (CI) for performing direct data exchange operations between different clusters, as shown in ②. Figure 1 As shown in ③, the entire ultrawide RISC-V vector processor can be viewed as a series of vector clusters that are started and synchronized through the REQ interface. The LS interface realizes the mapping of data from storage to the VRF within the processing channel. The processing unit then performs the actual operation and uses the CI interface to efficiently transfer data between different clusters without having to send data down to storage for data exchange.

[0066] First, the scalar core broadcasts the vector instructions to be processed to all clusters via the REQ interface through its L1 instruction cache. Upon receiving a request, each cluster synchronously decodes and executes each instruction, and only cluster 0 sends a response to the scalar core, returning an ACK, possible exception information, and other information including the scalar result. In the memory-to-VRF byte mapping, the i-th element always maps to the i(mod)L-th processing channel of the i / L(mod)C-th cluster, where L is the total number of processing channels (4 in this design), and C is the number of vector clusters. Figure 1 The gray data blocks illustrate the element storage mapping logic. Data is first distributed from storage to the corresponding cluster via the LS interface, and then distributed to the corresponding channel by the VLSU within the cluster.

[0067] The LS interface receives VLSU requests from various clusters and translates them into wider bus requests to access memory. To improve the interface's scalability and adapt to different unaligned requests, such as... Figure 2 As shown, this scheme implements byte alignment and rearrangement logic through a multi-stage pipeline, which is completed by the global memory access module, to transfer memory bytes to the correct cluster over multiple cycles. This approach trades latency for higher scalability, and long-vector applications typically have a higher tolerance for latency.

[0068] Figure 2 In this process, the VLSU of the vector cluster first sends bus request-related signals to the bus interface, such as the AR / AW signals in AXI. Then, it configures alignment and rearrangement registers based on the decoded instruction results. Since a long vector access typically spans multiple memory boundaries (such as cache lines or bus burst boundaries), the request splitting module in the address generation phase is responsible for splitting the request into multiple aligned, valid sub-requests. The alignment phase performs power-of-two shifts on unaligned data to adapt to the memory bus or vector cluster; the address generation phase performs request splitting and bandwidth conversion; and the rearrangement phase distributes the aligned data to different clusters based on the element width configuration. Both the alignment and rearrangement phases are logically correct thanks to registers, and their control signals are determined by the address, vector length, element width, etc. This information is recorded in the alignment table and rearrangement table, both maintained in the global memory access module. The VLSU within the cluster only needs to perform the rearrangement operation of data bytes to each channel, while the alignment process is already completed by the LS interface.

[0069] The CI interface employs a ring interconnect mechanism. Furthermore, the SLDUs in each cluster are extended to utilize data from the CI when needed. In most HPC and ML tasks, the most common operation is a sliding operation with a step size of 1, which only requires moving data between adjacent clusters. Considering the scalability of the ring structure, ring-interconnected CI is an excellent choice for supporting long-vector architectures.

[0070] To maximize the performance of the two most common sliding operations (sliding up one step and sliding down one step), each cluster supports a bidirectional 64-bit data link between two clusters, connecting to the preceding and following clusters respectively. For operations with a sliding distance greater than 1, the single-step sliding operation will be repeated. Figure 3 This demonstrates the basic process of single-step sliding in this solution. The CI interface also supports physical links for cross-cluster protocol operations; registers ensuring correct timing are located in each SLDU. It's important to note that there is no direct data exchange link between the different vector channels; during sliding, vector elements need to be popped into the SLDU and the SLDU needs to re-execute the injection operation.

[0071] In summary, the proposed ultra-wideband RISC-V vector processor for HPC and ML applications utilizes vector clustering and avoids fully connected memory interconnects, ensuring extremely high scalability. The segmented VRF makes VRF capacity expansion easier, scaling up to 64 Kibits of registers (the maximum register size supported by RVV), and supports efficient long vector operations with 8192 double-precision vector elements, demonstrating significant application potential in HPC and ML.

[0072] The ultrawide RISC-V long vector processor disclosed herein can compute long vectors quickly and efficiently. It adopts a dedicated hierarchical pipelined interconnect structure to solve the scalability problem of the full interconnect structure, enabling it to be expanded to 64 vector channels supporting double-precision floating-point operations, and supporting up to 8192 double-precision vector elements, which is the longest vector length allowed in the RISC-V vector extension specification. This enables long vector support on the extended vector processor architecture.

[0073] Combination Figure 4 As shown, this disclosure also provides a task processing device 400 based on adaptive block floating-point data, including a processor 404 and a memory 401. Optionally, the system may further include a communication interface 402 and a bus 403. The processor 404, communication interface 402, and memory 401 can communicate with each other via the bus 403. The communication interface 402 can be used for information transmission. The processor 404 can call logical instructions in the memory 401 to execute the method corresponding to the ultra-wide RISC-V long vector processor in the above embodiments.

[0074] Furthermore, the logic instructions in the aforementioned memory 401 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium.

[0075] The memory 401, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as program instructions / modules corresponding to the methods in the embodiments of this disclosure. The processor 404 executes functional applications and data processing by running the program instructions / modules stored in the memory 401, that is, it implements the method corresponding to the ultrawide RISC-V long vector processor in the above embodiments.

[0076] The memory 401 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the terminal device. Furthermore, the memory 401 may include high-speed random access memory and may also include non-volatile memory.

[0077] This disclosure provides a computer-readable storage medium storing computer-executable instructions configured to execute a method corresponding to an ultrawide RISC-V long vector processor.

[0078] The aforementioned computer-readable storage medium may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

[0079] The technical solutions of this disclosure can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes one or more instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of this disclosure. The aforementioned storage medium can be a non-transitory storage medium, including: a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and other media capable of storing program code; it can also be a transient storage medium.

[0080] The foregoing description and accompanying drawings fully illustrate embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. As used in the description of the embodiments, the singular forms “a,” “an,” and “(the)” are intended to equally include the plural forms unless the context clearly indicates otherwise. Similarly, the term “and / or” as used in this application means including one or more of the associated listed items and all possible combinations thereof. Additionally, when used in this application, the terms “comprise” and its variations “comprises” and / or “comprising” refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Unless otherwise specified, an element defined by the phrase "comprising a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes the element. In this document, each embodiment may focus on describing the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, then the relevant parts can be referred to the description of the method section.

[0081] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this disclosure. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0082] The methods and products (including but not limited to devices and equipment) disclosed in the embodiments herein can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units may be merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms. Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to implement this embodiment according to actual needs. Furthermore, the functional units in the embodiments of this disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0083] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than that shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. In the descriptions corresponding to the flowcharts and block diagrams in the accompanying drawings, the operations or steps corresponding to different blocks may also occur in a different order than disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in a block diagram and / or flowchart, and combinations of blocks in a block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0084] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0085] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0086] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0087] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0088] The systems and technologies described herein can be implemented in computing systems that include back-end components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include front-end components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected via digital data communication (e.g., a communication network) of any form or medium. Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0089] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0090] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this disclosure can be achieved, and this is not limited herein.

[0091] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. An ultrawide RISC-V long vector processor, characterized in that, The processor includes a 64-bit scalar RISC-V core and multiple vector clusters; Each vector cluster contains its own instruction dispatcher and instruction scheduler. The instruction dispatcher receives vector instructions from the scalar RISC-V core and distributes these instructions to idle processing channels. The instruction scheduler controls the execution order of instructions in time to ensure that instructions are executed in full parallel while ensuring that the dependencies are correct. Each channel is connected to the mask unit, sliding unit, and vector read / write unit via a fully interconnected cross switch. The fully interconnected cross switch and the mask unit perform conditional execution on elements in the vector instruction based on the mask register. The sliding unit is connected to other vector clusters to perform vector sliding operations, including sliding left / right to insert and extract elements. The vector read / write unit is responsible for handling reading or writing vector data to memory. Each vector cluster contains four processing channels to achieve a balance between energy consumption and performance; each processing channel contains processing units and vector register file blocks.

2. The processor according to claim 1, characterized in that, The vector cluster includes three scalable interfaces: a request interface for connecting the vector cluster to the scalar RISC-V core; a global load memory interface for connecting the vector cluster to L2 memory; and a cluster interconnect interface for performing direct data exchange operations between different clusters.

3. The processor according to claim 2, characterized in that, The entire ultrawide RISC-V vector processor is a vector cluster that is started and synchronized through a request interface. The global load storage interface realizes the mapping of data from storage to vector register files in the processing channel. The actual operation is then performed by the processing unit, and data is efficiently transferred between different clusters using the cluster interconnect interface without having to send data down to storage for data exchange.

4. The processor according to claim 2, characterized in that, The scalar RISC-V core broadcasts vector instructions to be processed to all clusters through its L1 instruction cache via a request interface. When a cluster receives a request, each cluster synchronously decodes and executes each instruction, and only cluster 0 sends a response to the scalar RISC-V core, returning an ACK, including possible exception information and other information including scalar results.

5. The processor according to claim 4, characterized in that, In the byte mapping from memory to vector register file, the i-th element is always mapped to the i(mod)L-th processing channel of the i / L(mod)C-th cluster, where L is the total number of processing channels and C is the number of vector clusters.

6. The processor according to claim 5, characterized in that, Data is first stored, then distributed to the corresponding cluster via the global loading storage interface, and then distributed to the corresponding channel by the vector read / write unit within the cluster.

7. The processor according to claim 6, characterized in that, The global load storage interface receives requests from the vector read / write units of each cluster and converts them into bus requests with a wider width to access memory. Byte alignment and rearrangement logic is implemented through multi-level pipelines and is completed by the global memory access module to transfer memory bytes to the correct cluster in multiple cycles.

8. The processor according to claim 6, characterized in that, The vector read / write unit of the vector cluster first sends a bus request signal to the bus interface, and then configures the alignment and rearrangement registers based on the decoded instruction result; The request splitting module in the address generation phase is responsible for splitting the corresponding request into multiple aligned and valid sub-requests; The alignment phase performs a power-of-2 shift on the unaligned data to fit the storage bus or vector cluster. During the address generation phase, request splitting and bandwidth conversion are performed; during the rearrangement phase, the aligned data is distributed to different clusters according to the element width configuration. The alignment and rearrangement stages are both guaranteed by registers to ensure logical correctness. The corresponding control signals are determined by the address, vector length, and element width. This information is recorded in the alignment table and the rearrangement table, and both tables are maintained in the global memory access module. The vector read / write units within the cluster only need to rearrange the data bytes into each channel; the alignment process has already been completed by the global load storage interface.

9. The processor according to claim 6, characterized in that, The cluster interconnection interface adopts a ring interconnection mechanism, and the sliding unit in each cluster is also extended to utilize data from the cluster interconnection interface when needed.

10. The processor according to claim 1, characterized in that, Each cluster supports two data links between the two clusters, with a bidirectional 64-bit bandwidth, connecting the previous cluster and the next cluster respectively; For operations with a sliding distance greater than 1, the single-step sliding operation will be repeated. The cluster interconnection interface supports physical links for cross-cluster protocol operations. Registers used to ensure correct timing are located in each sliding unit. There is no direct data interaction link between each vector channel. During sliding, vector elements need to be popped into the sliding unit and the sliding unit needs to re-execute the injection operation.

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