Generation method for standard cell library K library

Abstract

The invention discloses a method for generating a standard cell library K library, belongs to the field of integrated circuit design, solves the fundamental defects of flow disorder, module tight coupling and difficulty in expansion and maintenance in the prior art, and is a basis for realizing the characteristics of high efficiency and flexibility. The method comprises the following specific steps: front-end analysis and configuration; an SPICE simulation script is generated; sPICE simulation is executed in parallel; simulation result analysis and data processing; and generating a file in a Liberty format.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design, and specifically relates to a method for generating a standard cell library K. Background Technology

[0002] In the field of digital integrated circuit design, the process of characterizing standard cell libraries is often referred to as the "K-library." A standard cell library is a collection of pre-designed, simulated, and electrically characterized basic logic circuits. These circuits, called "standard cells," act like standardized building blocks, covering everything from simple logic gates (such as inverters and NAND gates) to complex combinational and sequential logic units (such as adders and flip-flops). Its core value lies in abstracting the complexity of the design from the low-level transistor level to the higher-level logic gate level, thereby achieving a high degree of design automation. A complete standard cell library not only defines the logical function and physical layout information (such as area and pin locations) of each cell, but more importantly, it precisely records the key performance parameters such as timing and power consumption of each cell under different process, voltage, and temperature (PVT) conditions through industry-standard Liberty (.lib) files. This serves as an indispensable data foundation connecting all design stages, from logic synthesis and placement / routing to final timing approval. A timing arc is the basic unit that describes the internal timing behavior of a standard cell. It defines a conditional signal propagation path from a certain input pin (or clock pin) of the cell to its output pin (or internal state node).

[0003] As semiconductor processes continue to shrink, the complexity of VLSI designs is increasing daily, placing unprecedented demands on the characterization of standard cell libraries, the cornerstone of design. However, existing open-source K-library tools and technologies, due to limitations in their design philosophy and architecture, can no longer meet the needs of modern IC design, especially the emerging Design-Process Co-Optimization (DTCO / STCO) methodologies. They generally suffer from incomplete functionality, inefficiency, and rigid architectures, all pointing to a core contradiction: the significant gap between the ever-increasing complexity of design requirements and the inadequacy of existing open-source tools. Specifically, a deficiency in existing technologies is the lack of a clear, efficient, and scalable unified characterization framework. This leads to numerous interconnected bottlenecks in terms of functional completeness, computational efficiency, and engineering practicality. Summary of the Invention

[0004] To overcome the shortcomings of existing technologies, this invention aims to provide a method for generating the standard cell library K-library, which addresses the challenges of standard cell library K-library in current VLSI design due to process node reduction and increased design complexity. The core innovation of this method lies in its adoption of a modular, front-end and back-end separated five-stage processing architecture, achieving the best balance between development flexibility and computational performance.

[0005] The technical problem solved by this invention can be achieved through the following specific technical solutions:

[0006] The method for generating the standard cell library K includes the following steps:

[0007] Step 1, Front-end parsing and configuration: Responsible for receiving and parsing user input information, providing the data foundation for subsequent automated K-library processes;

[0008] Step 2, SPICE simulation script generation: Connects the front-end configuration and simulation execution, and is responsible for automatically converting the task requirements parsed in Step 1 into executable SPICE simulation task scripts;

[0009] Step 3: Parallel execution of SPICE simulations: Execute the massive SPICE simulation tasks generated in Step 2 based on a parallel computing architecture and intelligent optimization algorithms;

[0010] Step 4, Simulation Result Analysis and Data Processing: This step involves extracting, calculating, and reconstructing the raw data generated by the parallel simulation in Step 3 into a structured intermediate data representation through a data processing flow.

[0011] Step 5: Generate Liberty format file: Convert the intermediate data structure from Step 4 into a Liberty format file that can be directly used by the downstream EDA toolchain.

[0012] Further, in step 1, the input files include configuration TCL files, template TCL files, netlist files, and process files. The user's configuration TCL files and template TCL files are parsed and executed by the TCL parser. All measurement parameters and measurement mode information required for simulation are extracted from the configuration TCL files. The index information for the K library, as well as the pin functions and direction information of the standard cells and the Boolean logic functions of the standard cells are extracted from the template TCL files for subsequent timing arc analysis. A mixed input excitation waveform generation technique is introduced to configure the mixing ratio of linear and exponential waveforms to simulate the signal waveform after being filtered by the parasitic effects of interconnects in the actual circuit.

[0013] Furthermore, in step 1, a time-series arc is automatically identified using a Boolean differential and SAT-based solution method. For a known Boolean function relationship o = f(I), the input is I = {i1, i2, ..., i...}n If the output is 0, then relative to the input variable i k The Boolean differential can be expressed as:

[0014]

[0015] in, This represents the XOR operation. Indicate i k For the opposite logical values, the SAT solver is used to perform constraint solving on each input variable, calculating the set of all solutions that make the Boolean function true when the variable is 0 and 1 respectively.

[0016] Furthermore, in step 2, the system will automatically construct simulation vectors based on the process files, netlist files, and specific parameters for generating timing arcs provided by the user, set appropriate excitation signal waveforms, configure load capacitance, and insert corresponding measurement statements to extract the required timing parameters and generate SPICE simulation scripts. During the generation process, the system will automatically adapt the corresponding syntax format according to the specified simulator type, including but not limited to simulation option settings, measurement statement formats, and output control.

[0017] Furthermore, in step 3, the specific content of the parallel execution of the SPICE simulation includes:

[0018] Step 3.1: Lock-free parallel computing architecture based on process pool;

[0019] Step 3.2: Dynamic scheduling and load balancing of LPT based on task prediction;

[0020] Step 3.3: Advanced Hybrid Iteration Acceleration for Constraint Measurement.

[0021] Furthermore, in step 4, the specific content of simulation result analysis and data processing includes:

[0022] Step 4.1 Unified parsing and parameter extraction of heterogeneous simulation results: Supports parsing simulation results in multiple formats, and supports parsing the output formats of three mainstream simulators: HSPICE, Spectre and Ngspice. By intelligently identifying the measurement file formats of different simulators, it automatically extracts key timing parameters. All extracted raw data are standardized to convert time parameters to nanoseconds, power consumption parameters to picowatts, and capacitance parameters to picofarads to ensure data consistency and accuracy.

[0023] Step 4.2, Liberty Data Structure Construction: Automatically construct a hierarchical data structure conforming to the Liberty standard based on a predefined template, and dynamically construct an intermediate data structure in memory; this data structure logically corresponds completely to the tree hierarchy of the Liberty file; for complex sequential logic units, the system can automatically identify and construct a complete module description through logical function analysis.

[0024] Step 4.3 Power Consumption Processing: When processing dynamic power consumption data, the system will intelligently match and retrieve the corresponding compensation value from the hidden power consumption simulation results based on the logical directionality of the current timing arc. This hidden power consumption compensation value will be evenly distributed among all relevant output pins and accurately subtracted from the original measured total dynamic power consumption value to obtain the dynamic switching power consumption that reflects the actual load switching consumption.

[0025] Furthermore, in step 5, a layered writing mechanism based on templates and recursive calls is adopted, following the syntax of the Liberty standard, to generate file content from top to bottom.

[0026] Compared with the prior art, the present invention has the following advantages:

[0027] (1) The present invention divides the entire process into five independent stages decoupled by a standardized data interface (such as JSON): 1) front-end parsing and configuration, 2) SPICE simulation script generation, 3) SPICE simulation parallel execution, 4) simulation result analysis and data processing, and 5) Liberty format file generation. This solves the fundamental defects of the prior art, such as chaotic process, tight module coupling, and difficulty in expansion and maintenance, and is the basis for realizing the high efficiency and flexibility of the present invention.

[0028] (2) In the front-end parsing stage, the problem of identifying valid timing arcs in the standard unit is formalized into a Boolean satisfiability (SAT) problem, which abandons the traditional inefficient truth table comparison method and solves its performance bottleneck when dealing with complex multi-input units.

[0029] (3) During the simulation execution phase, a lock-free parallel computing architecture based on an independent process pool is adopted to circumvent the GIL performance limit. More importantly, a dynamic task scheduling algorithm based on the longest processing time first (LPT) strategy is implemented on this architecture. This algorithm estimates the task time and prioritizes allocating long-running tasks to idle processes, thereby achieving load balancing. This combination solves the "long tail effect" and wasted computing resources caused by static allocation in existing technologies.

[0030] (4) When performing constraint measurements (such as setup / hold time), an iterative algorithm combining Brent's method and a result caching mechanism is employed. This algorithm prioritizes rapid iteration using the secant method or inverse quadratic interpolation, only backing up to the robust bisection method when necessary, and utilizes the caching mechanism to avoid redundant calculations of already simulated points. It solves the problems of slow convergence and numerous simulations in the traditional bisection method, and is one of the key technologies for improving the overall efficiency of the featureization process. Attached Figure Description

[0031] Figure 1 This is a flowchart of the method of the present invention. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0033] like Figure 1 As shown, a method for generating a standard unit library K includes the following steps:

[0034] (I) Step 1, Front-end parsing and configuration: responsible for receiving and parsing user input information to provide a data foundation for subsequent automated K-library processes.

[0035] (1) Input files include configuration TCL file, template TCL file, netlist file and process file.

[0036] Configure TCL file (Config Tcl): Users define global simulation parameters, PVT angle (Process, Voltage, Temperature), measurement threshold, measurement mode, simulator type selection, etc. through this file.

[0037] Template TCL file: Defines the logic function of standard cells, pin attributes (function and orientation) of standard cells, and index information used for timing simulation and power consumption simulation.

[0038] Netlist file: Provides the transistor-level circuit topology connections of standard cells, usually in SPICE format.

[0039] Process documentation: Defines the physical parameters of the underlying transistors at different process corners, and is usually provided directly by the foundry.

[0040] (2) The TCL parser parses and executes the user's configuration TCL file and template TCL file, extracts all the measurement parameters and measurement mode information required for simulation from the configuration TCL file, extracts the index information for the K library from the template TCL file, as well as the pin functions and direction information of the standard cell and the Boolean logic functions of the standard cell for subsequent timing arc analysis.

[0041] In the NLDM (Non-Linear Delay Model), the index includes index_1 and index_2. Index_1 records the rise time of the input stimulus, and index_2 records the load capacitance at the output. The input stimulus waveform is generated using index_1. To improve the consistency between simulation results and actual chip behavior, a hybrid input stimulus waveform generation technique is introduced. Users can configure the mixing ratio of linear and exponential waveforms, thereby more realistically simulating the signal waveform filtered by interconnect parasitic effects in actual circuits. This significantly improves the characterization accuracy of delay and transition times.

[0042] Timing arcs define the influence of input signal variations on the output signal, and are crucial information for simulation. Timing arcs that generate standard cells are identified by analyzing the functional information of standard cells in the user-input TCL file. To achieve efficient timing arc identification, this framework abandons the traditional, inefficient truth table comparison method and instead employs a method based on Boolean differentiation and the SAT solver to automatically identify timing arcs. Figure 1 The "Boolean Differential Analysis Timing Arc" is shown in the figure. The specific steps include: a) extracting the logical function expression of the unit; b) calculating the Boolean differential for each input; c) converting the Boolean differential expression into conjunctive normal form (CNF); d) calling the SAT solver to directly solve all the input condition combinations that can cause the output to flip, thereby accurately and efficiently identifying all timing arcs.

[0043] Given a known Boolean function relation o = f(I), the input is I = {i1, i2, ..., i...} n If the output is 0, then relative to the input variable i k The Boolean differential can be expressed as:

[0044]

[0045] Where ⊕ represents the XOR operation, Indicate i k The opposite logical value. Solving the problem of timing arcs can be viewed as finding all input vectors I. a This makes the Boolean differential 1, for each vector I a Both represent the initial state of the time-series arc vector, taking i... kThe opposite logical value yields the final state of the timing arc vector. Here, the SAT solver is used to solve for constraints on each input variable, calculating all solution sets that make the Boolean function true when the variable is 0 and 1 respectively. By calculating the symmetric difference between the two solution sets, all combinations of conditions that affect the output can be accurately identified. Furthermore, the system performs polarity analysis on each combination of conditions to determine whether the input change affects the output in a positive or negative direction. Based on the Boolean differential result and polarity information, the system can automatically generate complete timing arc information, including input / output pin relationships, timing arc type, trigger conditions, and simulation vectors. When processing sequential logic, the Boolean function, asynchronous pins, and clock pins are processed separately.

[0046] This method offers significant advantages over traditional manual analysis or simple pattern matching: it can handle Boolean functions of arbitrary complexity, is particularly suitable for standard cells with complex logic and multiple inputs / outputs, ensures the completeness and accuracy of timing arc identification, avoids omissions and errors that may occur in manual analysis, and is fully automated, greatly improving generation efficiency. This technology provides an accurate and reliable simulation scenario foundation for the subsequent SPICE simulation stage and is a key technical component in the entire Liberty timing library automatic generation process.

[0047] All the parsed information, including simulation parameters, unit functions, pin information, timing arcs, etc., is integrated and stored in a unified internal data structure (the "Configuration and Parameter Management" module in the figure), providing consistent data access for subsequent stages.

[0048] (ii) Step 2, SPICE simulation script generation: connects the front-end configuration and simulation execution, and is responsible for automatically converting the task requirements parsed in Step 1 into an executable SPICE simulation task script.

[0049] The system will automatically construct simulation vectors based on the user-provided process files, netlist files, and specific parameters for generating timing arcs, set appropriate excitation signal waveforms, configure load capacitance, and insert corresponding measurement statements to extract the required timing parameters (such as...). Figure 1The system generates independent, precisely configured SPICE simulation scripts for parameters such as Delay, Transition, Power, Leakage, Capacitance, and Constraint. Delay simulation measures signal propagation delay, transition time simulation measures signal rise and fall times, power consumption simulation calculates dynamic power consumption, constraint simulation measures setup and hold times, minimum pulse width simulation measures clock pulse width constraints, input capacitance simulation extracts pin capacitance characteristics, and leakage power consumption simulation calculates static power consumption. During generation, the system automatically adapts the corresponding syntax format based on the specified simulator type (HSPICE, Spectre, or NGSpice), including simulation option settings, measurement statement formats, and output control. The entire generation process is highly automated, dynamically adjusting the simulation task generation based on the unit's pin composition and timing arc type. This ensures that the generated SPICE scripts fully cover all necessary simulation scenarios while possessing good simulation efficiency and accuracy, laying a solid foundation for subsequent parallel simulation execution.

[0050] (III) Step 3: Parallel execution of SPICE simulation: Execute the massive SPICE simulation tasks generated in step 2 based on the parallel computing architecture and intelligent optimization algorithm.

[0051] (1) Lock-free parallel computing architecture based on process pool

[0052] To completely circumvent the performance bottleneck caused by the Python Global Interpreter Lock (GIL) in traditional multithreaded models, this application adopts a lock-free parallel computing architecture based on independent processes. At startup, this architecture pre-creates a set of independent subprocesses, each with its own memory space, based on the number of available CPU cores in the system. Each simulation task is encapsulated as an independent computing unit and distributed to the process pool. Because the processes are completely independent, they can be truly scheduled by the operating system to execute in parallel on different physical CPU cores, thereby achieving full utilization of computing resources. This design fundamentally solves the GIL limitation, allowing simulation throughput to scale almost linearly with the number of CPU cores, significantly shortening the overall K-library time for large-scale standard unit libraries.

[0053] (2) Dynamic scheduling and load balancing of LPT based on task prediction

[0054] To address the significant differences in execution time among different simulation tasks (e.g., iterative search-based constraint measurements take much longer than single-simulation latency measurements), this application integrates a dynamic task scheduling algorithm based on the Longest Processing Time (LPT) strategy. Before distributing simulation tasks, the scheduler assigns weights to the relative execution time of each task based on its type (e.g., latency, power consumption, constraints), categorizing them into high, medium, and low priorities. The scheduler continuously monitors the status of each child process in the process pool. Once a process becomes idle, the scheduler immediately selects the task with the longest estimated execution time (i.e., the highest priority task) from the queue of tasks to be executed and assigns it to the task.

[0055] By prioritizing these "heavy" tasks, this method ensures that the entire process pool will not be idle or waiting due to a few time-consuming tasks failing to complete in the later stages of the simulation cycle, thus effectively avoiding the "long tail effect" common in parallel computing. This intelligent scheduling strategy achieves excellent dynamic load balancing, significantly improving the overall utilization of computing resources and task execution efficiency.

[0056] (3) Advanced Hybrid Iterative Acceleration Algorithm for Constraint Measurement

[0057] For the most time-consuming timing constraint measurements (such as setup / hold time) in the K-library process, this application adopts a hybrid iterative acceleration algorithm based on Brent's Method with an integrated caching mechanism. This algorithm aims to quickly approximate the accurate constraint boundary with fewer simulations.

[0058] In each iteration, it prioritizes using faster convergence methods such as secant interpolation or inverse quadratic interpolation to predict the next sampling point. Only when the step size predicted by these methods exceeds a reasonable range or may lead to convergence failure will it automatically revert to the most robust bisection method, thus achieving a superlinear convergence speed far exceeding that of the traditional single bisection method while ensuring global convergence.

[0059] During the iterative search process, this invention introduces a simulation result caching mechanism. Before calculating each new sampling point, the system first checks whether the simulation result for that point already exists in the cache. If it does, the result is read directly from the cache, avoiding costly repetitive SPICE simulations. This mechanism is particularly effective in situations with dense search spaces or in the later stages of iteration, and can further significantly improve the overall execution efficiency of constraint measurements.

[0060] Through the synergistic effect of the multi-process parallel architecture, LPT dynamic scheduling, and hybrid iterative acceleration algorithm, this step can maximize computational efficiency while ensuring simulation accuracy, thus providing strong performance assurance for the rapid and reliable characterization of large-scale standard cell libraries.

[0061] (iv) Step 4, Simulation Result Analysis and Data Processing: This step extracts, calculates and reconstructs the large amount of heterogeneous raw data generated by the parallel simulation in step 3 into a unified and structured intermediate data representation through a highly automated data processing flow.

[0062] (1) Unified analysis and parameter extraction of heterogeneous simulation results

[0063] This application supports the parsing of simulation results in multiple formats, including output formats from three mainstream simulators: HSPICE, Spectre, and Ngspice. It intelligently identifies the measurement file formats (.mt0, .measure, etc.) of different simulators and automatically extracts key timing parameters. The system extracts key parameters from the simulation results, and all extracted raw data undergoes unit standardization, converting time parameters to nanoseconds, power consumption parameters to picowatts, and capacitance parameters to picofarads, ensuring data consistency and accuracy.

[0064] (2) Liberty data structure construction and power consumption handling

[0065] The system automatically constructs a hierarchical data structure conforming to the Liberty standard based on predefined templates, dynamically building a hierarchical, object-oriented intermediate data structure in memory. This data structure logically corresponds completely to the tree-like hierarchy of the Liberty file, including nodes such as libraries, operation conditions, lookup table templates, cells, pins, and timing arcs. In particular, for complex sequential logic units, the system can automatically identify and construct a complete (flip-flop) module description through logical function analysis.

[0066] To improve the accuracy of the power consumption model, an optional simulation-compensated method for precise dynamic power consumption correction is provided. When the user enables this advanced feature in the configuration, dynamic power consumption is calibrated using hidden power. Hidden power aims to accurately quantify the internal power consumption caused only by input pin state switching but not by output pin level transitions. This power consumption is often incorrectly included in the total dynamic power consumption in traditional measurements. Therefore, when processing dynamic power consumption data, the system intelligently matches and retrieves the corresponding compensation value from the hidden power consumption simulation results based on the logical directionality of the current timing arc (e.g., rising edge triggering or falling edge triggering). This hidden power consumption compensation value is then evenly distributed among all relevant output pins and precisely subtracted from the original measured total dynamic power consumption, resulting in a more accurate reflection of the dynamic switching power consumption. This method significantly improves the accuracy and reliability of the final power consumption model by actively eliminating systematic measurement errors in specific simulation scenarios.

[0067] Through this highly automated, multi-layered data extraction, standardization, structuring, and calibration process, the complex original simulation results are efficiently converted into an accurate, reliable, and uniformly formatted intermediate data representation (stored in JSON format), providing a solid and clean data foundation for the final generation of industrial-grade standard library files.

[0068] (V) Step 5, Liberty format file generation: Convert the intermediate data structure in step 4 into a Liberty format file that can be directly used by the downstream EDA toolchain.

[0069] (1) Hierarchical Liberty syntax generation and format standardization

[0070] This application employs a layered writing mechanism based on templates and recursive calls, strictly adhering to the Liberty standard's syntax specifications, and generating file content from top to bottom. This mechanism starts with the library-level global definition, recursively writing basic information such as operating conditions, voltage and temperature, and lookup table templates. Subsequently, it iterates through each standard cell in the library, generating detailed local information for each cell, including its pin definitions, timing arcs, and power consumption characteristics. It can automatically analyze data dimensions, calculate template dimensions, and generate correct references to the corresponding reference template (lut_table_template) in the cell description. This design ensures that the generated Liberty file is not only syntactically correct but also structurally clear and highly optimized, enabling efficient parsing by various EDA tools.

[0071] (2) Intelligent data structure mapping and content optimization processing

[0072] This application implements an intelligent mapping and conversion from JSON structure to Liberty syntax. The conversion process can deeply parse the hierarchy and type of JSON objects and accurately map them to the corresponding Liberty syntax groups. For timing units with complex functional logic (such as scan triggers with asynchronous set / reset), this stage has the ability to automatically process advanced logic and constraint expressions. It can completely and optimally convert all the functions of the ff module described in the internal data structure, including the logical expressions of the clock_pin and next_state functions, the trigger conditions of clear and preset, into complex Boolean expression strings required by the Liberty standard. This intelligent conversion ensures the correct and complete expression of the timing unit's function, while guaranteeing that the output Liberty file is concise, highly readable, and has good compatibility.

[0073] This converter transforms JSON time-series data into standard Liberty time-series library files through precise syntax mapping and intelligent content optimization, providing a directly usable time-series model for the EDA toolchain and completing the entire conversion process from SPICE simulation to an industry-standard time-series library.

[0074] Verification Implementation Examples

[0075] To systematically verify the practical engineering performance and technical superiority of the K-library of this invention at advanced process nodes, the widely recognized open-source 7nm FinFET PDK—ASAP7—was selected as the verification PDK. By performing a K-library analysis on the standard cell library in this PDK, a comprehensive horizontal comparison was conducted between this invention and current mainstream open-source tools and a leading commercial EDA tool, Cadence Liberate. During the evaluation preparation phase, it was noted that there was a compatibility issue between the process model files provided by the ASAP7 PDK and the open-source simulator Ngspice, resulting in the inability to perform simulations correctly. Due to this technical limitation, open-source tools that support Ngspice as the sole simulation backend, such as LCtime and CharLib, could not participate in this performance evaluation of the ASAP7 library. The entire evaluation setup and results are shown below:

[0076] (1) Evaluation settings

[0077] ① Target Library: The standard cell library in the open-source ASAP 77nm FinFET Process Design Kit (PDK) was selected as the K-library target. This library contains more than 230 standard cells with different drive strengths and functions, and is a typical representative for evaluating the performance of the K-library tool at advanced process nodes.

[0078] ② Evaluation Dimensions: This evaluation aims to comprehensively measure the overall performance of each framework in terms of both accuracy and efficiency. Accuracy assessment covers all key electrical characteristics, including leakage current, pin capacitance, delay, transition time, dynamic power consumption, and constraints. Efficiency is measured by the total runtime of the entire library K.

[0079] ③K Library Framework: The framework proposed in this invention uses the Spectre and HSPICE simulators supported by ASAP7.

[0080] ④ Comparison options: 1) Libretto, an open-source K-library tool that supports HSPICE emulators. 2) Cadence Liberate, a commercial K-library tool.

[0081] (2) Implementation steps

[0082] ① Environment Configuration and Benchmark Establishment: First, deploy all frameworks under test (this invention, Libretto) on a unified computing platform. Then, run the commercial tool Cadence Liberate to complete the K library of the ASAP7 library, generating the Liberty file as the final benchmark.

[0083] ② Framework Execution: Under the same PVT (process, voltage, temperature) angle as the baseline, the framework of this invention and Libretto were executed respectively, and the total time required for both to complete all K-library tasks was recorded. The framework of this application will employ both the Spectre simulator and the HSPICE simulator.

[0084] ③ Data Acquisition and Benchmarking Analysis: After each framework has finished running, collect the Liberty files it generates. Use scripts to compare the differences between the electrical parameters (delay, power consumption, etc.) output by each framework and the gold reference benchmark, and calculate the average relative error.

[0085] ④ Results Summary: The average relative error data and total runtime data of all frameworks are compiled and summarized into the final performance comparison results.

[0086] Table 5.Accuracy and runtime comparison among ZlibBoost and other open-source tools on ASAP7 7nm technology.

[0087]

[0088] (3) Comparison of evaluation results

[0089] The K-library of this invention stands in stark contrast to the evaluation results of other open-source tools on the ASAP77nm dataset. The K-library of this application demonstrates superior accuracy and efficiency. When using the Spectre simulator, the average errors of all its metrics are controlled at extremely low levels (e.g., latency error approximately 2.65%, power consumption error approximately 12.6%), with results highly consistent with commercial tools. Simultaneously, its runtime is highly competitive, on par with commercial tools. In contrast, the performance of the comparative solution Libretto, while capable of completing the process, suffers from serious issues with accuracy and efficiency. Its output results exhibit extremely high errors compared to the gold reference (e.g., latency error as high as 189%, power consumption error exceeding 2300%). Furthermore, its runtime is approximately 40 times longer than that of this invention, indicating inefficiency.

[0090] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for generating a standard unit library K, characterized in that, Includes the following steps: Step 1, Front-end parsing and configuration: Responsible for receiving and parsing user input information, providing the data foundation for subsequent automated K-library processes; Step 2, SPICE simulation script generation: Connects the front-end configuration and simulation execution, and is responsible for automatically converting the task requirements parsed in Step 1 into executable SPICE simulation task scripts; Step 3: Parallel execution of SPICE simulations: Execute the massive SPICE simulation tasks generated in Step 2 based on a parallel computing architecture and intelligent optimization algorithms; Step 4, Simulation Result Analysis and Data Processing: This step involves extracting, calculating, and reconstructing the raw data generated by the parallel simulation in Step 3 into a structured intermediate data representation through a data processing flow. Step 5: Generate Liberty format file: Convert the intermediate data structure from Step 4 into a Liberty format file that can be directly used by the downstream EDA toolchain.

2. The method for generating a standard unit library K library according to claim 1, characterized in that, In step 1, the input files include configuration TCL files, template TCL files, netlist files, and process files. The TCL parser parses and executes the user's configuration TCL files and template TCL files, extracts all the measurement parameters and measurement mode information required for simulation from the configuration TCL files, and extracts the index information for the K library, as well as the pin functions and direction information of the standard cells and the Boolean logic functions of the standard cells from the template TCL files for subsequent timing arc analysis. Furthermore, a hybrid input excitation waveform generation technique is introduced to configure the mixing ratio of linear and exponential waveforms in order to simulate the signal waveform after being filtered by the parasitic effect of interconnects in actual circuits.

3. The method for generating a standard unit library K library according to claim 2, characterized in that, In step 1, a time series arc is automatically identified using a Boolean differential and SAT solution method. For a known Boolean function relationship o = f(I), the input is I = {i1, i2, ..., i...} n If the output is 0, then relative to the input variable i k The Boolean differential can be expressed as: Where ⊕ represents the XOR operation, Indicate i k For the opposite logical values, the SAT solver is used to perform constraint solving on each input variable, calculating the set of all solutions that make the Boolean function true when the variable is 0 and 1 respectively.

4. The method for generating a standard unit library K library according to claim 1, characterized in that, In step 2, the system will automatically construct simulation vectors based on the process files, netlist files, and specific parameters for generating timing arcs provided by the user, set appropriate excitation signal waveforms, configure load capacitance, and insert corresponding measurement statements to extract the required timing parameters and generate SPICE simulation scripts. During the generation process, the system will automatically adapt the corresponding syntax format according to the specified simulator type, including but not limited to simulation option settings, measurement statement formats, and output control.

5. The method for generating a standard unit library K library according to claim 1, characterized in that, Step 3, the specific content of the parallel execution of SPICE simulation includes: Step 3.1: Lock-free parallel computing architecture based on process pool; Step 3.2: Dynamic scheduling and load balancing of LPT based on task prediction; Step 3.3: Advanced Hybrid Iteration Acceleration for Constraint Measurement.

6. The method for generating a standard unit library K library according to claim 1, characterized in that, Step 4, the specific content of simulation result analysis and data processing includes: Step 4.1 Unified parsing and parameter extraction of heterogeneous simulation results: Supports parsing simulation results in multiple formats, and supports parsing the output formats of three mainstream simulators: HSPICE, Spectre and Ngspice. By intelligently identifying the measurement file formats of different simulators, it automatically extracts key timing parameters. All extracted raw data are standardized to convert time parameters to nanoseconds, power consumption parameters to picowatts, and capacitance parameters to picofarads to ensure data consistency and accuracy. Step 4.2, Liberty Data Structure Construction: Automatically construct a hierarchical data structure conforming to the Liberty standard based on a predefined template, and dynamically construct an intermediate data structure in memory; this data structure logically corresponds completely to the tree hierarchy of the Liberty file; for complex sequential logic units, the system can automatically identify and construct a complete module description through logical function analysis. Step 4.3 Power Consumption Processing: When processing dynamic power consumption data, the system will intelligently match and retrieve the corresponding compensation value from the hidden power consumption simulation results based on the logical directionality of the current timing arc. This hidden power consumption compensation value will be evenly distributed among all relevant output pins and accurately subtracted from the original measured total dynamic power consumption value to obtain the dynamic switching power consumption that reflects the actual load switching consumption.

7. The method for generating a standard unit library K library according to claim 1, characterized in that, In step 5, a layered writing mechanism based on templates and recursive calls is adopted, following the syntax of the Liberty standard, to generate file content from top to bottom.

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