Layout file geometric data processing method, computer device and storage medium

Abstract

The invention provides a layout file geometric data processing method, a computer device and a storage medium. The method comprises the steps that a layout file of a three-dimensional chip is obtained, polygonal entities and layer information are extracted, the polygonal entities are distributed to corresponding layer containers, and an independent R tree index is created for each layer; performing connectivity analysis on the polygonal entity, and returning a connected component set and performance analysis statistical information; when an independent R-tree index is created for each layer, data of all polygonal entities of a single layer is obtained, a minimum boundary rectangle is generated for each polygonal entity, R-tree indexes are constructed for different layers in parallel by adopting a plurality of threads, whether the number of node entries of the R-tree indexes exceeds a splitting threshold value or not is judged, and if yes, splitting processing is carried out on nodes; and verifying the consistency of the created R tree index and the original data. The computer device and the storage medium can realize the method. The geometric data processing efficiency of the layout file can be improved.

Description

Technical Field

[0001] This invention relates to the technical field of battery internal resistance compensation calculation, specifically to a method for processing geometric data of layout files and a computer device and computer-readable storage medium for implementing this method. Background Technology

[0002] With the development of chip technology, 3D chips have been widely used, and their design efficiency is increasingly valued by researchers. The 3D chip design process involves multiple workflows and often requires the use of numerous EDA software programs. Therefore, a common format is typically needed to store the layout data of 3D chips, facilitating data transfer between different EDA software programs. GDSII (Graphic Data System II) is a common layout data exchange format in the integrated circuit design field. Its connectivity analysis is fundamental to key aspects such as physical verification, fault diagnosis, redundant structure design, 3D chip cross-layer interconnect verification, and layout simplification.

[0003] In the design process of 3D chips, it is necessary to perform connectivity analysis on the internal structure of the 3D chip based on its layout data, which involves analyzing the connectivity between multiple devices within the 3D chip. Traditional connectivity analysis methods mainly extract polygonal entities from each layer of the 3D chip's layout data and use a traversal method to check the intersection relationships between all polygonal entities, determining the connectivity between multiple polygonal entities based on these intersection relationships. However, traditional connectivity analysis methods have the following main shortcomings: First, global traversal is inefficient. Traditional methods require checking the intersection relationships between all polygon entities, resulting in a time complexity of O(n²). With increasing chip complexity, the processing requirements for millions of polygon entities in 3D chip design have reached a critical performance bottleneck. In scenarios involving millions of polygon entities in 3D chips, traditional methods require several hours to complete the connectivity analysis of a single network.

[0004] Second, cross-layer analysis is not precise enough. Because traditional analysis methods lack effective management of inter-layer relationships, they require checking all possible layer combinations, resulting in a large amount of invalid computation. In practical applications, invalid computation in cross-layer analysis accounts for more than 60%.

[0005] Third, excessive memory consumption. Because traditional methods require storing all the connectivity relationships between polygon entities, memory usage exceeds 10GB even at a scale of only a million, exceeding the memory capacity of a typical workstation.

[0006] Fourth, the response speed is slow. Because traditional methods still require global calculations when performing local network queries, they cannot achieve millisecond-level response times, which affects the efficiency of interactive design verification. Summary of the Invention

[0007] The primary objective of this invention is to provide a method for processing geometric data in layout files with fast connectivity analysis.

[0008] A second objective of the present invention is to provide a computer device for implementing the above-described method for processing geometric data of layout documents.

[0009] A third objective of this invention is to provide a readable storage medium for implementing the above-described method for processing geometric data of layout files.

[0010] To achieve the first objective of this invention, the layout file geometric data processing method provided by this invention includes acquiring the layout file of a 3D chip, parsing the layout file, and extracting polygon entities and layer information; assigning polygon entities to corresponding layer containers based on the layer labels of each layer, and creating an independent R-tree index for each layer; performing connectivity analysis on the polygon entities, and returning a set of connected components and performance analysis statistics; wherein, when creating an independent R-tree index for each layer, the data of all polygon entities in a single layer are acquired, and a minimum bounding rectangle is generated for each polygon entity; multiple threads in a thread pool are used to construct R-tree indexes for different layers in parallel, and it is determined whether the number of node entries in the R-tree index exceeds the splitting threshold. If so, the node is split; finally, the consistency between the created R-tree index and the original data is verified.

[0011] As can be seen from the above scheme, this invention constructs an R-tree index for each layer independently and utilizes multiple threads to build the R-tree index for each layer separately, with these threads running in parallel. By leveraging the independence of layer data, data contention between threads can be avoided, significantly shortening the R-tree index initialization time. Through parallel processing using multiple threads, for example, with each CPU core running a separate thread, the index construction time for 10 layers in an 8-core CPU environment is reduced from 28 seconds for serial processing to 5.2 seconds for parallel processing, representing a 5.4-fold efficiency improvement. The minimum bounding rectangle filtering of the R-tree can reduce the overhead of precise geometric calculations by more than 90%, thereby greatly improving the efficiency of connectivity analysis.

[0012] A preferred approach is to dynamically adjust the splitting threshold: determine the basic capacity of each node based on the hardware configuration, dynamically expand the basic capacity according to the total amount of available physical memory in the system, perform secondary optimization of the basic capacity based on the spatial distribution characteristics of polygon entities, and then dynamically correct the basic capacity based on the real-time load of the system.

[0013] Therefore, this invention dynamically adjusts the splitting threshold according to the actual computer hardware situation of the geometric data processing method for the layout file, thereby dynamically adjusting the number of entries in each node, avoiding the number of entries in a node being too large or too small, ensuring the balance of nodes after splitting, and thus avoiding the impact on the overall calculation efficiency due to the excessive number of entries in a certain node.

[0014] A further approach is to dynamically adjust the split threshold under pre-defined constraints; these constraints include: upper and lower capacity limits for each node and / or the threshold for each adjustment of the split threshold.

[0015] Therefore, by setting constraints for the dynamic adjustment of the split threshold, we can avoid unreasonable adjustments to the split threshold, thereby ensuring the balance of nodes after splitting.

[0016] A further approach is to use multiple threads in a thread pool to build R-tree indexes for different layers in parallel, with each thread building an R-tree index for one layer, and each thread running independently in parallel.

[0017] Therefore, since each thread runs independently, it can avoid mutual interference or influence when building R-tree indexes of different layers, thus ensuring the independence of R-tree index construction for each layer.

[0018] A further approach involves splitting the nodes by: calculating the distribution range of all entries of the target node on the X and Y axes, selecting the axis with the larger distribution range as the splitting axis, sorting all entries along the selected splitting axis according to preset rules, and dividing all entries under the target node into two or more new nodes according to the sorting results.

[0019] Therefore, the above method can ensure that the entries of the split nodes are basically equal, thus ensuring the balance of the split nodes.

[0020] A further approach involves splitting the nodes, which includes: when a new node needs to be inserted into the R-tree, calculating the area increment of multiple candidate child nodes, selecting several child nodes with the smallest area increment to form a candidate set, and selecting the child node whose smallest boundary rectangle can completely contain the rectangle to be inserted as the new node to be inserted.

[0021] Therefore, it can be seen that the new node inserted by the above method can completely contain the rectangle to be inserted, and the area increment is minimal, thus achieving the insertion of the new node with minimal resources.

[0022] A further approach involves performing connectivity analysis on polygonal entities, including: performing global connectivity analysis on the entire layout based on the input information, and / or performing local connectivity analysis on selected local layouts or polygonal entities.

[0023] Therefore, global connectivity analysis, local connectivity analysis, or both can be performed according to user needs to meet different design requirements.

[0024] A further approach involves performing global connectivity analysis on the entire map, including: traversing the polygon entity sets of each layer; for each polygon entity, calling the range retrieval interface based on the R-tree of its layer to obtain a set of candidate polygon entities that spatially overlap with the minimum bounding rectangle of that polygon entity; and performing connectivity analysis based on this set of candidate polygon entities. For selected local maps or polygon entities, local connectivity analysis involves: obtaining a specified starting polygon entity; using the starting polygon entity as the initial object for connectivity analysis; starting from the starting polygon entity, retrieving adjacent candidate polygon entities through the R-tree of its layer; after confirming that adjacent candidate polygon entities intersect with the starting polygon entity, adding the new polygon entity to the connectivity component until no more new polygon entities are added; this connectivity component forms a local network connected to the starting polygon entity; and performing connectivity analysis based on this local network.

[0025] To achieve the second objective described above, the computer device provided by the present invention includes a processor and a memory. The memory stores a computer program, and when the computer program is executed by the processor, it implements the various steps of the above-described layout file geometric data processing method.

[0026] To achieve the third objective mentioned above, the storage medium provided by the present invention stores a computer program, which, when executed by a processor, implements each step of the above-mentioned layout file geometric data processing method. Attached Figure Description

[0027] Figure 1 This is a flowchart of an embodiment of the geometric data processing method for layout files of the present invention.

[0028] Figure 2 This is a flowchart illustrating the parallel creation of R-tree indexes for multiple layers in an embodiment of the geometric data processing method for layout files of the present invention.

[0029] Figure 3 This is a flowchart illustrating connectivity analysis in an embodiment of the geometric data processing method for layout files of the present invention.

[0030] Figure 4This is a flowchart of cross-layer connectivity analysis in an embodiment of the geometric data processing method for map files of the present invention.

[0031] Figure 5 This is a flowchart of local connectivity analysis in an embodiment of the geometric data processing method for layout files of the present invention.

[0032] The present invention will be further described below with reference to the accompanying drawings and embodiments. Detailed Implementation

[0033] The layout file geometric data processing method of the present invention is used to process polygon entity data of a layout file of a three-dimensional chip, thereby analyzing the connectivity between polygon entities. The method of the present invention can be implemented on a computer device having a processor and a memory, the memory being a readable storage medium of the present invention, on which a computer program is stored, and the computer program, when executed by the processor, is the aforementioned layout file geometric data processing method.

[0034] Example of geometric data processing method for layout documents: See Figure 1 The layout file geometric data processing method in this embodiment first executes step S1 to obtain the layout file of the three-dimensional chip. Specifically, it reads the binary layout file of the three-dimensional chip to be processed, which can be a GDSII format layout file.

[0035] Then, step S2 is executed to parse the layout file and extract the polygon entity data and layer information from it. Specifically, by parsing the layout file, all geometric polygon entity data in the layout file is obtained, including metadata such as the vertex coordinate set, bounding box parameters, and layer identifier of each polygon entity. Furthermore, dereference operations are performed on reusable graphic elements (such as array references and structure references) in the layout file to generate a complete set of polygon instances.

[0036] Then, step S3 is executed, which uses a hash table structure to store polygon instances hierarchically based on the layer identifiers in the polygons, including LayerID and DataType, to establish a mapping relationship between "layers and polygon sets". For example, a hash table can be used as the basic structure, where the key is the layer identifier (LayerID + DataType combination) and the value is the set of polygon instances corresponding to that layer, stored in containers such as dynamic arrays or linked lists. Assume the current 3D chip layout file has a metal layer M1, a dielectric layer OX, and an active layer AA, with the following parameters for each layer: Metal layer M1 has LayerID=1 and DataType=0, corresponding to 500 polygon entities; dielectric layer OX has LayerID=2 and DataType=1, corresponding to 300 polygons; and active layer AA has LayerID=3 and DataType=0, corresponding to 200 polygons. When storing the data in a hash table, the following mapping relationship can be set: When Key=(1,0), the Value is the container storing the 500 "metal layer M1 polygon entities"; when Key=(2,1), the Value is the container storing the 300 "dielectric layer OX polygons", and so on.

[0037] In addition, this embodiment will also obtain the height parameters of each layer through a specified configuration file based on the physical properties of the layout design of the three-dimensional chip, such as the vertical height of the metal layer, and perform ordered sorting on all layers based on the height parameters to generate a physical layer sequence; and define the adjacency relationship between layers. For example, for any layer L(i) in the sequence, its adjacent layers are L(i-1) and L(i+1) that are adjacent in the sequence.

[0038] Then, step S4 is executed, creating an independent R-tree index for each layer in parallel. This embodiment constructs a layer-R-tree spatial index mapping table, allocating an independent R-tree index structure for each layer to store the minimum bounding rectangles and polygon pointers of all polygon entities within that layer. Furthermore, a disjoint-set data structure with path compression and rank-based merging optimization is initialized to dynamically manage the connected component relationships between polygons, where each polygon is initialized as an independent connected unit.

[0039] See Figure 2When creating an independent R-tree index for each layer, step S11 is first executed to obtain the data of all polygon entities in a single layer. Then, step S12 is executed to generate a minimum bounding rectangle for each polygon entity. Specifically, the bounding box generation method is called for each polygon entity to calculate its minimum bounding rectangle, which uses the minimum or maximum X-axis and Y-axis coordinates of the polygon as parameters and serves as the core key of the R-tree index. Additionally, degenerate polygons with an area of ​​0, such as line segments or points, are automatically filtered or marked as invalid. Furthermore, to avoid floating-point calculation errors, the boundary of the minimum bounding rectangle is slightly extended.

[0040] Then, step S13 is executed to initialize the R-tree index of the layer, and step S14 is executed to build the R-tree index for each layer using multiple threads from the thread pool. Since multiple threads run in parallel, the construction of the R-tree indexes for multiple layers is also processed in parallel. In this embodiment, the number of threads running in parallel is set to the number of CPU cores. In an 8-core CPU environment, 8 threads can run simultaneously, thus enabling the parallel construction of R-tree indexes for multiple layers. This embodiment uses a round-robin allocation method to assign layers to each thread, ensuring load balancing. Furthermore, lock-free parallelism is achieved through layer data isolation. Each thread only operates on the layer data assigned to it and does not access the data of other threads. Therefore, it can be ensured that the R-tree indexes for multiple layers are constructed independently.

[0041] When constructing the R-tree index for a layer, it's crucial to consider whether the number of entries in a node is excessive. If a node has too many entries, a new node needs to be inserted, and the node needs to be split to prevent excessive entries in a single node from impacting computational efficiency. Therefore, this embodiment sets a node splitting threshold. If the number of entries in a node exceeds the splitting threshold, that node needs to be split. Furthermore, the splitting threshold can be dynamically adjusted based on the actual hardware conditions, thereby maximizing operational efficiency within the limits of hardware resources.

[0042] This embodiment selects the insertion node based on the criterion of minimum area increment. Specifically, when a new rectangle needs to be inserted into the R-tree, the optimal child node is precisely selected to minimize redundant spatial expansion. First, the area increment of multiple candidate child nodes to be inserted needs to be calculated. For all direct child nodes of the current node, the area increment after merging the minimum bounding rectangle of each child node with the rectangle to be inserted can be calculated using the following formula: Area increment = Area of ​​the merged minimum bounding rectangle - Area of ​​the original minimum bounding rectangle of the child node, where the merged minimum bounding rectangle is the smallest rectangle that can simultaneously contain both the original minimum bounding rectangle of the child node and the rectangle to be inserted. Then, the child nodes with the smallest area increment are selected as the candidate set, prioritizing minimizing the overall spatial expansion after insertion and reducing invalid range scanning during subsequent queries. If multiple child nodes in the candidate set have the same area increment, the child nodes whose minimum bounding rectangle can completely contain the rectangle to be inserted are further selected. These child nodes do not require additional spatial expansion after merging, thus minimizing redundancy. Finally, if there are still multiple candidate child nodes after the above steps, select the child node with the smallest area of ​​the current smallest boundary rectangle as the insertion target. This can avoid inserting data into nodes that have been over-expanded and maintain the load balance of each child node.

[0043] If the number of entries stored in a node exceeds the splitting threshold, the node needs to be split. This embodiment uses linear splitting to divide the node, ensuring a balanced spatial distribution of child nodes after splitting. Specifically, first, for all entries (rectangles) within the node to be split, calculate their distribution range on the X and Y axes. The formula for calculating the distribution range is: Distribution Range = Maximum value on the coordinate axis - Minimum value on the coordinate axis. Then, select a splitting axis. Specifically, compare the distribution ranges on the X and Y axes, and select the axis with the larger distribution range as the splitting axis. This ensures splitting along the direction of the most dispersed data, reducing the overlap of the minimum boundary rectangles of the child nodes after splitting. Next, sort all entries along the selected splitting axis according to certain rules, such as ascending order. Split the sorted entries from the middle position, assigning the first half to the first new node and the second half to the second new node. This ensures a balanced number of entries in the two new nodes. Finally, calculate the minimum boundary rectangle of each of the two new nodes, i.e., the smallest rectangle containing all their respective entries, and use this as the boundary marker for the new nodes.

[0044] This embodiment also dynamically adjusts the node splitting threshold. By dynamically adjusting the splitting threshold, the core of balancing R-tree depth, number of nodes, and query efficiency can be achieved. This embodiment realizes the dynamic adjustment of the splitting threshold through a triple mechanism of hardware adaptation, data awareness, and load response.

[0045] First, this embodiment needs to determine the basic capacity of the node, i.e., hardware adaptation. This embodiment calculates the basic capacity of the node based on the CPU cache line size and the memory usage of a single entry. The formula for calculating the basic capacity is: Basic capacity = max(4, floor(CPU cache line size / 24)), where floor is the floor value rounded down. This method ensures that the memory usage of a single node is adapted to the CPU cache, reducing memory access overhead.

[0046] Then, the base capacity is dynamically expanded based on the total available physical memory of the system to avoid a surge in tree depth due to insufficient capacity when memory is plentiful. The formula for calculating the memory expansion factor is as follows: Memory expansion factor = 1 + log 10 (Total available physical memory, in GB), the formula for expanding capacity is as follows: Expanded capacity = Base capacity + 10 × Memory expansion factor. Since the expansion factor increases logarithmically with memory growth, the above method can avoid unlimited capacity expansion.

[0047] Then, the data features are dynamically adjusted. Based on the spatial distribution characteristics of the polygon entity data, the expanded capacity is optimized a second time. For example, if the spatial density is greater than 0.8, it means that the polygon distribution is dense and the minimum boundary rectangle overlap rate is high. The adjustment rule is to increase the capacity by 20% to reduce the splitting frequency of dense data and avoid the tree depth from growing too fast. If the polygon area variance is greater than a preset threshold, the adjustment rule is to reduce the capacity by 15% to reduce the coverage of a single node and improve the indexing accuracy of heterogeneous data. If the layer query hit rate is greater than 70%, it means that the layer is queried frequently. The adjustment rule is to reduce the capacity by 30% to reduce the node size of hot layers and accelerate the single-node scanning of high-frequency queries.

[0048] Finally, node capacity needs to be dynamically adjusted based on real-time system load to ensure efficiency and stability under high load. Specifically, when CPU utilization exceeds 80%, indicating tight computing resources, capacity needs to be increased by 20% to reduce splitting operations and lower computational overhead. If I / O port latency exceeds 40%, indicating slow storage access, capacity should be reduced by 15% to decrease node memory usage, improve cache hit rate, and reduce I / O port latency. If memory pressure exceeds 90%, indicating insufficient memory, capacity needs to be increased by 20% to reduce the total number of nodes, lower memory fragmentation, and reduce management overhead.

[0049] Furthermore, to prevent drastic fluctuations in capacity from causing imbalance in the R-tree structure, this embodiment also sets multiple constraints on node capacity. Specifically, a range constraint is set for node capacity, ultimately limiting the capacity of each node strictly to between 4 and 200 entries. This is because fewer than 4 entries would lead to uncontrolled R-tree depth, while more than 200 entries would reduce the query efficiency of a single node. Additionally, a magnitude constraint is set, ensuring that each capacity adjustment does not exceed ±30%, preventing a single adjustment from impacting the R-tree structure. Moreover, for different layers, such as the metal layer and dielectric layer of a chip, a splitting threshold is calculated independently to accommodate the differentiated characteristics of data in each layer.

[0050] This embodiment dynamically adjusts the splitting threshold, which is equivalent to dynamically adjusting the maximum number of entries that each node can accommodate. It reduces spatial redundancy by using the minimum area increment criterion. The linear splitting algorithm ensures node balance after splitting, and the dynamic threshold control of the R-tree depth reduces the number of level traversals. Furthermore, this embodiment employs a triple mechanism of hardware adaptation, data awareness, and load response to stably support the processing of billions of large-scale polygon entity data, catering to the needs of multiple fields such as integrated circuit layout and geographic information.

[0051] See Figure 2 After executing step S14, step S15 is also executed to verify the consistency between the created R-tree index and the original data. This involves performing integrity verification on the R-tree for each layer, including quantity consistency checks, minimum bounding rectangle accuracy verification, and sampling checks. When performing quantity consistency checks, it is necessary to ensure that the number of polygon entities in the R-tree index is completely consistent with the original number of polygons. Minimum bounding rectangle accuracy verification ensures that the error between the minimum bounding rectangle stored in the R-tree index and the calculated minimum bounding rectangle is within 1e-6. Sampling checks involve randomly selecting 10% of the polygon entities for index retrieval verification to ensure they can be correctly retrieved.

[0052] See Figure 1 After constructing R-tree indexes for multiple layers in parallel, step S5 is executed to perform connectivity analysis as needed. This embodiment can perform global connectivity analysis and local connectivity analysis according to user requirements, or only global connectivity analysis or only local connectivity analysis. One approach is to first perform global connectivity analysis to obtain a macroscopic result of connected components across the entire map, and then use local connectivity analysis to thoroughly investigate suspected abnormal components found globally, such as focusing on small areas to verify whether the connectivity logic conforms to the design.

[0053] See Figure 3Taking global connectivity analysis as an example, first, step S21 is executed to obtain the initial polygon entity data, and then step S22 is executed to obtain multiple candidate polygon entities in the R-tree structure. For example, the polygon sets of each layer are traversed. For each polygon entity, based on the R-tree index of its layer, the range retrieval interface is called to obtain the set of candidate polygons that have spatial overlap with the minimum boundary rectangle of the polygon entity.

[0054] Then, step S23 is executed to determine whether the current candidate polygon entity intersects with the previous candidate polygon entity. In this embodiment, the separating axis theorem is used to perform polygon entity intersection detection. Specifically, all edge vectors of the two polygon entities are extracted, and then the perpendicular vector of each edge is calculated. This perpendicular vector is used as a potential separating axis, and the two polygons are projected onto each separating axis. The projections are checked to see if they overlap. If there are non-overlapping projections, it is confirmed that the two polygons do not intersect; otherwise, it is determined that the two polygon entities intersect.

[0055] For complex polygon entities, this embodiment adopts the following optimization method: For complex polygon entities with more than 100 vertices, the Graham scan algorithm is first used to generate the convex hull. For polygon entities with more than 100 vertices after convex hull simplification, the Douglas-Peucker algorithm is used for further simplification. The simplification accuracy is controlled within the maximum allowable error of 0.1% of the diagonal length of the polygon bounding box.

[0056] Next, step S24 is executed to perform a union lookup set. Specifically, the root nodes of the two polygonal entities are obtained through the lookup interface, and the connected components are merged using path compression and rank-based merging strategies. Finally, the bounding box information of the root node is updated after merging, so that the bounding box information includes all child nodes.

[0057] Then, execute step S25 to add the newly discovered connected polygon entities to the expansion queue, and execute step S26 to determine whether the expansion queue is empty. If not, continue to return to step S22. If the expansion queue is empty, execute step S27 to output the results of the connected components.

[0058] For connectivity analysis across layers, see [link / reference]. Figure 4First, step S31 is executed to obtain the polygon entity data of the current layer. Then, step S32 is executed to obtain the polygon entity data of the adjacent layers. Next, step S33 is executed to perform an R-tree search of the adjacent layers. Then, step S34 is executed to filter by the minimum bounding rectangle, excluding obviously non-intersecting objects. Then, step S35 is executed to determine whether there are intersecting polygon entities across layers, that is, to confirm whether there are truly connected polygon entities. If so, step S36 is executed to mark the cross-layer connectivity, record the inter-layer connectivity relationship, and merge the connected components. Otherwise, return to step S33.

[0059] See Figure 5 For local connectivity analysis, first, step S41 is executed to obtain the user-input data, and then step S42 is executed to obtain the specified starting polygon entity, such as the user-specified coordinate point and its layer, and this polygon entity is used as the initial object for connectivity analysis. Next, step S43 is executed to initialize the extended queue, and then step S44 is executed to obtain the polygon entity to be processed.

[0060] This embodiment uses a breadth-first search strategy for local connectivity traversal. Starting from the initial polygon entity, it retrieves adjacent candidate polygons through the R-tree of its layer. After accurately detecting and confirming the existence of intersection relationships, the new polygon is added to the connectivity component and included in the subsequent expansion queue.

[0061] Therefore, steps S45 and S46 need to be executed simultaneously to search the R-trees of the same layer and the adjacent layers, respectively. For polygon entities involving cross-layer connectivity, candidate retrieval and intersection detection are only recursively performed in their adjacent layers. All objects included in the connected components are recorded through the processed polygon set to avoid duplicate detection and queue redundancy. Therefore, step S47 also needs to be executed to determine whether the candidate polygon entity intersects with the previous polygon entity. If so, step S48 is executed to perform a union lookup set and add the candidate polygon entity to the extended queue.

[0062] Then, execute step S49 to determine if the expansion queue is empty, that is, if no new polygon entities are added to the expansion queue, indicating that there are no new intersecting polygon entities, then terminate the expansion and execute step S50 to form a local network from the multiple polygon entities in the expansion queue and output the connected components.

[0063] See Figure 1After performing connectivity analysis, step S6 is executed last, returning the set of connected components and performance statistics. When performing performance statistics analysis, correctness verification is first required. Connected components are randomly selected, and the accuracy of the connectivity relationships is verified through manual review or comparison with traditional global traversal results. Then, efficiency evaluation is performed: the index construction time, connectivity analysis time (global connectivity analysis / local connectivity analysis), and the pruning rate of R-tree retrieval are calculated. Finally, the memory consumption of the index and connectivity relationship storage is statistically analyzed.

[0064] This invention adopts a three-in-one technical architecture of "hierarchical indexing-targeted retrieval-intelligent merging", which has the following significant advantages and unique features in the field of large-scale geometric spatial relationship processing.

[0065] First, this invention uses a hash table to independently store layer-level R-tree indexes, and combines this with a thread pool to build the indexes of each layer in parallel. By leveraging the independence of layer data, data contention between threads is avoided, significantly shortening the index initialization time. In an 8-core CPU environment, the index construction time for 10 layers is reduced from 28 seconds for serial processing to 5.2 seconds for parallel processing, an efficiency improvement of 5.4 times. The minimum bounding rectangle filtering of the R-tree can reduce the overhead of precise geometric calculations by more than 90%.

[0066] Second, this invention employs a breadth-first search traversal strategy, starting from a specified polygon and expanding only the geometric objects directly or indirectly connected to it. By using a set of already processed polygon pointers, redundant calculations are avoided, reducing invalid detection operations by over 90% in local analysis scenarios. In a map containing 1 million polygons, querying the connected network of a single polygon only requires processing approximately 500-2000 related polygon entities.

[0067] Third, for multi-layer layout design, this invention employs a hierarchical sequence sorted by the physical attributes of layers to accurately locate adjacent layers of connected graphics, strictly limiting cross-layer connectivity detection to physically related adjacent layers. Combined with R-tree retrieval between layers, this reduces the number of cross-layer candidate polygons by 70%-80%, improving cross-layer analysis efficiency by 3 to 5 times in a typical 10-layer metal wiring structure.

[0068] Fourth, the optimized disjoint-set data structure in this embodiment achieves near-constant time complexity for merging and searching connected components through path compression and rank-based merging; the bounding boxes of the R-tree minimize the number of polygons entering accurate detection by quickly filtering non-overlapping objects. Together, these two technologies improve the efficiency of single-polygon connectivity analysis by 3 to 5 times, reducing the connected network construction time from 2.3 seconds in traditional methods to 0.4 seconds in scenarios with 100,000 polygons.

[0069] Fifth, this invention utilizes a multi-level optimization mechanism of "spatial index pruning - local traversal - hierarchical constraints - structural optimization" to efficiently process complex map data containing tens of thousands to millions of polygons. In scenarios with 1 million polygons, the construction time of the locally connected network is controlled within 50 to 200 milliseconds, which is more than 1,000 times faster than traditional solutions, and reduces memory usage by more than 40%.

[0070] Computer device embodiment: The computer device in this embodiment may be a desktop computer or a data center or data station, which has a processor, a memory, and a computer program stored in the memory and executable on the processor, such as an information processing program for implementing the above-described information processing method. When the processor executes the computer program, it implements each step of the above-described geometric data processing method for layout files.

[0071] For example, a computer program can be divided into one or more modules, one or more of which are stored in memory and executed by a processor to complete the various modules of the present invention. One or more modules can be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of the computer program in a terminal device.

[0072] The processor referred to in this invention can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor. The processor is the control center of the terminal device, connecting various parts of the terminal device through various interfaces and lines.

[0073] Memory can be used to store computer programs and / or modules. The processor implements various functions of the terminal device by running or executing the computer programs and / or modules stored in the memory, and by accessing data stored in the memory. Memory may mainly include a program storage area and a data storage area. The program storage area may store the operating system, applications required for at least one function, etc.; the data storage area may store data created based on the use of the mobile phone, etc. In addition, memory may include high-speed random access memory, and may also include non-volatile memory, such as hard disks, RAM, plug-in hard disks, smart media cards (SMC), secure digital cards (SD cards), flash cards, at least one disk storage device, flash memory device, or other volatile solid-state storage devices.

[0074] Storage medium examples: If a computer program stored in a computer device is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of the present invention can also be implemented by a computer program instructing related hardware. This computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the various steps of the above-described layout file geometric data processing method.

[0075] Computer programs include computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. Computer-readable media can include: any entity or device capable of carrying computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in computer-readable media can be appropriately added to or subtracted according to the requirements of legislation and patent practice in a jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0076] Finally, it should be emphasized that the above are merely preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. Methods for processing geometric data in layout files, including: Obtain the layout file of the 3D chip, and parse the layout file to extract polygon entities and layer information; Its features are: The polygon entities are assigned to the corresponding layer containers based on the layer labels of each layer, and an independent R-tree index is created for each layer. Perform connectivity analysis on the polygonal entities and return a set of connected components and performance analysis statistics; Specifically, when creating an independent R-tree index for each layer, the data of all polygon entities in a single layer are obtained, and a minimum bounding rectangle is generated for each polygon entity. Multiple threads in a thread pool are used to construct R-tree indexes for different layers in parallel, and it is determined whether the number of node entries in the R-tree index exceeds the splitting threshold. If so, the node is split. Finally, the consistency between the created R-tree index and the original data is verified.

2. The method for processing geometric data of layout documents according to claim 1, characterized in that, Also includes: The splitting threshold is dynamically adjusted as follows: the basic capacity of each node is determined based on the hardware configuration, and the basic capacity is dynamically expanded according to the total amount of available physical memory in the system. The basic capacity is then optimized a second time according to the spatial distribution characteristics of the polygonal entities, and finally the basic capacity is dynamically corrected according to the real-time load of the system.

3. The method for processing geometric data of layout documents according to claim 2, characterized in that: When dynamically adjusting the splitting threshold, the splitting threshold is adjusted under preset constraints. The constraints include: upper and lower capacity limits for each node and / or the adjustment threshold for each split threshold.

4. The method for processing geometric data of layout documents according to any one of claims 1 to 3, characterized in that: When multiple threads in a thread pool are used to construct R-tree indexes for different layers in parallel, each thread is used to construct an R-tree index for one layer, and each thread runs independently in parallel.

5. The method for processing geometric data of layout documents according to any one of claims 1 to 3, characterized in that: Splitting nodes includes: For the target node to be split, calculate the distribution range of all entries of the target node on the X and Y axes, select the coordinate axis with the larger distribution range as the split axis, sort all entries along the selected split axis according to preset rules, and divide all entries under the target node into two or more new nodes according to the sorting results.

6. The method for processing geometric data of layout documents according to any one of claims 1 to 3, characterized in that: Splitting nodes includes: When a new node needs to be inserted into an R-tree, the area increment of multiple candidate child nodes is calculated, and several child nodes with the smallest area increment are selected to form a candidate set. From the candidate set, the child node whose smallest boundary rectangle can completely contain the rectangle to be inserted is selected as the new node to be inserted.

7. The method for processing geometric data of layout documents according to any one of claims 1 to 3, characterized in that: The connectivity analysis of the polygonal entities includes: performing global connectivity analysis on the entire layout based on the input information, and / or performing local connectivity analysis on selected local layouts or polygonal entities.

8. The method for processing geometric data of layout documents according to claim 7, characterized in that: The global connectivity analysis of the entire map includes: traversing the polygon entity set of each layer; for each polygon entity, based on the R-tree of its layer, calling the range retrieval interface to obtain the set of candidate polygon entities that have spatial overlap with the minimum boundary rectangle of the polygon entity. The local connectivity analysis of the selected local map or polygon entity includes: obtaining a specified starting polygon entity, using the starting polygon entity as the initial object of connectivity analysis, starting from the starting polygon entity, searching for adjacent candidate polygon entities through the R-tree of its layer, and after confirming that the adjacent candidate polygon entities have an intersection relationship with the starting polygon entity, adding the new polygon entity to the connectivity component until no more new polygon entities are added, and the connectivity component forms a local network connected to the starting polygon entity.

9. A computer device, characterized in that, It includes a processor and a memory, the memory storing a computer program, which, when executed by the processor, implements the various steps of the layout file geometric data processing method as described in any one of claims 1 to 8.

10. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, it implements the various steps of the layout file geometric data processing method as described in any one of claims 1 to 8.

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