Differential digital-to-analog converter

Abstract

The invention relates to the technical field of integrated circuits and provides a differential digital-to-analog converter. The differential digital-to-analog converter comprises two groups of N-bit resistor arrays and three-state switch arrays which have the same resistor array structure. The differential digital-to-analog converter provides a three-level sectional structure comprising three different reference voltages, reduces the area overhead of a switch, improves the conduction impedance matching, avoids the introduction of an additional dynamic circuit, facilitates the reduction of static power consumption, and improves the reliability of the converter. And application of a static circuit and related application of a high-precision resistance type digital-to-analog converter are facilitated.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a differential-to-analog converter. Background Technology

[0002] In the field of integrated circuit technology, resistive digital-to-analog converters (DACs) are widely used in low-speed DACs. Their accuracy is generally limited by the matching of unit resistance, switch on-resistance, and parasitic resistance of the layout traces. The matching of unit resistance can be improved by increasing the area; the matching of parasitic resistance of the layout traces can be improved through back-end simulation and trace optimization; and the matching of switch on-resistance can be improved by adjusting the width-to-length ratio of the switch or the gate-source voltage. The difficulty of this improvement increases exponentially with the increase in the number of bits in the DAC. For a 13-bit DAC, if only a full binary structure is used, the maximum and minimum width-to-length ratios of the switching transistors will differ by a factor of 4096. This results in very high area consumption for the switching transistors and significant layout trace complexity. To reduce the requirements for unit resistance matching, switch matching, and layout matching in high-precision DACs, a segmented structure is generally adopted. For example, an 8+5 segmented structure with 8-bit binary segments and 5-bit thermometer code segments can be used. In existing technologies, to further reduce the resistor area, switch area, and layout trace complexity, a three-level segmented structure is used, adding a third reference voltage between the first and second reference voltages. However, the three-level segmented structure introducing a third reference voltage places high demands on the matching of the switch on-resistance. This is because, for the same switch size, it is more susceptible to process variations, which can easily lead to mismatch between the switch on-resistance and the resistor array. One existing three-level differential FMM converter solution uses a transmission gate as the switch to reduce on-resistance, but this does not reduce the switch size, potentially causing switch malfunction in low-voltage designs. Another existing three-level differential FMM converter solution uses a charge pump to increase the switch's turn-on voltage, which can reduce switch size and improve on-resistance matching. However, this requires a large capacitor and a clock signal, introducing additional dynamic circuitry that may cause additional signal interference and is not conducive to reducing static power consumption in static circuit applications.

[0003] To this end, this application provides a differential fractional-to-analog converter, which offers a three-level segmented structure including three different reference voltages, reduces the area overhead of the switches and improves on-resistance matching, avoids the introduction of additional dynamic circuitry, helps reduce static power consumption, and is beneficial for static circuit applications and applications related to high-precision resistive digital-to-analog converters. Summary of the Invention

[0004] Firstly, this application provides a differential-to-analog converter (DAC). The DAC includes: two sets of N-bit resistor arrays having the same resistor array structure, where N is a positive integer greater than 1; the two sets of N-bit resistor arrays are respectively a P-terminal N-bit resistor array and an N-terminal N-bit resistor array; the output terminal of the P-terminal N-bit resistor array is the P-terminal output terminal of the DAC, and the output terminal of the N-terminal N-bit resistor array is the N-terminal output terminal of the DAC; and a tri-state switch array, used to select a P-type reference voltage, an N-type reference voltage, or an intermediate reference voltage as the input voltage of the two sets of N-bit resistor arrays based on a digital input signal; the P-type reference voltage is higher than the N-type reference voltage, and the intermediate reference voltage is between the P-type reference voltage and the N-type reference voltage; each of the P-terminal N-bit resistor array and the N-terminal N-bit resistor array includes multiple input terminals; and the tri-state switch array... The switching array includes multiple tri-state switching units corresponding one-to-one with the plurality of input terminals. Each of the multiple tri-state switching units includes a first N-type field-effect transistor pair connected to a common source. The drain of the first N-type field-effect transistor pair serves as the output of the corresponding tri-state switching unit when the intermediate reference voltage is selected. When the digital input signal is switched, the voltage of the gate of the first N-type field-effect transistor pair is located in the voltage domain associated with the P-type reference voltage. When the switching of the digital input signal is completed, the voltage of the gate of the first N-type field-effect transistor pair switches from the voltage domain associated with the P-type reference voltage to the voltage domain of a first power supply. The first power supply is used to provide a voltage equal to the sum of the P-type reference voltage and the intermediate reference voltage to clamp the voltage of the common source of the first N-type field-effect transistor pair to the intermediate reference voltage.

[0005] The first aspect of this application provides a three-level segmented structure including three different reference voltages, which reduces the area overhead of the switches and improves the on-resistance matching. It also avoids the introduction of additional dynamic circuitry, helps reduce static power consumption, and is beneficial for static circuit applications and applications related to high-precision resistive digital-to-analog converters.

[0006] In one possible implementation of the first aspect of this application, the intermediate reference voltage is the sum of a first ratio of the P-type reference voltage and a second ratio of the N-type reference voltage, wherein the sum of the first ratio and the second ratio is 1.

[0007] In one possible implementation of the first aspect of this application, the first ratio is 50% and the second ratio is 50%.

[0008] In one possible implementation of the first aspect of this application, the drain of the first N-type field-effect transistor pair is used to provide the input voltage of the corresponding input terminal of the P-terminal N-bit resistor array and the input voltage of the corresponding input terminal of the N-terminal N-bit resistor array, respectively, and the common source of the first N-type field-effect transistor pair is the switching short-circuit point of the corresponding input terminal of the P-terminal N-bit resistor array and the corresponding input terminal of the N-terminal N-bit resistor array.

[0009] In one possible implementation of the first aspect of this application, when the corresponding input terminal of the P-terminal N-bit resistor array and the corresponding input terminal of the N-terminal N-bit resistor array are shorted by a switch, the intermediate reference voltage is generated on the common source of the first N-type field-effect transistor pair.

[0010] In one possible implementation of the first aspect of this application, each of the plurality of three-state switching units includes a first N-type field-effect transistor pair connected to a common source, a P-type field-effect transistor pair connected to a common source, and a second N-type field-effect transistor pair connected to a common source. The voltage at the common source of the P-type field-effect transistor pair is clamped to the P-type reference voltage, and the voltage at the common source of the second N-type field-effect transistor pair is clamped to the N-type reference voltage. The drains of the first N-type field-effect transistor pair are respectively connected to the P-terminal common connection point and the N-terminal common connection point of the corresponding three-state switching unit. The drains of the P-type field-effect transistor pair are respectively connected to the P-terminal common connection point and the N-terminal common connection point. The drains of the second N-type field-effect transistor pair are respectively connected to the P-terminal common connection point and the N-terminal common connection point. The P-terminal common connection point is used to provide the input voltage to the corresponding input terminal of the P-terminal N-bit resistor array, and the N-terminal common connection point is used to provide the input voltage to the corresponding input terminal of the N-terminal N-bit resistor array.

[0011] In one possible implementation of the first aspect of this application, the digital input signal includes a first pair of digital control codes for controlling the gate voltage of the first N-type field-effect transistor pair to select the intermediate reference voltage as the input voltage of the corresponding input terminals of the two sets of N-bit resistor arrays; the digital input signal also includes a second pair of digital control codes for controlling the gate voltage of the P-type field-effect transistor pair to select the P-type reference voltage as the input voltage of the corresponding input terminals of the two sets of N-bit resistor arrays; and the digital input signal further includes a third pair of digital control codes for controlling the gate voltage of the second N-type field-effect transistor pair to select the N-type reference voltage as the input voltage of the corresponding input terminals of the two sets of N-bit resistor arrays.

[0012] In one possible implementation of the first aspect of this application, when any one of the first pair of digital control codes, the second pair of digital control codes, and the third pair of digital control codes undergoes code pattern switching, the voltage of the gate of the first N-type field-effect transistor pair is located in the voltage domain associated with the P-type reference voltage. When all the digital control codes of the first pair of digital control codes, the second pair of digital control codes, and the third pair of digital control codes complete code pattern switching, the voltage of the gate of the first N-type field-effect transistor pair switches from the voltage domain associated with the P-type reference voltage to the voltage domain of the first power supply.

[0013] In one possible implementation of the first aspect of this application, the differential-to-analog converter further includes a gate voltage control circuit, which includes a plurality of level shifting circuits. The plurality of level shifting circuits correspond one-to-one with the gates of the first N-type field-effect transistor pairs included in each of the plurality of tri-state switching units. The high power supply input of each of the plurality of level shifting circuits selects the output of the P-type reference voltage or the first power supply based on the gate voltage control signal. The gate voltage control signal is determined based on the change of the digital input signal. The outputs of each of the plurality of level shifting circuits are used to drive the corresponding gates of the corresponding first N-type field-effect transistor pairs of the corresponding tri-state switching units in the plurality of tri-state switching units.

[0014] In one possible implementation of the first aspect of this application, when the gate voltage control signal is low, the transmission gate pairs associated with the plurality of level shifting circuits are connected to the high power supply inputs of the respective plurality of level shifting circuits to the P-type reference voltage; when the gate voltage control signal is high, the transmission gate pairs associated with the plurality of level shifting circuits are connected to the high power supply inputs of the respective plurality of level shifting circuits to the output of the first power supply; and the outputs of the respective plurality of level shifting circuits are determined based on the first pair of digital control codes.

[0015] In one possible implementation of the first aspect of this application, the P-terminal N-bit resistor array includes an L-bit binary R-2R resistor array, an M-bit thermometer code resistor array, and a bridging resistor, wherein N = L + M, and L and M are both positive integers greater than 0. The output terminals of the L-bit binary R-2R resistor array and the M-bit thermometer code resistor array are connected through the bridging resistor. The L-bit binary R-2R resistor array constitutes the low-order segment of the P-terminal N-bit resistor array and includes L+1 resistor pairs. Among the L+1 resistor pairs, the 2nd to L+1th resistor pairs are arranged from the second farthest to the closest to the bridging resistor as the lowest to the highest order of resistance. The 1st resistor pair among the L+1 resistor pairs is the farthest from the bridging resistor and is a virtual resistor pair. The M-bit thermometer code resistor array constitutes the high-order segment of the P-terminal N-bit resistor array and includes 2 M -1 thermometer-coded resistor pair, the output terminal of the M-bit thermometer-coded resistor array serves as the output terminal of the P-terminal N-bit resistor array, and the tri-state switch array includes L+2 M Each three-state switch unit is used to connect the input terminals of the L+1 resistor pairs and the 2... M -1 thermometer-coded resistor pair input terminal, the digital input signal including L+2 M A 2-bit digital control code.

[0016] In one possible implementation of the first aspect of this application, the N-terminal N-bit resistor array includes an L-bit binary R-2R resistor array, an M-bit thermometer code resistor array, and a bridging resistor, wherein N = L + M, and L and M are both positive integers greater than 0. The output terminals of the L-bit binary R-2R resistor array and the M-bit thermometer code resistor array are connected through the bridging resistor. The L-bit binary R-2R resistor array constitutes the low-order segment of the N-terminal N-bit resistor array and includes L+1 resistor pairs. Among the L+1 resistor pairs, the 2nd to L+1th resistor pairs are arranged from the second farthest to the closest to the bridging resistor as the lowest to the highest order of resistance. The 1st resistor pair among the L+1 resistor pairs is the farthest from the bridging resistor and is a virtual resistor pair. The M-bit thermometer code resistor array constitutes the high-order segment of the N-terminal N-bit resistor array and includes 2 M -1 thermometer-coded resistor pair, the output terminal of the M-bit thermometer-coded resistor array serves as the output terminal of the N-bit resistor array, and the tri-state switch array includes L+2 M Each three-state switch unit is used to connect the input terminals of the L+1 resistor pairs and the 2... M -1 thermometer-coded resistor pair input terminal, the digital input signal including L+2 M A 2-bit digital control code.

[0017] In one possible implementation of the first aspect of this application, the differential fractional-to-analog converter is a three-level resistive high-precision digital-to-analog converter. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A schematic diagram of a differential fractional-to-analog converter provided in an embodiment of this application; Figure 2 A schematic diagram of a three-state switch unit in a three-state switch array of a differential fractional-to-analog converter provided in an embodiment of this application; Figure 3 A timing diagram showing the change of the gate voltage of the first N-type field-effect transistor pair in a three-state switching unit according to an embodiment of this application, relative to a digital input signal; Figure 4 A schematic diagram of an N-bit resistor array on the P-side of a differential fractional-to-analog converter provided in an embodiment of this application; Figure 5 This is a schematic diagram of an N-terminal N-bit resistor array for a differential fractional-to-analog converter provided in an embodiment of this application. Detailed Implementation

[0020] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0021] It should be understood that in the description of this application, "at least one" means one or more, and "multiple" means two or more. In addition, the words "first," "second," etc., unless otherwise stated, are used only for the purpose of distinguishing descriptions and should not be construed as indicating or implying relative importance or order.

[0022] Figure 1 This is a schematic diagram of a differential fractional-to-analog converter provided in an embodiment of this application. Figure 1As shown, the differential-to-analog converter includes two sets of N-bit resistor arrays with identical resistor array structures, where N is a positive integer greater than 1. The two sets of N-bit resistor arrays are a P-terminal N-bit resistor array A110 and an N-terminal N-bit resistor array A120, respectively. The output terminal of the P-terminal N-bit resistor array A110 is the P-terminal output terminal of the differential-to-analog converter, and the output terminal of the N-terminal N-bit resistor array A120 is the N-terminal output terminal of the differential-to-analog converter. The differential-to-analog converter also includes a tri-state switch array A130. The tri-state switch array A130 is used to select a P-type reference voltage, an N-type reference voltage, or an intermediate reference voltage as the input voltage of the two sets of N-bit resistor arrays based on a digital input signal. The P-type reference voltage is higher than the N-type reference voltage, and the intermediate reference voltage is between the P-type reference voltage and the N-type reference voltage. The P-terminal N-bit resistor array A110 and the N-terminal N-bit resistor array A120 each include multiple input terminals, and the tri-state switch array A130 includes multiple tri-state switch units corresponding one-to-one with the multiple input terminals. Each of the multiple tri-state switch units includes a first N-type field-effect transistor pair connected to a common source, with the drain of the first N-type field-effect transistor pair serving as the output of the corresponding tri-state switch unit when the intermediate reference voltage is selected. Furthermore, when the digital input signal is switched, the voltage of the gate of the first N-type field-effect transistor pair is located in the voltage domain associated with the P-type reference voltage, and when the digital input signal switching is completed, the voltage of the gate of the first N-type field-effect transistor pair switches from the voltage domain associated with the P-type reference voltage to the voltage domain of the first power supply. The first power supply is used to provide a voltage equal to the sum of the P-type reference voltage and the intermediate reference voltage to clamp the voltage of the common source of the first N-type field-effect transistor pair to the intermediate reference voltage.

[0023] See Figure 1This differential-to-analog converter (DAC) employs a three-level segmented structure, introducing three reference voltages: a P-type reference voltage, an N-type reference voltage, and an intermediate reference voltage. The P-type reference voltage is higher than the N-type reference voltage, and the intermediate reference voltage lies between the P-type and N-type reference voltages. Furthermore, the DAC includes two sets of N-bit resistor arrays with identical resistor array structures: a P-side N-bit resistor array A110 and an N-side N-bit resistor array A120. A three-state switch array A130 controls the selection of the corresponding reference voltage as the input voltage for these two sets of N-bit resistor arrays. Thus, by combining the specific structure of the N-bit resistor arrays, macroscopic adjustment accuracy is provided through the selection of the reference voltage, while microscopic adjustment accuracy is provided through the voltage division effect of the resistor arrays, thereby better meeting the adjustment requirements of the DAC. Here, because the intermediate reference voltage lies between the relatively high P-type reference voltage and the relatively low N-type reference voltage, the compatibility between the switch's on-resistance and the resistor array, i.e., on-resistance matching, needs to be considered. Furthermore, considering process variations, as well as the influence of operating temperature and voltage, the on-resistance of the switch may deviate from the design value, potentially leading to a mismatch between the on-resistance and the resistor array. Therefore, specialized optimization design is required for the selection of an intermediate reference voltage. This is because a P-type reference voltage can accommodate switches using P-type MOSFETs, while an N-type reference voltage can accommodate switches using N-type MOSFETs. However, the intermediate reference voltage is higher than the N-type reference voltage but lower than the P-type reference voltage. This means that the possibility of breakdown due to excessively high transient gate voltage must be considered, as well as the possibility of the switch failing to open or malfunctioning due to excessively low gate voltage. Additionally, the extra interference and increased static power consumption introduced by the dynamic circuit must also be taken into account. Therefore, for the selection of an intermediate reference voltage, each of the plurality of tri-state switching units has a specially optimized circuit and operating principle. Specifically, each of the plurality of tri-state switching units includes a first N-type MOSFET pair connected to a common source, with the drain of the first N-type MOSFET pair serving as the output of the corresponding tri-state switching unit when the intermediate reference voltage is selected. Here, the digital input signal is used to select a P-type reference voltage, an N-type reference voltage, or an intermediate reference voltage as the input voltage for the two sets of N-bit resistor arrays. When the digital input signal is switched, the gate voltage of the first N-type field-effect transistor pair is located in the voltage domain associated with the P-type reference voltage, and when the digital input signal switching is complete, the gate voltage of the first N-type field-effect transistor pair switches from the voltage domain associated with the P-type reference voltage to the voltage domain of the first power supply.Thus, considering the potential on-resistance issues of the switches and the mismatch of the resistor array under non-ideal conditions, a first power supply is introduced as an external power source to generate an intermediate reference voltage. This first power supply allows for voltage clamping at the intermediate reference voltage and requires relatively low drive capability, resulting in lower circuit overhead. In some embodiments, the first power supply can clamp the common source of the first N-type field-effect transistor (FET) to the intermediate reference voltage. However, considering the influence of various non-ideal conditions, an additional voltage source can be used to stabilize the common source of the first N-type FET at the desired intermediate reference voltage. Moreover, this additional voltage source only serves a voltage regulator function, therefore requiring less drive capability and resulting in lower circuit overhead.

[0024] Continue reading Figure 1The digital input signal can be multiple digital control codes used to control the gate voltage of the corresponding field-effect transistor (FET), thereby controlling the opening and closing of the FET, and further controlling the switch to select the corresponding reference voltage as the input to the resistor array. Here, when the digital input signal remains stable, that is, when the digital input signal switching is complete, the drain voltage of the first N-type FET pair is in a relatively stable state. This effectively prevents the transient gate voltage from exceeding the transient drain voltage by too much, thus avoiding FET breakdown due to excessively high transient gate voltage. However, when the digital input signal switches, this means that the input digital control code may change, for example, from "1100" to "0111". Therefore, the change in the code bit of the corresponding digital control code faced by each tri-state switch unit of the tri-state switch array is unpredictable. It may maintain the original control level, switch from high level to low level, or switch from low level to high level. This means that when the digital input signal changes, such as during switching, the drain voltage of the first N-type FET pair is in a relatively unstable state. Therefore, during the switching of the digital input signal, the gate voltage of the first N-type field-effect transistor pair is located in the voltage domain associated with the P-type reference voltage, where the P-type reference voltage is the highest of the three reference voltages, for example, 1.8 volts. The common-source voltage of the first N-type field-effect transistor pair is voltage-clamped at the intermediate reference voltage, for example, 0.9 volts. Then the voltage of the first power supply is equal to the sum of the P-type reference voltage and the intermediate reference voltage, which is 2.7 volts. Therefore, when the digital input signal is switched, the gate voltage of the first N-type field-effect transistor pair is located in the voltage domain associated with the P-type reference voltage (e.g., 1.8 volts). By utilizing the characteristic that the voltage of the drain of the first N-type field-effect transistor pair is less than the gate-drain breakdown voltage of the first N-type field-effect transistor pair (the transient voltage of the gate exceeds the transient voltage of the drain by too much, causing breakdown), the gate-drain breakdown phenomenon of the first N-type field-effect transistor pair can be avoided. Therefore, when the digital input signal is switched, the voltage difference between the gate and drain of the first N-type field-effect transistor pair gradually increases and tends to stabilize, while the voltage of the common source of the first N-type field-effect transistor pair is clamped at the intermediate reference voltage. When the digital input signal switching is completed, the voltage domain is switched, and the voltage of the gate of the first N-type field-effect transistor pair is switched from the voltage domain associated with the P-type reference voltage to the voltage domain of the first power supply. The voltage provided by the first power supply to drive the field-effect transistor is equal to the sum of the P-type reference voltage and the intermediate reference voltage (e.g., 2.7 volts).Thus, when the digital input signal completes the switching, the voltage of the gate of the first N-type field-effect transistor pair is raised to the voltage of the first power supply (2.7 volts) through voltage domain switching. This, combined with the fact that the voltage of the common source of the first N-type field-effect transistor pair is clamped at the intermediate reference voltage (0.9 volts), naturally makes the voltage difference between the gate and common source of the first N-type field-effect transistor pair equal to the P-type reference voltage (1.8 volts). Thus, by introducing the first power supply as an external power supply to generate a stable intermediate reference voltage, voltage clamping at the intermediate reference voltage can be achieved. Combined with the voltage domain switching operation, this not only avoids the phenomenon of transient voltage overshoot and breakdown that may occur during digital input signal switching, but also naturally works with the characteristic of the common source voltage being clamped at the intermediate reference voltage when the digital input signal is stable. Therefore, it overcomes the problems of switch on-resistance and resistor array mismatch that may occur under non-ideal conditions due to process deviations, operating voltage, and operating temperature, and significantly reduces the static power consumption of the external power supply, thereby reducing the switch size and switching area overhead. Furthermore, because the switch's turn-on voltage is not modified, but rather specifically optimized for selecting an intermediate reference voltage, no additional capacitors or clock are needed, thus avoiding additional dynamic circuitry and interference. Additionally, by setting the intermediate reference voltage to the midpoint between the P-type and N-type reference voltages, the voltage generated in an ideal short circuit will be the midpoint between these two voltages—the intermediate reference voltage. This means that by setting the intermediate reference voltage to the midpoint between the P-type and N-type reference voltages, the common-source connection naturally clamps the common-source voltage to the designed intermediate reference voltage. This results in the lowest possible static power consumption from the external power supply and optimized circuit area. Moreover, depending on specific needs, the intermediate reference voltage can be set to the weighted sum of the P-type and N-type reference voltages, providing greater adaptability. As described above, in some embodiments, the common source of the first N-type field-effect transistor can be clamped at an intermediate reference voltage using a first power supply. However, considering the influence of various non-ideal conditions, an additional voltage source can be used to stabilize the common source of the first N-type field-effect transistor at the desired intermediate reference voltage. Moreover, this additional voltage source only serves as a voltage regulator, so it does not require high driving capability, resulting in lower circuit overhead.

[0025] Continue reading Figure 1Through digital input signals, multiple different sets of digital control codes can be provided, each used to control a corresponding reference voltage. In some embodiments, the first N-type field-effect transistor pair is an N-type channel-metal-oxide-semiconductor (NMOS) pair that receives the intermediate reference voltage (VCM). Conversely, the tri-state switching unit may also include a P-type field-effect transistor pair as a P-type channel-metal-oxide-semiconductor (PMOS) pair that receives the P-type reference voltage (VREFP). The tri-state switching unit may also include a second N-type field-effect transistor pair as an NMOS pair that receives the N-type reference voltage (VREFN). Therefore, each tri-state switching unit may include a first N-type field-effect transistor pair connected by a common source, a P-type field-effect transistor pair connected by a common source, and a second N-type field-effect transistor pair connected by a common source. The voltage at the common source of the P-type field-effect transistor pair is clamped to the P-type reference voltage, and the voltage at the common source of the second N-type field-effect transistor pair is clamped to the N-type reference voltage. The drains of the first N-type field-effect transistor pair are connected to the P-terminal common connection point and the N-terminal common connection point of the corresponding tri-state switching unit, respectively. The drains of the P-type field-effect transistor pair are connected to the P-terminal common connection point and the N-terminal common connection point, respectively. The P-terminal common connection point provides the input voltage to the corresponding input terminal of the P-terminal N-bit resistor array, and the N-terminal common connection point provides the input voltage to the corresponding input terminal of the N-terminal N-bit resistor array. Thus, three different field-effect transistor pairs are provided to select the corresponding reference voltage as the input to the resistor array. Additionally, the digital input signal may include multiple sets of digital control codes for controlling the gate voltage of the corresponding field-effect transistor pair. In some embodiments, the digital input signal includes a first pair of digital control codes (Dcp and Dcn) for controlling the gate voltage of the first N-type field-effect transistor pair, a second pair of digital control codes (Dpp and Dpn) for controlling the gate voltage of the P-type field-effect transistor pair, and a third pair of digital control codes (Dnp and Dnn) for controlling the gate voltage of the second N-type field-effect transistor pair.Thus, a set of PMOS transistors is connected to the common source and clamped at VREFP. The gate voltage of this set of PMOS transistors is controlled by two external control signals, Dpp and Dpn, allowing VREFP to be selected as the input voltage for both the P-terminal and N-terminal N-bit resistor arrays. Similarly, a set of NMOS transistors is connected to the common source and clamped at VCM. The gate voltage of this set of NMOS transistors is controlled by two external control signals, Dcp and Dcn, allowing VCM to be selected as the input voltage for both the P-terminal and N-terminal N-bit resistor arrays. Finally, a set of NMOS transistors is connected to the common source and clamped at VREFN. The gate voltage of this set of NMOS transistors is controlled by two external control signals, Dnp and Dnn, allowing VREFN to be selected as the input voltage for both the P-terminal and N-terminal N-bit resistor arrays. Furthermore, VCM is the sum of the ratios of VREFP and VREFN, with a total ratio of 1. In some embodiments, the ratios are 50% each, which implies the lowest static power consumption. Furthermore, by providing additional gate voltage control circuitry, the voltage domain switching operation of the gate voltage of the first N-type field-effect transistor pair can be controlled, and a first power supply (VDDH) is introduced. This allows the gate voltage of the first N-type field-effect transistor pair to switch between the two voltage domains VREFP and VDDH, thereby realizing a specially optimized gate voltage control algorithm for the case of selecting an intermediate reference voltage, i.e., the NMOS corresponding to VCM. Thus, by selecting the reference voltage as the input voltage of the resistor array, the output of the analog voltage is finely controlled through voltage division within the resistor array.

[0026] In short, Figure 1 The differential-to-analog converter (DAC) shown introduces a high power supply, also known as a first power supply (VDDH), which provides a voltage equal to the sum of the P-type reference voltage and the intermediate reference voltage, i.e., VDDH = VREFP + VCM. This improves the conduction state of the first N-type MOSFET pair used for the third reference voltage switch in the DAC, reducing switch size and improving on-resistance matching. Since the high power supply VDDH drives the gate of the MOSFET, almost no static drive current is required, resulting in minimal analog circuit overhead for generating VDDH. It can be applied to various designs, including low-voltage, static, and dynamic circuits, without introducing additional noise interference, meeting high-precision design requirements. Furthermore, by employing a switching timing optimized for the intermediate reference voltage and combining it with changes in the digital input signal to operate voltage domain switching, the risk of NMOS transistor overvoltage failure can be avoided. This provides a three-level segmented structure with three different reference voltages, reduces the area overhead of the switches and improves on-resistance matching, avoids the introduction of additional dynamic circuitry, helps reduce static power consumption, and is beneficial for static circuit applications and applications related to high-precision resistive digital-to-analog converters.

[0027] Figure 2 This is a schematic diagram of a tri-state switching unit in a tri-state switching array of a differential-to-analog converter provided in an embodiment of this application. As described above, the P-terminal N-bit resistor array and the N-terminal N-bit resistor array each include multiple input terminals, and the tri-state switching array includes multiple tri-state switching units corresponding one-to-one with the multiple input terminals. Each of the multiple tri-state switching units includes a first N-type field-effect transistor pair (N-type field-effect transistor A210 and N-type field-effect transistor B220) connected to a common source. The drain of the first N-type field-effect transistor pair (N-type field-effect transistor A210 and N-type field-effect transistor B220) (drain 216 of N-type field-effect transistor A210 and drain 226 of N-type field-effect transistor B220) serves as the output of the corresponding tri-state switching unit when the intermediate reference voltage is selected. Furthermore, when the digital input signal is switched, the voltage of the gates (gate 212 of N-type field-effect transistor A210 and gate 222 of N-type field-effect transistor B220) of the first N-type field-effect transistor pair (N-type field-effect transistor A210 and N-type field-effect transistor B220) is located in the voltage domain associated with the P-type reference voltage 290. And when the digital input signal is switched, the voltage of the gates (gate 212 of N-type field-effect transistor A210 and gate 222 of N-type field-effect transistor B220) of the first N-type field-effect transistor pair (N-type field-effect transistor A210 and N-type field-effect transistor B220) switches from the voltage domain associated with the P-type reference voltage 290 to the voltage domain of the first power supply 209. The first power supply 209 is used to provide a voltage equal to the sum of the P-type reference voltage 290 and the intermediate reference voltage 294 so as to clamp the voltage of the common source (source 214 of N-type field effect transistor A210 and source 224 of N-type field effect transistor B220) of the first N-type field effect transistor pair (N-type field effect transistor A210 and N-type field effect transistor B220) at the intermediate reference voltage 294.

[0028] See Figure 2Each of the plurality of three-state switching units includes a first N-type field-effect transistor pair (N-type field-effect transistor A210 and N-type field-effect transistor B220) connected to a common source, a P-type field-effect transistor pair (P-type field-effect transistor A230 and P-type field-effect transistor B240) connected to a common source, and a second N-type field-effect transistor pair (N-type field-effect transistor C250 and N-type field-effect transistor D260) connected to a common source. Thus, three different field-effect transistor pairs are provided for selecting the corresponding reference voltage as the input to the resistor array. The voltage at the common source of the P-type field-effect transistor pair (P-type field-effect transistor A230 and P-type field-effect transistor B240) is clamped to the P-type reference voltage 290. The voltage at the common source of the second N-type field-effect transistor pair (N-type field-effect transistor C250 and N-type field-effect transistor D260) is clamped to the N-type reference voltage 292. The drains of the first N-type field-effect transistor pair (N-type field-effect transistor A210 and N-type field-effect transistor B220) (N-type field-effect transistor A210 and N-type field-effect transistor B220) are respectively connected to the P-terminal common connection point 280 and the N-terminal common connection point 282 of the corresponding three-state switching unit. The drains of the P-type MOSFET pair (P-type MOSFET A230 and P-type MOSFET B240) (drain 236 of P-type MOSFET A230 and drain 246 of P-type MOSFET B240) are respectively connected to the P-terminal common connection point 280 and the N-terminal common connection point 282. The drains of the second N-type MOSFET pair (N-type MOSFET C250 and N-type MOSFET D260) (drain 256 of N-type MOSFET C250 and drain 266 of N-type MOSFET D260) are respectively connected to the P-terminal common connection point 280 and the N-terminal common connection point 282. The P-terminal common connection point 280 is used to provide the input voltage to the corresponding input terminal of the P-terminal N-bit resistor array, and the N-terminal common connection point 282 is used to provide the input voltage to the corresponding input terminal of the N-terminal N-bit resistor array. Thus, a three-level segmented structure with three different reference voltages is provided, and a specially optimized gate voltage control algorithm is implemented by providing an additional gate voltage control circuit 202.Furthermore, by utilizing the three common-source MOSFET pairs mentioned above, and connecting the drain of the MOSFET to a common connection point as the output of the three-state switching unit, the voltage can be clamped at the intermediate reference voltage 294 using the first power supply 209. Combined with voltage domain switching operation, this not only avoids the phenomenon of transient voltage overload and breakdown that may occur during digital input signal switching, but also naturally leverages the characteristic of the common-source voltage being clamped at the intermediate reference voltage 294 when the digital input signal is stable. Therefore, it overcomes the problem of switch on-resistance and resistor array mismatch that may occur due to process deviations, operating voltage, and operating temperature under non-ideal conditions, and significantly reduces the static power consumption of the external power supply, thus reducing the switch size and switch area overhead. In addition, because the switch turn-on voltage is not changed, but a special optimization design is made for the case of selecting the intermediate reference voltage 294, no additional capacitors and clock are required, thus avoiding additional dynamic circuits and additional interference factors.

[0029] See Figure 2The digital input signal includes a first pair of digital control codes 204 for controlling the voltage of the gates (gate 212 of N-type MOSFET A210 and gate 222 of N-type MOSFET B220) of the first N-type MOSFET pair (N-type MOSFET A210 and N-type MOSFET B220) to select the intermediate reference voltage 294 as the input voltage of the corresponding input terminals of the two sets of N-bit resistor arrays. The digital input signal also includes a second pair of digital control codes 206 for controlling the voltage of the gates (gate 232 of P-type MOSFET A230 and gate 242 of P-type MOSFET B240) of the P-type MOSFET pair (P-type MOSFET A230 and P-type MOSFET B240) to select the P-type reference voltage 290 as the input voltage of the corresponding input terminals of the two sets of N-bit resistor arrays. The digital input signal also includes a third pair of digital control codes 208 for controlling the voltage of the gates (gate 252 of N-type MOSFET C250 and gate 262 of N-type MOSFET D260) of the second N-type field-effect transistor pair (N-type MOSFET C250 and N-type MOSFET D260) to select the N-type reference voltage 292 as the input voltage of the corresponding input terminals of the two sets of N-bit resistor arrays. Thus, three different MOSFET pairs are provided for selecting the corresponding reference voltage as the input to the resistor array. Furthermore, by utilizing multiple sets of different digital control codes, the gate voltage of the corresponding MOSFET pair can be controlled. Therefore, by selecting the reference voltage as the input voltage of the resistor array, the voltage division within the resistor array achieves the effect of finely controlling the analog voltage output. Furthermore, the first pair of digital control codes 204 does not directly act on the gates (gate 212 of N-type MOSFET A210 and gate 222 of N-type MOSFET B220) of the first pair of N-type MOSFETs (N-type MOSFET A210 and N-type MOSFET B220). Instead, it implements a specially optimized gate voltage control algorithm through the gate voltage control circuit 202. Thus, the introduction of the first power supply 209 overcomes the problem of mismatch in the switching impedance and resistor array that may occur due to process deviations, operating voltage, and operating temperature under non-ideal conditions. Moreover, by utilizing the gate voltage control circuit 202 to optimize the switching timing for the intermediate reference voltage and combining it with changes in the digital input signal to operate the voltage domain switching, the risk of NMOS transistor overvoltage failure can be avoided. Additionally, when the digital input signal is stable, it naturally clamps the voltage at the intermediate reference voltage 294 in conjunction with the common-source voltage.

[0030] Continue reading Figure 2When any one of the first pair of digital control codes 204, the second pair of digital control codes 206, and the third pair of digital control codes 208 undergoes a code pattern switch, the voltage of the gates (gate 212 of N-type MOSFET A210 and gate 222 of N-type MOSFET B220) of the first N-type MOSFET pair (N-type MOSFET A210 and N-type MOSFET B220) is located in the voltage domain associated with the P-type reference voltage 290. When all the digital control codes in the first pair of digital control codes 204, the second pair of digital control codes 206, and the third pair of digital control codes 208 complete the code pattern switch, the voltage of the gates (gate 212 of N-type MOSFET A210 and gate 222 of N-type MOSFET B220) of the first N-type MOSFET pair (N-type MOSFET A210 and N-type MOSFET B220) switches from the voltage domain associated with the P-type reference voltage 290 to the voltage domain of the first power supply 209. When the digital input signal is switched, it means that the input digital control code may change, for example, from "1100" to "0111". Therefore, the change of the corresponding digital control code bit faced by each tri-state switch unit of the tri-state switch array is unpredictable. It may remain at the original control level, or it may switch from high level to low level, or from low level to high level. This means that when the digital input signal changes, such as when it is switched, the voltage of the drain of the first N-type field-effect transistor pair (N-type field-effect transistor A210 and N-type field-effect transistor B220) is in a relatively unstable state. Therefore, when the digital input signal is switched, the voltage of the gates (gate 212 of N-type MOSFET A210 and gate 222 of N-type MOSFET B220) of the first N-type MOSFET pair (N-type MOSFET A210 and N-type MOSFET B220) is located in the voltage domain associated with the P-type reference voltage 290. In this way, by utilizing the characteristic that the voltage of the drains (drain 216 of N-type MOSFET A210 and drain 226 of N-type MOSFET B220) of the first N-type MOSFET pair (N-type MOSFET A210 and N-type MOSFET B220) is less than the gate-drain breakdown voltage of the first N-type MOSFET pair (N-type MOSFET A210 and N-type MOSFET B220), the gate-drain breakdown phenomenon of the first N-type MOSFET pair (N-type MOSFET A210 and N-type MOSFET B220) can be avoided.Therefore, when the digital input signal is switched, the gate-drain voltage difference of the first N-type field-effect transistor pair (N-type field-effect transistor A210 and N-type field-effect transistor B220) gradually increases and tends to stabilize. At the same time, the voltage of the common source of the first N-type field-effect transistor pair (N-type field-effect transistor A210 and N-type field-effect transistor B220) is clamped at the intermediate reference voltage 294. When the digital input signal switching is completed, a voltage domain switching is performed. The voltage of the gates (gate 212 of N-type field-effect transistor A210 and gate 222 of N-type field-effect transistor B220) of the first N-type field-effect transistor pair (N-type field-effect transistor A210 and N-type field-effect transistor B220) is switched from the voltage domain associated with the P-type reference voltage 290 to the voltage domain of the first power supply 209. The voltage provided by the first power supply 209 for driving the field-effect transistors is equal to the sum of the P-type reference voltage 290 and the intermediate reference voltage 294. Thus, when the digital input signal completes the switching, the voltage of the gates (gate 212 of N-type MOSFET A210 and gate 222 of N-type MOSFET B220) of the first N-type MOSFET pair (N-type MOSFET A210 and N-type MOSFET B220) is raised to the voltage of the first power supply 209 through voltage domain switching. This combines the voltage of the common source (source 214 of N-type MOSFET A210 and source 224 of N-type MOSFET B220) of the first N-type MOSFET pair (N-type MOSFET A210 and N-type MOSFET B220) with the voltage of the intermediate reference voltage 294, naturally making the gate-source voltage difference of the first N-type MOSFET pair (N-type MOSFET A210 and N-type MOSFET B220) the P-type reference voltage 290.

[0031] Continue reading Figure 2 The differential-to-analog converter further includes a gate voltage control circuit 202. The gate voltage control circuit 202 includes multiple level shifting circuits, and each of the multiple level shifting circuits corresponds to the first N-type field-effect transistor pair included in each of the multiple tri-state switching units. Figure 2 The example shows the gates of N-type field-effect transistors A210 and B220 in a three-state switching unit. Figure 2 The example illustrates a one-to-one correspondence between the gate 212 of N-type field-effect transistor A210 and the gate 222 of N-type field-effect transistor B220 in a tri-state switching unit. The high power input of each of the plurality of level-shifting circuits selects the output of the P-type reference voltage 290 or the first power supply 209 based on a gate voltage control signal, and the gate voltage control signal is determined based on changes in the digital input signal. The outputs of each of the plurality of level-shifting circuits are respectively used to drive the corresponding pair of first N-type field-effect transistors (B220) in the corresponding tri-state switching unit of the plurality of tri-state switching units. Figure 2 The example shows the corresponding gates (A210 and B220) of an N-type field-effect transistor in a three-state switching unit. Figure 2 The example illustrates the gate 212 of N-type field-effect transistor A210 and the gate 222 of N-type field-effect transistor B220 in a tri-state switching unit. Thus, by utilizing the gate voltage control circuit 202, the switching timing optimized for the intermediate reference voltage 294 is implemented. By combining the changes in the digital input signal to operate the switching of the voltage domain, the risk of NMOS transistor overvoltage failure can be avoided.

[0032] Figure 3 This is a timing diagram illustrating the change in gate voltage of the first N-type field-effect transistor pair in a three-state switching unit according to an embodiment of this application, relative to a digital input signal. (See also...) Figure 1 and Figure 2 The tri-state switching unit includes a PMOS with its source connected to a first reference voltage VREFP, an NMOS with its source connected to a second reference voltage VREFN, and an NMOS with its source connected to a third reference voltage VCM. The gate of the PMOS located at the P-terminus of the tri-state switching array, with its source connected to the first reference voltage VREFP, receives the first set of digital input signals Dpp. <L+2 M -1:0> Control, the gate of the NMOS located at the P terminal, whose source is connected to the second reference voltage VREFN, receives the second set of digital input signals Dnp. <L+2 M -1:0> Control, the gate of the NMOS located at the P terminal, whose source is connected to the third reference voltage VCM, receives the third set of digital input signals Dcp. <L+2 M -1:0> Control. Conversely, in the three-state switch array, the gate of the PMOS located at the N-terminal, whose source is connected to the first reference voltage VREFP, receives the fourth set of digital input signals Dpn. <L+2 M -1:0> Control, the gate of the NMOS located at the N terminal with its source connected to the second reference voltage VREFN receives the fifth set of digital input signals Dnn. <L+2 M -1:0> Control, the gate of the NMOS located at the N terminal with its source connected to the third reference voltage VCM receives the sixth group of digital input signals Dcn. <L+2 M -1:0> Control. The drains of the three MOSFETs in the three-state switching unit are connected to each other to form a common connection point, which serves as the output of the three-state switching unit and is connected to the input terminal in the resistor array. It can be seen that... Figure 3 The example illustrates how a gate voltage control circuit optimizes the switching timing for an intermediate reference voltage. By combining changes in the digital input signal to control the switching of the voltage domain, the risk of NMOS transistor overvoltage failure can be avoided. Specifically, Figure 3The example illustrates a switching method for a differential-to-analog converter corresponding to the third reference voltage VCM, i.e., the intermediate reference voltage, which is the gate voltage control algorithm of the NMOS corresponding to VCM. It can be seen that the first set of digital input signals Dpp... <L+2 M -1:0>, the second group of digital input signals Dnp <L+2 M -1:0>, the third group of digital input signals Dcp <L+2 M -1:0>, the fourth group of digital input signals Dpn <L+2 M -1:0>, the fifth group of digital input signals Dnn <L+2 M -1:0>, the sixth group of digital input signals Dcn <L+2 M When the -1:0> change occurs, the gate voltage control signal (VDD_SEL) is low; the first group of digital input signals Dpp <L+2 M -1:0>, the second group of digital input signals Dnp <L+2 M -1:0>, the third group of digital input signals Dcp <L+2 M -1:0>, the fourth group of digital input signals Dpn <L+2 M -1:0>, the fifth group of digital input signals Dnn <L+2 M -1:0>, the sixth group of digital input signals Dcn <L+2 M After the -1:0> change stabilizes, the gate voltage control signal (VDD_SEL) goes high. Thus, the gate voltage control signal (VDD_SEL) is determined based on the change in the digital input signal. In the first group of digital input signals Dpp... <L+2 M When the value changes (e.g., during the transition between Dpp_data0 and Dpp_data1), the gate voltage control signal (VDD_SEL) is set low. This allows the P-type reference voltage to be selected based on the gate voltage control signal, ensuring that the gate voltage of the first N-type MOSFET pair is located in the voltage domain associated with the P-type reference voltage when the digital input signal is switched. Conversely, in the first set of digital input signals Dpp... <L+2 MWhen the signal is stable, such as during the duration of Dpp_data2 and Dpp_datan, the gate voltage control signal (VDD_SEL) is set to high. This allows the output of the first power supply to be selected based on the gate voltage control signal. Thus, when the digital input signal switching is complete, the gate voltage of the first N-type MOSFET pair switches from the voltage domain associated with the P-type reference voltage to the voltage domain of the first power supply. In this way, by introducing the first power supply as an external power source to generate a stable intermediate reference voltage, voltage clamping can be achieved at the intermediate reference voltage. Combined with the voltage domain switching operation, this not only avoids the phenomenon of transient voltage overshoot and breakdown that may occur during digital input signal switching, but also naturally allows the voltage of the common source to be clamped at the intermediate reference voltage when the digital input signal is stable. Therefore, it overcomes the problem of switch on-resistance and resistor array mismatch that may occur due to process deviations, operating voltage, and operating temperature under non-ideal conditions, and significantly reduces the static power consumption of the external power supply, thereby reducing switch size and switching area overhead. Furthermore, because the switch's turn-on voltage is not altered, but rather specifically optimized for selecting an intermediate reference voltage, no additional capacitors or clock are required, thus avoiding additional dynamic circuitry and interference. In some embodiments, the common-source of the first N-type MOSFET can be clamped at the intermediate reference voltage using the first power supply. However, considering the influence of various non-ideal conditions, an additional voltage source can be used to stabilize the common-source of the first N-type MOSFET at the desired intermediate reference voltage. Moreover, this additional voltage source only serves as a voltage regulator, therefore requiring minimal drive capability and resulting in lower circuit overhead.

[0033] See Figure 1 , Figure 2 and Figure 3 In one possible implementation, the intermediate reference voltage is the sum of a first ratio of the P-type reference voltage and a second ratio of the N-type reference voltage, where the sum of the first and second ratios is 1. Thus, by combining the specific structure of the N-bit resistor array, macroscopic adjustment accuracy can be provided through the selection of the reference voltage, while microscopic adjustment accuracy can be provided through the voltage division effect of the resistor array, thereby better meeting the adjustment requirements of the digital-to-analog converter.

[0034] In some embodiments, the first ratio is 50% and the second ratio is 50%. Thus, by setting the intermediate reference voltage to be the midpoint between the P-type and N-type reference voltages, the common-source connection naturally clamps the voltage of the common source to the designed intermediate reference voltage, which means that the static power consumption of the external power supply is minimized and the circuit area is optimized.

[0035] In some embodiments, the drains of the first N-type field-effect transistor pair are used to provide the input voltages of the corresponding input terminals of the P-terminal N-bit resistor array and the N-terminal N-bit resistor array, respectively. The common source of the first N-type field-effect transistor pair is the switching short-circuit point of the corresponding input terminals of the P-terminal N-bit resistor array and the N-terminal N-bit resistor array. Thus, by introducing a first power supply as an external power supply to generate a stable intermediate reference voltage, the voltage can be clamped at the intermediate reference voltage. Combined with voltage domain switching operations, this not only avoids the phenomenon of transient voltage overshoot and breakdown that may occur during digital input signal switching, but also naturally allows the voltage of the common source to be clamped at the intermediate reference voltage when the digital input signal is stable. Therefore, it overcomes the problem of switch on-resistance and resistor array mismatch that may occur due to process deviations, operating voltage, and operating temperature under non-ideal conditions, and significantly reduces the static power consumption of the external power supply, thereby reducing switch size and switching area overhead. Furthermore, because the switch's on-state voltage was not altered, but rather specifically optimized for selecting an intermediate reference voltage, no additional capacitors or clock are needed, thus avoiding additional dynamic circuitry and interference. By setting the intermediate reference voltage to the midpoint between the P-type and N-type reference voltages, the voltage generated in an ideal short circuit would be the midpoint between these two voltages—the intermediate reference voltage. This means that by setting the intermediate reference voltage to the midpoint between the P-type and N-type reference voltages, the common-source connection naturally clamps the common-source voltage to the designed intermediate reference voltage. This results in the lowest possible static power consumption from the external power supply and optimized circuit area.

[0036] In some embodiments, when the corresponding input terminal of the P-terminal N-bit resistor array and the corresponding input terminal of the N-terminal N-bit resistor array are shorted by a switch, the intermediate reference voltage is generated on the common source of the first N-type field-effect transistor pair. Thus, ideally, if a short circuit occurs, the generated voltage is the midpoint between the P-type and N-type reference voltages, i.e., the intermediate reference voltage. This means that by setting the intermediate reference voltage to the midpoint between the P-type and N-type reference voltages, the voltage at the common source is naturally clamped to the designed intermediate reference voltage using the common source connection. This implies that the static power consumption of the external power supply is minimized and the circuit area is optimized. Considering non-ideal situations, a first power supply is introduced as an external power supply to generate a stable intermediate reference voltage, and voltage clamping at the intermediate reference voltage can be achieved using the first power supply. Furthermore, in some embodiments, the first power supply can clamp the common source of the first N-type field-effect transistor to the intermediate reference voltage. However, considering the influence of various non-ideal situations, an additional voltage source can be used to support stabilizing the common source of the first N-type field-effect transistor at the desired intermediate reference voltage. Moreover, this additional voltage source only serves to regulate voltage, so it does not require high driving capability and has low circuit overhead.

[0037] In one possible implementation, each of the plurality of tri-state switching units includes a first N-type field-effect transistor pair connected to a common source, a P-type field-effect transistor pair connected to a common source, and a second N-type field-effect transistor pair connected to a common source. The voltage at the common source of the P-type field-effect transistor pair is clamped to the P-type reference voltage, and the voltage at the common source of the second N-type field-effect transistor pair is clamped to the N-type reference voltage. The drains of the first N-type field-effect transistor pair are respectively connected to the P-terminal common connection point and the N-terminal common connection point of the corresponding tri-state switching unit. The drains of the P-type field-effect transistor pair are respectively connected to the P-terminal common connection point and the N-terminal common connection point. The drains of the second N-type field-effect transistor pair are respectively connected to the P-terminal common connection point and the N-terminal common connection point. The P-terminal common connection point is used to provide the input voltage to the corresponding input terminal of the P-terminal N-bit resistor array, and the N-terminal common connection point is used to provide the input voltage to the corresponding input terminal of the N-terminal N-bit resistor array. Thus, three different MOSFET pairs are provided to select the corresponding reference voltage as the input to the resistor array. Furthermore, by utilizing three common-source MOSFET pairs and connecting the drains of the MOSFETs to a common connection point as the output of the tri-state switching unit, the voltage can be clamped to an intermediate reference voltage using the first power supply. Combined with voltage domain switching operation, this not only avoids the possibility of transient voltage overshoot and breakdown during digital input signal switching, but also naturally leverages the common-source voltage clamping characteristic when the digital input signal is stable. Therefore, it overcomes the on-resistance and resistor array mismatch problems that may occur under non-ideal conditions due to process variations, operating voltage, and operating temperature, and significantly reduces the static power consumption of the external power supply, thereby reducing switch size and area overhead. Additionally, because the switch-on voltage is not changed, but specifically optimized for selecting an intermediate reference voltage, no additional capacitors or clock are needed, thus avoiding additional dynamic circuitry and interference factors.

[0038] In some embodiments, the digital input signal includes a first pair of digital control codes for controlling the gate voltage of the first N-type field-effect transistor pair to select the intermediate reference voltage as the input voltage of the corresponding input terminals of the two sets of N-bit resistor arrays. The digital input signal also includes a second pair of digital control codes for controlling the gate voltage of the P-type field-effect transistor pair to select the P-type reference voltage as the input voltage of the corresponding input terminals of the two sets of N-bit resistor arrays. The digital input signal further includes a third pair of digital control codes for controlling the gate voltage of the second N-type field-effect transistor pair to select the N-type reference voltage as the input voltage of the corresponding input terminals of the two sets of N-bit resistor arrays. Thus, three different field-effect transistor pairs are provided for selecting the corresponding reference voltage as the input to the resistor array. Furthermore, by utilizing multiple sets of different digital control codes, the gate voltage of the corresponding field-effect transistor pairs can be controlled. Therefore, by selecting the reference voltage as the input voltage of the resistor array, the voltage division within the resistor array achieves the effect of finely controlling the analog voltage output.

[0039] In some embodiments, when any one of the first pair of digital control codes, the second pair of digital control codes, and the third pair of digital control codes undergoes code pattern switching, the voltage at the gate of the first N-type field-effect transistor pair is located in the voltage domain associated with the P-type reference voltage. When all the digital control codes in the first pair of digital control codes, the second pair of digital control codes, and the third pair of digital control codes complete code pattern switching, the voltage at the gate of the first N-type field-effect transistor pair switches from the voltage domain associated with the P-type reference voltage to the voltage domain of the first power supply. When the digital input signal is switched, this means that the input digital control code may change, for example, from "1100" to "0111". Therefore, the change in the code bit of the corresponding digital control code faced by each tri-state switch unit of the tri-state switch array is unpredictable; it may remain at the original control level, switch from high level to low level, or switch from low level to high level. This means that when the digital input signal changes, for example, during switching, the voltage at the drain of the first N-type field-effect transistor pair is in a relatively unstable state. Therefore, during the switching of the digital input signal, the gate voltage of the first N-type field-effect transistor pair is located in the voltage domain associated with the P-type reference voltage. During the switching of the digital input signal, the voltage difference between the gate and drain of the first N-type field-effect transistor pair gradually increases and stabilizes, while the common-source voltage of the first N-type field-effect transistor pair is clamped at the intermediate reference voltage. When the switching of the digital input signal is complete, a voltage domain switch occurs, and the gate voltage of the first N-type field-effect transistor pair switches from the voltage domain associated with the P-type reference voltage to the voltage domain of the first power supply. The voltage provided by the first power supply to drive the field-effect transistors is equal to the sum of the P-type reference voltage and the intermediate reference voltage (e.g., 2.7 volts). Thus, when the digital input signal completes the switching, the voltage of the gate of the first N-type field-effect transistor pair is raised to the voltage of the first power supply (2.7 volts) through voltage domain switching. This, combined with the fact that the voltage of the common source of the first N-type field-effect transistor pair is clamped at the intermediate reference voltage (0.9 volts), naturally makes the voltage difference between the gate and common source of the first N-type field-effect transistor pair equal to the P-type reference voltage (1.8 volts). Thus, by introducing the first power supply as an external power supply to generate a stable intermediate reference voltage, voltage clamping at the intermediate reference voltage can be achieved. Combined with the voltage domain switching operation, this not only avoids the phenomenon of transient voltage overshoot and breakdown that may occur during digital input signal switching, but also naturally works with the characteristic of the common source voltage being clamped at the intermediate reference voltage when the digital input signal is stable. Therefore, it overcomes the problems of switch on-resistance and resistor array mismatch that may occur under non-ideal conditions due to process deviations, operating voltage, and operating temperature, and significantly reduces the static power consumption of the external power supply, thereby reducing the switch size and switching area overhead.In addition, because the switch's turn-on voltage was not changed, but rather a specially optimized design was made for the case of selecting an intermediate reference voltage, no additional capacitors and clocks are needed, thus avoiding additional dynamic circuits and additional interference factors.

[0040] In some embodiments, the differential-to-analog converter further includes a gate voltage control circuit, which comprises multiple level shifting circuits. Each level shifting circuit corresponds one-to-one with the gate of the first N-type field-effect transistor pair included in each of the multiple tri-state switching units. The high power input of each level shifting circuit selects either the P-type reference voltage or the output of the first power supply based on a gate voltage control signal. Furthermore, the gate voltage control signal is determined based on changes in the digital input signal. The outputs of each level shifting circuit are used to drive the corresponding gates of the corresponding first N-type field-effect transistor pairs in the corresponding tri-state switching units. Thus, by utilizing the gate voltage control circuit, a switching timing optimized for an intermediate reference voltage is achieved. By combining changes in the digital input signal to operate the voltage domain switching, the risk of NMOS transistor overvoltage failure can be avoided.

[0041] In some embodiments, when the gate voltage control signal is low, the transmission gate pairs associated with the plurality of level-shifting circuits are connected to the high power supply inputs of each of the plurality of level-shifting circuits and then to the P-type reference voltage. When the gate voltage control signal is high, the transmission gate pairs associated with the plurality of level-shifting circuits are connected to the high power supply inputs of each of the plurality of level-shifting circuits and then to the output of the first power supply. Furthermore, the outputs of each of the plurality of level-shifting circuits are determined based on the first pair of digital control codes. Thus, by utilizing the gate voltage control circuit and the level-shifting circuit, a switching timing optimized for the intermediate reference voltage is achieved. By combining changes in the digital input signal to operate the voltage domain switching, the risk of NMOS transistor overvoltage failure can be avoided.

[0042] In one possible implementation, the P-terminal N-bit resistor array includes an L-bit binary R-2R resistor array, an M-bit thermometer code resistor array, and a bridging resistor, where N = L + M, and L and M are both positive integers greater than 0. The output terminals of the L-bit binary R-2R resistor array and the M-bit thermometer code resistor array are connected through the bridging resistor. The L-bit binary R-2R resistor array constitutes the low-order segment of the P-terminal N-bit resistor array and includes L+1 resistor pairs. Among the L+1 resistor pairs, the 2nd to L+1th resistor pairs are arranged from the second furthest to the closest to the bridging resistor as the lowest to the highest order of resistance. The first resistor pair among the L+1 resistor pairs is the furthest from the bridging resistor and is a dummy resistor pair. The M-bit thermometer code resistor array constitutes the high-order segment of the P-terminal N-bit resistor array and includes 2 M -1 thermometer-coded resistor pair, the output terminal of the M-bit thermometer-coded resistor array serves as the output terminal of the P-terminal N-bit resistor array, and the tri-state switch array includes L+2 M Each three-state switch unit is used to connect the input terminals of the L+1 resistor pairs and the 2... M -1 thermometer-coded resistor pair input terminal, the digital input signal including L+2 M This involves an N-bit digital control code. By combining this with the specific structure of an N-bit resistor array, macroscopic adjustment accuracy can be provided through the selection of a reference voltage, while microscopic adjustment accuracy can be provided through the voltage division effect of the resistor array, thus better meeting the adjustment requirements of digital-to-analog converters (DACs). Utilizing the segmented structure of an L-bit binary R-2R resistor array and an M-bit thermometer-code resistor array helps reduce the requirements of high-precision DACs on unit resistance matching, switch matching, and layout matching.

[0043] In one possible implementation, the N-terminal N-bit resistor array includes an L-bit binary R-2R resistor array, an M-bit thermometer code resistor array, and a bridging resistor, where N = L + M, and L and M are both positive integers greater than 0. The output terminals of the L-bit binary R-2R resistor array and the M-bit thermometer code resistor array are connected through the bridging resistor. The L-bit binary R-2R resistor array constitutes the low-order segment of the N-terminal N-bit resistor array and includes L+1 resistor pairs. Among the L+1 resistor pairs, the 2nd to L+1th resistor pairs are arranged from the second farthest to the closest to the bridging resistor as the lowest to the highest order of resistance. The first resistor pair among the L+1 resistor pairs is the farthest from the bridging resistor and is a virtual resistor pair. The M-bit thermometer code resistor array constitutes the high-order segment of the N-terminal N-bit resistor array and includes 2 M-1 thermometer-coded resistor pair, the output terminal of the M-bit thermometer-coded resistor array serves as the output terminal of the N-bit resistor array, and the tri-state switch array includes L+2 M Each three-state switch unit is used to connect the input terminals of the L+1 resistor pairs and the 2... M -1 thermometer-coded resistor pair input terminal, the digital input signal including L+2 M This involves an N-bit digital control code. By combining this with the specific structure of an N-bit resistor array, macroscopic adjustment accuracy can be provided through the selection of a reference voltage, while microscopic adjustment accuracy can be provided through the voltage division effect of the resistor array, thus better meeting the adjustment requirements of digital-to-analog converters (DACs). Utilizing the segmented structure of an L-bit binary R-2R resistor array and an M-bit thermometer-code resistor array helps reduce the requirements of high-precision DACs on unit resistance matching, switch matching, and layout matching.

[0044] In one possible implementation, the differential analog-to-digital converter is a three-level resistive high-precision digital-to-analog converter. This provides a three-level segmented structure with three different reference voltages, reduces switching area overhead, improves on-resistance matching, avoids the introduction of additional dynamic circuitry, helps reduce static power consumption, and is beneficial for static circuit applications and applications related to high-precision resistive digital-to-analog converters.

[0045] Figure 4 This is a schematic diagram of an N-bit resistor array on the P-side of a differential fractional-to-analog converter provided in an embodiment of this application. Figure 4 As shown, the P-terminal N-bit resistor array B410 includes an L-bit binary R-2R resistor array A450, an M-bit thermometer code resistor array A454, and a bridging resistor A452. Here, N = L + M, where L and M are both positive integers greater than 0. The output terminals of the L-bit binary R-2R resistor array A450 and the M-bit thermometer code resistor array A454 are connected via the bridging resistor A452. The L-bit binary R-2R resistor array A450 constitutes the low-order segment of the P-terminal N-bit resistor array B410 and includes L+1 resistor pairs. Among the L+1 resistor pairs, the 2nd to L+1th resistor pairs are arranged from the second furthest to the closest to the bridging resistor A452, representing the least significant to the most significant resistor pair. The first resistor pair among the L+1 resistor pairs, being the furthest from the bridging resistor A452, is a dummy resistor pair. The M-bit thermometer-type resistor array A454 constitutes the high-bit segment of the P-terminal N-bit resistor array B410 and includes 2 M-1 thermometer-coded resistor pair. The output terminal of the M-bit thermometer-coded resistor array A454 serves as the output terminal 456 of the P-terminal N-bit resistor array B410. Furthermore, the tri-state switch array includes L+2... M Each three-state switch unit is used to connect the input terminals of the L+1 resistor pairs and the 2... M -1 thermometer-coded resistor pair input terminal, the digital input signal including L+2 M This involves an N-bit digital control code. By combining this with the specific structure of an N-bit resistor array, macroscopic adjustment accuracy can be provided through the selection of a reference voltage, while microscopic adjustment accuracy can be provided through the voltage division effect of the resistor array, thus better meeting the adjustment requirements of digital-to-analog converters (DACs). Utilizing the segmented structure of an L-bit binary R-2R resistor array and an M-bit thermometer-code resistor array helps reduce the requirements of high-precision DACs on unit resistance matching, switch matching, and layout matching.

[0046] Figure 5 This is a schematic diagram of an N-terminal N-bit resistor array for a differential fractional-to-analog converter provided in an embodiment of this application. Figure 5 As shown, the N-terminal N-bit resistor array B520 includes an L-bit binary R-2R resistor array B550, an M-bit thermometer code resistor array B554, and a bridging resistor B552. Where N = L + M, and L and M are both positive integers greater than 0. The output of the L-bit binary R-2R resistor array B550 is connected to the output of the M-bit thermometer code resistor array B554 via the bridging resistor B552. The L-bit binary R-2R resistor array B550 constitutes the low-order segment of the N-terminal N-bit resistor array B520 and includes L+1 resistor pairs. Among the L+1 resistor pairs, the 2nd to L+1th resistor pairs are arranged from the second furthest to the closest to the bridging resistor B552, representing the least significant to the most significant resistor pair. The first resistor pair among the L+1 resistor pairs, being the furthest from the bridging resistor B552, is a dummy resistor pair. The M-bit thermometer-type resistor array B554 constitutes the high-bit segment of the N-terminal N-bit resistor array B520 and includes 2 M -1 thermometer-coded resistor pair. The output terminal of the M-bit thermometer-coded resistor array B554 serves as the output terminal 556 of the N-bit resistor array B520. Furthermore, the tri-state switch array includes L+2... M Each three-state switch unit is used to connect the input terminals of the L+1 resistor pairs and the 2... M -1 thermometer-coded resistor pair input terminal, the digital input signal including L+2 MThis involves an N-bit digital control code. By combining this with the specific structure of an N-bit resistor array, macroscopic adjustment accuracy can be provided through the selection of a reference voltage, while microscopic adjustment accuracy can be provided through the voltage division effect of the resistor array, thus better meeting the adjustment requirements of digital-to-analog converters (DACs). Utilizing the segmented structure of an L-bit binary R-2R resistor array and an M-bit thermometer-code resistor array helps reduce the requirements of high-precision DACs on unit resistance matching, switch matching, and layout matching.

[0047] The methods and devices provided in this application are based on the same inventive concept. Since the principles by which the methods and devices solve problems are similar, the embodiments, implementation methods, examples, or methods of implementation of the methods and devices can be referred to each other, and repeated details will not be repeated. This application also provides a system comprising multiple computing devices, the structure of each computing device of which can refer to the structure of the computing devices described above. The functions or operations achievable by this system can refer to the specific implementation steps in the above method embodiments and / or the specific functions described in the above device embodiments, and will not be repeated here.

[0048] This application also provides a computer-readable storage medium storing computer instructions. When these computer instructions are executed on a computer device (such as one or more processors), they can implement the method steps described in the above method embodiments. The specific implementation of the above method steps by the processor of the computer-readable storage medium can refer to the specific operations described in the above method embodiments and / or the specific functions described in the above device embodiments, and will not be repeated here.

[0049] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. This application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Embodiments of this application can be implemented wholly or partially by software, hardware, firmware, or any other combination. When implemented in software, the above embodiments can be implemented wholly or partially as a computer program product. This application can take the form of a computer program product embodied on one or more computer-usable storage media containing computer-usable program code. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. Computer-readable storage media can be any available medium that a computer can access, or a data storage device such as a server or data center that contains one or more sets of available media. Available media can be magnetic media (such as floppy disks, hard disks, and magnetic tapes), optical media, or semiconductor media. Semiconductor media can be solid-state drives, random access memory, flash memory, read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, or any other suitable form of storage medium.

[0050] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. Each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1One or more processes and / or boxes Figure 1 The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0051] In the above embodiments, the descriptions of each embodiment have their own emphasis. Parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of the embodiments of this application. The steps in the methods of the embodiments of this application can be adjusted in order, combined, or deleted according to actual needs; the modules in the systems of the embodiments of this application can be divided, combined, or deleted according to actual needs. If these modifications and variations of the embodiments of this application fall within the scope of the claims of this application and their equivalents, then this application also intends to include these modifications and variations.

Claims

1. A differential fractional-to-analog converter, characterized in that, The differential fractional-to-analog converter includes: Two sets of N-bit resistor arrays with the same resistor array structure, where N is a positive integer greater than 1, the two sets of N-bit resistor arrays are a P-terminal N-bit resistor array and an N-terminal N-bit resistor array, the output terminal of the P-terminal N-bit resistor array is the P-terminal output terminal of the differential fractional-to-analog converter, and the output terminal of the N-terminal N-bit resistor array is the N-terminal output terminal of the differential fractional-to-analog converter. A three-state switch array is used to select a P-type reference voltage, an N-type reference voltage, or an intermediate reference voltage as the input voltage for the two sets of N-bit resistor arrays based on a digital input signal. The P-type reference voltage is higher than the N-type reference voltage, and the intermediate reference voltage is between the P-type and N-type reference voltages. The P-terminal N-bit resistor array and the N-terminal N-bit resistor array each include multiple input terminals. The tri-state switch array includes multiple tri-state switch units corresponding one-to-one with the multiple input terminals. Each of the multiple tri-state switch units includes a first N-type field-effect transistor pair connected to a common source. The drain of the first N-type field-effect transistor pair serves as the output of the corresponding tri-state switch unit when the intermediate reference voltage is selected. When the digital input signal is switched, the voltage of the gate of the first N-type field-effect transistor pair is located in the voltage domain associated with the P-type reference voltage. When the digital input signal is switched, the voltage of the gate of the first N-type field-effect transistor pair switches from the voltage domain associated with the P-type reference voltage to the voltage domain of the first power supply. The first power supply is used to provide a voltage equal to the sum of the P-type reference voltage and the intermediate reference voltage to clamp the voltage of the common source of the first N-type field-effect transistor pair to the intermediate reference voltage.

2. The differential-to-analog converter according to claim 1, characterized in that, The intermediate reference voltage is the sum of a first ratio of the P-type reference voltage and a second ratio of the N-type reference voltage, wherein the sum of the first ratio and the second ratio is 1.

3. The differential-to-analog converter according to claim 2, characterized in that, The first ratio is 50%, and the second ratio is 50%.

4. The differential-to-analog converter according to claim 3, characterized in that, The drain of the first N-type field-effect transistor pair is used to provide the input voltage of the corresponding input terminal of the P-terminal N-bit resistor array and the input voltage of the corresponding input terminal of the N-terminal N-bit resistor array, respectively. The common source of the first N-type field-effect transistor pair is the switching short-circuit point of the corresponding input terminal of the P-terminal N-bit resistor array and the corresponding input terminal of the N-terminal N-bit resistor array.

5. The differential-to-analog converter according to claim 4, characterized in that, When the corresponding input terminal of the P-terminal N-bit resistor array and the corresponding input terminal of the N-terminal N-bit resistor array are shorted by a switch, the intermediate reference voltage is generated on the common source of the first N-type field-effect transistor pair.

6. The differential-to-analog converter according to claim 1, characterized in that, Each of the plurality of tri-state switching units includes a first N-type field-effect transistor pair connected to a common source, a P-type field-effect transistor pair connected to a common source, and a second N-type field-effect transistor pair connected to a common source. The voltage at the common source of the P-type field-effect transistor pair is clamped to the P-type reference voltage, and the voltage at the common source of the second N-type field-effect transistor pair is clamped to the N-type reference voltage. The drains of the first N-type field-effect transistor pair are respectively connected to the P-terminal common connection point and the N-terminal common connection point of the corresponding tri-state switching unit. The drains of the P-type field-effect transistor pair are respectively connected to the P-terminal common connection point and the N-terminal common connection point. The drains of the second N-type field-effect transistor pair are respectively connected to the P-terminal common connection point and the N-terminal common connection point. The P-terminal common connection point is used to provide the input voltage to the corresponding input terminal of the P-terminal N-bit resistor array, and the N-terminal common connection point is used to provide the input voltage to the corresponding input terminal of the N-terminal N-bit resistor array.

7. The differential-to-analog converter according to claim 6, characterized in that, The digital input signal includes a first pair of digital control codes for controlling the gate voltage of the first N-type field-effect transistor pair to select the intermediate reference voltage as the input voltage of the corresponding input terminals of the two sets of N-bit resistor arrays. The digital input signal also includes a second pair of digital control codes for controlling the gate voltage of the P-type field-effect transistor pair to select the P-type reference voltage as the input voltage of the corresponding input terminals of the two sets of N-bit resistor arrays. The digital input signal also includes a third pair of digital control codes for controlling the gate voltage of the second N-type field-effect transistor pair to select the N-type reference voltage as the input voltage of the corresponding input terminals of the two sets of N-bit resistor arrays.

8. The differential-to-analog converter according to claim 7, characterized in that, When any one of the first pair of digital control codes, the second pair of digital control codes, and the third pair of digital control codes performs a code pattern switch, the voltage of the gate of the first N-type field-effect transistor pair is located in the voltage domain associated with the P-type reference voltage. When all the digital control codes in the first pair of digital control codes, the second pair of digital control codes, and the third pair of digital control codes complete the code pattern switch, the voltage of the gate of the first N-type field-effect transistor pair switches from the voltage domain associated with the P-type reference voltage to the voltage domain of the first power supply.

9. The differential-to-analog converter according to claim 8, characterized in that, The differential-to-analog converter further includes a gate voltage control circuit, which includes multiple level shifting circuits. Each level shifting circuit corresponds one-to-one with the gate of the first N-type field-effect transistor pair included in each of the multiple tri-state switching units. The high power input of each of the multiple level shifting circuits selects the output of the P-type reference voltage or the first power supply based on the gate voltage control signal. The gate voltage control signal is determined based on the change of the digital input signal. The outputs of each of the multiple level shifting circuits are used to drive the corresponding gate of the corresponding first N-type field-effect transistor pair of the corresponding tri-state switching unit in the multiple tri-state switching units.

10. The differential-to-analog converter according to claim 9, characterized in that, When the gate voltage control signal is low, the transmission gate pairs associated with the plurality of level shifting circuits are connected to the high power supply inputs of the respective plurality of level shifting circuits and to the P-type reference voltage. When the gate voltage control signal is high, the transmission gate pairs associated with the plurality of level shifting circuits are connected to the high power supply inputs of the respective plurality of level shifting circuits and to the output of the first power supply. Furthermore, the outputs of the respective plurality of level shifting circuits are determined based on the first pair of digital control codes.

11. The differential-to-analog converter according to claim 1, characterized in that, The P-terminal N-bit resistor array includes an L-bit binary R-2R resistor array, an M-bit thermometer code resistor array, and a bridging resistor, where N = L + M, and L and M are both positive integers greater than 0. The output terminals of the L-bit binary R-2R resistor array and the M-bit thermometer code resistor array are connected through the bridging resistor. The L-bit binary R-2R resistor array constitutes the low-order segment of the P-terminal N-bit resistor array and includes L+1 resistor pairs. Among the L+1 resistor pairs, the 2nd to L+1th resistor pairs are arranged from the second farthest to the closest to the bridging resistor as the lowest to the highest order of resistance. The first resistor pair among the L+1 resistor pairs is the farthest from the bridging resistor and is a virtual resistor pair. The M-bit thermometer code resistor array constitutes the high-order segment of the P-terminal N-bit resistor array and includes 2 M -1 thermometer-coded resistor pair, the output terminal of the M-bit thermometer-coded resistor array serves as the output terminal of the P-terminal N-bit resistor array, and the tri-state switch array includes L+2 M Each three-state switch unit is used to connect the input terminals of the L+1 resistor pairs and the 2... M -1 thermometer-coded resistor pair input terminal, the digital input signal including L+2 M A 2-bit digital control code.

12. The differential-to-analog converter according to claim 1, characterized in that, The N-terminal N-bit resistor array includes an L-bit binary R-2R resistor array, an M-bit thermometer code resistor array, and a bridging resistor, where N = L + M, and L and M are both positive integers greater than 0. The output terminals of the L-bit binary R-2R resistor array and the M-bit thermometer code resistor array are connected through the bridging resistor. The L-bit binary R-2R resistor array constitutes the low-order segment of the N-terminal N-bit resistor array and includes L+1 resistor pairs. Among the L+1 resistor pairs, the 2nd to L+1th resistor pairs are arranged from the second farthest to the closest to the bridging resistor as the lowest to the highest order of resistance. The first resistor pair among the L+1 resistor pairs is the farthest from the bridging resistor and is a virtual resistor pair. The M-bit thermometer code resistor array constitutes the high-order segment of the N-terminal N-bit resistor array and includes 2 M -1 thermometer-coded resistor pair, the output terminal of the M-bit thermometer-coded resistor array serves as the output terminal of the N-bit resistor array, and the tri-state switch array includes L+2 M Each three-state switch unit is used to connect the input terminals of the L+1 resistor pairs and the 2... M -1 thermometer-coded resistor pair input terminal, the digital input signal including L+2 M A 2-bit digital control code.

13. The differential-to-analog converter according to claim 1, characterized in that, The differential analog-to-digital converter is a three-level resistive high-precision digital-to-analog converter.

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