High-voltage Resurf LDMOS device structure resistant to single-particle burnout

Abstract

The invention provides a high-voltage Resurf LDMOS (Laterally Diffused Metal Oxide Semiconductor) device structure capable of resisting a single-particle burning effect. The device comprises a P-type substrate, an N-type epitaxy, a P-type buried layer, a P-type well region, a source region P + injection, an N-type well region, a source region N + injection, a drain region N + injection, a gate oxide layer, a field oxide layer, polycrystalline silicon and metal. According to the invention, the unequal-length P-type buried layer is introduced into the N-type drift region, and the P-type buried layer is directly connected with the P-type substrate, so that an extra leakage path is provided for hole current generated by single-particle radiation. A long P-type buried layer is introduced below an N-type drift region to improve the extraction capability of hole current, a short P-type buried layer is introduced above the N-type drift region to relieve the electric field concentration phenomenon of a drain side N + region, and the unequal-length P-type buried layers act together to inhibit the parasitic triode self-maintenance phenomenon caused by single-particle incidence and improve the single-particle burnout resistance of the device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power devices, specifically relating to a high-voltage LDMOS device structure resistant to single-event burn-out. Background Art

[0002] With the development of my country's aerospace industry, high-voltage integrated circuits are widely used in aerospace electronic systems. The space environment contains high-energy particles that can cause radiation damage to devices, leading to the failure of aerospace equipment. One of the most common radiation effects is the single-event effect. Laterally diffused metal-oxide-semiconductor (LDMOS) devices are core components of high-voltage integrated circuits. LDMOS devices operate at high voltages and have large internal electric fields, making them susceptible to severe single-event burn-out effects. Therefore, it is necessary to research high-voltage LDMOS devices resistant to single-event burn-out.

[0003] To address the single-event burn-out problem in high-voltage LDMOS devices, suppress the activation of parasitic transistors, and reduce the electric field modulation effect of missed detection, this invention proposes a high-voltage resurf method resistant to single-event burn-out. LDMOS Device Structure. To address the single-event burn-out problem in high-voltage LDMOS devices and suppress the activation of parasitic transistors, this invention proposes a high-voltage LDMOS device structure resistant to single-event burn-out. In the space environment, high-energy particles will enter the LDMOS device, generating a large number of electron-hole pairs along the incident path through energy deposition. Under the influence of an electric field, electrons and holes move towards the drain and source, respectively, forming a transient current. Some holes flow into the P-well (the base region of the parasitic transistor) and then out from the body electrode P+. The hole current generates a voltage drop in the base region, causing the P-well / N+ junction (base / emitter junction) to be forward biased, and the parasitic transistor to turn on. Electrons from the source N+ enter the drift region through the P-well, causing the device to experience the Kirk effect. The electric field peak is concentrated at the drain, strongly ionizing more electron-hole pairs. Holes move towards the source under the influence of the electric field, providing a stable positive feedback current to the base region, ultimately leading to device burn-out. This invention employs a non-uniform P-type buried layer within the drift region. On one hand, it reduces the hole current flowing through the P-type well region (parasitic transistor base region), suppressing the turn-on of the parasitic transistor. On the other hand, the shorter P-type buried layer modulates the leakage electric field, suppressing the phenomenon of leakage electric field concentration, preventing the formation of positive feedback, and effectively improving the single-event burn-out resistance of high-voltage LDMOS devices. Summary of the Invention

[0004] To achieve the above-mentioned objectives, the technical solution of this invention is as follows:

[0005] A high-voltage Resurf LDMOS device structure resistant to single-particle burn-out is defined as follows: the x-direction is the direction from the source electrode 10 to the drain electrode 12, the y-direction is the direction from the source electrode 10 to the first conductivity type substrate 1, and the z-direction is perpendicular to the x and y directions.

[0006] The AA' section is defined as a section parallel to the xy plane that points from the source electrode 10 to the drain electrode 12 and passes through the polysilicon gate electrode 11. The BB' section is defined as a section parallel to the xz plane that points from the first conductivity type well region 2 to the second conductivity type drift region 3 and passes through the first conductivity type short buried layer region 14 and the second conductivity type well region 4. The CC' section is defined as a section parallel to the xz plane that points from the first conductivity type well region 2 to the second conductivity type drift region 3 and passes through the first conductivity type long buried layer region 15.

[0007] In the AA' cross section, there are a first conductivity type substrate 1 located at the bottom layer, a first conductivity type well region 2 located at the upper left of the first conductivity type substrate 1, a second conductivity type drift region 3 located at the upper right of the first conductivity type substrate 1, a first conductivity type long buried layer region 15 located at the lower left of the second conductivity type drift region 3, a first conductivity type short buried layer region 14 located at the upper left of the second conductivity type drift region 3, a second conductivity type well region 4 located at the upper right of the second conductivity type drift region 3, a first conductivity type body region 5 located at the upper left of the first conductivity type well region 2, a second conductivity type source region 6 located inside the first conductivity type well region 2, a second conductivity type drain region 8 located inside the second conductivity type well region 4, a field oxide layer 7 located above the second conductivity type drift region 3, a gate oxide layer 9 located above the first conductivity type well region 2, a source electrode 10 located above the first conductivity type body region 5 and the second conductivity type source region 6, a polysilicon gate electrode 11 located above the gate oxide layer 9, a drain electrode 12 located above the second conductivity type drain region 8, and a substrate electrode 13 located below the first conductivity type substrate 1.

[0008] In a preferred embodiment, on the BB' section, the first conductivity type substrate 1 and the first conductivity type well region 2 located below the device surround the second conductivity type drift region 3 in the z direction, and are connected to a potential equal to that of the source electrode 10 through the substrate electrode 13.

[0009] As a preferred embodiment, the first conductivity type short buried layer region 14 and the first conductivity type long buried layer region 15 located inside the second conductivity type drift region 3 of the device penetrate the second conductivity type drift region 3 in the z direction and are directly connected to the first conductivity type substrate 1, providing an additional leakage path for ionized hole current extraction.

[0010] As a preferred embodiment, in the AA' cross-section, the first conductivity type long buried layer region 15 located to the lower left of the second conductivity type drift region 3 of the device has its left boundary close to the first conductivity type well region 2 and its right boundary close to the second conductivity type well region 4, thereby improving the ability to extract hole current.

[0011] As a preferred embodiment, in the AA' cross section, the first conductivity type short buried layer region 14 located to the upper left of the second conductivity type drift region 3 of the device has its left boundary close to the first conductivity type well region 2, and its right boundary far from the second conductivity type well region 4 and not exceeding the right boundary of the first conductivity type long buried layer region 15. This prevents the introduction of electric field peaks in the second conductivity type well region 4, suppresses the electric field modulation phenomenon caused by electron concentration, and reduces the electric field of the second conductivity type drain region 8.

[0012] As a preferred embodiment, in the AA' section, a secondary first conductive type buried layer region 16 and a secondary first conductive type long buried layer region 17 are provided between the first conductive type short buried layer region 14 and the first conductive type long buried layer region 15 within the second conductive type drift region 3; the secondary first conductive type buried layer region 16 and the secondary first conductive type long buried layer region 17 penetrate the second conductive type drift region 3 in the z direction, and the lengths of the first conductive type short buried layer region 14, the first conductive type long buried layer region 15, the secondary first conductive type buried layer region 16, and the secondary first conductive type long buried layer region 17 increase sequentially.

[0013] As a preferred embodiment, when the first conductivity type doped impurity is acceptor type and the second conductivity type doped impurity is donor type, the drain electrode is biased to a positive potential relative to the source electrode; when the first conductivity type doped impurity is donor type and the second conductivity type doped impurity is acceptor type, the drain electrode is biased to a negative potential relative to the source electrode.

[0014] The beneficial effects of this invention are as follows: This invention provides a high-voltage Resurf LDMOS device structure resistant to single-event burnout. A non-uniform length first conductivity type buried layer region is introduced into the second conductivity type drift region 3, providing an additional leakage path for ionized hole current extraction. The long first conductivity type buried layer region 15 improves the hole current extraction capability, while the short first conductivity type buried layer region avoids introducing electric field peaks into the second conductivity type well region 4, suppressing electric field modulation phenomena caused by electron concentration, preventing positive feedback, avoiding device burnout caused by single-event effects, and improving the device's resistance to single-event burnout. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of a conventional high-voltage LDMOS structure.

[0016] Figure 2 This is a three-dimensional structural diagram of the high-voltage Resurf LDMOS device according to Embodiment 1 of the present invention.

[0017] Figure 3 This is a cross-sectional view of the high-voltage Resurf LDMOS device in Embodiment 1 of the present invention.

[0018] Figure 4 This is a BB' cross-sectional view of the high-voltage Resurf LDMOS device in Embodiment 1 of the present invention.

[0019] Figure 5 This is a CC' cross-sectional view of the high-voltage Resurf LDMOS device of Embodiment 1 of the present invention.

[0020] Figure 6 This is a three-dimensional structural diagram of the high-voltage Resurf LDMOS device according to Embodiment 2 of the present invention.

[0021] Figure 7 This is a front view of the high-voltage Resurf LDMOS device according to Embodiment 2 of the present invention along the DD' structure. DD' is defined as a cross-section parallel to the xy plane that runs from the source electrode 10 to the drain electrode 12 and passes through the polysilicon gate electrode 11.

[0022] 1 is a substrate of the first conductivity type, 2 is a well region of the first conductivity type, 3 is a drift region of the second conductivity type, 4 is a well region of the second conductivity type, 5 is a body region of the first conductivity type, 6 is a source region of the second conductivity type, 7 is a field oxide layer, 8 is a drain region of the second conductivity type, 9 is a gate oxide layer, 10 is a source electrode, 11 is a polysilicon gate electrode, 12 is a drain electrode, 13 is a substrate electrode, 14 is a short buried layer region of the first conductivity type, 15 is a long buried layer region of the first conductivity type, 16 is a secondary buried layer region of the first conductivity type, and 17 is a secondary buried layer region of the first conductivity type. Detailed Implementation

[0023] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0024] Figure 1This is a schematic diagram of a conventional high-voltage LDMOS structure. High-energy particles are incident into the LDMOS device, where energy deposition generates a large number of electron-hole pairs along the incident path. Under the influence of an electric field, electrons and holes move towards the drain and source, respectively, forming a transient current. Some holes flow into the P-well (the base region of the parasitic transistor) and then out from the body electrode P+. The hole current generates a voltage drop in the base region, causing the P-well / N+ junction (base / emitter junction) to be forward biased, and the parasitic transistor to turn on. Electrons from the source N+ pass through the P-well into the drift region, causing the device to experience the Kirk effect. The electric field peak is concentrated at the drain, strongly ionizing the drain and generating more electron-hole pairs. Holes move towards the source under the influence of the electric field, providing a stable positive feedback current to the base region, ultimately leading to device burnout.

[0025] To prevent the parasitic transistor from turning on, this invention introduces non-uniformly long short and long buried layers of the first conductivity type in the second conductivity type drift region 3, as shown in the device structure. Figure 2 As shown, the first conductivity type short buried layer region 14 and the first conductivity type long buried layer region 15 provide additional hole current discharge paths. The first conductivity type long buried layer region 15 has a longer length, with its left boundary close to the first conductivity type well region 2 and its right boundary close to the second conductivity type well region 4, improving the hole current extraction capability. The first conductivity type short buried layer region 14 has a shorter length, with its left boundary close to the first conductivity type well region 2 and its right boundary far from the second conductivity type well region 4, not exceeding the right boundary of the first conductivity type long buried layer region 15, preventing the introduction of electric field peaks in the second conductivity type well region 4, suppressing the electric field modulation phenomenon caused by electron concentration, reducing the electric field of the second conductivity type drain region 8, preventing the formation of positive feedback, avoiding device burn-out caused by single-event effects, and improving the device's resistance to single-event burn-out. Figure 3 As shown. The first conductivity type short buried layer region 14 and the first conductivity type long buried layer region 15 of this invention penetrate the second conductivity type drift region in the main viewing direction of the device and are directly connected to the first conductivity type substrate 1, as shown. Figure 4 , Figure 5 As shown. Alternatively, a stepped first conductivity type buried layer distribution can be used, such as... Figure 6 As shown, all of these can effectively improve the device's resistance to single-event burn-out. Also, as a preferred embodiment, the stepped distribution of the first conductivity type short buried layer region 14, the first conductivity type long buried layer region 15, the secondary first conductivity type buried layer region 16, and the secondary first conductivity type long buried layer region 17 in the second conductivity type drift region 3 of the high-voltage Resurf LDMOS device of the present invention all have different lengths. The left boundary is close to the first conductivity type well region 2, and the right boundary gradually approaches the second conductivity type well region 4 from top to bottom, as shown... Figure 7 As shown, such structures can effectively improve the device's resistance to single-event burn-out.

[0026] Example 1

[0027] like Figure 2 As shown, this embodiment provides a high-voltage Resurf LDMOS device structure resistant to single-event burn-out.

[0028] The x-direction is defined as the direction from the source electrode 10 to the drain electrode 12, the y-direction is defined as the direction from the source electrode 10 to the first conductivity type substrate 1, and the z-direction is perpendicular to x and y.

[0029] The AA' section is defined as a section parallel to the xy plane that points from the source electrode 10 to the drain electrode 12 and passes through the polysilicon gate electrode 11. The BB' section is defined as a section parallel to the xz plane that points from the first conductivity type well region 2 to the second conductivity type drift region 3 and passes through the first conductivity type short buried layer region 14 and the second conductivity type well region 4. The CC' section is defined as a section parallel to the xz plane that points from the first conductivity type well region 2 to the second conductivity type drift region 3 and passes through the first conductivity type long buried layer region 15.

[0030] In the AA' cross section, there are a first conductivity type substrate 1 located at the bottom layer, a first conductivity type well region 2 located at the upper left of the first conductivity type substrate 1, a second conductivity type drift region 3 located at the upper right of the first conductivity type substrate 1, a first conductivity type long buried layer region 15 located at the lower left of the second conductivity type drift region 3, a first conductivity type short buried layer region 14 located at the upper left of the second conductivity type drift region 3, a second conductivity type well region 4 located at the upper right of the second conductivity type drift region 3, a first conductivity type body region 5 located at the upper left of the first conductivity type well region 2, a second conductivity type source region 6 located inside the first conductivity type well region 2, a second conductivity type drain region 8 located inside the second conductivity type well region 4, a field oxide layer 7 located above the second conductivity type drift region 3, a gate oxide layer 9 located above the first conductivity type well region 2, a source electrode 10 located above the first conductivity type body region 5 and the second conductivity type source region 6, a polysilicon gate electrode 11 located above the gate oxide layer 9, a drain electrode 12 located above the second conductivity type drain region 8, and a substrate electrode 13 located below the first conductivity type substrate 1.

[0031] like Figure 4 As shown, in the BB' section, the first conductivity type substrate 1 and the first conductivity type well region 2 located below the device surround the second conductivity type drift region 3 in the z direction, and are connected to a potential equal to that of the source electrode 10 through the substrate electrode 13.

[0032] like Figure 5 As shown, the first conductivity type short buried layer region 14 and the first conductivity type long buried layer region 15, located inside the second conductivity type drift region 3 of the device, penetrate the second conductivity type drift region 3 in the z direction and are directly connected to the first conductivity type substrate 1, providing an additional leakage path for ionized hole current extraction.

[0033] like Figure 3 As shown, the first conductivity type short buried layer region 14 and the first conductivity type long buried layer region 15 in the second conductivity type drift region 3 have different lengths. In the AA' cross-section, the first conductivity type long buried layer region 15 located in the lower left of the second conductivity type drift region 3 has its left boundary close to the first conductivity type well region 2 and its right boundary close to the second conductivity type well region 4, which improves the ability to extract hole current. In the AA' cross-section, the first conductivity type short buried layer region 14 located in the upper left of the second conductivity type drift region 3 has its left boundary close to the first conductivity type well region 2 and its right boundary far from the second conductivity type well region 4 and not exceeding the right boundary of the first conductivity type long buried layer region 15, which prevents the introduction of electric field peaks in the second conductivity type well region 4, suppresses the electric field modulation phenomenon caused by electron concentration, and reduces the electric field of the second conductivity type drain region 8.

[0034] When the first conductivity type doped impurity is acceptor type and the second conductivity type doped impurity is donor type, the drain electrode is biased to a positive potential relative to the source electrode; when the first conductivity type doped impurity is donor type and the second conductivity type doped impurity is acceptor type, the drain electrode is biased to a negative potential relative to the source electrode.

[0035] Example 2

[0036] like Figure 6 As shown, the difference between this embodiment and Embodiment 1 is that, in the AA' cross-section, a secondary first-conductivity type buried layer region 16 and a secondary first-conductivity type long buried layer region 17 are provided between the first conductivity type short buried layer region 14 and the first conductivity type long buried layer region 15 within the second conductivity type drift region 3; the secondary first-conductivity type buried layer region 16 and the secondary first-conductivity type long buried layer region 17 penetrate the second conductivity type drift region 3 in the z direction, and the lengths of the first conductivity type short buried layer region 14, the first conductivity type long buried layer region 15, the secondary first conductivity type buried layer region 16, and the secondary first conductivity type long buried layer region 17 increase sequentially, with the buried layer regions distributed in a stepped manner, as shown... Figure 7 As shown.

[0037] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A high-voltage Resurf LDMOS device structure resistant to single-event burn-out, characterized in that: The x-direction is defined as the direction from the source electrode (10) to the drain electrode (12), the y-direction is the direction from the source electrode (10) to the first conductivity type substrate (1), and the z-direction is perpendicular to x and y. The AA' section is defined as a section parallel to the xy plane that points from the source electrode (10) to the drain electrode (12) and passes through the polysilicon gate electrode (11). The BB' section is defined as a section parallel to the xz plane that points from the first conductivity type well region (2) to the second conductivity type drift region (3) and passes through the first conductivity type short buried layer region (14) and the second conductivity type well region (4). The CC' section is defined as a section parallel to the xz plane that points from the first conductivity type well region (2) to the second conductivity type drift region (3) and passes through the first conductivity type long buried layer region (15). In the AA' cross section, there are a first conductivity type substrate (1) located at the bottom layer, a first conductivity type well region (2) located to the upper left of the first conductivity type substrate (1), a second conductivity type drift region (3) located to the upper right of the first conductivity type substrate (1), a first conductivity type long buried layer region (15) located to the lower left of the second conductivity type drift region (3), a first conductivity type short buried layer region (14) located to the upper left of the second conductivity type drift region (3), a second conductivity type well region (4) located to the upper right of the second conductivity type drift region (3), and a first conductivity type body region (5) located to the upper left of the first conductivity type well region (2). The second conductivity type source region (6) is located inside the first conductivity type well region (2), the second conductivity type drain region (8) is located inside the second conductivity type well region (4), the field oxide layer (7) is located above the second conductivity type drift region (3), the gate oxide layer (9) is located above the first conductivity type well region (2), the source electrode (10) is located above the first conductivity type body region (5) and the second conductivity type source region (6), the polysilicon gate electrode (11) is located above the gate oxide layer (9), the drain electrode (12) is located above the second conductivity type drain region (8), and the substrate electrode (13) is located below the first conductivity type substrate (1).

2. The high-voltage Resurf LDMOS device structure resistant to single-event burn-out according to claim 1, characterized in that: In the BB' section, the first conductivity type substrate (1) and the first conductivity type well region (2) located below the device surround the second conductivity type drift region (3) in the z direction and are connected to a potential equal to that of the source electrode (10) through the substrate electrode (13).

3. The high-voltage Resurf LDMOS device structure resistant to single-event burn-out according to claim 1, characterized in that: The first conductivity type short buried layer region (14) and the first conductivity type long buried layer region (15) located inside the second conductivity type drift region (3) of the device penetrate the second conductivity type drift region (3) in the z direction and are directly connected to the first conductivity type substrate (1), providing an additional leakage path for ionized hole current extraction.

4. The high-voltage Resurf LDMOS device structure resistant to single-event burn-out according to claim 1, characterized in that: On the AA' cross section, the first conductivity type long buried layer region (15) is located to the lower left of the second conductivity type drift region (3) of the device. Its left boundary is close to the first conductivity type well region (2), and its right boundary is close to the second conductivity type well region (4), which improves the ability to extract hole current.

5. The high-voltage Resurf LDMOS device structure resistant to single-event burn-out according to claim 1, characterized in that: On the AA' cross section, the first conductivity type short buried layer region (14) located to the left and above the second conductivity type drift region (3) of the device has a left boundary close to the first conductivity type well region (2) and a right boundary far from the second conductivity type well region (4) and not exceeding the right boundary of the first conductivity type long buried layer region (15). This prevents the introduction of electric field peaks in the second conductivity type well region (4), suppresses the electric field modulation phenomenon caused by electron concentration, and reduces the electric field of the second conductivity type drain region (8).

6. The high-voltage Resurf LDMOS device structure resistant to single-event burn-out according to claim 1, characterized in that: In the AA' section, a secondary first conductive type buried layer region (16) and a secondary first conductive type long buried layer region (17) are set between the first conductive type short buried layer region (14) and the first conductive type long buried layer region (15) in the second conductive type drift region (3); the secondary first conductive type buried layer region (16) and the secondary first conductive type long buried layer region (17) penetrate the second conductive type drift region (3) in the z direction, and the lengths of the first conductive type short buried layer region (14), the first conductive type long buried layer region (15), the secondary first conductive type buried layer region (16), and the secondary first conductive type long buried layer region (17) increase sequentially.

7. A high-voltage LDMOS device structure resistant to single-event burn-out according to any one of claims 1 to 6, characterized in that: When the first conductivity type doped impurity is acceptor type and the second conductivity type doped impurity is donor type, the drain electrode is biased to a positive potential relative to the source electrode; when the first conductivity type doped impurity is donor type and the second conductivity type doped impurity is acceptor type, the drain electrode is biased to a negative potential relative to the source electrode.

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