Double-pulse test method and test circuit

Abstract

The invention relates to a double-pulse test method and a test circuit. The method comprises the following steps: providing a double-pulse test circuit; the double-pulse test circuit comprises an energy charging circuit and a resonance circuit, the resonance circuit is a half-bridge LC resonance circuit or a full-bridge LC resonance circuit, and the energy charging circuit comprises a power supply and a bus capacitor; the bus capacitor is charged through the power supply; in response to charging the bus capacitor to the target voltage, disconnecting the power supply from the bus capacitor and the resonant circuit; and applying a control voltage to the control ends of the upper bridge and the lower bridge in the resonant circuit, obtaining a gate-source voltage, a drain-source voltage and a drain-source current of each switching tube in the resonant circuit under the control voltage, and obtaining a test result according to the gate-source voltage, the drain-source voltage and the drain-source current. According to the invention, the characteristics of the MOS tube in the LLC converter during actual work can be analyzed. Based on the test result obtained by the method, an important reference basis can be provided for model selection of the primary MOS transistor of the LLC converter, and poor products caused by design errors and improper model selection are avoided.

Description

Technical Field

[0001] This invention relates to the testing of the electrical performance of semiconductor devices, and in particular to a dual-pulse testing method and a dual-pulse testing circuit. Background Technology

[0002] LLC converters possess numerous advantages, including simple structure, fewer components, high power density, and high efficiency, and are currently widely used and researched in both engineering and academia. The dual-pulse test platform is an important tool for analyzing the performance of power devices. Through dual-pulse testing, the switching and commutation process of power devices in actual topologies can be quickly simulated, facilitating the analysis of the switching and reverse recovery characteristics of power devices. This provides guidance for power device selection and drive circuit design in converters. Furthermore, the dual-pulse test platform can also test the ultimate capabilities of power devices, facilitating the analysis of failure mechanisms in actual topologies.

[0003] A traditional dual-pulse test circuit consists of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and a diode. It can be used to simulate the hard-switching commutation process between the MOSFET and the diode, and to test and analyze the switching and reverse recovery characteristics of power devices during this process. However, this dual-pulse test circuit cannot simulate the commutation process of soft-switching circuits such as LLC converters. Summary of the Invention

[0004] Therefore, it is necessary to provide a double-pulse test method and test circuit that can simulate the characteristics of a MOSFET when it is actually working in an LLC converter.

[0005] A dual-pulse testing method includes: Step A, providing a dual-pulse testing circuit; the dual-pulse testing circuit includes a charging circuit and a resonant circuit, the resonant circuit being a half-bridge LC resonant circuit or a full-bridge LC resonant circuit, the charging circuit including a power supply and a bus capacitor; Step B, charging the bus capacitor through the power supply; Step C, in response to the bus capacitor being charged to a target voltage, disconnecting the power supply from the bus capacitor and the resonant circuit; Step D, applying control voltages to the control terminals of the upper and lower bridges in the resonant circuit, and obtaining the gate-source voltage, drain-source voltage, and drain-source current of each switch in the resonant circuit under the control voltage; Step E, obtaining the test result based on the gate-source voltage, drain-source voltage, and drain-source current.

[0006] The aforementioned dual-pulse test method can analyze the characteristics of MOSFETs during actual operation in LLC converters. The test results obtained using this method can provide important reference for the selection of primary-side MOSFETs in LLC converters, avoiding product defects caused by design errors and improper selection.

[0007] In one embodiment, step D, applying the control voltage, includes simulating the ZVS commutation process of the LLC converter.

[0008] In one embodiment, step D includes performing a turn-on test of the upper bridge under zero-current turn-on conditions at time t0; step E includes performing turn-on process and loss test analysis of the upper bridge under zero-current turn-on conditions at time t0; step D includes performing a turn-off test of the upper bridge at time t1; step E includes performing a turn-off process and loss test analysis of the upper bridge at time t1; step D includes performing a turn-on test of the lower bridge under ZVS soft-turn-on conditions at time t2; step E includes performing a turn-off test of the lower bridge under ZVS soft-turn-on conditions at time t2; step D includes performing a turn-off test of the lower bridge at time t4; step E includes performing a turn-off process and loss test analysis of the lower bridge at time t4; step D includes performing a turn-on test of the upper bridge under ZVS soft-turn-on conditions at time t5; step E includes performing a turn-on process test analysis of the upper bridge under ZVS soft-turn-on conditions at time t5.

[0009] In one embodiment, during the time period t0 to t1, the upper bridge is turned on and the lower bridge is turned off; during the time period t1 to t2, both the upper and lower bridges are turned off; during the time period t2 to t4, the upper bridge is turned off and the lower bridge is turned on; and during the time period t4 to t5, both the upper and lower bridges are turned off.

[0010] In one embodiment, the time periods t1 to t2 and t4 to t5 are dead time periods, and step E further includes determining whether the dead time setting corresponding to the control voltage is reasonable.

[0011] In one embodiment, the switching transistor is a MOSFET, and step D, applying the control voltage, includes simulating the body diode hard recovery condition of the MOSFET during the startup process of the LLC converter.

[0012] In one embodiment, at times t0 to t1, the upper bridge is turned on and the lower bridge is turned off; at times t1 to t2, both the upper and lower bridges are turned off; at times t2 to t3, the upper bridge is turned off and the lower bridge is turned on; at times t3 to t4, both the upper and lower bridges are turned off; at times t4 to t5, the upper bridge is turned on and the lower bridge is turned off; step E includes testing the reverse recovery capability and reverse recovery limit operating capability of the body diode of the MOSFET during the startup process of the LLC converter at time t4.

[0013] In one embodiment, step D, applying the control voltage, includes simulating the LLC converter operating in the capacitive operating region.

[0014] In one embodiment, during the time period t0 to t1, the upper bridge is on and the lower bridge is off; during the time period t1 to t2, both the upper and lower bridges are off; during the time period t2 to t4, the upper bridge is off and the lower bridge is on; during the time period t4 to t5, the upper bridge is off and the lower bridge is on; during the time period t5 to t6, both the upper and lower bridges are off; and during the time period t6 to t7, the upper bridge is on and the lower bridge is off.

[0015] The switching transistor is a MOSFET, and step E includes testing the reverse recovery limit capability of the body diode when the LLC converter experiences a hard recovery condition of the body diode of the MOSFET in the capacitive operating region at time t6.

[0016] A dual-pulse test circuit includes: a charging circuit, including a power supply, a bus capacitor, and a first switch; a resonant circuit connected to the bus capacitor, wherein the resonant circuit is a half-bridge LC resonant circuit or a full-bridge LC resonant circuit, and the first switch is used to control whether the power supply is connected to the bus capacitor and the resonant circuit; and a driving circuit, used to provide control voltage to the control terminals of the upper and lower bridges in the resonant circuit.

[0017] The aforementioned dual-pulse test circuit can analyze the characteristics of MOSFETs during actual operation in LLC converters. The test results obtained using this method can provide important reference for the selection of primary-side MOSFETs in LLC converters, avoiding product defects caused by design errors and improper selection.

[0018] In one embodiment, the resonant circuit is a half-bridge LC resonant circuit, including a half-bridge circuit and an LC series resonant circuit. The first end of the half-bridge circuit is connected to the first end of the bus capacitor, and the second end of the half-bridge circuit is connected to the second end of the bus capacitor. One end of the LC series resonant circuit is connected to the second end of the half-bridge circuit, and the other end of the LC series resonant circuit is connected to the common terminal of the upper and lower bridges of the half-bridge circuit. The LC series resonant circuit includes a resonant inductor and a resonant capacitor connected in series.

[0019] In one embodiment, the resonant circuit is a full-bridge LC resonant circuit, comprising a full-bridge circuit and an LC series resonant circuit. The first terminal of the full-bridge circuit is connected to the first terminal of the bus capacitor, and the second terminal of the full-bridge circuit is connected to the second terminal of the bus capacitor. One terminal of the LC series resonant circuit is connected to the common terminal of one upper and lower bridge of the full-bridge circuit, and the other terminal of the LC series resonant circuit is connected to the common terminal of the other upper and lower bridge of the full-bridge circuit. The LC series resonant circuit includes a resonant inductor and a resonant capacitor connected in series.

[0020] In one embodiment, the dual-pulse test circuit further includes a discharge branch connected in parallel with the bus capacitor, the discharge branch including a second switch and a discharge resistor.

[0021] Based on all the above embodiments, this application provides a dual-pulse test method and test circuit. Compared with the traditional dual-pulse test platform, it can simulate the soft-switching ZVS commutation process of LLC converter, the hard-switching commutation process during startup, and the commutation process in the capacitive operating region, and can more realistically test the actual working characteristics of MOSFETs in soft-switching topologies such as LLC. Attached Figure Description

[0022] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.

[0023] Figure 1 This is a flowchart of a dual-pulse testing method in one embodiment of this application;

[0024] Figure 2a This is a circuit schematic diagram of a dual-pulse test circuit according to one embodiment of this application. Figure 2b This is a circuit schematic diagram of a dual-pulse test circuit in another embodiment of this application;

[0025] Figure 3a This is the control voltage waveform of the upper and lower bridges before and after disconnecting the first switch SW1 in step S140 of one embodiment of the half-bridge type of this application. Figure 3b This is the control voltage waveform of the upper and lower bridges before and after disconnecting the first switch SW1 in step S140 of the full-bridge type of this application;

[0026] Figure 4a These are the relevant waveforms of the half-bridge double-pulse test circuit in Embodiment 1 of this application. Figure 4b These are the relevant waveforms of the full-bridge dual-pulse test circuit in Embodiment 1 of this application;

[0027] Figure 5a These are the relevant waveforms of the half-bridge double-pulse test circuit in Embodiment 2 of this application. Figure 5b These are the relevant waveforms of the full-bridge dual-pulse test circuit in Embodiment 2 of this application;

[0028] Figure 6a This is the equivalent circuit of the half-bridge double-pulse test circuit in the first working mode of this application. Figure 6b This is the equivalent circuit of the full-bridge double-pulse test circuit in the first working mode of this application;

[0029] Figure 7aThis is the equivalent circuit of the half-bridge double-pulse test circuit in the second working mode of this application. Figure 7b This is the equivalent circuit of the full-bridge double-pulse test circuit in the second working mode of this application;

[0030] Figure 8a This is the equivalent circuit of the three-mode half-bridge double-pulse test circuit in this application. Figure 8b This is the equivalent circuit of the full-bridge double-pulse test circuit in the three working modes of this application;

[0031] Figure 9a This is the equivalent circuit of the four-time half-bridge double-pulse test circuit in this application. Figure 9b This is the equivalent circuit of the full-bridge dual-pulse test circuit in the four working modes of this application;

[0032] Figure 10a This is the equivalent circuit of the half-bridge double-pulse test circuit in the five working modes of this application. Figure 10b This is the equivalent circuit of the full-bridge double-pulse test circuit in the fifth working mode of this application;

[0033] Figure 11a This is the equivalent circuit of the half-bridge double-pulse test circuit in the sixth operating mode of this application. Figure 11b This is the equivalent circuit of the full-bridge double-pulse test circuit in operating mode six of this application;

[0034] Figure 12a This is the equivalent circuit of the half-bridge double-pulse test circuit in the seventh operating mode of this application. Figure 12b This is the equivalent circuit of the full-bridge double-pulse test circuit in operating mode seven of this application;

[0035] Figure 13a These are the relevant waveforms of the half-bridge double-pulse test circuit in Embodiment 3 of this application. Figure 13b These are the relevant waveforms of the full-bridge double-pulse test circuit in Embodiment 3 of this application. Detailed Implementation

[0036] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0038] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0039] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0040] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0041] As described in the background section, a traditional dual-pulse test circuit consisting of a MOSFET and a diode cannot simulate the switching process of resonant topologies such as LLC converters. Therefore, it cannot accurately reflect the switching characteristics of the MOSFET during ZVS (zero-voltage switching) soft-switching commutation and capacitive operating region commutation. When the LLC converter experiences a hard recovery condition due to imperfect control logic, the body diode of the primary-side MOSFET will exhibit a strong reverse recovery phenomenon. If its performance is poor, it can easily lead to MOSFET failure, becoming a significant potential factor causing overall system failure. Furthermore, the traditional dual-pulse test circuit cannot accurately reflect the MOSFET's performance under this actual operating condition.

[0042] Therefore, this application proposes a dual-pulse test method and test procedure, which can simulate the ZVS soft-switching commutation process of LLC converter, and can conveniently test and analyze the switching characteristics of MOSFETs during the process. It can also simulate the commutation process of LLC converter when it is operating in the capacitive region and the hard recovery commutation process during startup, and test and analyze the switching characteristics and limiting capabilities of MOSFETs during the process.

[0043] Figure 1 This is a flowchart of a double-pulse testing method in one embodiment of this application, including the following steps:

[0044] S110 provides a dual-pulse test circuit.

[0045] In one embodiment of this application, the dual-pulse test circuit is a resonant dual-pulse test circuit, including a charging circuit and a resonant circuit. The charging circuit includes a power supply and a bus capacitor. The resonant circuit can be a half-bridge LC resonant circuit or a full-bridge LC resonant circuit.

[0046] See Figure 2a In one embodiment of this application, the half-bridge LC resonant circuit includes a half-bridge circuit and an LC series resonant circuit. The LC series resonant circuit includes resonant inductors L connected in series. r and resonant capacitor C r The first terminal of the half-bridge circuit is connected to the bus capacitor C. busThe first terminal of the half-bridge circuit is connected to the bus capacitor C. bus The second end. One end of the LC series resonant circuit is connected to the second end of the half-bridge circuit, and the other end of the LC series resonant circuit is connected to the common terminal of the upper and lower bridges of the half-bridge circuit (i.e., the common terminal of the upper bridge Q1 and the lower bridge Q2).

[0047] See Figure 2b In one embodiment of this application, the full-bridge LC resonant circuit includes a full-bridge circuit and an LC series resonant circuit. The LC series resonant circuit includes resonant inductors L connected in series. r and resonant capacitor C r The first terminal of the full-bridge circuit is connected to the bus capacitor C. bus The first terminal of the full-bridge circuit is connected to the bus capacitor C. bus The second end. One end of the LC series resonant circuit is connected to the common terminal of one upper and lower bridge of the full bridge circuit (i.e., the common terminal of upper bridge Q1 and lower bridge Q2), and the other end of the LC series resonant circuit is connected to the common terminal of the other upper and lower bridge of the full bridge circuit (i.e., the common terminal of upper bridge Q3 and lower bridge Q4).

[0048] S120 charges the bus capacitor through the power supply of the dual-pulse test circuit.

[0049] In one embodiment of this application, the power source is an adjustable DC power supply (DC Source). The charging circuit includes a first switch SW1 connected in series with the DC Source, which controls whether the DC Source is connected to the bus capacitor C. bus It is connected to the resonant circuit. That is, when the first switch SW1 is closed, the DC Source supplies power to the bus capacitor C. bus Charging is performed. In one embodiment of this application, the output voltage of the DC Source is V. DD .

[0050] S130 charges the voltage across the bus capacitor to the target voltage.

[0051] After the first switch SW1 is closed, the DC Source begins to supply power to the bus capacitor C. bus Charge until the bus capacitor C is charged. bus The voltage across the terminals is charged to V. DD .

[0052] S140, disconnect the power supply from the bus capacitor and the resonant circuit.

[0053] Bus capacitor C bus The voltage across the terminals is charged to V. DD When the time comes, disconnect the first switch SW1.

[0054] S150: Obtain the gate-source voltage, drain-source voltage, and drain-source current of each MOSFET under the control waveform.

[0055] The driving circuit outputs control voltages to the control terminals (i.e., the gates of each MOSFET) of the upper and lower bridges in the resonant circuit, and acquires parameter information such as gate-source voltage, drain-source voltage, and drain-source current of each MOSFET under the control voltage waveform. To ensure that the half-bridge / full-bridge LC resonant circuit has an accurate zero initial state at the start of testing, Figure 2a In the illustrated embodiment, the gates of MOS transistors Q1 and Q2 are applied with the following... Figure 3a The control voltage waveform shown; Figure 2b In the illustrated embodiment, the gates of MOS transistors Q1, Q2, Q3, and Q4 are subjected to an application such as Figure 3b The control voltage waveform is shown.

[0056] S160 obtains the test results based on the gate-source voltage, drain-source voltage, and drain-source current.

[0057] The aforementioned dual-pulse test method can analyze the characteristics of MOSFETs during actual operation in LLC converters. The test results obtained using this method can provide important reference for the selection of primary-side MOSFETs in LLC converters, avoiding product defects caused by design errors and improper selection.

[0058] In one embodiment of this application, the dual-pulse test circuit further includes a bus capacitor C. bus The parallel discharge branch includes a second switch SW2 and a discharge resistor R2. After step S160, the process further includes closing the second switch SW2 to discharge the bus capacitor C through the discharge resistor R2. bus Resonant inductor L r and resonant capacitor C r The steps of energy on the surface.

[0059] In one embodiment of this application, step S150 includes: simulating the ZVS commutation process of the LLC converter.

[0060] Specifically, in one embodiment of this application, step S150 includes performing a turn-on test of the upper bridge under zero-current turn-on conditions at time t0, and step S160 includes performing turn-on process and loss test analysis of the upper bridge under zero-current turn-on conditions at time t0. Step S150 includes performing a turn-off test of the upper bridge at time t1, and step S160 includes performing a turn-off process and loss test analysis of the upper bridge at time t1. Step S150 includes performing a turn-on test of the lower bridge under ZVS soft-turn-on conditions at time t2, and step S160 includes performing a turn-on process test analysis of the lower bridge under ZVS soft-turn-on conditions at time t2. Step S150 includes performing a turn-off test of the lower bridge at time t4, and step S160 includes performing a turn-off process and loss test analysis of the lower bridge at time t4. Step S150 includes performing a turn-on test of the upper bridge under ZVS soft-turn-on conditions at time t5, and step S160 includes performing a turn-on process test analysis of the upper bridge under ZVS soft-turn-on conditions at time t5.

[0061] In one embodiment of this application, during the time period from t0 to t1, the upper bridge is on and the lower bridge is off; during the time period from t1 to t2, both the upper and lower bridges are off; during the time period from t2 to t4, the upper bridge is off and the lower bridge is on; and during the time period from t4 to t5, both the upper and lower bridges are off.

[0062] In one embodiment of this application, the time periods t1 to t2 and t4 to t5 are dead time periods. Step S160 further includes determining whether the dead time setting corresponding to the control voltage waveform is reasonable.

[0063] Example 1:

[0064] The following analysis uses a half-bridge LC resonant circuit as an example to illustrate the ZVS soft-switching commutation process of an LLC converter operating in the inductive region. The corresponding waveforms are shown below. Figure 4a As shown.

[0065] According to the test requirements, the current I of MOSFET Q2 during ZVS soft turn-on is determined by the following formula (1). Lr1 and its corresponding duty cycle time T on1 .

[0066] (1)

[0067] The current I of MOSFET Q1 during ZVS soft turn-on is determined by the following formula (2). Lr2 and its corresponding duty cycle time T on2 :

[0068] (2)

[0069] Dead Time T dead1 and T dead2It can be determined by the following formulas (3) and (4) respectively, or the larger value of the two can be selected uniformly.

[0070] (3)

[0071] (4)

[0072] Where C eq The equivalent junction capacitance of the MOSFET can be obtained from the datasheet of the MOSFET under test.

[0073] During the time interval t0~t1, MOSFET Q1 is turned on and MOSFET Q2 is turned off, C bus Starting with MOSFET Q1, the resonant inductor L is supplied... r and resonant capacitor C r Charging, resonant current i Lr The drain-source current i of MOSFET Q1 Q1 and the resonant voltage v Cr As the current gradually increases, the flow path is as follows: Figure 6a As shown. At point t0, the gate voltage v of MOSFET Q1 when it is turned on with zero current can be tested. GS Waveform, drain-source current i DS Waveform and its corresponding di / dt value, drain-source voltage v DS The waveform and its corresponding dv / dt value and zero-current turn-on loss, etc.

[0074] During the time interval t1~t2, MOSFET Q1 is turned off, MOSFET Q2 remains turned off, and the test circuit enters the dead time, with the resonant current i... Lr The junction capacitance C of MOSFET Q1 eq1 Charging affects the junction capacitance C of MOSFET Q2. eq2 Discharge occurs, and the current gradually commutates from the conductive channel of MOSFET Q1 to the body diode of MOSFET Q2. The current path is as follows: Figure 7a As shown. At point t1, i Lr and i Q1 Rise to I Lr1 v Cr Rise to V Cr1 At this point, the voltage of MOSFET Q1 when it is turned off can be tested. GS Waveform, i DS Waveform and its corresponding di / dt value, v DS The waveform and its corresponding dv / dt value and turn-off loss are obtained. By testing and analyzing the waveform during the time interval t1 to t2, the dead time T can also be determined. dead1 Is the choice reasonable?

[0075] During the time period t2~t3, MOSFET Q1 remains off, and MOSFET Q2 is on. Q2 By-I Lr1 Gradually rising (i Lr byI Lr1 (gradually decreasing), v Cr By V Cr1 Continue to rise, i Lr The MOSFET Q2 is turned on by both its body diode and the conductive channel. The current path is as follows: Figure 8a As shown. At point t2, the voltage of MOSFET Q2 during ZVS soft-start can be tested. GS Waveform, i DS Waveform and its corresponding di / dt value, v DS Waveform and its corresponding dv / dt value.

[0076] During the time period t3~t4, MOSFET Q1 remains off and MOSFET Q2 remains on. Lr The MOSFET Q2 changes from being jointly turned on by its body diode and conductive channel to being turned on by its conductive channel alone. At point t3, i Q2 Rise to 0 (i Lr (decreased to 0), v Cr Rise to V Cr2 Then it gradually decreases, and the current path is as follows: Figure 9a As shown.

[0077] During the time interval t4~t5, MOSFET Q1 remains off, MOSFET Q2 remains off, and the test circuit re-enters the dead time. Lr The junction capacitance C of MOSFET Q2 eq2 Charging affects the junction capacitance C of MOSFET Q1. eq1 Discharge occurs, and the current gradually commutates from the conductive channel of MOSFET Q2 to the body diode of MOSFET Q1. The current path is as follows: Figure 10a As shown. At point t4, i Q2 Rise to -I Lr2 (i Lr Drop to I Lr2 ), v Cr The value continues to decrease; at this point, Q2's value at shutdown can be tested. GS Waveform, i DS Waveform and its corresponding di / dt value, v DS The waveform and its corresponding dv / dt value and turn-off loss, etc., can be analyzed by testing the waveform in the time interval t4~t5, and the dead time T can also be determined. dead1 Is the choice reasonable?

[0078] During the time period t5~t6, MOSFET Q1 is turned on, while MOSFET Q2 remains off. Q1and i Lr byI Lr2 Gradually rising, v Cr Continue to decline, i Lr The MOSFET Q1 is turned on by both its body diode and the conductive channel. The current path is as follows: Figure 11a As shown. At point t5, the voltage of MOSFET Q1 during ZVS soft-start can be tested. GS waveform, i DS Waveform and its corresponding di / dt value, v DS The waveform and its corresponding dv / dt value.

[0079] The working mode and test waveforms for the time period t6~t7 are similar to those for the time period t0~t1, and will not be described again.

[0080] When the resonant circuit is a full-bridge LC resonant circuit, the double-pulse test method is similar to that for a half-bridge LC resonant circuit; see relevant waveforms. Figure 4b The corresponding equivalent circuit reference Figure 6b , Figure 7b , Figure 8b , Figure 9b , Figure 10b , Figure 11b .

[0081] In one embodiment of this application, step S150 includes: simulating the hard recovery condition of the body diode of the MOS transistor during the startup process of the LLC converter.

[0082] Specifically, in one embodiment of this application, during times t0 to t1, the upper bridge is on and the lower bridge is off; during times t1 to t2, both the upper and lower bridges are off; during times t2 to t3, the upper bridge is off and the lower bridge is on; during times t3 to t4, both the upper and lower bridges are off; and during times t4 to t5, the upper bridge is on and the lower bridge is off. Step S160 includes testing the reverse recovery capability and reverse recovery limit operating capability of the body diode of the LLC converter during startup at time t4.

[0083] Example 2:

[0084] The following analysis, using a half-bridge LC resonant circuit as an example, details the hard recovery commutation process of the MOSFET's body diode during the startup of an LLC converter. The corresponding waveforms are shown below. Figure 5a As shown.

[0085] Based on the test requirements, select the appropriate I according to equation (1). Lr1 and its corresponding duty cycle time T on1 The current I during hard recovery of the body diode of MOSFET Q2 under this operating condition is determined by the following formula (5). Lr2 and its corresponding duty cycle time Ton2 :

[0086] (5)

[0087] Dead Time T dead1 and T dead2 It can be determined by equations (3) and (4) respectively, or the larger of the two can be chosen, where C eq This information can be obtained from the datasheet of the MOSFET under test.

[0088] The working mode and waveform of the time period t0~t3 are exactly the same as those of the time period t0~t3 in Example 1, and will not be described again.

[0089] During the time interval t3~t4, MOSFET Q1 remains off, MOSFET Q2 is off, and the test circuit re-enters the dead time. At this time, i Lr The current will continue to freewheel in the body diode of MOSFET Q2, and the current flow path is as follows: Figure 7a As shown.

[0090] During the time interval t4~t5, MOSFET Q1 is turned on, while MOSFET Q2 remains off. Because at point t4, i... Lr The current still freewheels in the body diode of MOSFET Q2. The conduction of MOSFET Q1 causes a strong reverse recovery phenomenon in the body diode of MOSFET Q2, known as the hard recovery commutation process of the body diode. The current flow path is as follows: Figure 12a As shown. At this point, the reverse recovery capability of the body diode of MOSFET Q2 can be tested, including the reverse recovery peak current I. rrm The di / dt parameter can also be used to test the gate oscillation of MOSFET Q1 caused by the reverse recovery of the body diode of MOSFET Q2. GS i DS Current spikes, dv / dt, and di / dt. Furthermore, by adjusting I... Lr2 The size and turn-on speed of MOSFET Q1 can simulate reverse recovery under different operating conditions, and can also test the reverse recovery limit capability of the body diodes of MOSFET Q1 and MOSFET Q2 under this operating condition.

[0091] When the resonant circuit is a full-bridge LC resonant circuit, the double-pulse test method is similar to that for a half-bridge LC resonant circuit; see relevant waveforms. Figure 5b The corresponding equivalent circuit reference Figure 7b , Figure 12b .

[0092] In one embodiment of this application, step S150 of applying the control voltage includes: simulating the LLC converter operating under capacitive conditions.

[0093] In one embodiment of this application, during the time period t0 to t1, the upper bridge is on and the lower bridge is off; during the time period t1 to t2, both the upper and lower bridges are off; during the time period t2 to t4, the upper bridge is off and the lower bridge is on; during the time period t4 to t5, the upper bridge is off and the lower bridge is on; during the time period t5 to t6, both the upper and lower bridges are off; and during the time period t6 to t7, the upper bridge is on and the lower bridge is off.

[0094] Step S160 includes testing the reverse recovery limit capability of the body diode when the LLC converter experiences a hard recovery condition of the body diode of the MOSFET in the capacitive operating region at time t6.

[0095] Example 3:

[0096] The following analysis uses a half-bridge LC resonant circuit as an example to illustrate the commutation process of an LLC converter in the capacitive operating region. The corresponding waveforms are shown below. Figure 13a As shown.

[0097] Based on the test requirements, select the appropriate I according to equation (1). Lr1 and its corresponding duty cycle time T on1 The current I of the body diode of MOSFET Q2 during hard recovery under this operating condition is determined by the following formula (6). Lr2 and its corresponding duty cycle time T on2 :

[0098] (6)

[0099] Dead Time T dead1 and T dead2 It can be determined by equations (3) and (4) respectively, or the larger of the two can be chosen, where C eq This information can be obtained from the datasheet of the MOSFET under test.

[0100] The working mode and waveform of the time period t0~t4 are exactly the same as those of the time period t0~t4 in Example 1, and will not be described again.

[0101] During the time interval t4~t5, MOSFET Q1 remains off and MOSFET Q2 remains on. At point t4, i Lr At zero crossing, the circuit becomes conductive again, with the body diode and the conductive channel of MOSFET Q2 working together. The current flow path is as follows: Figure 8a As shown.

[0102] During the time interval t5~t6, MOSFET Q1 remains off, MOSFET Q2 remains off, and the test circuit re-enters the dead time. Lr The current continues to freewheel in the body diode of MOSFET Q2, and the current flow path is as follows: Figure 7a As shown.

[0103] During the time interval t6~t7, MOSFET Q1 is turned on, while MOSFET Q2 remains off. Because at point t6, i Lr The current still freewheels in the body diode of MOSFET Q2. When MOSFET Q1 is turned on, a strong reverse recovery phenomenon occurs in the body diode of MOSFET Q2, which is the so-called hard recovery commutation process in the capacitive operating region. The current flow path is as follows: Figure 12a As shown. At this point, the reverse recovery capability of the body diode of MOSFET Q2 can be tested, including the reverse recovery peak current I. rrm The di / dt parameter can also be used to test the gate oscillation of MOSFET Q1 caused by the reverse recovery of the body diode of MOSFET Q2. GS i DS Current spikes, dv / dt, and di / dt. Furthermore, by adjusting I... Lr2 The size and turn-on speed of MOSFET Q1 can simulate reverse recovery under different operating conditions, and can also test the reverse recovery limit capability of the body diodes of MOSFET Q1 and MOSFET Q2 under this operating condition.

[0104] When the resonant circuit is a full-bridge LC resonant circuit, the double-pulse test method is similar to that for a half-bridge LC resonant circuit; see relevant waveforms. Figure 13b The corresponding equivalent circuit reference Figure 7b , Figure 8b , Figure 12b . Figure 6a , Figure 6b , Figure 7a , Figure 7b , Figure 8a , Figure 8b , Figure 9a , Figure 9b , Figure 10a , Figure 10b , Figure 11a , Figure 11b , Figure 12a , Figure 12b , Figure 13a , Figure 13b The dashed part of the circuit indicates that the current does not flow through the dashed part in the equivalent circuit during the corresponding time period.

[0105] This application provides a dual-pulse test circuit, including:

[0106] The charging circuit includes a power supply, a bus capacitor, and a first switch;

[0107] The resonant circuit is connected to the bus capacitor. The resonant circuit is a half-bridge LC resonant circuit or a full-bridge LC resonant circuit. The first switch is used to control whether the power supply is connected to the bus capacitor and the resonant circuit.

[0108] The driving circuit is used to provide control voltage to the control terminals of the upper and lower bridges in the resonant circuit.

[0109] See Figure 2a In one embodiment of this application, the half-bridge LC resonant circuit includes a half-bridge circuit and an LC series resonant circuit. The LC series resonant circuit includes resonant inductors L connected in series. r and resonant capacitor C r The first terminal of the half-bridge circuit is connected to the bus capacitor C. bus The first terminal of the half-bridge circuit is connected to the bus capacitor C. bus The second end. One end of the LC series resonant circuit is connected to the second end of the half-bridge circuit, and the other end of the LC series resonant circuit is connected to the common terminal of the upper and lower bridges of the half-bridge circuit (i.e., the common terminal of the upper bridge Q1 and the lower bridge Q2).

[0110] exist Figure 2a In the illustrated embodiment, the dual-pulse test circuit further includes a connection to the bus capacitor C. bus The parallel discharge branch includes the second switch SW2 and the discharge resistor R2.

[0111] exist Figure 2a In the illustrated embodiment, the power supply is an adjustable DC power supply (DC Source). The charging circuit includes a first switch SW1 connected in series with the DC Source, which controls whether the DC Source is connected to the bus capacitor C. bus It is connected to the resonant circuit.

[0112] exist Figure 2a In the embodiment shown, the charging circuit also includes a current-limiting resistor R1 connected in series with the DC source.

[0113] See Figure 2b In one embodiment of this application, the full-bridge LC resonant circuit includes a full-bridge circuit and an LC series resonant circuit. The LC series resonant circuit includes resonant inductors L connected in series. r and resonant capacitor C r The first terminal of the full-bridge circuit is connected to the bus capacitor C. bus The first terminal of the full-bridge circuit is connected to the bus capacitor C. bus The second end. One end of the LC series resonant circuit is connected to the common terminal of one upper and lower bridge of the full bridge circuit (i.e., the common terminal of upper bridge Q1 and lower bridge Q2), and the other end of the LC series resonant circuit is connected to the common terminal of the other upper and lower bridge of the full bridge circuit (i.e., the common terminal of upper bridge Q3 and lower bridge Q4).

[0114] exist Figure 2b In the illustrated embodiment, the dual-pulse test circuit further includes a connection to the bus capacitor C. busThe parallel discharge branch includes the second switch SW2 and the discharge resistor R2.

[0115] exist Figure 2b In the illustrated embodiment, the power supply is an adjustable DC power supply (DC Source). The charging circuit includes a first switch SW1 connected in series with the DC Source, which controls whether the DC Source is connected to the bus capacitor C. bus It is connected to the resonant circuit.

[0116] exist Figure 2b In the embodiment shown, the charging circuit also includes a current-limiting resistor R1 connected in series with the DC source.

[0117] In one embodiment of this application, the first switch SW1 and the second switch SW2 are mechanical switches. In other embodiments of this application, the first switch SW1 and the second switch SW2 may also be replaced by MOSFETs, relays, circuit breakers, etc., connected back-to-back.

[0118] In one embodiment of this application, the resonant inductor L r It is an air-core inductor. In other embodiments of this application, the resonant inductor L r It can be replaced by other inductors with low permeability.

[0119] In one embodiment of this application, the resonant capacitor C r It is a metallized thin-film capacitor. In other embodiments of this application, the resonant capacitor C r It can be replaced by surface mount capacitors such as NP0 or C0G.

[0120] In one embodiment of this application, MOSFETs Q1, Q2, Q3, and Q4 can be replaced by power devices such as SiC MOSFETs or GaN HEMTs.

[0121] Based on all the above embodiments, this application provides a dual-pulse test method and test circuit. Compared with the traditional dual-pulse test platform, it can simulate the soft-switching ZVS commutation process of LLC converter, the hard-switching commutation process during startup, and the commutation process in the capacitive operating region, and can more realistically test the actual working characteristics of MOSFETs in soft-switching topologies such as LLC.

[0122] It should be understood that although the steps in the flowchart of this application are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart of this application may include multiple steps or multiple stages, which are not necessarily completed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps.

[0123] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0124] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0125] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A double-pulse testing method, comprising: Step A: Provide a dual-pulse test circuit; The dual-pulse test circuit includes a charging circuit and a resonant circuit. The resonant circuit is a half-bridge LC resonant circuit or a full-bridge LC resonant circuit. The charging circuit includes a power supply and a bus capacitor. Step B: Charge the bus capacitor using the power supply; Step C: In response to the bus capacitor being charged to the target voltage, disconnect the power supply from the bus capacitor and the resonant circuit; Step D: Apply control voltage to the control terminals of the upper bridge and the lower bridge in the resonant circuit, and obtain the gate-source voltage, drain-source voltage and drain-source current of each switch in the resonant circuit under the control voltage; Step E: Obtain the test results based on the gate-source voltage, drain-source voltage, and drain-source current.

2. The double-pulse testing method according to claim 1, characterized in that, The step of applying the control voltage in step D includes: simulating the ZVS commutation process of the LLC converter.

3. The double-pulse testing method according to claim 2, characterized in that, Step D includes performing a turn-on test of the upper bridge under zero-current turn-on conditions at time t0, and step E includes performing a turn-on process and loss test analysis of the upper bridge under zero-current turn-on conditions at time t0. Step D includes performing a shutdown test on the upper bridge at time t1, and step E includes performing a shutdown process and loss test analysis on the upper bridge at time t1. Step D includes performing an activation test of the lower bridge under ZVS soft-start conditions at time t2, and step E includes performing an activation process test analysis of the lower bridge under ZVS soft-start conditions at time t2. Step D includes performing a shutdown test on the lower bridge at time t4, and step E includes performing a shutdown process and loss test analysis on the lower bridge at time t4. Step D includes performing an activation test of the upper bridge under ZVS soft-start conditions at time t5, and step E includes performing an activation process test analysis of the upper bridge under ZVS soft-start conditions at time t5.

4. The double-pulse testing method according to claim 3, characterized in that, During the time period from t0 to t1, the upper bridge is turned on and the lower bridge is turned off. During the time period t1 to t2, the upper bridge and the lower bridge are turned off; during the time period t2 to t4, the upper bridge is turned off and the lower bridge is turned on; during the time period t4 to t5, the upper bridge and the lower bridge are turned off.

5. The double-pulse testing method according to claim 3 or 4, characterized in that, The time periods t1 to t2 and t4 to t5 are dead time. Step E also includes determining whether the dead time set for the control voltage is reasonable.

6. The double-pulse testing method according to claim 1, characterized in that, The switching transistor is a MOSFET, and step D, applying the control voltage, includes simulating the hard recovery condition of the body diode of the MOSFET during the startup process of the LLC converter.

7. The double-pulse testing method according to claim 6, characterized in that, At times t0 to t1, the upper bridge is turned on and the lower bridge is turned off. During the time period t1 to t2, the upper bridge and the lower bridge are turned off; during the time period t2 to t3, the upper bridge is turned off and the lower bridge is turned on; during the time period t3 to t4, the upper bridge and the lower bridge are turned off. During the time period from t4 to t5, the upper bridge is turned on and the lower bridge is turned off. Step E includes testing the reverse recovery capability and reverse recovery limit operating capability of the body diode of the MOSFET during the startup process of the LLC converter at time t4.

8. The double-pulse testing method according to claim 1, characterized in that, The step of applying the control voltage in step D includes: simulating the LLC converter under capacitive operating conditions.

9. The double-pulse testing method according to claim 8, characterized in that, During the time period from t0 to t1, the upper bridge is turned on and the lower bridge is turned off. During the period from t1 to t2, the upper bridge and the lower bridge are turned off; during the period from t2 to t4, the upper bridge is turned off and the lower bridge is turned on; during the period from t4 to t5, the upper bridge is turned off and the lower bridge is turned on; during the period from t5 to t6, the upper bridge and the lower bridge are turned off. During the time period from t6 to t7, the upper bridge is turned on and the lower bridge is turned off. The switching transistor is a MOSFET, and step E includes testing the reverse recovery limit capability of the body diode when the LLC converter experiences a hard recovery condition of the body diode of the MOSFET in the capacitive operating region at time t6.

10. A dual-pulse test circuit, characterized in that, include: The charging circuit includes a power supply, a bus capacitor, and a first switch; A resonant circuit is connected to the bus capacitor. The resonant circuit is a half-bridge LC resonant circuit or a full-bridge LC resonant circuit. The first switch is used to control whether the power supply is connected to the bus capacitor and the resonant circuit. A driving circuit is used to provide control voltage to the control terminals of the upper bridge and the lower bridge in the resonant circuit.

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