Data processing method for chip, chip and electronic equipment

Abstract

The embodiment of the invention provides a data processing method for a chip, the chip and electronic device.The method comprises the steps that in response to a target triggering condition, counting values of all performance counters in the chip are grouped and collected, and multiple sets of counting data are obtained; each group of counting data comprises counting values of a plurality of performance counters; performing compression processing on the multiple groups of counting data to obtain multiple groups of compressed counting data; and respectively sending the plurality of groups of compressed counting data to a memory. Therefore, on one hand, the dumping efficiency of the count value of the performance counter can be improved, and the overall performance of the chip is improved; on the other hand, the problem that the counting data of each group cannot be matched easily due to too many groups can be improved, and the accuracy after the counting value data dumped in groups are recombined is improved; and on the other hand, time consumed by the user to wait for numerical value dump of the performance counter can be reduced, and user experience is improved.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of computer technology, and in particular to a data processing method for a chip, a chip, and an electronic device. Background Technology

[0002] Performance counters are tools within a chip used to monitor and record performance data. These counters allow developers to obtain various performance metrics during chip operation, such as frame rate, resource utilization, and power consumption, thus helping to optimize application performance. In practice, a large number of performance counters are typically defined within the chip. When a performance counter's count value dump condition is triggered, the count value of each performance counter is dumped to video memory and / or system memory for use by the application.

[0003] In related technologies, due to the large number of performance counters in a chip, the count values ​​of each performance counter are usually transferred in groups. However, in related technologies, the total data transfer time is relatively long, which affects the overall performance of the chip, and the recombined data after grouping and transferring is prone to inaccuracy. Summary of the Invention

[0004] In view of the above, this disclosure provides at least one data processing method for a chip, a chip, and an electronic device.

[0005] The technical solution of this disclosure embodiment is implemented as follows: This disclosure provides a data processing method for a chip, the method comprising: In response to the target triggering condition, the count values ​​of each performance counter in the chip are collected in groups to obtain multiple sets of count data; each set of count data contains the count values ​​of multiple performance counters; Multiple sets of counting data are compressed separately to obtain multiple sets of compressed counting data; Multiple sets of compressed counting data are sent to the memory respectively.

[0006] This disclosure provides a chip, including: The count value collection module is used to collect the count values ​​of each performance counter in the chip in groups, resulting in multiple sets of count data; each set of count data contains the count values ​​of multiple performance counters. The compression module is used to compress multiple sets of counting data separately to obtain multiple sets of compressed counting data. The sending module is used to send multiple sets of compressed counting data to the memory respectively.

[0007] This disclosure provides an electronic device, including a processor and a memory, wherein the processor includes the chip described in the above embodiments.

[0008] This disclosure provides a computer program product, including a computer program or instructions, which, when executed by a processor, implement the steps of the data processing method described in the above embodiments.

[0009] In this embodiment, in response to a target triggering condition, the count values ​​of each performance counter in the chip are collected in groups to obtain multiple sets of count data; each set of count data contains the count values ​​of multiple performance counters; the multiple sets of count data are compressed to obtain multiple sets of compressed count data; and the multiple sets of compressed count data are sent to the memory respectively. Thus, by collecting and compressing the count values ​​of each performance counter in groups within the chip before sending them to the memory, the bandwidth occupied by the transfer of count value data from the chip to the memory can be reduced, thereby reducing the number of groups. This, on the one hand, accelerates the efficiency of performance counter value dumping, improving the overall chip performance; on the other hand, it improves the problem of mismatched count data caused by too many groups, improving the accuracy of the recombined count value data after group dumping; and furthermore, it reduces the time users spend waiting for performance counter value dumping, improving the user experience.

[0010] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the technical solutions of this disclosure. Attached Figure Description

[0011] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the specification, serve to illustrate the technical solutions of this disclosure.

[0012] Figure 1 This is a schematic diagram illustrating the implementation flow of a data processing method for a chip provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of the composition structure of a chip provided in an embodiment of this disclosure; Figure 3 This is a schematic diagram illustrating the implementation architecture of the performance counter's count value dumping process in related technologies; Figure 4 A schematic diagram illustrating the implementation architecture of a data processing method provided in an embodiment of this application; Figure 5 This is a schematic diagram illustrating the implementation of compressing count values ​​in a data processing method provided in an embodiment of this disclosure; Figure 6 This is a schematic diagram of the composition structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0013] To make the objectives, technical solutions, and advantages of this disclosure clearer, the technical solutions of this disclosure are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this disclosure. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0014] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0015] The terms “first / second / third” are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that “first / second / third” may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0016] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. The terminology used herein is for descriptive purposes only and is not intended to limit the scope of this disclosure.

[0017] To better understand the solutions of the embodiments of this disclosure, the data processing methods of chips in related technologies will be described below.

[0018] In related technologies, the process of grouping and dumping performance counter values ​​in chips is lengthy due to the large number of performance counters and consequently, the large number of groups, thus impacting overall chip performance. Furthermore, because chips operate dynamically, the performance counter values ​​collected and dumped at different times can vary. With a large number of groups, the collection and dumping times for different groups can differ significantly, leading to data inconsistencies when recombining the different groups.

[0019] In view of this, embodiments of the present disclosure provide a data processing method for a chip. This method can be executed by the chip. In some embodiments, the chip can be any suitable processor chip. For example, the processor chip can be at least one of, but not limited to, a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose graphics processing unit (GPGPU), and a data processing unit (DPU). Figure 1 This is a schematic diagram illustrating the implementation flow of a data processing method for a chip provided in an embodiment of this disclosure, as shown below. Figure 1 As shown, the method may include the following steps S101 to S103: Step S101: In response to the target triggering condition, the count values ​​of each performance counter in the chip are collected in groups to obtain multiple sets of count data; each set of count data contains the count values ​​of multiple performance counters.

[0020] Here, the target triggering condition can include any suitable condition for triggering the dumping of performance counter count values. When the target triggering condition is met, the chip begins to collect the count values ​​of each performance counter in groups. For example, the target triggering condition can include at least one of the following: reaching a target time, the difference between the current time and the last time the performance counter count value dump was triggered being a target duration, or the target task execution being completed. Among these, the target time, target duration, and target task can be set according to actual needs.

[0021] In some implementations, the target triggering condition may include a task triggering condition. The chip may, in response to the task triggering condition, collect the count values ​​of multiple performance counters in the chip in groups. The task triggering condition may include the completion of execution of an independent task (such as a kick task) within the chip. For example, a performance counter count dump may be triggered at the end of each independent task execution, i.e., a kick mode. Alternatively, a performance counter count dump may be triggered at the end of execution of multiple independent tasks. Yet another example is that a performance counter count dump may be triggered at the end of execution of the target task.

[0022] In some implementations, the target triggering condition may include a time-triggered condition. The chip may, in response to the time-triggered condition, collect the count values ​​of multiple performance counters in the chip in groups. The time-triggered condition may include a preset time period. For example, the performance counter count values ​​may be dumped once every preset time period, i.e., an interval mode.

[0023] In some implementations, in response to a target triggering condition, the count values ​​of each performance counter in the chip can be collected and grouped to obtain multiple sets of count data. Here, any suitable method can be used to group the count values ​​of each performance counter to obtain multiple sets of count values, each set of count values ​​constituting a set of count data. For example, the count values ​​of each performance counter can be randomly grouped to obtain multiple sets of count data. Alternatively, the count values ​​of each performance counter can be uniformly grouped to obtain multiple sets of count data, with each set containing the same number of count values.

[0024] In some implementations, the step S101 above, which involves collecting the count values ​​of each performance counter in the chip in groups to obtain multiple sets of count data, may include: Step S111: In response to the target triggering condition, the performance counters are grouped to obtain multiple counter groups; Step S112: Collect the count values ​​of each performance counter in the same counter group to obtain a set of count data.

[0025] Here, any suitable grouping method can be used to group the performance counters, and this disclosure does not limit this.

[0026] For example, performance counters can be randomly grouped to obtain multiple counter groups. Alternatively, performance counters can be evenly grouped to obtain multiple counter groups, with each performance counter in the same group having the same number of counters. Yet another example is grouping performance counters according to the pipeline they belong to, resulting in multiple counter groups where each performance counter in the same group belongs to the same pipeline.

[0027] In some implementations, the chip may include a count value collection module that can collect the count values ​​of each performance counter in the chip in groups in response to a target trigger condition, thereby obtaining multiple sets of count data.

[0028] Step S102: Compress the multiple sets of counting data to obtain multiple sets of compressed counting data.

[0029] Here, any suitable compression method can be used to compress each group of counting data separately to obtain a set of compressed counting data corresponding to each group of counting data. This embodiment of the disclosure does not limit this.

[0030] In some implementations, lossless compression can be used to compress multiple sets of counting data separately, resulting in multiple sets of compressed counting data. This reduces compression loss and improves the accuracy of the recombined counting values ​​after grouping and dumping.

[0031] For example, lossless compression methods may include, but are not limited to, at least one of the following: Exponential Golomb coding, Huffman coding, predictive coding, LZ series algorithms, and Burrows-Wheeler Transform (BWT) algorithms. Among these, the LZ series algorithms can use a dictionary to store encountered strings and replace repeated strings with their corresponding indices, thereby achieving compression. The BWT algorithm can rearrange the input data, grouping similar characters together, and then use algorithms (such as Move-to-Front algorithm, run-length encoding, etc.) to further compress the rearranged data.

[0032] Step S103: Send the multiple sets of compressed counting data to the memory respectively.

[0033] Here, the memory may include, but is not limited to, at least one of video memory, system memory, etc.

[0034] In some implementations, the chip can send each set of compressed counting data to the video memory via an internal interface.

[0035] In some implementations, the chip can send each set of compressed counting data to the video memory via an internal interface, and then transfer each set of compressed counting data to the system memory via the video memory.

[0036] In this embodiment, in response to a target triggering condition, the count values ​​of each performance counter in the chip are collected in groups to obtain multiple sets of count data; each set of count data contains the count values ​​of multiple performance counters; the multiple sets of count data are compressed to obtain multiple sets of compressed count data; and the multiple sets of compressed count data are sent to the memory respectively. Thus, by collecting and compressing the count values ​​of each performance counter in groups within the chip before sending them to the memory, the bandwidth occupied by the transfer of count value data from the chip to the memory can be reduced, thereby reducing the number of groups. This, on the one hand, accelerates the efficiency of performance counter value dumping, improving the overall chip performance; on the other hand, it improves the problem of mismatched count data caused by too many groups, improving the accuracy of the recombined count value data after group dumping; and furthermore, it reduces the time users spend waiting for performance counter value dumping, improving the user experience.

[0037] In some embodiments, the above data processing method may further include the following step S121: Step S121: Based on the target compression method, compress the multiple sets of count data respectively to obtain multiple sets of compressed count data; the grouping method of each performance counter corresponds to the compression ratio influence factor of the target compression method.

[0038] The grouping method for each performance counter corresponds to the compression ratio influence factor of the target compression method. This means that the grouping method for each performance counter is adapted to the compression ratio influence factor of the target compression method. In this way, under this grouping method, the multiple sets of count data collected from the multiple counter groups obtained by grouping can have a high degree of compression during the compression processing of the target compression method, for example, the compression ratio is less than the preset compression ratio threshold.

[0039] In some implementations, the target compression method may be preset, and the grouping of the performance counters may be determined based on the compression ratio influence factor of the target compression method. For example, the target compression method may include exponential Golomb coding, Huffman coding, or predictive coding, etc.

[0040] The compression ratio influencing factor of the target compression method refers to the factors that affect the data compression ratio when the target compression method is used for data compression. Here, compression ratio refers to the ratio of the size of the compressed data to the size of the original data. For example, the compression ratio influencing factor may include, but is not limited to, at least one of the following: the degree of difference between count values ​​in the count data to be compressed, the number of identical count values, etc.

[0041] In some implementations, the lower the degree of difference between the count values ​​in the count data, the smaller the compression ratio (i.e., the higher the degree of compression) when the count data is compressed using the target compression method. The compression ratio influence factor of the target compression method may include at least one of the degree of difference between the count values ​​of each performance counter, the degree of difference between the counting frequencies of each performance counter, etc.

[0042] For example, the target compression method may include exponential Golomb coding. In the process of compressing count data using exponential Golomb coding, the lower the difference between the count values, the smaller the compression ratio and the higher the compression degree. Therefore, based on the difference between the count values ​​of each performance counter, multiple performance counters with small differences in count values ​​can be grouped into the same group to obtain multiple counter groups. Alternatively, based on the difference between the counting frequencies of each performance counter, multiple performance counters with small differences in counting frequencies can be grouped into the same group to obtain multiple counter groups. In this way, the difference between the count values ​​in the same group of collected count data can be reduced, thereby improving the compression degree of the count data.

[0043] In some implementations, the more identical count values ​​there are in the count data, the lower the compression ratio and the higher the compression degree when the count data is compressed using the target compression method. Therefore, the compression ratio influence factor of the target compression method may include the number of identical count values ​​in the count values ​​of each performance counter.

[0044] For example, target compression methods can include Huffman coding. Huffman coding can reduce the overall data size by constructing a variable-length coding table, assigning shorter codes to frequently occurring symbols and longer codes to infrequent symbols. Therefore, in the process of compressing counting data using Huffman coding, the more identical count values ​​there are among the count values, the lower the compression ratio and the higher the compression degree. Thus, based on the count values ​​of each performance counter, multiple counter groups can be obtained, ensuring that the frequency of identical count values ​​within the same counter group exceeds a preset frequency threshold. This increases the frequency of identical count values ​​within each group, thereby improving the compression degree of the counting data.

[0045] In some implementations, the distribution characteristics of the count values ​​in each group of count data can be determined, and the target compression method can be determined based on these characteristics. For example, if the maximum difference between the count values ​​in the same group of count data is less than a difference threshold, exponential Golomb coding can be selected as the target compression method to improve the compression level of the count data. Similarly, if the most frequent count value in the same group of count data corresponds to a frequency exceeding a frequency threshold, Huffman coding can be selected as the target compression method to improve the compression level of the count data.

[0046] In some implementations, the distribution characteristics of the count values ​​in each group of count data can be determined, and the target compression method can be determined based on these characteristics. For example, if the maximum difference between the count values ​​in the same group of count data is less than a difference threshold, exponential Golomb coding can be selected as the target compression method to improve the compression level of the count data. Similarly, if the most frequent count value in the same group of count data corresponds to a frequency exceeding a frequency threshold, Huffman coding can be selected as the target compression method to improve the compression level of the count data.

[0047] In some implementations, after grouping the performance counters, the counting frequency of each performance counter in the same group can be determined, and the target compression method can be determined based on the counting frequency of each performance counter in the same group. For example, if the maximum difference between the counting frequencies of each performance counter in the same group is less than a frequency difference threshold, exponential Golomb coding can be selected as the target compression method to improve the compression degree of the count data.

[0048] In the above embodiments, multiple sets of counting data are compressed separately based on the target compression method to obtain multiple sets of compressed counting data. The grouping method for each performance counter corresponds to the compression ratio influence factor of the target compression method. Thus, because the compression ratio influence factor of the target compression method is considered during the grouping process of each performance counter, the compression level can be improved during the separate compression processing of multiple sets of counting data based on the target compression method. This further reduces the bandwidth usage of the count value data transmitted from the chip to the memory, and consequently, further reduces the number of groups.

[0049] In some embodiments, grouping the performance counters in step S111 to obtain multiple counter groups may include the following step S131: Step S131: When the compression ratio influence factor of the target compression method includes the degree of difference between count values, the performance counters are grouped based on the counting frequency of each performance counter to obtain multiple counter groups.

[0050] Here, the counting frequency of the performance counter can be a fixed value or it can change dynamically according to the real-time load of the chip. This disclosure does not limit this.

[0051] In some implementations, multiple frequency ranges can be predetermined, and multiple performance counters whose counting frequencies fall within the same frequency range can be grouped into multiple counter groups. This way, since the differences in count values ​​among multiple performance counters within the same frequency range are relatively small, the differences in count values ​​among the performance counters within the same group are also relatively small. The multiple frequency ranges can be determined by those skilled in the art based on actual conditions. For example, if the chip's clock frequency is F, [0, F] can be divided into multiple frequency ranges in a uniform or non-uniform manner.

[0052] Understandably, performance counters are reset to zero after each collection. Therefore, the performance counter count during each dump is typically affected by the counter's counting frequency. Thus, the difference in counting frequencies between performance counters reflects the difference in their count values. Therefore, considering the difference in count values ​​among the compression factors of the target compression method, grouping performance counters by taking into account their counting frequencies can improve the compression efficiency of the counted data.

[0053] In some embodiments, each performance counter is divided into multiple counter groups based on the counting frequency. The difference between the counting frequencies of each performance counter in the counter group is less than a difference threshold. The lower the degree of difference between the count values ​​in the count data, the smaller the compression ratio of the count data compressed using the target compression method.

[0054] Here, the difference threshold can be a value set according to the actual situation, and this embodiment of the disclosure is not limited in this regard. For example, the difference threshold can be 0, 1, 2, 5, 10, etc.

[0055] In the above embodiments, multiple performance counters whose counting frequencies differ by less than a difference threshold are grouped together, and the count values ​​of each performance counter within the same group are considered as a single set of counting data. This reduces the degree of difference between count values ​​within each group of counting data, thereby improving the compression level when the counting data is compressed using the target compression method.

[0056] In some embodiments, dividing each performance counter into multiple counter groups based on the counting frequency described above may include at least one of the following steps S141 and S142: Step S141: Divide the first performance counter in each of the performance counters into the first counter group; the counting frequency of the first performance counter is less than the difference threshold.

[0057] It is understandable that if the counting frequency of the first performance counter is less than the difference threshold, then the difference between the counting frequencies of each first performance counter is also less than the difference threshold.

[0058] For example, if the counting frequency of some performance counters in the chip is extremely low, close to 0, then these performance counters can be identified as the first performance counters, and each of the first performance counters can be divided into the first counter group. Since the counting values ​​of these performance counters are relatively close, they can be collected into the same group of counting data for compression.

[0059] In this way, by dividing each first performance counter into the same group and collecting the count values ​​of each first performance counter into the same group of count data, the degree of difference between the count values ​​within the group of count data can be reduced, thereby improving the compression degree of the count data compressed using the target compression method.

[0060] Step S142: The second performance counter in each of the performance counters is assigned to a second counter group; the difference between the counting frequency of the second performance counter and the clock frequency of the chip is less than the difference threshold.

[0061] It is understandable that, since the counting frequency of the performance counter is usually less than or equal to the clock frequency of the chip, if the difference between the counting frequency of the second performance counter and the clock frequency of the chip is less than the difference threshold, then the difference between the counting frequencies of each second performance counter is also less than the difference threshold.

[0062] For example, if some performance counters in a chip have extremely high counting frequencies, close to the chip's clock frequency, then these performance counters can be designated as second performance counters, and each second performance counter can be assigned to a second counter group. Since the counting values ​​of these performance counters are relatively close, they can be collected into the same group of counting data for compression.

[0063] In this way, by dividing each of the second performance counters into the same group and collecting the count values ​​of each of the second performance counters into the same group of count data, the degree of difference between the count values ​​within the group of count data can be reduced, thereby improving the compression degree of the count data compressed using the target compression method.

[0064] In some embodiments, the above-described method of dividing each performance counter into multiple counter groups based on the counting frequency may further include the following steps S151 to S152: Step S151: Determine a plurality of third performance counters from each of the performance counters; the counting frequency of the third performance counters is determined based on the real-time load of the chip.

[0065] Step S152: Based on the load type and / or the pipeline to which they belong, group each of the third performance counters to obtain multiple third counter groups.

[0066] Here, the counting frequency of the third performance counter is determined based on the real-time load of the chip, meaning that the counting frequency of the third performance counter changes dynamically with the real-time load of the chip.

[0067] For example, the third performance counter may include a thread counter, the counting frequency of which may dynamically change with the real-time load of the chip. When the real-time load of the chip is large, the counting frequency of the thread counter is large, and when the real-time load of the chip is small, the counting frequency of the thread counter is small.

[0068] For example, the third performance counter may include a read request counter, the counting frequency of which may dynamically change with the real-time read request load of the chip. When the real-time read request load of the chip is large, the counting frequency of the read request counter is large, and when the real-time read request load of the chip is small, the counting frequency of the read request counter is small.

[0069] Performance counters can correspond to specific load types. For example, load types can include, but are not limited to, at least one of communication type, computation type, memory access type, etc.

[0070] A performance counter can belong to a pipeline (i.e., its associated pipeline). The pipeline to which a performance counter belongs refers to the processing stage in the chip's data processing flow where the performance counter operates. For example, in the case of a GPU, the pipeline to which a performance counter belongs can include, but is not limited to, at least one of the application stage, geometry stage, rasterization stage, fragment processing stage, etc.

[0071] It is understandable that among the third performance counters whose counting frequency dynamically changes with the chip's real-time load, multiple third performance counters with the same load type and / or belonging to the same pipeline usually have similar counting frequencies, meaning their count values ​​are usually similar. Therefore, by fully considering the load type and / or pipeline to which the counters belong during the grouping process, the count values ​​of the third performance counters within the same group can be made more similar. This reduces the degree of difference between count values ​​within the count data and improves the compression level when using the target compression method.

[0072] In some embodiments, grouping the performance counters in step S111 above to obtain multiple counter groups may include the following steps S161 to S162: Step S161: Determine the grouping granularity based on the maximum transmission bandwidth between the chip and the memory, and the reference compression ratio corresponding to the target compression method.

[0073] Step S162: Based on the grouping granularity, the performance counters are grouped to obtain multiple counter groups.

[0074] Here, maximum transmission bandwidth refers to the maximum data transmission bandwidth that can be supported when data is transmitted between the chip and the memory.

[0075] The reference compression ratio corresponding to the target compression method represents a reference compression ratio for data compression using the target compression method. In some embodiments, the reference compression ratio corresponding to the target compression method can be estimated in advance based on the compression processing logic of the target compression method. In some embodiments, the reference compression ratio corresponding to the target compression method can be determined based on the historical compression ratios of count data compressed using the target compression method in historical compression processes.

[0076] It should be noted that the amount of data in the count values ​​of each performance counter in a chip is usually fixed. Therefore, the maximum transmission bandwidth between the chip and the memory can reflect the number of count values ​​that the chip can send to the memory at a time.

[0077] Group granularity refers to the number of performance count values ​​contained in each counter group, and it also reflects the number of count values ​​contained in each group of count data. In implementation, the group granularity can be determined in any suitable way based on the maximum transmission bandwidth between the chip and the memory, and the reference compression ratio corresponding to the target compression method. This disclosure does not limit this.

[0078] In some implementations, the packet granularity is directly proportional to the maximum transmission bandwidth and / or inversely proportional to the reference compression ratio. For example, the larger the maximum transmission bandwidth, the larger the packet granularity; the smaller the maximum transmission bandwidth, the smaller the packet granularity. Similarly, the larger the reference compression ratio (corresponding to a lower degree of compression), the smaller the packet granularity; the smaller the maximum transmission bandwidth (corresponding to a higher degree of compression), the larger the packet granularity.

[0079] In some implementations, a reference number of count values ​​corresponding to the compressed count data that the chip can send to the memory in a single transmission can be estimated based on the maximum transmission bandwidth between the chip and the memory, and a reference compression ratio corresponding to the target compression method. The grouping granularity is then determined based on this reference number. The grouping granularity can be equal to the number of count values ​​corresponding to the compressed count data that the chip can send to the memory in a single transmission (i.e., the aforementioned reference number), or it can be an integer multiple of this reference number.

[0080] In some implementations, the reference number of count values ​​corresponding to the compressed count data that the chip can send to the memory in a single transmission can be estimated based on the maximum transmission bandwidth between the chip and the memory, the reference compression ratio corresponding to the target compression method, and the data volume of a single count value.

[0081] The step S102, which involves compressing multiple sets of counting data to obtain multiple sets of compressed counting data, may include the following step S163: Step S163: Based on the target compression method, compress the multiple sets of counting data respectively to obtain multiple sets of compressed counting data.

[0082] Here, step S163 corresponds to step S121 in the foregoing embodiment, and the implementation of step S121 can be referred to in the implementation.

[0083] In the above embodiments, the grouping granularity is determined based on the maximum transmission bandwidth between the chip and the memory, and the reference compression ratio corresponding to the target compression method. Based on the grouping granularity, each performance counter is grouped to obtain multiple counter groups. Based on the target compression method, multiple groups of counting data are compressed separately to obtain multiple groups of compressed counting data. Thus, because the maximum transmission bandwidth between the chip and the memory, as well as the reference compression ratio corresponding to the target compression method, are comprehensively considered in determining the grouping granularity, the data size of each group of compressed counting data obtained after compression is more closely matched to the maximum transmission bandwidth. This improves the bandwidth utilization during the transmission of compressed counting data and further enhances the overall chip performance.

[0084] In some embodiments, determining the grouping granularity based on the maximum transmission bandwidth between the chip and the memory, and the reference compression ratio corresponding to the target compression method, as described in step S161, may include the following step S171: Step S171: Determine the packet granularity based on the ratio of the maximum transmission bandwidth to the reference data volume; the reference data volume is the product of the data volume of a single count value and the reference compression rate.

[0085] Here, the amount of data for a single count value can be preset, and this embodiment of the present disclosure does not limit this. For example, in a chip, a data bit width of 32 bits can be used to represent the count value of a performance counter, then the amount of data for a single count value is 32 bits. As another example, in a chip, a data bit width of 64 bits can be used to represent the count value of a performance counter, then the amount of data for a single count value is 64 bits.

[0086] In some implementations, the ratio of the maximum transmission bandwidth to the reference data size can be determined as the packet granularity. For example, if the maximum transmission bandwidth is B, the data size of a single count value is L, and the reference compression ratio is R, then the ratio of the reference data size is R×L, and the packet granularity N can be B / (R×L).

[0087] In some implementations, the packet granularity can be determined as m times the ratio of the maximum transmission bandwidth to the reference data size, where m is a positive integer. For example, if the maximum transmission bandwidth is B, the data size of a single count value is L, and the reference compression ratio is R, then the ratio of the reference data size is R×L, and the packet granularity N can be (B×m) / (R×L).

[0088] Understandably, since the reference data size is the product of the data size of a single count value and the reference compression ratio, it reflects the average data size of a single count value after compression. Therefore, the ratio of the maximum transmission bandwidth to the reference data size reflects the reference number of count values ​​corresponding to the compressed count data that the chip can send to the memory in a single transmission. Thus, based on the ratio of the maximum transmission bandwidth to the reference data size, a more suitable grouping granularity can be determined, making the data size of each group of compressed count data more compatible with the maximum transmission bandwidth, thereby further improving bandwidth utilization during the transmission of compressed count data.

[0089] In some embodiments, multiple sets of compressed count data in the memory are used to decompress and combine to obtain chip performance data.

[0090] For example, after the compressed counting data is sent to the memory, the application processing the counting data can decompress the compressed data to recover the count values ​​of each performance counter. Furthermore, the application can combine the count values ​​of each performance counter according to the actual application scenario to obtain the chip's performance data during operation, such as frame rate, utilization, and power consumption. The application can run on a processor, which may include the chip or the main processor. Combining the count values ​​of each performance counter can include combining the count values ​​of different performance counters. For example, for a multi-core chip, the count values ​​of the frame processing counters corresponding to each core can be added together to obtain the total frame processing count of the chip, and thus the chip's frame rate. Combining the count values ​​of each performance counter can also include adding all the count values ​​of the same performance counter within a set statistical period. For example, all the count values ​​of the read data counter in the chip within the current statistical period can be added together to obtain the total number of read data operations by the chip in that current statistical period.

[0091] This disclosure provides a chip, Figure 2 This is a schematic diagram of the composition structure of a chip provided in an embodiment of this disclosure, such as... Figure 2 As shown, the chip 200 includes: a count value collection module 210, a compression module 220, and a transmission module 230, wherein: The count value collection module 210 is used to collect the count values ​​of each performance counter in the chip in groups to obtain multiple sets of count data; each set of count data contains the count values ​​of multiple performance counters; Compression module 220 is used to compress multiple sets of counting data respectively to obtain multiple sets of compressed counting data; The sending module 230 is used to send multiple sets of the compressed counting data to the memory respectively.

[0092] In some embodiments, the count value collection module is further configured to: group the performance counters to obtain multiple counter groups; and collect the count values ​​of each performance counter in the same counter group to obtain a set of count data.

[0093] In some implementations, the compression module is further configured to: compress multiple sets of the count data respectively based on the target compression method to obtain multiple sets of compressed count data; and group each of the performance counters in a manner corresponding to the compression ratio influence factor of the target compression method.

[0094] In some implementations, the count value collection module is further configured to: group the performance counters based on their counting frequencies, in cases where the compression ratio influence factor of the target compression method includes the degree of difference between the count values, to obtain multiple counter groups.

[0095] In some implementations, each of the performance counters is divided into multiple counter groups based on the counting frequency. The difference between the counting frequencies of each performance counter in the counter group is less than a difference threshold. The lower the degree of difference between the count values ​​in the count data, the smaller the compression ratio of the count data compressed using the target compression method.

[0096] In some implementations, the count value collection module is further configured to: assign a first performance counter among the performance counters to a first counter group; the counting frequency of the first performance counter is less than the difference threshold; assign a second performance counter among the performance counters to a second counter group; the difference between the counting frequency of the second performance counter and the clock frequency of the chip is less than the difference threshold.

[0097] In some implementations, the count value collection module is further configured to: determine a plurality of third performance counters from each of the performance counters; the counting frequency of the third performance counters is determined based on the real-time load of the chip; and group each of the third performance counters based on the load type and / or the pipeline to which they belong to, to obtain a plurality of third counter groups.

[0098] In some implementations, the count value collection module is further configured to: determine the grouping granularity based on the maximum transmission bandwidth between the chip and the memory, and the reference compression ratio corresponding to the target compression method; group each of the performance counters based on the grouping granularity to obtain multiple counter groups; the compression module is further configured to: compress multiple groups of the count data respectively based on the target compression method to obtain multiple groups of compressed count data.

[0099] In some implementations, the count collection module is further configured to: determine the packet granularity based on the ratio of the maximum transmission bandwidth to the reference data volume; the reference data volume is the product of the data volume of a single count value and the reference compression ratio.

[0100] In some embodiments, multiple sets of compressed count data in the memory are used to decompress and combine to obtain the chip's performance data.

[0101] The following describes the application of the data processing method for chips provided in this disclosure in a real-world scenario, using a GPU chip as an example.

[0102] In related technologies, GPU chip designers define a large number of performance counters on the internal pipeline of the GPU chip. When the performance counter count value dump condition is triggered, the count value of each performance counter is dumped to the video memory. Then, the driver reads these count values ​​from the video memory into the system memory so that the application can use them. Figure 3 This is a schematic diagram illustrating the implementation architecture of the performance counter's count value dumping process in related technologies, such as... Figure 3As shown, a GPU chip can have multiple GPU modules (such as a first GPU module 310, a second GPU module 320, ..., an Nth GPU module 3N0, etc., where N can be an integer greater than 1); each GPU module can include a performance counter assembler and an interface arbiter. For example, the first GPU module 310 includes a first performance counter assembler 311 and a first interface arbiter 312, the second GPU module 320 includes a second performance counter assembler 321 and a second interface arbiter 322, and so on. The GPU module 3N0 includes the Nth performance counter assembler 3N1 and the Nth interface arbiter 3N2, etc. When the performance counter count value dumping condition is triggered, each performance counter assembler collects the count values ​​of each performance counter and uses the corresponding interface arbiter to send the collected count values ​​of each performance counter to the memory interface arbiter 34 through the storage interface via the internal interface 33. Then, the memory interface arbiter 34 uses the memory interface arbiter 34 to dump the collected count values ​​of each performance counter to the video memory 51. Then, the driver reads the count values ​​in the video memory 51 into the system memory 52.

[0103] However, as GPU chips become larger, the number of performance counters defined in the chip also increases. Dumping too many counter values ​​will consume too much video memory bandwidth, leading to a decrease in the overall performance of the GPU chip.

[0104] In some related technologies, all performance counters in a chip can be grouped, and the count values ​​of one group of performance counters can be dumped at a time. By dumping multiple times, the count values ​​of all groups of performance counters can be collected. Then, the software concatenates the count values ​​of each group of performance counters together to form complete count data. For example, when the collection of performance counter count values ​​is triggered by running game frames, the count values ​​of all performance counters in the chip can be collected by running the game frames multiple times.

[0105] However, the scheme for calculating the count value of the group dump performance counter in related technologies has at least the following problems: 1) GPUs are dynamically changing during runtime. The count values ​​of the performance counters in the dump will vary at different times. When there are a large number of groups, this can easily lead to data mismatch when the count values ​​of different groups of performance counters are recombined.

[0106] 2) After grouping, the overall dump time of the performance counter count values ​​increases with the increase of the number of groups, and users need to spend a long time waiting for the dump to complete.

[0107] Based on this, the present disclosure provides a data processing method for a chip. This method improves the performance counter value dumping process by adding a compression module inside the GPU chip to compress the collected performance counter values ​​before writing them to the video memory and system memory via internal and storage interfaces. This reduces the bandwidth occupied during the transfer of counter value data from inside the chip to the video memory and from the video memory to the system memory, thereby reducing the number of packets and accelerating the performance counter value dumping process.

[0108] Figure 4 This is a schematic diagram illustrating the implementation architecture of a data processing method provided in an embodiment of this application, such as... Figure 4 As shown, the data processing method can be implemented by a GPU chip, which may include multiple GPU modules (such as a first GPU module 310, a second GPU module 320, ..., an Nth GPU module 3N0, etc.). Each GPU module may include a performance counter assembler (corresponding to the count value collection module in the aforementioned embodiments), a lossless compression module (corresponding to the compression module in the aforementioned embodiments), and an interface arbitrator (corresponding to the sending module in the aforementioned embodiments). For example, the first GPU module 310 includes a first performance counter assembler 311, a first lossless compression module 313, and a first interface arbitrator 312; the second GPU module 320 includes a second performance counter assembler 321, a second lossless compression module 323, and a second interface arbitrator 322; and the Nth GPU module 3N0 includes an Nth performance counter assembler 3N1, an Nth lossless compression module 3N3, and an Nth interface arbitrator 3N2. The performance counter assembler can perform at least the following functions: first, connect several performance counters; second, collect the count values ​​of several performance counters in groups at a specific time (e.g., when the performance counter count value dumping condition is triggered), obtain multiple sets of count data, and send the collected multiple sets of count data to the corresponding lossless compression module for compression processing. The lossless compression module is used to compress each set of count data separately to obtain multiple sets of compressed count data, and uses the corresponding interface arbitrator to send each set of compressed count data to the memory interface arbitrator 34 through the storage interface via the internal interface 33. Then, the memory interface arbitrator 34 uses the received sets of compressed count data to dump to the video memory 51, and then the driver reads the compressed count data in the video memory 51 into the system memory 52.

[0109] In some implementations, depending on the compression algorithm, the selection strategy may differ when selecting a set of performance counters (corresponding to the counter group in the aforementioned embodiments) to compress the count values ​​of the set of performance counters.

[0110] In some implementations, the lossless compression module can use exponential Golomb coding as the target compression method to compress count data. Under this compression method, the smaller the variation between values ​​within the data to be compressed, the higher the degree of compression.

[0111] For example, in practical applications, performance counters are mainly single-bit counting (i.e., the value increments by 1 with each count), and the number of multi-bit counting performance counters is negligible. Based on the frequency of value change (i.e., counting frequency), the performance counters in a chip can be divided into three categories: 1) A performance counter with an extremely low frequency of numerical change (close to 0) is denoted as a low-frequency counter (corresponding to the first performance counter in the aforementioned embodiment). 2) The performance counter whose value changes dynamically with the load is denoted as the intermediate frequency performance counter (corresponding to the third performance counter in the aforementioned embodiment).

[0112] 3) A performance counter with an extremely high frequency of numerical change (close to the clock frequency) is denoted as a high-frequency performance counter (corresponding to the second performance counter in the aforementioned embodiment).

[0113] For low-frequency counters and high-frequency performance counters, the count values ​​of each low-frequency counter are relatively close, and the data of each high-frequency performance counter are also similar. Therefore, the low-frequency counters can be grouped together to compress their count values ​​as a group, and the high-frequency counters can be grouped together to compress their count values ​​as a group, thereby improving the compression degree. For mid-frequency performance counters, they can be grouped according to the corresponding load type and the GPU pipeline to which they belong. Mid-frequency performance counters with similar numerical variation patterns can be grouped together to compress the corresponding count values, reduce the differences between the count values ​​in the same group, and improve the compression degree.

[0114] In some implementations, the performance counter assembler can optionally send the count values ​​of M performance counters to the lossless compression module for compression at a time, where M is an integer greater than 1. For example... Figure 5 As shown, M performance counters are grouped together. The performance counter assembler can collect the count values ​​of the M performance counters each time, such as count value 1, count value 2, ..., count value M, and send the count values ​​of the M performance counters as a group to the lossless compression module 32.

[0115] After compression, the count data becomes compressed count data, which can be written to and transferred from video memory to system memory in a shorter time. Applications processing the count data can decompress the compressed data to recover the count values ​​of each performance counter.

[0116] In this embodiment, from a hardware perspective, the data transmission bandwidth usage during the performance counter value dumping process is reduced, thus minimizing the performance impact on normal GPU tasks (such as running games, playing videos, and performing data calculations). This can improve the overall performance of the GPU chip and reduce the number of groups, improving the problem of mismatched count data caused by excessive groups and enhancing the accuracy of the recombined count values ​​after group dumping. From a software perspective, the time spent by users waiting for the performance counter value dumping is reduced, which can significantly improve the user experience.

[0117] It should be noted that the descriptions of the various embodiments above tend to emphasize the differences between them, while their similarities or commonalities can be referred to interchangeably. The descriptions of the chip embodiments above are similar to those of the method embodiments above, and have similar beneficial effects. In some embodiments, the functions or modules included in the chip provided by this disclosure can be used to perform the methods described in the method embodiments above. For technical details not disclosed in the device embodiments of this disclosure, please refer to the descriptions of the method embodiments of this disclosure for understanding.

[0118] This disclosure provides an electronic device, Figure 6 This is a schematic diagram of the composition structure of an electronic device provided in an embodiment of the present disclosure, such as... Figure 6 As shown, the electronic device 60 includes a processor 61 and a memory 62, and the processor 61 includes the chip 200 in the above embodiment.

[0119] This disclosure provides a computer program product, including a computer program or instructions, which, when executed by a processor, implement the steps of the data processing method described in the above embodiments.

[0120] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above steps / processes do not imply a sequential order of execution; the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above embodiments of this disclosure are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0121] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0122] In the several embodiments provided in this disclosure, it should be understood that the disclosed chips and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0123] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; they may be located in one place or distributed across multiple network units; some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, the functional units in the embodiments of this disclosure may all be integrated into one processing unit, or each unit may be a separate unit, or two or more units may be integrated into one unit; the integrated unit may be implemented in hardware or in a combination of hardware and software functional units.

[0124] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0125] The above description is merely an embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A data processing method for a chip, characterized in that, The method includes: In response to a target triggering condition, the count values ​​of each performance counter in the chip are collected in groups to obtain multiple sets of count data; each set of count data contains the count values ​​of multiple performance counters; The multiple sets of counting data are compressed separately to obtain multiple sets of compressed counting data; The compressed counting data is sent to the memory in multiple sets.

2. The data processing method according to claim 1, characterized in that, The grouping collects the count values ​​of each performance counter in the chip, obtaining multiple sets of count data, including: The performance counters are grouped to obtain multiple counter groups; Collect the count values ​​of each performance counter in the same counter group to obtain a set of count data.

3. The data processing method according to claim 2, characterized in that, The method further includes: Based on the target compression method, multiple sets of the count data are compressed separately to obtain multiple sets of compressed count data; the grouping method of each performance counter corresponds to the compression ratio influence factor of the target compression method.

4. The data processing method according to claim 3, characterized in that, The process of grouping the performance counters to obtain multiple counter groups includes: When the compression ratio influence factor of the target compression method includes the degree of difference between count values, the performance counters are grouped based on their counting frequency to obtain multiple counter groups.

5. The data processing method according to claim 4, characterized in that, Based on the counting frequency, each of the performance counters is divided into multiple counter groups. The difference between the counting frequencies of each performance counter in the counter group is less than the difference threshold. The lower the degree of difference between the count values ​​in the counting data, the smaller the compression ratio of the counting data compressed using the target compression method.

6. The data processing method according to claim 5, characterized in that, The performance counters are divided into multiple counter groups based on the counting frequency, including at least one of the following: The first performance counter in each of the aforementioned performance counters is assigned to a first counter group; the counting frequency of the first performance counter is less than the difference threshold. The second performance counter in each of the performance counters is assigned to a second counter group; the difference between the counting frequency of the second performance counter and the clock frequency of the chip is less than the difference threshold.

7. The data processing method according to claim 6, characterized in that, The method of dividing each performance counter into multiple counter groups based on the counting frequency also includes: Multiple third performance counters are determined from the aforementioned performance counters; the counting frequency of the third performance counters is determined based on the real-time load of the chip. Based on the load type and / or the pipeline to which they belong, the third performance counters are grouped to obtain multiple third counter groups.

8. The data processing method according to claim 2, characterized in that, The process of grouping the performance counters to obtain multiple counter groups includes: The grouping granularity is determined based on the maximum transmission bandwidth between the chip and the memory, and the reference compression ratio corresponding to the target compression method. Based on the grouping granularity, the performance counters are grouped to obtain multiple counter groups; The step of compressing multiple sets of counting data to obtain multiple sets of compressed counting data includes: Based on the target compression method, multiple sets of the counting data are compressed to obtain multiple sets of compressed counting data.

9. The data processing method according to claim 8, characterized in that, The determination of grouping granularity based on the maximum transmission bandwidth between the chip and the memory, and the reference compression ratio corresponding to the target compression method, includes: The packet granularity is determined based on the ratio of the maximum transmission bandwidth to the reference data volume; the reference data volume is the product of the data volume of a single count value and the reference compression ratio.

10. The data processing method according to any one of claims 1 to 9, characterized in that, The multiple sets of compressed count data in the memory are used to decompress and combine the data to obtain the performance data of the chip.

11. A chip, characterized in that, include: The count value collection module is used to collect the count values ​​of each performance counter in the chip in groups to obtain multiple sets of count data; Each set of the count data contains the count values ​​of multiple performance counters; The compression module is used to compress the multiple sets of counting data respectively to obtain multiple sets of compressed counting data; The sending module is used to send multiple sets of the compressed counting data to the memory respectively.

12. An electronic device, characterized in that, It includes a processor and memory, the processor including the chip as described in claim 11.

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