Cascade input comparator with low noise and low power consumption

Abstract

The invention discloses a low-noise low-power-consumption cascade input comparator which comprises a pre-amplification stage and a latch stage, the pre-amplification stage is used for amplifying a pair of differential signals input from the outside, the amplified differential signals are obtained and output to the latch stage, and the latch stage is used for latching the amplified differential signals. The latch stage is used for keeping a latch state and outputting a differential comparison result, the pre-amplification stage is used for inputting a pair of differential signals by arranging a three-stage cascade structure consisting of three pairs of input geminate transistors, and is used for preventing all connection nodes of the pre-amplification stage and the latch stage from being completely discharged to the ground by arranging a pair of cross coupling geminate transistors, so that charge storage is realized; the circuit has the advantages of low input reference noise, no consumption of a large amount of extra area and power consumption, small area and low power consumption.

Description

Technical Field

[0001] This invention relates to comparators, and more particularly to a low-noise, low-power cascaded input comparator. Background Technology

[0002] In modern electronic systems, analog-to-digital converters (ADCs) play a crucial role, serving as a bridge between the physical and digital worlds. As an important module in signal processing systems, ADCs are widely used in various sensing systems, mobile devices, and the increasingly prevalent wearable devices. Among them, successive approximation ADCs (SAR ADCs), thanks to their highly digitized structure, are easily scalable across different processes and power supply voltages, driving the development of SAR ADCs towards higher precision and lower power consumption.

[0003] As the core module of a SAR ADC, the comparator accounts for 50%-60% of the SAR ADC's power consumption and is also the main source of quantization noise. The comparator's performance indicators, such as delay, noise, and power consumption, directly determine the SAR ADC's conversion speed, accuracy, and power consumption. With the development of integrated circuit technology, advanced processes and low power supply voltage designs have placed more stringent requirements on quantization noise, necessitating low-power, low-noise comparators for SAR ADCs to achieve better performance. Comparators can be divided into two categories: static comparators and dynamic comparators. Static comparators are always in operation, relying on quiescent current to sustain operation, resulting in high static power consumption and low operating speed. Dynamic comparators rely on clock signal control, consuming energy only during the comparison phase, and have no static power consumption, resulting in lower power consumption and faster operating speed compared to static comparators.

[0004] Strong ARM latch comparators are commonly used dynamic comparators, featuring full-swing output and strong positive feedback, and were widely used in early SAR ADCs. However, because Strong ARM latch comparators are single-stage architectures consisting of a differential input stage and a latch stage, the lack of isolation between the differential input stage and the latch stage makes them susceptible to noise and power supply voltage disturbances.

[0005] As an alternative to the Strong ARM latch comparator, the dual-tailed dynamic latch comparator adopts a two-stage structure consisting of a preamplifier stage and a latch stage. The dynamic preamplifier is used as the preamplifier stage and is separated from the latch stage. It is not easily affected by noise and power supply voltage disturbances, can achieve a larger input common-mode range, and is more suitable for low-voltage operation.

[0006] Figure 1This demonstrates a widely used conventional dual-tailed latch comparator, comprising two stages: a preamplifier stage and a latch stage. The preamplifier stage consists of NMOS transistors M1, M2, and M3 and PMOS transistors M4 and M5, while the latch stage consists of NMOS transistors M6, M7, M8, and M9 and PMOS transistors M10, M11, M12, and M13. When the clock signal CLK = 0 (i.e., CLK is low), the dual-tailed latch comparator is in the reset phase, with M4 and M5 turned on and M3 turned off. At this time, nodes N and P are pre-charged to a high level. Simultaneously, the signal CLKB = 1 (i.e., CLKB is high), turning on M6 and M9, and resetting nodes OUTP and OUTN to a low level. When the clock signal CLK = 1 (i.e., CLK is high), the dual-tailed latch comparator is in the comparison phase, M3 is in the on state, and M4 and M5 are in the off state. Nodes N and P begin to discharge. Due to the different input signals INN and INP voltages, the discharge rates of nodes N and P are different, and the conduction times of M10 and M11 will be inconsistent. When the common-mode voltage of nodes N and P approaches the threshold voltage of M10 and M11, the latch stage starts to work. The voltages of nodes N and P are amplified by the positive feedback of the cross-coupled latch structure composed of transistors M7, M12, M8, and M13, and finally output high or low levels at the output terminals OUTP and OUTN.

[0007] With the development of integrated circuit technology, advanced processes and low power supply voltage designs have placed more stringent requirements on quantization noise. SAR ADCs require low-power, low-noise comparators to achieve better performance. The pre-amplification stage of the aforementioned dual-tailed latch comparator is mainly used for voltage amplification; therefore, the noise and power consumption of this dual-tailed latch comparator largely depend on its pre-amplification stage. The main noise source is the input pair composed of NMOS transistors M1 and M2, and the input reference noise power σ of NMOS transistor M1 is... amp，M1 The input reference noise power σ of M2 amp，M2 This can be expressed using formulas (1) and (2) respectively:

[0008]

[0009] Where k is the Boltzmann constant, with a value of 1.38 × 10⁻²³ J / K, T is the thermodynamic temperature, typically T = 300 K, γ is the noise scaling factor, ζ is a non-ideal constant, approximated as 1 for molecules in the calculation, q is the electron charge, with a value of 1.6 × 10⁻¹⁹ C, and V TH C represents the threshold voltage of NMOS transistors M1 and M2. N Let C be the capacitance at node N. P Let C be the capacitance at node P. Therefore, the input reference noise power of the aforementioned dual-tailed latch comparator is mainly related to the capacitance C. N and CP This is relevant. Currently, dual-tailed latch comparators typically increase C by adding load capacitors at nodes N and P. N and C P To reduce its input reference noise (i.e., equivalent input noise). However, according to the above formulas (1) and (2), for every halving of the input reference noise power of NMOS transistors M1 and M2, C N and C P It needs to be increased to 4 times its original size, which will not only consume a lot of extra area, but also result in high power consumption due to repeated charging and discharging of the added capacitor. Summary of the Invention

[0010] The technical problem to be solved by the present invention is to provide a low-noise, low-power cascaded input comparator that has low input reference noise, does not consume a large amount of additional area and power consumption, and has a small area and low power consumption.

[0011] The technical solution adopted by the present invention to solve the above-mentioned technical problems is as follows: a low-noise, low-power cascaded input comparator, including a pre-amplification stage and a latching stage. The pre-amplification stage is used to amplify a pair of externally input differential signals to obtain an amplified differential signal, which is then output to the latching stage. The latching stage is used to latch the amplified differential signal, maintain the latched state, and output the differential comparison result. The pre-amplification stage uses a three-stage cascaded structure composed of three pairs of input transistors to input a pair of differential signals, and uses a pair of cross-coupled transistors to prevent all connection nodes of the pre-amplification stage and the latching stage from being completely discharged to ground, thereby achieving charge preservation.

[0012] Compared with the prior art, the advantages of this invention are that by setting a three-stage cascaded structure consisting of three pairs of input transistors in the pre-amplification stage to input a pair of differential signals, the pair of differential signals is first amplified three times through the three-stage cascaded structure when input to the pre-amplification stage, which significantly improves the gain of the pre-amplification stage and reduces the impact of noise on the input pair of differential signals, thereby reducing the input reference noise. In addition, by setting a pair of cross-coupled transistors, all connection nodes of the pre-amplification stage and the latching stage are prevented from being completely discharged to ground. Charge is stored at the connection nodes of the pre-amplification stage and the latching stage that are not completely discharged to ground. The stored charge can be reused in the reset phase of the next working cycle of the low-noise, low-power cascaded input comparator, thereby reducing power consumption. Thus, this invention has low input reference noise without the need for additional large-size and high-power capacitors. Compared with large-size and high-power capacitors, the three-stage cascaded structure and the cross-coupled transistors not only have smaller power consumption and smaller footprint, but the cross-coupled transistors can also reduce power consumption, thus avoiding the consumption of a large amount of extra area and power. The overall area is small and the power consumption is low.

[0013] Furthermore, the pre-amplification stage includes 15 NMOS transistors, which are respectively named as the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor, the eighth MOS transistor, the ninth MOS transistor, the tenth MOS transistor, the eleventh MOS transistor, the twelfth MOS transistor, the thirteenth MOS transistor, the fourteenth MOS transistor, and the fifteenth MOS transistor. The first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor, the fourteenth MOS transistor, and the fifteenth MOS transistor are all NMOS transistors, while the eighth MOS transistor, the ninth MOS transistor, the tenth MOS transistor, the eleventh MOS transistor, the twelfth MOS transistor, and the thirteenth MOS transistor form a cross-coupled pair.

[0014] Furthermore, the drain of the first MOSFET, the source of the fourth MOSFET, and the drain of the eighth MOSFET are connected; the source of the first MOSFET and the drain of the fourteenth MOSFET are connected; the gates of the first MOSFET, the fourth MOSFET, and the sixth MOSFET are connected, and their connection terminals are the first input terminals of the pre-amplification stage, receiving the input signal INP. The drain of the second MOSFET, the source of the fifth MOSFET, and the drain of the thirteenth MOSFET are connected; the source of the second MOSFET and the drain of the fifteenth MOSFET are connected; the gates of the second MOSFET, the fifth MOSFET, and the seventh MOSFET are connected, and their connection terminals are the second input terminals of the pre-amplification stage, receiving the input signal INN. Input signals INP and INN are a differential signal pair. The gates of the third MOSFET, the eighth MOSFET, the ninth MOSFET, the tenth MOSFET, and the eleventh MOSFET are also connected. The gates of the twelfth and thirteenth MOS transistors are connected, and their connection terminals are the clock terminals of the pre-amplification stage, used to input the clock signal CLK. The drain of the third MOS transistor is connected to the source of the fourteenth and fifteenth MOS transistors, respectively. The source of the third MOS transistor is the ground terminal of the pre-amplification stage, used for grounding. The drains of the fourth, sixth, and ninth MOS transistors are connected. The drains of the sixth, tenth, and fifteenth MOS transistors are connected, and their connection terminals are the first output terminals of the pre-amplification stage. The drains of the fifth, seventh, and twelfth MOS transistors are connected. The drains of the seventh, eleventh, and fourteenth MOS transistors are connected, and their connection terminals are the second output terminals of the pre-amplification stage. The sources of the eighth to thirteenth MOS transistors are all connected to the power supply voltage VDD.

[0015] Furthermore, the latch stage includes eight MOS transistors, which are referred to as the sixteenth MOS transistor, the seventeenth MOS transistor, the eighteenth MOS transistor, the nineteenth MOS transistor, the twentieth MOS transistor, the twenty-first MOS transistor, the twenty-second MOS transistor, and the twenty-third MOS transistor. The sixteenth MOS transistor, the seventeenth MOS transistor, the eighteenth MOS transistor, and the nineteenth MOS transistor are all NMOS transistors, while the twentieth MOS transistor, the twenty-first MOS transistor, the twenty-second MOS transistor, and the twenty-third MOS transistor are all PMOS transistors.

[0016] Furthermore, the source terminals of the sixteenth MOS transistor to the nineteenth MOS transistor are connected, and their connection terminals are the ground terminals of the latch stage for grounding. The gate terminals of the sixteenth MOS transistor and the nineteenth MOS transistor are connected, and their connection terminals are the clock terminals of the latch stage for receiving the clock signal CLKB, which is the inverted signal of the clock signal CLK. The drain terminals of the sixteenth MOS transistor, the seventeenth MOS transistor, the twentieth MOS transistor, the eighteenth MOS transistor, and the twenty-third MOS transistor are connected, and their connection terminals are the first output terminals OUTP of the latch stage. The drain terminals of the nineteenth MOS transistor, the eighteenth MOS transistor, and the twenty-first MOS transistor are connected. The drain of the 17th MOS transistor, the gate of the 22nd MOS transistor, and the gate of the 23rd MOS transistor are connected, and their connection point is the second output terminal OUTN of the latch stage. The gate of the 20th MOS transistor is the first input terminal of the latch stage and is connected to the first output terminal of the pre-amplification stage. The source of the 20th MOS transistor is connected to the drain of the 22nd MOS transistor. The gate of the 21st MOS transistor is the second input terminal of the latch stage and is connected to the second output terminal of the pre-amplification stage. The source of the 21st MOS transistor is connected to the drain of the 23rd MOS transistor. The sources of the 22nd and 23rd MOS transistors are both connected to the power supply voltage VDD. The first and second output terminals of the latch stage are used to output the differential comparison result. Attached Figure Description

[0017] Figure 1 This is a circuit diagram of a traditional dual-tailed latch comparator.

[0018] Figure 2 This is a circuit diagram of the low-noise, low-power cascaded input comparator of the present invention;

[0019] Figure 3 This is a layout of the low-noise, low-power cascaded input comparator of the present invention;

[0020] Figure 4 This is a schematic diagram of the voltage variation at the pre-amplifier stage of the low-noise, low-power cascaded input comparator of the present invention.

[0021] Figure 5 This is a simulation diagram of the voltage changes at the two output terminals of the preamplifier stage of the low-noise, low-power cascaded input comparator of the present invention.

[0022] Figure 6 This is a functional simulation diagram of the low-noise, low-power cascaded input comparator of the present invention. Detailed Implementation

[0023] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0024] Example 1: A low-noise, low-power cascaded input comparator includes a pre-amplification stage and a latching stage. The pre-amplification stage amplifies a pair of externally input differential signals to obtain an amplified differential signal, which is then output to the latching stage. The latching stage latches the amplified differential signal, maintains the latched state, and outputs the differential comparison result. The pre-amplification stage uses a three-stage cascaded structure consisting of three pairs of input transistors to input a pair of differential signals, and uses a pair of cross-coupled transistors to prevent all connection nodes of the pre-amplification stage and the latching stage from being completely discharged to ground, thus achieving charge preservation.

[0025] In this embodiment, when a pair of differential signals are input to the pre-amplification stage, they are first amplified three times through a three-stage cascaded structure. This amplifies the differential signals by a factor of three, significantly improving the gain of the pre-amplification stage and reducing the impact of noise on the differential signals, thereby reducing input reference noise. Additionally, a pair of cross-coupled transistors prevents the connection node between the pre-amplification stage and the latch stage from completely discharging to ground. Charge is stored at this incompletely discharged connection node, and the stored charge can be reused during the reset phase of the next operating cycle of the low-noise, low-power cascaded input comparator, thus reducing power consumption. Since both the three-stage cascaded structure and the pair of cross-coupled transistors are implemented using MOSFETs, their power consumption and area are smaller compared to capacitors, thus avoiding significant additional area and power consumption. The overall area is small, and the cross-coupled transistors further reduce power consumption, resulting in lower overall power consumption.

[0026] Example 2: This example is basically the same as Example 1, except that: Figure 2As shown, in this embodiment, the pre-amplification stage includes 15 NMOS transistors, which are respectively named as the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, the fourth MOS transistor M4, the fifth MOS transistor M5, the sixth MOS transistor M6, the seventh MOS transistor M7, the eighth MOS transistor M8, the ninth MOS transistor M9, the tenth MOS transistor M10, the eleventh MOS transistor M11, the twelfth MOS transistor M12, the thirteenth MOS transistor M13, the fourteenth MOS transistor M14, and the fifteenth MOS transistor M15. 4. The fifth MOSFET M5, the sixth MOSFET M6, the seventh MOSFET M7, the fourteenth MOSFET M14, and the fifteenth MOSFET M15 are all NMOS transistors. The eighth MOSFET M8, the ninth MOSFET M9, the tenth MOSFET M10, the eleventh MOSFET M11, the twelfth MOSFET M12, and the thirteenth MOSFET M13 are all PMOS transistors. The first MOSFET M1, the second MOSFET M2, the fourth MOSFET M4, the fifth MOSFET M5, the sixth MOSFET M6, and the seventh MOSFET M7 form three pairs of input transistors. The fourteenth MOSFET M14 and the fifteenth MOSFET M15 form a cross-coupled pair.

[0027] In this embodiment, the drain of the first MOSFET M1, the source of the fourth MOSFET M4, and the drain of the eighth MOSFET M8 are connected. The connection point is called node N1, and the voltage at that point is denoted as V. N1 The source of the first MOSFET M1 is connected to the drain of the fourteenth MOSFET M14. The gates of the first MOSFET M1, the fourth MOSFET M4, and the sixth MOSFET M6 are connected, and their connection point is the first input terminal of the pre-amplifier stage, receiving the input signal INP. The drain of the second MOSFET M2, the source of the fifth MOSFET M5, and the drain of the thirteenth MOSFET M13 are connected. This connection point is called node P1, and the voltage at that point is denoted as V. P1The source of the second MOSFET M2 and the drain of the fifteenth MOSFET M15 are connected. The gates of the second MOSFET M2, the fifth MOSFET M5, and the seventh MOSFET M7 are connected, and their connection point is the second input terminal of the pre-amplification stage, receiving the input signal INN. The input signals INP and INN are a differential signal pair. The gates of the third MOSFET M3, the eighth MOSFET M8, the ninth MOSFET M9, the tenth MOSFET M10, the eleventh MOSFET M11, and the tenth MOSFET M2 are connected. The gates of the second MOSFET M12 and the thirteenth MOSFET M13 are connected, and their connection terminals are the clock terminals of the pre-amplifier stage, used to input the clock signal CLK. The drain of the third MOSFET M3 is connected to the source of the fourteenth MOSFET M14 and the source of the fifteenth MOSFET M15, respectively. The source of the third MOSFET M3 is the ground terminal of the pre-amplifier stage, used for grounding. The drains of the fourth MOSFET M4, the source of the sixth MOSFET M6, and the drain of the ninth MOSFET M9 are connected, and the connection point is called node N2, where the voltage is denoted as V. N2 The drain of the sixth MOSFET M6, the drain of the tenth MOSFET M10, and the gate of the fifteenth MOSFET M15 are connected, and their connection point is the first output terminal of the pre-amplification stage (called node N3), where the voltage is denoted as V. N3 The drain of the fifth MOSFET M5, the source of the seventh MOSFET M7, and the drain of the twelfth MOSFET M12 are connected. This connection point is called node P2, and the voltage at this point is denoted as V. P2 The drain of the seventh MOSFET M7, the drain of the eleventh MOSFET M11, and the gate of the fourteenth MOSFET M14 are connected, and their connection point is the second output terminal of the pre-amplification stage (called node P3), where the voltage is denoted as V. P3 The sources of the eighth MOSFET M8 to the thirteenth MOSFET M13 are all connected to the power supply voltage VDD.

[0028] In this embodiment, the latch stage includes eight MOS transistors, which are referred to as the sixteenth MOS transistor M16, the seventeenth MOS transistor M17, the eighteenth MOS transistor M18, the nineteenth MOS transistor M19, the twentieth MOS transistor M20, the twenty-first MOS transistor M21, the twenty-second MOS transistor M22, and the twenty-third MOS transistor M23. The sixteenth MOS transistor M16, the seventeenth MOS transistor M17, the eighteenth MOS transistor M18, and the nineteenth MOS transistor M19 are all NMOS transistors, while the twentieth MOS transistor M20, the twenty-first MOS transistor M21, the twenty-second MOS transistor M22, and the twenty-third MOS transistor M23 are all PMOS transistors.

[0029] In this embodiment, the source terminals of the sixteenth MOSFET M16 to the nineteenth MOSFET M19 are connected, and their connection terminals are the ground terminals of the latch stage for grounding. The gates of the sixteenth MOSFET M16 and the nineteenth MOSFET M19 are connected, and their connection terminals are the clock terminals of the latch stage for receiving the clock signal CLKB, which is the inverted signal of the clock signal CLK. The drains of the sixteenth MOSFET M16, the drains of the seventeenth MOSFET M17, the drains of the twentieth MOSFET M20, the gates of the eighteenth MOSFET M18, and the gates of the twenty-third MOSFET M23 are connected, and their connection terminals are the first output terminals OUTP of the latch stage. The drains of the nineteenth MOSFET M19, the drains of the eighteenth MOSFET M18, and the gates of the twenty-first MOSFET M19 are connected. The drain of M21, the gate of the seventeenth MOSFET M17, and the gate of the twenty-second MOSFET M22 are connected, and their connection point is the second output terminal OUTN of the latch stage. The gate of the twentieth MOSFET M20 is the first input terminal of the latch stage and is connected to the first output terminal of the pre-amplification stage. The source of the twentieth MOSFET M20 is connected to the drain of the twenty-second MOSFET M22. The gate of the twenty-first MOSFET M21 is the second input terminal of the latch stage and is connected to the second output terminal of the pre-amplification stage. The source of the twenty-first MOSFET M21 is connected to the drain of the twenty-third MOSFET M23. The sources of the twenty-second MOSFET M22 and the twenty-third MOSFET M23 are both connected to the power supply voltage VDD. The first and second output terminals of the latch stage are used to output the differential comparison result.

[0030] The low-noise, low-power cascaded input comparator of this invention is laid out in a completely symmetrical manner using TSMC's 65nm process, as shown in the following diagram. Figure 3 As shown, analysis Figure 3 It can be seen that the effective area of ​​the low-noise, low-power cascaded input comparator of the present invention is 114µm. 2 (7.52μm×15.16μm), with a relatively small area consumed.

[0031] The working principle of the low-noise, low-power cascaded input comparator of this invention is as follows:

[0032] When the clock signal CLK = 0 (low level), the low-noise, low-power cascaded input comparator of this invention is in the reset phase. The eighth, ninth, tenth, eleventh, eleventh, and thirteenth MOS transistors M10, M11, M12, and M13 are turned on. The internal nodes N1, N2, N3, P1, P2, and P3 of the preamplifier stage are reset to high level. At the same time, the clock signal CLKB = 1 (high level), the sixteenth and nineteenth MOS transistors M16 and M19 are turned on, and the first output terminal OUTP and the second output terminal OUTN of the latch stage are both reset to low level.

[0033] When the clock signal CLK = 1 (high level), the low-noise, low-power cascaded input comparator of this invention is in the comparison phase, the third MOSFET M3 is turned on, and the first MOSFET M1, second MOSFET M2, fourth MOSFET M4, fifth MOSFET M5, sixth MOSFET M6, and seventh MOSFET M7, which are three pairs of input transistors in a three-stage cascaded structure, are turned on in sequence and have corresponding slow-down outputs. First, the voltage V at node N1... N1 and the voltage V at node P1 P1 The voltage V decreases at different rates depending on the magnitudes of the input signals INP and INN. Assuming input signal INN > input signal INP, then... P1 The voltage drops faster, reaching the voltage value that turns on the fifth MOSFET M5 more quickly. After the fifth MOSFET M5 turns on, the voltage V at node P2 will... P2 The voltage starts to decrease, and after a period of time, when the fourth MOSFET M4 also turns on, the voltage V at node N2... N2 It then begins to decrease at a slower rate. When the voltage V P2 When the voltage drops to the level that turns on the seventh MOSFET M7, the voltage V at node P3 is... P3 The voltage starts to decrease, and after a period of time, when the sixth MOSFET M6 also turns on, the voltage V at node N3... N3 It begins to decrease at a slower rate. At this point, the differential signal pair consisting of input signals INP and INN has undergone three amplifications, increasing the gain by approximately three times. When the voltage V at node P3... P3 When the voltage drops to near the threshold voltage of the fourteenth MOSFET M14, the discharge rate of node N3 decreases, and eventually tends to remain static as the fourteenth MOSFET M14 is completely turned off. At this point, the voltage V of node N3 is... N3 The charge will remain unchanged and will be stored at node N3, reused when node N3 is charged in the next clock cycle to reduce power consumption. Finally, when the voltage V at node P3... P3 When the voltage drops to the threshold voltage of the 21st MOSFET M21, the latch stage starts to work, latches the amplified differential signal, and finally outputs a pair of differential comparison results at its first output terminal OUTP and second output terminal OUTN. The pair of differential comparison results consists of a high level and a low level.

[0034] When the input signal INN > the input signal INP, node N3 will store charge, and node P3 will completely discharge. When the input signal INP > the input signal INN, node P3 will store charge, and node N3 will completely discharge.

[0035] Figure 4 The voltage variation process of each node in the pre-amplifier stage of the low-noise, low-power cascaded input comparator of the present invention is shown. Figure 4 China V COMThe common-mode voltage of the differential input signals INN and INP is (INN+INP) / 2, V. TH The threshold voltages for the first MOSFET M1, the second MOSFET M2, the fourth MOSFET M4, the fifth MOSFET M5, the sixth MOSFET M6, and the seventh MOSFET M7 are given. The node voltages corresponding to larger input signals decrease faster. For example, if input signal INP > input signal INN, then V... N1 V N2 V N3 The decline was relatively rapid, V P1 V P2 V P3 The decline is slower, and vice versa, V N1 V N2 V N3 The decline was slow, V P1 V P2 V P3 The decline was relatively rapid.

[0036] Under the conditions of a clock signal frequency of 500MHz and differential signals INP and INN with a common-mode voltage of 0.6mV, the voltages of nodes N3 and P3 in the preamplifier stage of the low-noise, low-power cascaded input comparator of this invention were simulated, and the results are as follows: Figure 5 The simulation diagram shows the voltage changes at nodes N3 and P3. Analysis. Figure 5 It can be seen that the voltage V P3 The direct drop from high to low level indicates that node P3 is completely discharged. N3 The fact that the voltage drops from high level to a certain point and then stops indicates that node N3 stops discharging after a certain period of time, thus storing a portion of the charge for reuse.

[0037] The low-noise, low-power cascaded input comparator of this invention was simulated under the conditions of a clock signal frequency of 500MHz and input signals INP and INN being differential signals with a common-mode voltage of 0.6mV. The results are as follows: Figure 6 The simulation diagram shown is for functional purposes. Analysis. Figure 6 It can be seen that when the input signal INP > INN, the first output terminal OUTP of the latch stage outputs a high level, and the second output terminal OUTN outputs a low level. When the input signal INN > INP, the second output terminal OUTN of the latch stage outputs a high level, and the first output terminal OUTP outputs a low level. Therefore, it can be seen that the low-noise, low-power cascaded input comparator of the present invention has correct operating logic.

[0038] In the low-noise, low-power cascaded input comparator of the present invention, the gains provided by the input pairs of transistors M1 and M2, M4 and M5, M6 and M7 in the pre-amplification stage are all the same as those provided by a pair of input transistors in a conventional dual-tailed latch comparator. Therefore, compared with the conventional dual-tailed latch comparator using a single input pair, the low-noise, low-power cascaded input comparator of the present invention increases the gain of the pre-amplification stage by approximately three times through the three pairs of input transistors M1 and M2, M4 and M5, and M6 and M7.

[0039] The total input reference noise σ of the low-noise, low-power cascaded input comparator of this invention c It can be represented as:

[0040]

[0041] Where σ amp For the input reference noise of the single-input pair transistors, A v For the gain of a single-input pair transistor, σ latch Let S represent the latch stage noise, and S be the number of cascaded input pairs. The low-noise, low-power cascaded input comparator of this invention uses three pairs of input transistors: the first MOS transistor M1, the second MOS transistor M2, the fourth MOS transistor M4, the fifth MOS transistor M5, and the sixth MOS transistor M6 and the seventh MOS transistor M7 cascaded together. Therefore, S = 3. Clearly, compared to traditional dual-tailed latch comparators, the low-noise, low-power cascaded input comparator of this invention effectively reduces the overall input reference noise and achieves the same noise requirements with lower power consumption.

[0042] The pre-amplifier stage of the low-noise, low-power cascaded input comparator of this invention, after incorporating the fourteenth MOSFET M14 and the fifteenth MOSFET M15, prevents nodes N3 and P3 from completely discharging to ground, allowing the charge to be stored and reused during the reset phase of the next cycle, thereby reducing power consumption. When the input signal INN > INP, node N3 stores charge, and node P3 completely discharges. The energy saved by each charge reuse is:

[0043] ΔE=VDD·C N ·V N3

[0044] Where C N Let V be the parasitic capacitance at node N3, and V be the voltage at node N3. N3 After the comparison, it will remain unchanged, and its magnitude is related to the differential input signals INN and INP. If the voltage difference between the differential input signals INN and INP is large, the fourteenth MOSFET M14 will turn off earlier, causing V... N3Maintain a higher voltage. If the voltage difference between the differential input signals INN and INP is small, the fourteenth MOSFET M14 will turn off later, at which point V N3 If the level has dropped to a low level, it will lead to a decrease in charge reuse efficiency.

[0045] When the input signal INP > INN, node P3 will store charge, and node N3 will be completely discharged. The energy saved by each charge reuse is:

[0046] ΔE=VDD·C P ·V P3

[0047] Where C P Let V be the parasitic capacitance at node P3, and V be the voltage at node P3. P3 After the comparison, it will remain unchanged, and its magnitude is related to the differential input signals INN and INP. If the voltage difference between the differential input signals INN and INP is large, the fifteenth MOSFET M15 will turn off earlier, causing V... P3 Maintain a higher voltage. If the voltage difference between the differential input signals INN and INP is small, the fifteenth MOSFET M15 will turn off later, at which point V P3 If the level drops to a low point, it will lead to a decrease in charge reuse efficiency. After testing, Figure 1 To achieve the same noise level as the low-noise, low-power cascaded input comparator of this invention, a conventional dual-tailed latch comparator would require capacitors with a capacitance of approximately 11.6 fF at nodes N and P, respectively. These capacitors would have a surface area of ​​approximately 49.6 μm. 2 With a clock signal frequency of 500MHz and the same input signal, the average power consumption of the conventional dual-tailed latch comparator with added capacitors is about 41.7% higher than the average power consumption of the low-noise, low-power cascaded input comparator of this invention.

Claims

1. A low-noise, low-power cascaded input comparator, comprising a pre-amplification stage and a latching stage, wherein the pre-amplification stage amplifies a pair of externally input differential signals to obtain amplified differential signals which are output to the latching stage, and the latching stage latches the amplified differential signals, maintains the latched state, and outputs the differential comparison result, characterized in that... The pre-amplification stage inputs a pair of differential signals by setting up a three-stage cascaded structure consisting of three pairs of input transistors, and sets up a pair of cross-coupled transistors to prevent all connection nodes of the pre-amplification stage and the latching stage from being completely discharged to ground, thereby achieving charge preservation.

2. The low-noise, low-power cascaded input comparator according to claim 1, characterized in that... The pre-amplification stage includes 15 NMOS transistors, which are referred to as the first MOS transistor, second MOS transistor, third MOS transistor, fourth MOS transistor, fifth MOS transistor, sixth MOS transistor, seventh MOS transistor, eighth MOS transistor, ninth MOS transistor, tenth MOS transistor, eleventh MOS transistor, twelfth MOS transistor, thirteenth MOS transistor, fourteenth MOS transistor, and fifteenth MOS transistor. The first MOS transistor, second MOS transistor, third MOS transistor, fourth MOS transistor, fifth MOS transistor, sixth MOS transistor, fourteenth MOS transistor, and fifteenth MOS transistor are all NMOS transistors, while the eighth MOS transistor, ninth MOS transistor, tenth MOS transistor, eleventh MOS transistor, twelfth MOS transistor, and thirteenth MOS transistor are all PMOS transistors. The first MOS transistor, second MOS transistor, fourth MOS transistor, fifth MOS transistor, sixth MOS transistor, and seventh MOS transistor form three input pairs, and the fourteenth MOS transistor and fifteenth MOS transistor form a cross-coupled pair.

3. The low-noise, low-power cascaded input comparator according to claim 2, characterized in that... The drain of the first MOSFET, the source of the fourth MOSFET, and the drain of the eighth MOSFET are connected. The source of the first MOSFET and the drain of the fourteenth MOSFET are connected. The gates of the first MOSFET, the fourth MOSFET, and the sixth MOSFET are connected, and their connection points are the first input terminals of the pre-amplification stage, receiving the input signal INP. The drains of the second MOSFET, the source of the fifth MOSFET, and the drain of the thirteenth MOSFET are connected. The source of the second MOSFET and the drain of the fifteenth MOSFET are connected. The gates of the second MOSFET, the fifth MOSFET, and the seventh MOSFET are connected, and their connection points are the second input terminals of the pre-amplification stage, receiving the input signal INN. Input signals INP and INN are a differential signal pair. The gates of the third MOSFET, the eighth MOSFET, the ninth MOSFET, the tenth MOSFET, and the eleventh MOSFET are connected. The gates of the twelfth and thirteenth MOS transistors are connected, and their connection terminals are the clock terminals of the pre-amplification stage, used to input the clock signal CLK. The drain of the third MOS transistor is connected to the source of the fourteenth and fifteenth MOS transistors, respectively. The source of the third MOS transistor is the ground terminal of the pre-amplification stage, used for grounding. The drains of the fourth, sixth, and ninth MOS transistors are connected. The drains of the sixth, tenth, and fifteenth MOS transistors are connected, and their connection terminals are the first output terminals of the pre-amplification stage. The drains of the fifth, seventh, and twelfth MOS transistors are connected. The drains of the seventh, eleventh, and fourteenth MOS transistors are connected, and their connection terminals are the second output terminals of the pre-amplification stage. The sources of the eighth to thirteenth MOS transistors are all connected to the power supply voltage VDD.

4. The low-noise, low-power cascaded input comparator according to claim 3, characterized in that... The latch stage includes eight MOS transistors, which are referred to as the sixteenth MOS transistor, the seventeenth MOS transistor, the eighteenth MOS transistor, the nineteenth MOS transistor, the twentieth MOS transistor, the twenty-first MOS transistor, the twenty-second MOS transistor, and the twenty-third MOS transistor. The sixteenth MOS transistor, the seventeenth MOS transistor, the eighteenth MOS transistor, and the nineteenth MOS transistor are all NMOS transistors, while the twentieth MOS transistor, the twenty-first MOS transistor, the twenty-second MOS transistor, and the twenty-third MOS transistor are all PMOS transistors.

5. A low-noise, low-power cascaded input comparator according to claim 4, characterized in that... The source terminals of the sixteenth MOSFET and the nineteenth MOSFET are connected, and their connection terminals are the ground terminals of the latch stage for grounding. The gate terminals of the sixteenth MOSFET and the nineteenth MOSFET are connected, and their connection terminals are the clock terminals of the latch stage for receiving the clock signal CLKB, which is the inverted signal of the clock signal CLK. The drain terminals of the sixteenth MOSFET, the seventeenth MOSFET, the twentieth MOSFET, the eighteenth MOSFET, and the twenty-third MOSFET are connected, and their connection terminals are the first output terminals OUTP of the latch stage. The drain terminals of the nineteenth MOSFET, the eighteenth MOSFET, and the twenty-first MOSFET are also connected. The gates of the seventeenth MOS transistor and the twenty-second MOS transistor are connected, and their connection point is the second output terminal OUTN of the latch stage. The gate of the twentieth MOS transistor is the first input terminal of the latch stage and is connected to the first output terminal of the pre-amplification stage. The source of the twentieth MOS transistor is connected to the drain of the twenty-second MOS transistor. The gate of the twenty-first MOS transistor is the second input terminal of the latch stage and is connected to the second output terminal of the pre-amplification stage. The source of the twenty-first MOS transistor is connected to the drain of the twenty-third MOS transistor. The sources of the twenty-second and twenty-third MOS transistors are both connected to the power supply voltage VDD. The first and second output terminals of the latch stage are used to output the differential comparison result.

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