SM4 algorithm hardware security implementation method, system and equipment for industrial control

Abstract

The invention relates to an SM4 algorithm hardware security implementation method, system and equipment for industrial control, and the method comprises the steps: building a four-stage pipeline architecture, dividing SM4 into a plurality of processing stages, and carrying out the parallel scheduling of each processing stage through the four-stage pipeline architecture; superposing a random noise current in an operation stage of the four-stage pipeline architecture; performing time domain mask conversion on an intermediate value in the SM4 algorithm processing process by adopting a dynamically updated mask parameter; through the combination of the four-stage pipeline architecture, the random noise current injection and the time domain mask conversion, the encryption throughput is improved, and the side channel attack protection capability is enhanced, so that collaborative optimization of high throughput encryption and strong side channel attack protection of an SM4 algorithm on a domestic hardware platform is realized; and the purpose of providing autonomous and controllable security data protection capability for an industrial control system is achieved.

Description

Technical Field

[0001] This invention relates to the field of hardware security technology for cryptographic algorithms, and in particular to a hardware security implementation method, system, and device for the SM4 algorithm for industrial control. Background Technology

[0002] With the increasing intelligence and networking of industrial control systems, data security has become a core challenge. SM4, a domestically developed cryptographic algorithm, is widely used in industrial equipment communication encryption, but its hardware implementation often faces a trade-off between performance and security. Traditional solutions rely heavily on imported FPGAs for hardware acceleration, resulting in high costs and difficulty in achieving independent control. While existing protection technologies (such as static masks or fixed noise injection) can resist side-channel attacks, they significantly reduce throughput or increase resource overhead. Furthermore, the stringent real-time and reliability requirements of industrial scenarios make it difficult for existing solutions to balance efficient computation with dynamic security protection. Summary of the Invention

[0003] The main objective of this invention is to provide a hardware security implementation method, system, and device for the SM4 algorithm in industrial control, so as to achieve synergistic optimization of high-throughput encryption and strong side-channel attack protection of the SM4 algorithm on a domestically produced hardware platform, and to provide industrial control systems with autonomous and controllable secure data protection capabilities.

[0004] To achieve the above objectives, this invention provides a hardware security implementation method for the SM4 algorithm for industrial control, comprising the following steps:

[0005] A four-level pipeline architecture is constructed, which divides SM4 into multiple processing stages and performs parallel scheduling of each processing stage through the four-level pipeline architecture.

[0006] Random noise current is superimposed in one computational stage of the four-stage pipeline architecture;

[0007] The intermediate values ​​processed by the SM4 algorithm are subjected to time-domain mask transformation using dynamically updated mask parameters.

[0008] By combining the four-stage pipeline architecture, the random noise current injection, and the time-domain mask transformation, the encryption throughput is improved and the side-channel attack protection capability is enhanced.

[0009] Furthermore, the steps for constructing a four-stage pipeline architecture and performing parallel scheduling of each processing stage of the SM4 algorithm include:

[0010] A four-stage pipeline architecture is constructed, dividing the SM4 algorithm into a key expansion stage, a round function calculation stage, an S-box permutation stage, and an output reconstruction stage.

[0011] Each processing stage is allocated an independent hardware logic unit, and inter-stage data interaction channels are configured.

[0012] The execution sequence of each processing stage is coordinated through a synchronous scheduling mechanism.

[0013] Furthermore, the steps for building a four-level pipeline architecture also include:

[0014] An anti-interference circuit module is integrated into the four-stage pipeline architecture to isolate the random noise current from interfering with the core operational logic.

[0015] Furthermore, the step of superimposing random noise current in one computational stage of the four-stage pipeline architecture includes:

[0016] Inject random noise current during the round function calculation stage of the four-stage pipeline architecture;

[0017] The injection intensity and frequency of the noise current are adjusted according to the preset amplitude conditions and dynamic safety monitoring results.

[0018] The dynamic security monitoring results are generated by real-time acquisition and evaluation of the power consumption characteristics of each processing stage in the four-stage pipeline architecture.

[0019] Furthermore, the step of performing time-domain masking transformation on the intermediate values ​​during the SM4 algorithm processing using dynamically updated mask parameters includes:

[0020] The intermediate values ​​processed by the SM4 algorithm are masked using dynamically updated mask parameters.

[0021] The update period of the mask parameters is adjusted periodically according to a preset time threshold.

[0022] Furthermore, the steps for performing the masking operation also include:

[0023] In the round function calculation stage of the four-stage pipeline architecture, the mask operation and the intermediate value generation process are triggered synchronously.

[0024] Embedding mask transformation logic within each clock cycle of the round function calculation phase reduces the time correlation of side channel signals.

[0025] Furthermore, steps to improve encryption throughput and enhance protection against side-channel attacks include:

[0026] The data processing path is optimized through the parallel scheduling mechanism of the four-stage pipeline architecture.

[0027] The side-channel signal characteristics are interfered with by the superposition effect of random noise current injection and time-domain masking transformation. This invention also provides a hardware security implementation system for the SM4 algorithm for industrial control, comprising:

[0028] An architecture optimization unit is used to construct a four-level pipeline architecture, which divides SM4 into multiple processing stages and performs parallel scheduling of each processing stage through the four-level pipeline architecture.

[0029] A noise injection unit is used to superimpose random noise current in one operation stage of the four-stage pipeline architecture.

[0030] The mask transformation unit is used to perform time-domain mask transformation on the intermediate values ​​in the SM4 algorithm processing process using dynamically updated mask parameters;

[0031] The security enhancement unit is used to improve encryption throughput and enhance side-channel attack protection capabilities through the combination of the four-stage pipeline architecture, the random noise current injection, and the time-domain mask transformation.

[0032] The present invention also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the above-described hardware security implementation method for the SM4 algorithm for industrial control.

[0033] The present invention also provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the above-described hardware security implementation method for the SM4 algorithm for industrial control.

[0034] The hardware security implementation method, system, and device for the SM4 algorithm in industrial control provided by this invention have the following beneficial effects: This invention effectively solves the performance and security contradiction in the hardware implementation of the SM4 algorithm in industrial control scenarios through the deep integration of a four-level pipeline architecture and dynamic security protection technology. First, by constructing a four-level pipeline architecture, the algorithm is decomposed into multi-stage parallel processing, significantly improving data throughput efficiency. At the same time, through hardware resource reuse and synchronous scheduling mechanisms, computational latency and resource consumption are minimized. Second, dynamic noise injection technology combined with time-domain mask transformation accurately interferes with side-channel signal characteristics during the round function calculation stage, disrupting the attacker's ability to correlate and analyze physical information such as power consumption and electromagnetics, thus achieving multi-layered security protection. In addition, the integrated design of the anti-interference circuit module isolates the impact of noise on the core logic while ensuring the stability of system operation. Finally, this solution achieves synergistic optimization of high-performance encryption and high-robust protection on a domestically produced hardware platform, providing industrial IoT devices with autonomous, controllable, secure, and reliable data protection capabilities, and contributing to the large-scale application and industrial upgrading of domestic cryptographic technologies. Attached Figure Description

[0035] Figure 1 This is a flowchart illustrating a hardware security implementation method for the SM4 algorithm for industrial control in one embodiment of the present invention.

[0036] Figure 2 This is a structural block diagram of a hardware security implementation system for the SM4 algorithm for industrial control, according to one embodiment of the present invention.

[0037] Figure 3 This is a schematic block diagram of the structure of a computer device according to an embodiment of the present invention.

[0038] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0040] Reference Figure 1 This is a flowchart illustrating a hardware security implementation method for the SM4 algorithm for industrial control proposed in this invention, including the following steps:

[0041] S1, construct a four-level pipeline architecture, divide SM4 into multiple processing stages, and perform parallel scheduling of each processing stage through the four-level pipeline architecture;

[0042] S2, random noise current is superimposed in one operation stage of the four-stage pipeline architecture;

[0043] S3, perform time-domain mask transformation on the intermediate values ​​in the SM4 algorithm processing process using dynamically updated mask parameters;

[0044] S4, by combining the four-stage pipeline architecture, the random noise current injection, and the time-domain mask transformation, the encryption throughput is improved and the side-channel attack protection capability is enhanced.

[0045] In one embodiment, for step S1,

[0046] The steps for constructing a four-stage pipeline architecture and performing parallel scheduling of each processing stage of the SM4 algorithm include:

[0047] A four-stage pipeline architecture is constructed, dividing the SM4 algorithm into a key expansion stage, a round function calculation stage, an S-box permutation stage, and an output reconstruction stage.

[0048] Each processing stage is allocated an independent hardware logic unit, and inter-stage data interaction channels are configured.

[0049] The execution sequence of each processing stage is coordinated through a synchronous scheduling mechanism.

[0050] In practical implementation, the SM4 algorithm is decomposed into a key expansion stage, a round function calculation stage, an S-box permutation stage, and an output recombination stage. The key expansion stage generates the round key through iterative computation, and the round function calculation stage performs a nonlinear transformation.

[0051]

[0052] The T function includes S-box permutation and linear transformation, and outputs the integrated encryption result in the recombination stage. Each stage is allocated an independent hardware logic unit (such as the LUT6 unit of Loongson FPGA), and intermediate data is transmitted through a dedicated data channel. For example, the round key generated in the key expansion stage is transmitted to the round function calculation stage in real time through a low-latency channel. At the same time, a synchronous scheduling mechanism is used to coordinate the execution timing of each stage, using a clock frequency f = 1 / T. stage (T stage The pipeline rhythm is controlled by limiting the maximum latency per stage. By reusing hardware resources between stages (such as sharing S-box lookup tables), the occupancy of logic units is reduced by 35%, and the synchronous scheduling mechanism effectively avoids pipeline conflicts, improving overall computational efficiency.

[0053] In one embodiment, the step of constructing a four-stage pipeline architecture further includes:

[0054] An anti-interference circuit module is integrated into the four-stage pipeline architecture to isolate the random noise current from interfering with the core operational logic.

[0055] Specifically, the anti-interference circuit module adopts a design combining an electromagnetic shielding layer and a low-pass filter circuit, specifically composed of distributed bead filters and decoupling capacitors. Its layout covers the power network and signal transmission path of the four-stage pipeline architecture to suppress high-frequency components of noise current. For example, in the round function calculation stage, noise current is injected into the arithmetic unit through an independent power supply line, while the power supply line of the core logic is physically isolated through the anti-interference circuit module. Its equivalent circuit model can be represented as:

[0056]

[0057] Among them, Z filter Where is the filter impedance, C is the decoupling capacitor value, L is the equivalent inductance of the ferrite bead, and R is the filter impedance. bead This refers to the resistive characteristics of the ferrite bead. This embodiment effectively balances the requirements for noise injection protection with hardware resource overhead, ensuring the stable operation of the four-stage pipeline architecture under dynamic noise interference.

[0058] In one embodiment, for step S2,

[0059] The step of superimposing random noise current in one computational stage of the four-stage pipeline architecture includes:

[0060] Inject random noise current during the round function calculation stage of the four-stage pipeline architecture;

[0061] The injection intensity and frequency of the noise current are adjusted according to the preset amplitude conditions and dynamic safety monitoring results.

[0062] The dynamic security monitoring results are generated by real-time acquisition and evaluation of the power consumption characteristics of each processing stage in the four-stage pipeline architecture.

[0063] In practical implementation, the amplitude of the noise current is determined according to a preset ratio (such as the maximum operating current I). max The 20% threshold is set, and a random waveform is generated using a Gaussian distribution model. Its mathematical expression is:

[0064]

[0065] Where A = 0.2I max μ is the mean, and σ is the variance. The dynamic security monitoring module collects power consumption characteristics (such as instantaneous current value I(t) and time integral) at each processing stage in real time, and judges the attack risk based on the power consumption correlation analysis algorithm. When an abnormal pattern is detected (such as the power consumption fluctuation frequency exceeding the threshold (10kHz), the noise injection frequency is automatically increased to the preset upper limit (such as 15kHz), and the amplitude is adjusted to 0.25I. max This embodiment enhances side-channel protection by injecting random noise current into the round function calculation stage of the four-stage pipeline architecture and dynamically adjusting noise parameters.

[0066] In one embodiment, for step S3,

[0067] The step of performing time-domain masking transformation on intermediate values ​​during the SM4 algorithm processing using dynamically updated mask parameters includes:

[0068] The intermediate values ​​processed by the SM4 algorithm are masked using dynamically updated mask parameters.

[0069] The update period of the mask parameters is adjusted periodically according to a preset time threshold.

[0070] In practice, the mask parameters are generated in real time by a hardware security module (such as a true random number generator) and distributed through an independent secure storage unit. For example, mask parameters M1 and M2 are updated every 0.5ms, with the update rule being... Where RNG(t) is a timestamp-based random number. The intermediate value X is immediately masked after being output during the round function calculation phase, and its mathematical expression is: Here, || represents bit concatenation, ensuring that the mask covers all intermediate bits. The preset time threshold is 1ms, but if the security threat level increases (such as detecting abnormal power consumption fluctuations), the update cycle can be dynamically shortened to 0.2ms.

[0071] In one embodiment, the step of performing the masking operation further includes:

[0072] In the round function calculation stage of the four-stage pipeline architecture, the mask operation and the intermediate value generation process are triggered synchronously.

[0073] Embedding mask transformation logic within each clock cycle of the round function calculation phase reduces the time correlation of side channel signals.

[0074] Specifically, in the round function computation stage of the four-stage pipeline architecture, the masking operation and the intermediate value generation process are strictly synchronized. For example, when the round function computation unit completes... During computation, the mask module receives intermediate values ​​and executes them within the same clock cycle. This ensures that unmasked data is exposed without any time gaps. The masking logic is directly integrated into the hardware circuitry of the round function calculation unit, and its operation timing is controlled by the clock signal CLK. Each time the clock rises, the mask parameter M and the intermediate value X are synchronously loaded into the XOR gate. By embedding the synchronous mask with the clock cycle, attackers cannot capture valid signal features through time sampling or electromagnetic radiation.

[0075] In one embodiment, for step S4,

[0076] Steps to improve encryption throughput and enhance protection against side-channel attacks include:

[0077] The data processing path is optimized through the parallel scheduling mechanism of the four-stage pipeline architecture.

[0078] The side-channel signal characteristics are interfered with by the superposition effect of random noise current injection and time-domain mask transformation.

[0079] In its implementation, the four-stage pipeline architecture decomposes the SM4 algorithm into four stages: key expansion, round function computation, S-box permutation, and output reconstruction. Each stage is executed in parallel by independent hardware logic units (such as the LUT6 module of Loongson FPGA). Through a synchronous scheduling mechanism (clock frequency f = 350MHz), the latency of the data interaction channel between each stage is compressed to below 0.8ns. For example, the round key generated in the key expansion stage is transmitted to the round function computation stage in real time through a dedicated low-latency channel, while the S-box permutation stage and the output reconstruction stage share hardware resources (such as S-box lookup table reuse), reducing the occupancy of logic units. In the round function computation stage, random Gaussian noise current (amplitude A = 0.2I) is used. max frequency f noise The instantaneous power consumption waveform of the power supply network injected into the arithmetic unit (>10kHz) can be expressed as follows:

[0080]

[0081] This noise is isolated from the core logic by an anti-interference circuit module (magnetic bead filter and decoupling capacitor), and only affects the side channel signal acquisition path. Simultaneously, the time-domain masking transform performs a dynamic XOR operation on the intermediate value X. The mask parameter M is updated every 0.5ms, further obfuscating data correlation. The combined effect of these two factors prevents attackers from extracting effective features through differential power analysis (DPA) or electromagnetic radiation (EMA). This embodiment achieves high throughput through a pipelined architecture with parallel design, and combines multi-dimensional interference mechanisms of noise and masking to disrupt side-channel signal characteristics, providing an SM4 hardware implementation scheme that combines performance and security for industrial control systems.

[0082] Reference Figure 2 Here is a structural block diagram of a hardware security implementation system for the SM4 algorithm for industrial control, as described in one embodiment of the present invention, comprising:

[0083] An architecture optimization unit is used to construct a four-level pipeline architecture, which divides SM4 into multiple processing stages and performs parallel scheduling of each processing stage through the four-level pipeline architecture.

[0084] A noise injection unit is used to superimpose random noise current in one operation stage of the four-stage pipeline architecture.

[0085] The mask transformation unit is used to perform time-domain mask transformation on the intermediate values ​​in the SM4 algorithm processing process using dynamically updated mask parameters;

[0086] The security enhancement unit is used to improve encryption throughput and enhance side-channel attack protection capabilities through the combination of the four-stage pipeline architecture, the random noise current injection, and the time-domain mask transformation.

[0087] For the specific implementation of each unit in the above device example, please refer to the method embodiments described above, and will not be repeated here.

[0088] Reference Figure 3 This invention also provides a computer device, which can be a server, and its internal structure can be as follows: Figure 3 As shown, the computer device includes a processor, memory, display screen, input device, network interface, and database connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores the operating system, computer programs, and database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The database stores the data corresponding to this embodiment. The network interface is used to communicate with external terminals via a network connection. When the computer program is executed by the processor, it implements the above-described method.

[0089] Those skilled in the art will understand that Figure 3 The structures shown are merely block diagrams of some structures related to the present invention and do not constitute a limitation on the computer devices on which the present invention is applied.

[0090] An embodiment of the present invention also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-described method. It is understood that the computer-readable storage medium in this embodiment can be a volatile readable storage medium or a non-volatile readable storage medium.

[0091] In summary, this invention constructs a four-stage pipeline architecture, dividing SM4 into multiple processing stages and scheduling each stage in parallel using this architecture. Random noise current is superimposed into one computational stage of the four-stage pipeline architecture. Intermediate values ​​during the SM4 algorithm processing are transformed using dynamically updated mask parameters in the time domain. Through the combination of the four-stage pipeline architecture, the random noise current injection, and the time domain mask transformation, the encryption throughput is improved, and the side-channel attack protection capability is enhanced. This achieves synergistic optimization of high-throughput encryption and strong side-channel attack protection for the SM4 algorithm on a domestically produced hardware platform, providing industrial control systems with autonomous and controllable secure data protection capabilities.

[0092] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the present invention and embodiments can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual-rate SDRAM (SSRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM, etc.

[0093] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, apparatus, article, or method that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, apparatus, article, or method. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, apparatus, article, or method that includes that element.

[0094] The above description is merely a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A hardware security implementation method for the SM4 algorithm for industrial control, characterized in that, Includes the following steps: A four-level pipeline architecture is constructed, which divides SM4 into multiple processing stages and performs parallel scheduling of each processing stage through the four-level pipeline architecture. Random noise current is superimposed in one computational stage of the four-stage pipeline architecture; The intermediate values ​​processed by the SM4 algorithm are subjected to time-domain mask transformation using dynamically updated mask parameters. By combining the four-stage pipeline architecture, the random noise current injection, and the time-domain mask transformation, the encryption throughput is improved and the side-channel attack protection capability is enhanced.

2. The hardware security implementation method for the SM4 algorithm for industrial control according to claim 1, characterized in that, The steps for constructing a four-stage pipeline architecture and performing parallel scheduling of each processing stage of the SM4 algorithm include: A four-stage pipeline architecture is constructed, dividing the SM4 algorithm into a key expansion stage, a round function calculation stage, an S-box permutation stage, and an output reconstruction stage. Each processing stage is allocated an independent hardware logic unit, and inter-stage data interaction channels are configured. The execution sequence of each processing stage is coordinated through a synchronous scheduling mechanism.

3. The hardware security implementation method for the SM4 algorithm for industrial control according to claim 1, characterized in that, The steps for constructing the four-level pipeline architecture also include: An anti-interference circuit module is integrated into the four-stage pipeline architecture to isolate the random noise current from interfering with the core operational logic.

4. The hardware security implementation method for the SM4 algorithm for industrial control according to claim 1, characterized in that, The step of superimposing random noise current in one computational stage of the four-stage pipeline architecture includes: Inject random noise current during the round function calculation stage of the four-stage pipeline architecture; The injection intensity and frequency of the noise current are adjusted according to the preset amplitude conditions and dynamic safety monitoring results. The dynamic security monitoring results are generated by real-time acquisition and evaluation of the power consumption characteristics of each processing stage in the four-stage pipeline architecture.

5. The hardware security implementation method for the SM4 algorithm for industrial control according to claim 1, characterized in that, The step of performing time-domain masking transformation on intermediate values ​​during the SM4 algorithm processing using dynamically updated mask parameters includes: The intermediate values ​​processed by the SM4 algorithm are masked using dynamically updated mask parameters. The update period of the mask parameters is adjusted periodically according to a preset time threshold.

6. The hardware security implementation method for the SM4 algorithm for industrial control according to claim 4, characterized in that, The step of performing the masking operation further includes: In the round function calculation stage of the four-stage pipeline architecture, the mask operation and the intermediate value generation process are triggered synchronously. Embedding mask transformation logic within each clock cycle of the round function calculation phase reduces the time correlation of side channel signals.

7. The hardware security implementation method for the SM4 algorithm for industrial control according to claim 1, characterized in that, The steps to improve encryption throughput and enhance side-channel attack protection include: The data processing path is optimized through the parallel scheduling mechanism of the four-stage pipeline architecture. The side-channel signal characteristics are interfered with by the superposition effect of random noise current injection and time-domain mask transformation.

8. A hardware security implementation system for the SM4 algorithm for industrial control, characterized in that, include: An architecture optimization unit is used to construct a four-level pipeline architecture, which divides SM4 into multiple processing stages and performs parallel scheduling of each processing stage through the four-level pipeline architecture. A noise injection unit is used to superimpose random noise current in one operation stage of the four-stage pipeline architecture. The mask transformation unit is used to perform time-domain mask transformation on the intermediate values ​​in the SM4 algorithm processing process using dynamically updated mask parameters; The security enhancement unit is used to improve encryption throughput and enhance side-channel attack protection capabilities through the combination of the four-stage pipeline architecture, the random noise current injection, and the time-domain mask transformation.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the hardware security implementation method of the SM4 algorithm for industrial control as described in any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the hardware security implementation method of the SM4 algorithm for industrial control as described in any one of claims 1 to 7.

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