Multi-time programmable memory device and preparation method thereof
By introducing Schottky contact structures and floating gate recess designs into multi-programmable memory devices, the problem of short circuit between the control gate and the channel caused by high-voltage programming is solved, resulting in higher reliability and shorter programming time.
Patent Information
- Application Number
- CN202511031798.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-25
- Publication Date
- 2025-10-31
AI Technical Summary
Existing multiple programmable memory devices are prone to short circuits between the control gate and the active channel during high-voltage programming, affecting the long-term reliability and lifespan of the device.
By introducing a Schottky contact structure into the memory device and employing a groove design for the floating gate region, electron tunneling is triggered by a very small forward voltage, avoiding short circuits between the control gate and the channel during high-voltage programming, while also shortening the electron transport path.
This improves the reliability and lifespan of the memory cells, reduces programming time, and enhances the operating efficiency of the device.
Smart Images
Figure CN120881993A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductors, and more specifically, to a multiple programmable memory device and a method for fabricating the same. Background Technology
[0002] Multi-Time Programmable (MTP) memory cells are a widely used non-volatile memory technology in integrated circuits. They enable post-chip parameter calibration, customer-customized functions, and can serve as internal memory storage modules within the chip. The basic principle of MTP technology is to control the capture and release of charge in the floating gate (FG), thereby adjusting the threshold voltage of the transistor and further influencing the output current characteristics to achieve data writing and erasing operations.
[0003] Existing MTP memory cells typically employ a floating gate structure, such as Figure 2 As shown. During programming operations (such as...) Figure 2 Path ① shown) or erase operation (such as Figure 2 As shown in path ②, in order to inject or remove charge carriers from the floating gate layer, a large voltage difference, approximately 4V, is typically applied between the source (S) and drain (D), while a high voltage of at least 8V is applied to the control gate (CG). This high voltage condition facilitates the entry or exit of charge carriers into or from the floating gate layer via tunneling.
[0004] However, the above operating method places high demands on the quality of the oxide layer beneath the control gate. On the one hand, the oxide layer needs to have a low defect and trap density to reduce charge loss during tunneling; on the other hand, the oxide layer needs to have sufficient thickness to withstand repeated high-voltage stress. With the increase of programming and erasing cycles, under the continuous high electric field, more defects and traps will gradually be generated in the oxide layer beneath the control gate, which may eventually lead to a short circuit between the control gate and the active channel, causing device failure and affecting its long-term reliability and lifespan.
[0005] There are currently no effective solutions to the problems in the relevant technologies. Summary of the Invention
[0006] In view of the problems in the related technologies, the present invention proposes a multiple programmable memory device and its manufacturing method to overcome the above-mentioned technical problems existing in the existing related technologies.
[0007] Therefore, the specific technical solution adopted by the present invention is as follows:
[0008] According to one aspect of the present invention, a multiple programmable memory device is provided, the memory device comprising: a substrate, wherein a buried oxide layer is disposed inside the substrate, and a first groove is formed at the top of the substrate; both the top of the substrate and the inner wall of the first groove are provided with oxide layers, a floating gate region is provided at the top of the oxide layer located on the inner wall of the first groove, and an insulating layer cooperating with the oxide layer is provided at the top of the floating gate region.
[0009] Furthermore, in order to shorten the programming time of the memory cell, a second groove is symmetrically formed at the top of the insulating layer to match the top of the buried oxide layer, and a third groove is formed on one side of the top of the insulating layer to match the top of the substrate. A barrier layer metal is provided on the inner wall of the second groove.
[0010] Furthermore, to avoid short circuits between the control gate and the active region channel and extend the lifespan of the memory cell, a metal silicide is disposed inside the third groove. The source electrode is disposed inside the barrier layer metal on the side away from the floating gate region, and the drain electrode is disposed inside the barrier layer metal on the side closer to the floating gate region. A control gate that cooperates with the insulating layer is disposed at the top of the metal silicide. The depth of the first groove is 1 / 6 to 1 / 4 of the longitudinal height of the substrate, and the substrate is intrinsic semiconductor silicon.
[0011] According to another aspect of the present invention, a method for fabricating a multiple-programmable memory device is also provided, the method comprising:
[0012] S1, Implanting a dose of 1×10⁻⁶ into the substrate 17 ~1×10 19 The oxygen atoms are removed and annealed at a temperature of 1200℃~1400℃ to allow the oxygen atoms to react with the interior of the substrate, forming a buried oxide layer below the substrate surface.
[0013] S2. Use a photomask to perform photolithography on the substrate surface, etch in the area without photoresist coverage to form the first groove, and remove the residual photoresist.
[0014] S3. An oxide layer is deposited on the substrate surface, and polysilicon is deposited and filled on the oxide layer surface. The polysilicon in the non-target area is removed by photolithography using a mask to form a floating gate area.
[0015] S4. An insulating material is deposited on the surface of the oxide layer to form an insulating layer, and a mask is used for selective etching to form the second and third grooves.
[0016] S5. Deposit barrier layer metal in the second and third grooves, remove the remaining barrier layer metal with the insulating layer as the etching stop layer, and fill the grooves with refractory metal to form metal silicide;
[0017] S6. Deposit fill metal in the barrier layer metal representation and remove the remaining metal to form the source, control gate, and drain, and the control gate extends laterally to cover the right edge of the floating gate region.
[0018] The beneficial effects of this invention are as follows:
[0019] This invention introduces a Schottky contact structure between the control gate and the active channel region. Under the condition of applying a very small positive voltage, the control gate can trigger electrons to tunnel from the channel region to the floating gate region, thereby achieving effective programming of the floating gate. This avoids the short circuit problem between the control gate and the channel that may be caused by the traditional high-voltage long-term programming process, thus improving the reliability and lifespan of the memory cell. In addition, since the floating gate region adopts a groove structure design, the electron transmission path is effectively shortened, thereby reducing the programming time and improving the operating efficiency of the device. Attached Figure Description
[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0021] Figure 1 This is a flowchart of a method for fabricating a multiple-programmable memory device according to an embodiment of the present invention;
[0022] Figure 2 This is a schematic diagram of the structure of a conventional multiple programmable device in a method for fabricating a multiple programmable memory device according to an embodiment of the present invention;
[0023] Figure 3 This is one of the structural schematic diagrams of a method for fabricating a multiple programmable memory device according to an embodiment of the present invention;
[0024] Figure 4 This is a second schematic diagram of a method for fabricating a multiple programmable memory device according to an embodiment of the present invention;
[0025] Figure 5 This is a third schematic diagram of a method for fabricating a multiple programmable memory device according to an embodiment of the present invention;
[0026] Figure 6 This is a fourth schematic diagram of a method for fabricating a multiple programmable memory device according to an embodiment of the present invention;
[0027] Figure 7 This is the fifth schematic diagram of a method for fabricating a multiple programmable memory device according to an embodiment of the present invention;
[0028] Figure 8 This is a schematic diagram of the structure of a method for fabricating a multiple programmable memory device according to an embodiment of the present invention.
[0029] In the picture:
[0030] 100. Substrate; 101. Buried oxide layer; 102. First trench; 103. Oxide layer; 104. Floating gate region; 105. Insulating layer; 106. Second trench; 107. Third trench; 108. Barrier layer metal; 109. Metal silicide; 110. Control gate; 201. Source; 202. Drain. Detailed Implementation
[0031] To further illustrate the various embodiments, the present invention provides accompanying drawings, which are part of the disclosure of the present invention. These drawings are mainly used to illustrate the embodiments and can be used in conjunction with the relevant descriptions in the specification to explain the operating principles of the embodiments. With reference to these drawings, those skilled in the art should be able to understand other possible implementation methods and the advantages of the present invention.
[0032] According to an embodiment of the present invention, a multiple programmable memory device and a method for manufacturing the same are provided.
[0033] The present invention will now be further described in conjunction with the accompanying drawings and specific embodiments, such as... Figures 3-8 As shown, according to an embodiment of the present invention, the multiple programmable memory device includes: a substrate 100, a buried oxide layer 101 disposed inside the substrate 100, and a first groove 102 formed at the top of the substrate 100; an oxide layer 103 is disposed at the top of the substrate 100 and the inner wall of the first groove 102, a floating gate region 104 is disposed at the top of the oxide layer 103 located on the inner wall of the first groove 102, and an insulating layer 105 cooperating with the oxide layer 103 is disposed at the top of the floating gate region 104.
[0034] It should be added that, such as Figure 3 As shown, a substrate 100 is provided, with a dose of 1×10⁻⁶ implanted face-down on its side. 17 ~1×10 19 Oxygen atoms are removed, and then high-temperature annealing is performed at a temperature of 1200℃ to 1400℃, so that the oxygen atoms react with the interior of the substrate 100, and finally a buried oxide layer 101 is formed under the surface of the substrate 100.
[0035] like Figure 4As shown, on the positive surface of substrate 100, based on a photomask, a groove 102 is etched downwards at the location without photoresist openings through photolithography. The depth of the groove 102 is 1 / 6 to 1 / 4 of the longitudinal height h of substrate 100. Finally, the unwanted photoresist is removed. Specifically, on the positive surface of substrate 100, based on a patterned photomask, the following steps are taken: ① spin-coating photoresist and soft baking; ② aligning and exposing the photoresist to be etched; ③ hardening after development to remove the photoresist on the upper surface of the area to be etched; ④ etching the groove 102 downwards at the location without photoresist openings to form the groove 102. Etching can be performed using plasma etching or dry etching.
[0036] like Figure 5 As shown, an oxide layer 103 is deposited on the positive surface of the substrate 100. Then, polysilicon is deposited and filled on the surface of the oxide layer 103. Finally, photolithography is performed using a photomask to etch away the excess polysilicon, forming the floating gate region 104. Specifically, an oxide layer 103 is deposited on the positive surface of the substrate 100 by vapor deposition. Then, polysilicon is deposited and filled on the surface of the oxide layer 103. Finally, using a photomask, photolithography is performed to etch away the excess polysilicon, resulting in the floating gate region 104.
[0037] In this optional embodiment, the top end of the insulating layer 105 is symmetrically provided with a second groove 106 that matches the top end of the buried oxide layer 101.
[0038] In this optional embodiment, a third groove 107 is provided on one side of the top end of the insulating layer 105 to cooperate with the top end of the substrate 100.
[0039] In this optional embodiment, the inner wall of the second groove 106 is provided with a barrier layer metal 108.
[0040] In this alternative embodiment, the interior of the third groove 107 is provided with metal silicide 109.
[0041] In this optional embodiment, a source electrode 201 is disposed inside the barrier layer metal 108 on the side away from the floating gate region 104, and a drain electrode 202 is disposed inside the barrier layer metal 108 on the side close to the floating gate region 104.
[0042] In this alternative embodiment, a control gate 110 that cooperates with the insulating layer 105 is provided at the top of the metal silicide 109.
[0043] In this optional embodiment, the depth of the first groove 102 is 1 / 6 to 1 / 4 of the longitudinal height of the substrate 100.
[0044] In this alternative embodiment, the substrate 100 is intrinsic semiconductor silicon.
[0045] It should be added that, such as Figure 6 As shown, an insulating material is deposited on its front side to form an insulating layer 105. Based on a photomask, a photolithography step is performed to etch away part of the insulating layer 105, the oxide layer 103, and the substrate 100, forming grooves 106 and 107 respectively. The longitudinal depth of the groove 106 reaches the upper surface of the buried oxide layer 101, and the longitudinal depth of the groove 107 reaches the upper surface of the substrate 100.
[0046] like Figure 7 As shown, a barrier metal layer is deposited face down on the surface of the device. An insulating layer 105 is used as an etching stop layer to etch away the excess barrier metal layer, leaving only the barrier metal layer 108 in the groove 106. A refractory metal layer is then filled into the groove 107 through a mask to form a metal silicide 109.
[0047] like Figure 8 As shown, through a metallization process, filler metal is deposited face-down on the memory cell, and then excess metal is removed to form the source 201, control gate 110, and drain 202; the control gate extends laterally to the right side of the floating gate region 104. Specifically, through a metallization process, filler metal is deposited face-down on the device using a sputtering process, and then excess metal is removed by alignment and positioning using a pattern mask, ultimately forming the source 201, control gate 110, and drain 202.
[0048] Furthermore, the working principle of a multiple programmable memory device is as follows: When a positive voltage (0.8V~1.5V) is applied to the control gate 110, a Schottky contact is formed between the control gate 110 and the active channel region in the substrate 100. At the same time, the control gate 110 is forward biased relative to the active channel region. Electrons are swept from the active channel region to the control gate 110. A positive voltage difference (source voltage > drain voltage) is applied between the source and drain. Under the action of the electric field, electrons in the control gate 110 will gradually accumulate in the left region of the control gate 110, resulting in a reduction of the charge in the control gate 110 region above the floating gate region 104, forming a positive charge region. As a result, electrons in the induced channel tunnel into the floating gate region 104, achieving the programming effect. At the same time, since the floating gate region adopts a groove structure, the distance of electron tunneling to the floating gate region 104 is shortened, that is, the programming time is shortened.
[0049] like Figure 1 As shown, according to another embodiment of the present invention, a method for fabricating a multiple-programmable memory device is also provided, the method comprising:
[0050] S1. Implant a dose of 1×10⁻⁶ into the substrate 100. 17 ~1×10 19The oxygen atoms are removed and annealed at a temperature of 1200℃~1400℃ to allow the oxygen atoms to react with the interior of the substrate 100, forming a buried oxide layer 101 below the surface of the substrate 100.
[0051] S2. Photolithography is performed on the surface of the substrate 100 using a mask. Etching is performed in the area without photoresist coverage to form the first groove 102, and the residual photoresist is removed.
[0052] S3. An oxide layer 103 is deposited on the surface of the substrate 100, and polysilicon is deposited on the surface of the oxide layer 103. The polysilicon in the non-target area is removed by photolithography using a mask to form a floating gate region 104.
[0053] S4. An insulating material is deposited on the surface of the oxide layer 103 to form an insulating layer 105, and selective etching is performed using a mask to form a second groove 106 and a third groove 107.
[0054] S5. Deposit barrier layer metal 108 in the second groove 106 and the third groove 107, remove the remaining barrier layer metal 108 with the insulating layer 105 as the etching stop layer, and fill the groove 107 with refractory metal to form metal silicide 109.
[0055] S6. Deposit fill metal in barrier layer metal 108 and remove the remaining metal to form source 201, control gate 110, and drain 202, and the control gate 110 extends laterally to cover the right edge of floating gate region 104.
[0056] In summary, by utilizing the above-mentioned technical solution of the present invention, by introducing a Schottky contact structure between the control gate 110 and the active channel region, the control gate 110 can trigger electrons to tunnel from the channel region to the floating gate region 104 when a very small positive voltage is applied, thereby achieving effective programming of the floating gate. This avoids the short circuit problem between the control gate and the channel that may be caused by the traditional high-voltage long-term programming process, thereby improving the reliability and service life of the memory cell. In addition, since the floating gate region 104 adopts a groove structure design, the electron transmission path is effectively shortened, thereby reducing the programming time and improving the operating efficiency of the device.
[0057] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A reprogrammable memory device, characterized in that, The storage device includes: a substrate (100), wherein a buried oxide layer (101) is disposed inside the substrate (100), and a first groove (102) is formed at the top of the substrate (100); An oxide layer (103) is provided on the top of the substrate (100) and the inner wall of the first groove (102). A floating gate region (104) is provided on the top of the oxide layer (103) located on the inner wall of the first groove (102). An insulating layer (105) that cooperates with the oxide layer (103) is provided on the top of the floating gate region (104).
2. The reprogrammable memory device according to claim 1, characterized in that, The top of the insulating layer (105) is symmetrically provided with a second groove (106) that matches the top of the buried oxide layer (101).
3. The multiple programmable memory device according to claim 2, characterized in that, A third groove (107) is provided on one side of the top end of the insulating layer (105) to cooperate with the top end of the substrate (100).
4. A multiple-programmable memory device according to claim 3, characterized in that, The inner wall of the second groove (106) is provided with a barrier layer metal (108).
5. A multiple-programmable memory device according to claim 4, characterized in that, The interior of the third groove (107) is provided with metal silicide (109).
6. A multiple-programmable memory device according to claim 5, characterized in that, A source electrode (201) is disposed inside the barrier layer metal (108) on the side away from the floating gate region (104), and a drain electrode (202) is disposed inside the barrier layer metal (108) on the side close to the floating gate region (104).
7. A multiple-programmable memory device according to claim 6, characterized in that, The top of the metal silicide (109) is provided with a control gate (110) that cooperates with the insulating layer (105).
8. A multiple-programmable memory device according to claim 7, characterized in that, The depth of the first groove (102) is 1 / 6 to 1 / 4 of the longitudinal height of the substrate (100).
9. A multiple-programmable memory device according to claim 1, characterized in that, The substrate (100) is intrinsic semiconductor silicon.
10. A method for fabricating a multiple programmable memory device, used to fabricate the multiple programmable memory device according to any one of claims 1-9, characterized in that, The preparation method includes: S1, injecting a dose of 1×10 into the substrate (100). 17 ~1×10 19 The oxygen atoms are annealed at a temperature of 1200℃~1400℃ to allow the oxygen atoms to react with the interior of the substrate (100) and form a buried oxide layer (101) below the surface of the substrate (100). S2. Photolithography is performed on the surface of the substrate (100) using a mask, etching is performed in the area without photoresist coverage to form the first groove (102), and the residual photoresist is removed. S3. An oxide layer (103) is deposited on the surface of the substrate (100), and polysilicon is deposited on the surface of the oxide layer (103). The polysilicon in the non-target area is removed by photolithography using a mask to form a floating gate area (104). S4. An insulating material is deposited on the surface of the oxide layer (103) to form an insulating layer (105), and selective etching is performed using a mask to form a second groove (106) and a third groove (107). S5. Deposit barrier layer metal (108) in the second groove (106) and the third groove (107), remove the remaining barrier layer metal (108) with the insulating layer (105) as the etching stop layer, and fill the groove (107) with refractory metal to form metal silicide (109). S6. Deposit fill metal in the barrier layer metal (108) and remove the remaining metal to form a source (201), a control gate (110), and a drain (202), and the control gate (110) extends laterally to cover the right edge of the floating gate region (104).