SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device structure for optimizing switching characteristics and preparation method

Abstract

The invention discloses a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device structure for optimizing switching characteristics and a preparation method thereof, and provides a silicon carbide MOSFET device for reducing reverse output capacitance Crss, increasing input capacitance Ciss and increasing output capacitance Coss to improve Crosstalk voltage spike and a preparation method thereof. By introducing the composite gate oxide structure, the high-K material passivation layer and the P + structure at the bottom of the P-WELL into the planar silicon carbide MOSFET device, the reverse output capacitance Crss can be effectively reduced, the input capacitance Ciss can be increased, the output capacitance Coss can be increased, and finally, the Vgs voltage peak in the Crosstalk turn-off process can be effectively improved, and the performance of the device is improved. The breakdown and burnout of the device caused by overhigh voltage in the on-off process of the device are prevented, and the service life of the device is prolonged. Besides, the device structure and the preparation method are simple, and the effect is remarkable, so that high-performance and batch preparation and production can be realized, and the device has huge market potential and wide application prospects.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device fabrication, specifically to a SiC MOSFET device structure and fabrication method with optimized switching characteristics. Background Technology

[0002] SiC power devices offer significant advantages in demanding environments requiring frequent power conversion, miniaturization / lightweighting, and high-temperature resistance. They can meet the application requirements of high temperature, high voltage, and high power, and are widely used in new energy vehicles, photovoltaics, and industrial control. As a representative of wide-bandgap semiconductors, SiC, with its ultra-high efficiency, excellent heat resistance, and miniaturization characteristics, is profoundly revolutionizing the new energy vehicle, 5G communication, and green energy industries, and powerfully driving the upgrade and development of third-generation semiconductor technology.

[0003] In the field of power devices, switching characteristics are a key indicator for evaluating device performance. In some converter topologies with upper and lower transistors, the dV / dt generated by the switching action of the active transistor can produce a displacement current through the reverse capacitance of its counterpart transistor. This can cause excessive voltage spikes at VGS of the counterpart transistor, potentially damaging its gate, affecting device lifespan, or even causing gate breakdown.

[0004] In the field of power semiconductor device applications, switching characteristics are a core indicator for evaluating the dynamic performance, losses, and reliability of devices. However, in some converter topologies with complementary switching structures of upper and lower transistors (such as half-bridge and full-bridge), a key challenge lies in the gate crosstalk phenomenon induced during switching. When the active transistor turns off, its rapid drain-source voltage change couples through the inherent reverse transfer capacitance of its counterpart, generating a significant displacement current. This displacement current flows through the gate loop impedance of the counterpart, inducing an unexpected negative voltage spike on the gate-source voltage of the counterpart. This voltage spike is potentially harmful. An excessively large negative spike may cause excessive negative bias of the counterpart, exceeding the tolerance limit of its gate oxide layer, leading to gate damage or transient gate breakdown. Even if breakdown does not occur immediately, repeated stress may accelerate device aging, significantly shorten the lifespan of power devices, and ultimately affect the long-term operational reliability of the entire power electronic system. Summary of the Invention

[0005] Purpose of the invention: The purpose of this invention is to provide a SiC MOSFET device structure and fabrication method with optimized switching characteristics. By introducing a composite gate oxide structure, a high-k passivation layer, and a P-WELL bottom P+ structure into the planar silicon carbide MOSFET device, the device can be effectively prevented from being damaged by excessive voltage during turn-on and turn-off, thereby improving the device's lifespan.

[0006] Technical solution: The present invention proposes a SiC MOSFET device structure with optimized switching characteristics, comprising a substrate, an epitaxial layer above the substrate, a first stepped region in the epitaxial layer, a second stepped region below the first stepped region, a source region, a well region, polysilicon, and a high-k passivation layer in the first stepped region;

[0007] The well region is located outside the first and second stepped regions. A gate dielectric layer is provided on the upper surface of the epitaxial layer, the first dielectric layer, and the source region. A high-k dielectric layer is provided on the surface of the gate dielectric layer. The high-k dielectric layer has a recess. The polysilicon is surrounded by a high-k passivation layer, and the bottom of the polysilicon protrudes and is accommodated in the recess of the high-k dielectric layer. The bottom of the polysilicon is in contact with the upper surface of the high-k dielectric layer. The lower surface of the high-k passivation layer is in contact with the high-k dielectric layer. A source ohmic contact layer is provided around the gate dielectric layer. A source electrode is provided above the source ohmic contact layer. A recessed gate window is provided at the center of the high-k passivation layer for placing the gate electrode. A drain ohmic contact layer is provided on the lower surface of the substrate. A drain electrode is provided on the lower surface of the drain ohmic contact layer.

[0008] Preferably, the depth of the first stepped region is 0.4–2 μm, the width is 0.3–2.0 μm, and the doping concentration is 1e17–1e19 cm⁻¹. -3 The second step region has a depth of 1.4–3.0 μm, a width of 0.5–1.0 μm, and a doping concentration of 1e17–1e19 cm⁻¹. -3 .

[0009] Preferably, the source region has a depth of 0.4–3.0 μm, a width of 0.5–1.0 μm, and a doping concentration of 1e17–1e19 cm⁻¹. -3 The depth of the well region is 0.4–1.0 μm, and the doping concentration is 1e17–1e18 cm⁻¹. -3 .

[0010] Preferably, the thickness of the gate dielectric layer is 10–20 nm.

[0011] Preferably, the high-K dielectric layer and the high-K passivation layer are made of Al2O3, TiO2, ZrO2, or HfO2.

[0012] A method for fabricating a SiC MOSFET device structure with optimized switching characteristics includes the following steps:

[0013] S1: An epitaxial layer is formed on the upper surface of the substrate;

[0014] S2: A first step region is formed in the epitaxial layer by ion implantation, and a second step region is formed below the first step region;

[0015] S3: A source region is formed in the first step region;

[0016] S4: A trap area is formed around the first and second stepped areas;

[0017] S5: A gate dielectric layer is formed on the upper surface of the epitaxial layer, the first step region, and the source region;

[0018] S6: A high-K dielectric layer is deposited on the upper surface of the gate dielectric layer;

[0019] S7: Polycrystalline silicon is deposited on the upper surface of the high-K dielectric layer;

[0020] S8: A high-K passivation layer is formed on the periphery of the polysilicon and on the upper surface of the well region, and a source window is formed on the periphery of the high-K passivation layer;

[0021] S9: A source ohmic contact layer is formed within the source window;

[0022] S10: The gate window is etched at the center of the high-K passivation layer to expose the polysilicon;

[0023] S11: The gate electrode is formed within the gate window, and the source electrode is formed on the upper surface of the source ohmic contact layer;

[0024] S12: Thin the bottom of the substrate and form the drain ohmic contact layer on the lower surface of the thinned substrate;

[0025] S13: The drain electrode is formed on the lower surface of the drain ohmic contact layer.

[0026] Preferably, step S2 includes the following steps:

[0027] S2.1: An ion implantation mask layer is formed on the surface of the epitaxial layer. The ion implantation mask layer consists of two dielectric film layers, wherein the first dielectric film layer is silicon nitride or polycrystalline silicon with a thickness of 0.5 to 1.5 μm; and the second dielectric film layer is silicon oxide with a thickness of 3 to 5 μm.

[0028] S2.2: Photoresist is coated on the upper surface of the ion implantation mask layer, and the photoresist is patterned using a photolithography process to form a patterned photoresist.

[0029] S2.3: Based on the patterned photoresist, an etching process is used to etch the ion implantation mask layer to form an ion implantation window; wherein, the etching process completely etches away the second dielectric film layer in S2.1, and the etching process will automatically stop at the surface of the first dielectric layer;

[0030] S2.4: Remove the patterned photoresist while retaining the etched ion implantation mask layer;

[0031] S2.5: Based on the etched ion implantation mask layer, perform aluminum ion implantation on the epitaxial layer to form a first step region;

[0032] S2.6: Continue the aluminum ion implantation process on the epitaxial layer to form a second step region below the first step region.

[0033] Preferably, step S6 specifically includes the following steps:

[0034] S6.1: On the surface of the gate dielectric layer formed by the thermal oxidation process, a high-K dielectric layer with a thickness of 30-80 nm is grown using a low-pressure chemical vapor deposition process.

[0035] S6.2: Coat the upper surface of the high-K dielectric layer with photoresist, and use photolithography to pattern the photoresist to form a patterned photoresist;

[0036] S6.3: The high-k dielectric layer is etched using an etching process based on the patterned photoresist;

[0037] S6.4: Remove the patterned photoresist, retaining the high-k dielectric layer in the desired middle and edge regions.

[0038] Preferably, step S8 specifically includes the following steps:

[0039] S8.1: A high-K passivation dielectric layer with a thickness of 30-80 nm is grown on the polycrystalline silicon using a low-pressure chemical vapor deposition process;

[0040] S8.2: Photoresist is coated on the upper surface of the high-K passivation dielectric layer, and the photoresist is patterned using a photolithography process to form a patterned photoresist.

[0041] S8.3: The high-K passivation dielectric layer is etched using an etching process based on the patterned photoresist.

[0042] S8.4: Remove the patterned photoresist, retaining the desired high-k passivation dielectric layer.

[0043] Preferably, in step S12, the substrate thickness is reduced to 120–180 μm.

[0044] Beneficial effects: 1) The present invention optimizes the device structure. By introducing a composite gate oxide structure, a high-K passivation layer and a bottom P+ structure of P-WELL into the planar silicon carbide MOSFET device, it can effectively reduce the reverse output capacitance Crss, increase the input capacitance Ciss, and increase the output capacitance Coss. Ultimately, this can effectively improve the Vgs voltage spike during the turn-off crosstalk process, prevent the device from being damaged by excessive voltage during the turn-on and turn-off process, and improve the device's service life.

[0045] 2) The device structure and preparation method of the present invention are simple and effective, thus enabling high-performance, mass production and manufacturing, with huge market potential and broad application prospects. Attached Figure Description

[0046] Figure 1 A schematic diagram of the S1 cross-section of a SiC MOSFET device provided in an embodiment of the present invention;

[0047] Figure 2 A schematic diagram of the S2.5 cross section of the SiC MOSFET device provided in an embodiment of the present invention;

[0048] Figure 3 A schematic diagram of the S2.6 cross section of the SiC MOSFET device provided in an embodiment of the present invention;

[0049] Figure 4 A schematic diagram of the S3 section of a SiC MOSFET device provided in an embodiment of the present invention;

[0050] Figure 5 A schematic diagram of the S4 cross-section of a SiC MOSFET device provided in an embodiment of the present invention;

[0051] Figure 6 A schematic diagram of the S5 cross-section of a SiC MOSFET device provided in an embodiment of the present invention;

[0052] Figure 7 A schematic diagram of the S6 cross-section of a SiC MOSFET device provided in an embodiment of the present invention;

[0053] Figure 8 A schematic diagram of the S7 cross-section of a SiC MOSFET device provided in an embodiment of the present invention;

[0054] Figure 9 A schematic diagram of the S8 cross-section of a SiC MOSFET device provided in an embodiment of the present invention;

[0055] Figure 10 A schematic diagram of the S9 cross-section of a SiC MOSFET device provided in an embodiment of the present invention;

[0056] Figure 11 A schematic diagram of the S10 cross-section of a SiC MOSFET device provided in an embodiment of the present invention;

[0057] Figure 12 This is a schematic diagram of the S11 cross-section of a SiC MOSFET device provided in an embodiment of the present invention;

[0058] Figure 13 A schematic diagram of the S12 cross-section of a SiC MOSFET device provided in an embodiment of the present invention;

[0059] Figure 14 A schematic diagram of the S13 cross-section of a SiC MOSFET device provided in an embodiment of the present invention;

[0060] Figure 15 This is a flowchart of the fabrication method for SiC MOSFET devices. Detailed Implementation

[0061] like Figure 1-14 As shown, the present invention proposes a SiC MOSFET device structure with optimized switching characteristics, comprising a heavily doped substrate 101 of a first doping type, a lightly doped epitaxial layer 102 of a first doping type located on the upper surface of the substrate 101, a first stepped region 103 of a second doping type located in the epitaxial layer 102, a second stepped region 104 of a second doping type located below the first stepped region 103, a source region 105 of a first doping type located in the first stepped region 103 of the second doping type, a heavily doped well region 106 of the second doping type located in the first stepped region 103 and the second stepped region 104 and located outside the source region 105, and a gate dielectric layer 107 located between the epitaxial layer 102 and the first stepped region 103. A high-k dielectric layer 108 is located on the upper surface of the gate dielectric layer 107, on the upper surface of the step region 103 and the source region 105; a first-doped polysilicon 109 is located on the upper surface of the high-k dielectric layer 108; a high-k passivation layer 110 is located on the surface of the polysilicon 109; a source ohmic contact layer 112 is located on the upper surface of the first-doped source region 105; a drain ohmic contact layer 116 is located on the lower surface of the substrate 101; a gate electrode 114 is located on the upper surface of the polysilicon 109; a source electrode 115 is located on the upper surface of the source ohmic contact layer 112; and a drain electrode 117 is located on the lower surface of the drain ohmic contact layer 116.

[0062] The first doping type is N-type, and the second doping type is P-type. The first step region 103 of the second doping type has a depth of 0.4–2 μm, a width of 0.3–2.0 μm, and a doping concentration of 1e17–1e19 cm⁻¹. -3The second-step region 104 of the second doping type has a depth of 1.4–3.0 μm, a width of 0.5–1.0 μm, and a doping concentration of 1e17–1e19 cm⁻³. The heavily doped source region 105 of the second doping type has a depth of 0.4–3.0 μm, a width of 0.5–1.0 μm, and a doping concentration of 1e17–1e19 cm⁻³. -3 The depth of the first-type doped well region 106 is 0.4–1.0 μm, and the doping concentration is 1e17–1e18 cm⁻¹. -3 The gate dielectric layer 107 has a thickness of 10–20 nm. The high-K dielectric layer 108 is made of Al2O3, TiO2, ZrO2, or HfO2. The high-K passivation layer 110 is made of Al2O3, TiO2, ZrO2, or HfO2.

[0063] The aluminum ion implantation process involves two steps of doping concentration, with the second step region having a high 104 doping concentration. This increases the depletion layer capacitance of the drain-source pn junction, thereby increasing the output capacitance Coss and improving turn-off loss. This effectively mitigates the damage to the SiC MOSFET gate reliability caused by the turn-off crosstalk.

[0064] Adding a high-k dielectric layer 108 above the gate dielectric layer 107 at the middle and edge positions serves two purposes. First, the gate dielectric layer 107 at the middle and edge is prone to breakdown; therefore, thickening it with a high-k dielectric material reduces the risk of breakdown, thus improving the gate oxide strength and long-term stability of the device. Second, thickening the gate dielectric layer 107 at the middle position helps reduce the gate-drain capacitance, thereby improving the Vo change during the turn-off process. DG The resulting displacement current reduces the voltage drop in the drive circuit, thereby reducing the voltage spikes introduced by the crosstalk.

[0065] It should be noted that using a high-k dielectric material for the passivation layer allows for a thinner passivation layer, thereby increasing the gate-source parallel structure capacitance Cpp, which in turn increases the gate-source capacitance C. GS C GS The increase in charge can better absorb charge, which is beneficial to enhance the anti-interference ability of the MOSFET and improve the stability and reliability of the circuit.

[0066] A method for fabricating SiC MOSFETs with optimized switching characteristics includes the following steps:

[0067] S1: An epitaxial layer 102 is formed on the upper surface of the substrate 101;

[0068] S2: A first step region 103 is formed in the epitaxial layer 102 by ion implantation;

[0069] S3: A second step zone 104 is formed below the first step zone 103;

[0070] S4: Source region 105 is formed in the first step region 103;

[0071] S5: A trap area 106 is formed around the first step area 103 and the second step area 104;

[0072] S6: A gate dielectric layer 107 is formed on the upper surface of the epitaxial layer 102, the first step region 103 and the source region 105;

[0073] S7: A high-K dielectric layer 108 is deposited on the upper surface of the gate dielectric layer 107;

[0074] S8: Polysilicon 109 is deposited on the upper surface of the high-K dielectric layer 108;

[0075] S9: A high-K passivation layer 110 is formed on the periphery of the polysilicon 109 and on the upper surface of the well region, and a source window 111 is formed on the periphery of the high-K passivation layer 110;

[0076] S10: A source ohmic contact layer 112 is formed within the source window 111;

[0077] S11: Gate window 113 is etched at the center of high-K passivation layer 110 to expose polysilicon 109;

[0078] S12: A gate electrode 114 is formed in the gate window 113, and a source electrode 115 is formed on the upper surface of the source ohmic contact layer 112.

[0079] S13: Thin the bottom of the substrate 101 and form a drain ohmic contact layer 117 on the lower surface of the thinned substrate 101;

[0080] S14: Drain electrode 121 is formed on the lower surface of drain ohmic contact layer 117.

[0081] Step S2 includes the following steps:

[0082] S2.1: An ion implantation mask layer is formed on the surface of the epitaxial layer 102;

[0083] S2.2: Photoresist is coated on the upper surface of the ion implantation mask layer, and the photoresist is patterned using photolithography processes such as exposure, development and hardening to form a patterned photoresist.

[0084] S2.3: Based on the patterned photoresist, an etching process is used to etch the ion implantation mask layer to form an ion implantation window;

[0085] S2.4: Remove the patterned photoresist while retaining the etched ion implantation mask layer;

[0086] S2.5: Based on the etched ion implantation mask layer, perform aluminum ion implantation on the epitaxial layer 102 to form the first step region 103 of the second doping type;

[0087] S2.6: Continue the aluminum ion implantation process on the epitaxial layer 102 to form a highly doped second-stage region 104 below the first-stage region 103.

[0088] It should be noted that the present invention performs two steps of doping concentration in the aluminum ion implantation process, and the second step region has a high doping concentration of 104, which increases the depletion layer capacitance of the drain-source pn junction, thereby increasing the output capacitance Coss and improving the turn-off loss. This effectively reduces the damage to the gate reliability of SiC MOSFET caused by the turn-off crosstalk.

[0089] Step S6 includes the following steps:

[0090] S6.1 On the surface of the gate dielectric 107 layer formed by thermal oxidation, a high-k dielectric layer with a thickness of 30-80 nm is grown using low-pressure chemical vapor deposition (LPCVD).

[0091] S6.2 Photoresist is coated on the upper surface of the high-K dielectric layer 107, and the photoresist is patterned using photolithography processes such as exposure, development and hardening to form a patterned photoresist.

[0092] S6.3 Based on the patterned photoresist, the high-K dielectric layer 107 is etched using an etching process;

[0093] S6.4 Remove the patterned photoresist, retaining the high-K dielectric layer 107 for the required middle and edge regions;

[0094] It should be noted that the present invention adds a high-k dielectric layer 107 at the middle and edge positions above the gate dielectric layer 107. Firstly, the gate dielectric layer 107 at the middle and edge is prone to breakdown; therefore, thickening it with a high-k dielectric material reduces the risk of breakdown, thus improving the gate oxide strength and long-term stability of the device. Secondly, thickening the gate dielectric layer 107 at the middle position helps reduce the gate-drain capacitance, thereby improving the Vo change during the turn-off process. DG The resulting displacement current reduces the voltage drop in the drive circuit, thereby reducing the voltage spikes introduced by the crosstalk.

[0095] Step S8 includes the following steps:

[0096] S8.1: A high-k passivation dielectric layer 110 with a thickness of 30-80 nm is grown on top of polycrystalline silicon 109 using a low-pressure chemical vapor deposition (LPCVD) process.

[0097] S8.2: Photoresist is coated on the upper surface of the high-K passivation dielectric layer 110, and the photoresist is patterned by photolithography processes such as exposure, development and hardening to form a patterned photoresist.

[0098] S8.3: The high-K passivation dielectric layer 110 is etched using an etching process based on the patterned photoresist;

[0099] S8.4: Remove the patterned photoresist, retaining the required high-k passivation dielectric layer 110;

[0100] It should be noted that the present invention uses a high-k dielectric material for the passivation layer, which can reduce the thickness of the high-k passivation dielectric layer 110, thereby increasing the gate-source parallel structure capacitance Cpp, that is, increasing the gate-source capacitance C. GS C GS The increase of N+ can better absorb charge, which is beneficial to enhance the anti-interference ability of MOSFET and improve the stability and reliability of circuit; the bottom of the first doped N+ substrate 101 is thinned to 120-180um.

Claims

1. A SiC MOSFET device structure with optimized switching characteristics, characterized in that, It includes a substrate (101), an epitaxial layer (102) above the substrate (101), a first step region (103) in the epitaxial layer (102), a second step region (104) below the first step region (103), a source region (105) in the first step region (103), a well region (106), polysilicon (109), and a high-k passivation layer (110); The well region (106) is located outside the first stepped region (103) and the second stepped region (104). A gate dielectric layer (107) is provided on the upper surface of the epitaxial layer (102), the first dielectric layer (103), and the source region (105). A high-K dielectric layer (108) is provided on the surface of the gate dielectric layer (107). The high-K dielectric layer (108) has a recess. The polysilicon (109) is surrounded by a high-K passivation layer (110), and the bottom of the polysilicon (109) protrudes and is received in the recess of the high-K dielectric layer (108). The bottom of the polysilicon (109) is flush with the high-K passivation layer (110). The upper surface of the dielectric layer (108) is in contact with the lower surface of the high-K passivation layer (110), and the gate dielectric layer (107) is surrounded by a source ohmic contact layer (112). A source electrode (115) is provided above the source ohmic contact layer (112). A recessed gate window (113) is provided at the center of the high-K passivation layer (110) for placing the gate electrode (114). A drain ohmic contact layer (116) is provided on the lower surface of the substrate (101), and a drain electrode (117) is provided on the lower surface of the drain ohmic contact layer (116).

2. The SiC MOSFET device structure with optimized switching characteristics according to claim 1, characterized in that, The first step region (103) has a depth of 0.4–2 μm, a width of 0.3–2.0 μm, and a doping concentration of 1e17–1e19 cm⁻¹. -3 The second step region (104) has a depth of 1.4–3.0 μm, a width of 0.5–1.0 μm, and a doping concentration of 1e17–1e19 cm⁻¹. -3 .

3. The SiC MOSFET device structure with optimized switching characteristics according to claim 1, characterized in that, The source region (105) has a depth of 0.4–3.0 μm, a width of 0.5–1.0 μm, and a doping concentration of 1e17–1e19 cm⁻¹. -3 The depth of the well region (106) is 0.4–1.0 μm, and the doping concentration is 1e17–1e18 cm⁻¹. -3 .

4. The SiC MOSFET device structure with optimized switching characteristics according to claim 1, characterized in that, The thickness of the gate dielectric layer (107) is 10-20 nm.

5. The SiC MOSFET device structure with optimized switching characteristics according to claim 1, characterized in that, The high-K dielectric layer (108) and high-K passivation layer (110) are made of Al2O3, TiO2, ZrO2, and HfO2.

6. A method for fabricating a SiC MOSFET device structure with optimized switching characteristics according to any one of claims 1-5, characterized in that, Includes the following steps: S1: An epitaxial layer (102) is formed on the upper surface of the substrate (101); S2: A first step region (103) is formed in the epitaxial layer (102) by ion implantation, and a second step region (104) is formed below the first step region (103); S3: A source region (105) is formed in the first step region (103); S4: A trap area (106) is formed around the first step area (103) and the second step area (104); S5: A gate dielectric layer (107) is formed on the upper surface of the epitaxial layer (102), the first step region (103) and the source region (105); S6: A high-K dielectric layer (108) is deposited on the upper surface of the gate dielectric layer (107); S7: Polycrystalline silicon (109) is deposited on the upper surface of the high-K dielectric layer (108); S8: A high-K passivation layer (110) is formed on the periphery of the polysilicon (109) and on the upper surface of the well region, and a source window (111) is formed on the periphery of the high-K passivation layer (110); S9: A source ohmic contact layer (112) is formed within the source window (111); S10: The gate window (113) is etched at the center of the high-K passivation layer (110) to expose the polysilicon (109); S11: The gate electrode (114) is formed in the gate window (113), and the source electrode (115) is formed on the upper surface of the source ohmic contact layer (112); S12: Thin the bottom of the substrate (101) and form the drain ohmic contact layer (117) on the lower surface of the thinned substrate (101); S13: The drain electrode (121) is formed on the lower surface of the drain ohmic contact layer (117).

7. The method for fabricating the SiC MOSFET device structure with optimized switching characteristics according to claim 6, characterized in that, Step S2 includes the following steps: S2.1: An ion implantation mask layer is formed on the surface of the epitaxial layer (102). The ion implantation mask layer consists of two dielectric film layers, wherein the first dielectric film layer is silicon nitride or polysilicon with a thickness of 0.5 to 1.5 μm; and the second dielectric film layer is silicon oxide with a thickness of 3 to 5 μm. S2.2: Photoresist is coated on the upper surface of the ion implantation mask layer, and the photoresist is patterned using a photolithography process to form a patterned photoresist. S2.3: Based on the patterned photoresist, an etching process is used to etch the ion implantation mask layer to form an ion implantation window; wherein, the etching process completely etches away the second dielectric film layer in S2.1, and the etching process will automatically stop at the surface of the first dielectric layer; S2.4: Remove the patterned photoresist while retaining the etched ion implantation mask layer; S2.5: Based on the etched ion implantation mask layer, perform aluminum ion implantation on the epitaxial layer (102) to form the first step region (103); S2.6: Continue the aluminum ion implantation process on the epitaxial layer (102) to form a second step region (104) below the first step region.

8. The method for fabricating the SiC MOSFET device structure with optimized switching characteristics according to claim 6, characterized in that, Step S6 specifically includes the following steps: S6.1: On the surface of the gate dielectric layer (107) formed by the thermal oxidation process, a high-K dielectric layer (108) with a thickness of 30-80 nm is grown by low-pressure chemical vapor deposition. S6.2: Photoresist is coated on the upper surface of the high-K dielectric layer (108), and the photoresist is patterned using a photolithography process to form a patterned photoresist; S6.3: The high-K dielectric layer (108) is etched using an etching process based on the patterned photoresist; S6.4: Remove the patterned photoresist, retaining the high-k dielectric layer (108) in the desired middle and edge regions.

9. The method for fabricating the SiC MOSFET device structure with optimized switching characteristics according to claim 6, characterized in that, Step S8 specifically includes the following steps: S8.1: A high-K passivation dielectric layer (110) with a thickness of 30-80 nm is grown on the polycrystalline silicon (109) using a low-pressure chemical vapor deposition process; S8.2: Photoresist is coated on the upper surface of the high-K passivation dielectric layer (110), and the photoresist is patterned using a photolithography process to form a patterned photoresist; S8.3: The high-K passivation dielectric layer (110) is etched using an etching process based on the patterned photoresist; S8.4: Remove the patterned photoresist, leaving the desired high-k passivation dielectric layer (110).

10. The method for fabricating the SiC MOSFET device structure with optimized switching characteristics according to claim 6, characterized in that, In step S12, the thickness of the substrate (101) is reduced to 120-180 μm.

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