Transient response enhanced multi-loop low-dropout linear regulator

Abstract

The application provides a transient response enhanced multi-loop low-dropout linear voltage regulator, comprising: a bias module for providing a bias voltage; a band gap reference module for providing a reference voltage; a power tube for providing an output voltage; a voltage follower for generating a control voltage and a driving current based on the bias voltage and the reference voltage; a source-coupled error amplifier for generating a gain voltage according to the output voltage and the control voltage; a common gate for generating a first voltage according to the reference voltage and the gain voltage; a pseudo-differential common gate for generating a second voltage according to the reference voltage and the gain voltage; and a dynamic super source follower for forming a push-pull structure at the gate of the power tube according to the first voltage and the second voltage. The application can effectively improve the transient response performance of the voltage regulator.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit applications, and in particular to a transient response enhanced multi-loop low dropout linear regulator. BACKGROUND

[0002] With the rapid development of technology, portable electronic devices play an increasingly important role in our daily life and work. This trend not only promotes the progress of hardware technology, but also puts forward higher requirements for power management technology. In order to meet the needs of various portable devices for stable and reliable power supply, a variety of power supply solutions have emerged in the market, thereby enriching the entire electronic product ecosystem.

[0003] Low dropout linear regulator (LDO, Low Dropout Regulator) as a kind of efficient and common voltage stabilizing device, has been widely used in miniaturized electronic devices. Its excellent noise suppression ability, small size and easy integration make it the first choice in many application scenarios. However, the traditional LDO design usually relies on a large external capacitor to maintain the stability of the output voltage, especially in the case of rapid load current change. This dependence on large external capacitors brings problems such as large space occupation, cost increase and slow response speed, which poses a significant challenge to modern electronic devices that pursue compact and thin design.

[0004] In order to solve these problems, output capacitorless low dropout linear regulator (OCL-LDO, Output-Capacitorless Low-Dropout Regulator) has emerged. OCL-LDO reduces the dependence on large external capacitors by optimizing the circuit architecture, making the design more compact and economical. However, although OCL-LDO has made progress in reducing the number of components, the performance of OCL-LDO in transient response is poor, which limits its application in high dynamic load conditions. SUMMARY

[0005] In view of the problems existing in the prior art, the present application proposes a transient response enhanced multi-loop low dropout linear regulator, which mainly solves the problem of poor LDO transient response performance in related technologies.

[0006] In order to achieve the above-mentioned purpose and other purposes, the technical scheme adopted by the present application is as follows.

[0007] The application provides a transient response enhanced multi-loop low-dropout linear voltage regulator, which comprises a biasing module, a bandgap reference module, a power tube, a voltage follower, a source-coupled error amplifier, a common-gate, a pseudo-differential common-gate and a dynamic super source follower.

[0008] In an embodiment of the application, the biasing module comprises a current source and a first biasing transistor; the input end of the current source is connected to a power voltage, and the output end is connected to the drain of the first biasing transistor; the source of the first biasing transistor is connected to the ground, and the gate and the drain are short-circuited as the output end of the biasing module to output the biasing voltage.

[0009] In an embodiment of the application, the common-gate comprises a first transistor and a third transistor; the gate of the first transistor is connected to the reference voltage, the drain is connected to the drain of the third transistor, and the source is connected to the input end of the common-gate; the source of the third transistor is connected to the power voltage, and the gate and the drain are short-circuited as the output end of the common-gate.

[0010] In an embodiment of the application, the pseudo-differential common-gate comprises a second transistor and a fourth transistor; the gate of the second transistor is connected to the reference voltage, the source is connected to the non-inverted input end of the pseudo-differential common-gate, and the drain is connected to the drain of the fourth transistor as the output end of the pseudo-differential common-gate; the source of the fourth transistor is connected to the power voltage, and the gate is connected to the output end of the common-gate as the inverted input end of the pseudo-differential common-gate.

[0011] In an embodiment of the application, the source-coupled error amplifier comprises a first common-gate transconductance and a second common-gate transconductance; the non-inverted input end of the first common-gate transconductance is connected to the inverted input end of the second common-gate transconductance as the non-inverted input end of the source-coupled error amplifier; the inverted input end of the first common-gate transconductance is connected to the non-inverted input end of the second common-gate transconductance as the inverted input end of the source-coupled error amplifier; the output end of the first common-gate transconductance is connected to the non-inverted input end of the pseudo-differential common-gate; and the output end of the second common-gate transconductance is connected to the input end of the common-gate.

[0012] In an embodiment of the present application, the first common-gate transconductance and the second common-gate transconductance have the same circuit structure, and the first common-gate transconductance comprises a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor; a source of the fifth transistor is connected to the output voltage as a non-inverted input terminal of the first common-gate transconductance, a drain is connected to a drain of the seventh transistor as an output terminal of the first common-gate transconductance, and a gate is connected to a gate of the sixth transistor; a source of the sixth transistor is a inverted input terminal of the first common-gate transconductance, a gate is connected to a drain, and the drain is connected to a drain of the eighth transistor; a gate of the seventh transistor and a gate of the eighth transistor are connected to the bias voltage; and a source of the seventh transistor and a source of the eighth transistor are grounded.

[0013] The second common-gate transconductance comprises a ninth transistor, a tenth transistor, an eleventh transistor and a twelfth transistor; a source of the ninth transistor is connected to the control voltage as a non-inverted input terminal of the second common-gate transconductance, a drain is connected to a drain of the eleventh transistor as an output terminal of the second common-gate transconductance, and a gate is connected to a gate of the tenth transistor; a source of the tenth transistor is a inverted input terminal of the second common-gate transconductance, a gate is connected to a drain, and the drain is connected to a drain of the twelfth transistor; a gate of the eleventh transistor and a gate of the twelfth transistor are connected to the bias voltage; and a source of the eleventh transistor and a source of the twelfth transistor are grounded.

[0014] In an embodiment of the present application, the voltage follower comprises a second bias transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor and a twentieth transistor; a source of the second bias transistor, a source of the nineteenth transistor and a source of the twentieth transistor are grounded; a source of the fifteenth transistor, a source of the sixteenth transistor, a source of the seventeenth transistor and a source of the eighteenth transistor are connected to the power supply voltage; a gate of the thirteenth transistor is connected to the reference voltage, a source is connected to a source of the fourteenth transistor and a drain of the second bias transistor respectively, and a drain is connected to a drain of the fifteenth transistor; a gate of the second bias transistor is connected to the bias voltage; a gate of the fourteenth transistor is connected to a drain of the nineteenth transistor and a drain of the seventeenth transistor respectively to output the control voltage; a drain of the thirteenth transistor is connected to a drain of the fifteenth transistor, a gate of the fifteenth transistor and a gate of the seventeenth transistor respectively; a drain of the fourteenth transistor is connected to a drain of the sixteenth transistor, a gate of the sixteenth transistor and a gate of the eighteenth transistor respectively, a drain of the eighteenth transistor is connected to a gate of the nineteenth transistor, a gate of the twentieth transistor and a drain of the twentieth transistor respectively.

[0015] In an embodiment of the present application, the dynamic super source follower comprises a twenty-first transistor, a twenty-second transistor, a twenty-third transistor and a first resistor; a gate of the twenty-first transistor is an inverting input terminal of the dynamic super source follower and is connected to an output terminal of the common gate; a gate of the twenty-second transistor is a non-inverting input terminal of the dynamic super source follower and is connected to an output terminal of the pseudo differential common gate; a source of the twenty-first transistor is connected to the power supply voltage, and a drain of the twenty-first transistor is connected to a source of the twenty-second transistor and a drain of the twenty-third transistor as an output terminal of the dynamic super source follower; a drain of the twenty-second transistor is connected to a gate of the twenty-third transistor and is connected to the ground through the first resistor; and a source of the twenty-third transistor is connected to the ground.

[0016] In an embodiment of the present application, the transient response enhanced multi-loop low-dropout linear regulator further comprises a frequency compensation module, which is arranged between the drain of the power transistor and the non-inverting input terminal of the dynamic super source follower.

[0017] As described above, the transient response enhanced multi-loop low-dropout linear regulator provided by the present application has the following beneficial effects.

[0018] According to the present application, the dynamic super source follower is used to perform push-pull processing at the gate of the power transistor, which can effectively improve the transient response performance under low power consumption conditions. In addition, the common gate, the pseudo differential common gate and the source coupled error amplifier are combined to form multiple feedback loops in the linear regulator, thereby ensuring low output ripple, high gain, wide bandwidth and high stability. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 FIG. 1 is a circuit architecture schematic diagram of a transient response enhanced multi-loop low-dropout linear regulator according to an embodiment of the present application;

[0020] Figure 2 FIG. 2 is a circuit schematic diagram of a transient response enhanced multi-loop low-dropout linear regulator according to an embodiment of the present application;

[0021] Figure 3 FIG. 3 shows a frequency characteristic curve of the transient response enhanced multi-loop low-dropout linear regulator;

[0022] Figure 4 FIG. 4 shows a transient response curve of the transient response enhanced multi-loop low-dropout linear regulator. DETAILED DESCRIPTION

[0023] Following embodiments of the present application are explained by way of specific examples, and other advantages and effects of the present application can be easily understood by those skilled in the art from the description. The present application can also be implemented or applied in other different embodiments, and various modifications or changes can be made to the details based on different views and applications without departing from the spirit of the present application. It should be noted that the following examples and features in the examples can be combined with each other without conflict.

[0024] It should be noted that the diagrams provided in the following examples only schematically illustrate the basic concept of the present application, and only the components related to the present application are shown in the diagrams, not the number, shape and size of the components when actually implemented. The actual implementation of each component may be a random change in shape, number and proportion, and the layout pattern of the components may be more complex.

[0025] Terminology:

[0026] A system-on-chip, commonly referred to as a system on chip (SoC), is a highly integrated microelectronic device.

[0027] Quiescent current (IQ), or power dissipation, is a key parameter for measuring the efficiency of a linear regulator. It represents the current consumed by the regulator itself in addition to the load current when it is operating normally. Specifically, the quiescent current includes the current required for internal circuit operation, such as the power consumption of the reference voltage source, error amplifier and other control circuits.

[0028] The inventors have found that:

[0029] As a highly efficient and common voltage regulator device, the low dropout regulator (LDO) has been widely used in small electronic devices. Its excellent noise suppression capability, small size and easy integration make it the first choice in many application scenarios. However, traditional LDO design usually relies on a large external capacitor to maintain the stability of the output voltage, especially in the case of rapid changes in load current. This dependence on large external capacitors brings problems such as large space occupation, cost increase and slow response speed, which poses a significant challenge to modern electronic devices that pursue compact and thin design.

[0030] To address these issues, output-capacitorless low-dropout regulators (OCL-LDOs) have emerged. OCL-LDOs optimize circuit architecture to reduce dependence on external large-capacitance capacitors, making designs more compact and economical. However, despite progress in reducing component count, OCL-LDOs perform poorly in transient response, limiting their application in high-dynamic-load conditions.

[0031] Therefore, how to provide a low-dropout linear regulator that can both reduce power consumption and improve transient response performance has become a technical problem to be solved. The ideal design not only overcomes the space and cost problems of traditional LDOs, but also finds the best balance point between transient response, power consumption and stability. Through innovative circuit design and optimization, a more efficient and energy-saving power management solution can be achieved to meet the demand for high-performance power supply in modern portable electronic devices.

[0032] The embodiment of the present application provides a transient response enhanced multi-loop low-dropout linear regulator, and the technical scheme of the present application will be described in detail below in conjunction with specific embodiments.

[0033] Please refer to Figure 1 , Figure 1A circuit architecture schematic diagram of a transient response enhanced multi-loop low-dropout linear voltage regulator in an embodiment of the present application. The voltage regulator of the embodiment of the present application comprises: a biasing module for providing a bias voltage; a bandgap reference module for providing a reference voltage; a power tube for providing an output voltage; a voltage follower for generating a control voltage and a driving current based on the bias voltage and the reference voltage; a source-coupled error amplifier for generating a gain voltage according to the output voltage and the control voltage; a common-gate for generating a first voltage according to the reference voltage and the gain voltage; a pseudo-differential common-gate for generating a second voltage according to the reference voltage and the gain voltage; a dynamic super source follower for forming a push-pull structure at the gate of the power tube according to the first voltage and the second voltage; wherein the source of the power tube is connected to a power supply voltage, the gate of the power tube is connected to the output end of the dynamic super source follower, and the drain of the power tube outputs the output voltage. Specifically, the biasing module can provide a bias voltage for part of the transistors in the voltage follower and the source-coupled error amplifier; the bandgap reference module can provide a reference voltage for part of the transistors in the voltage follower, the common-gate and the pseudo-differential common-gate; the voltage follower is connected to the reference voltage and provides the control voltage Vset and the driving current for the source-coupled error amplifier; the source-coupled error amplifier consists of two common-gate transconductances and generates a gain voltage according to the output voltage VOUT and the control voltage Vset output by the voltage follower, which is transmitted to the common-gate and the pseudo-differential common-gate. The output end of the dynamic super source follower is connected to the gate of the power tube MP, forming a push-pull structure at the gate of the power tube, and the output signals of the common-gate and the pseudo-differential common-gate are respectively connected to the non-inverting input end and the inverting input end of the dynamic super source follower, so that the dynamic super source follower performs push-pull processing at the gate of the power tube, enhancing the transient response performance. The power tube MP performs intelligent charging and discharging operation based on the two-stage gain voltage input by the dynamic super source follower, and outputs the corresponding output voltage V OUT .

[0034] As Figure 2 shown, the biasing module comprises a current source I bias , a first biasing transistor M B1 , the input end of the current source I bias is connected to a power supply voltage V IN , the output end of the current source is connected to the drain of the first biasing transistor M B1 , the drain of the first biasing transistor M B1 is also connected to the gate of the first biasing transistor M B1 , the gate of the first biasing transistor M B1 is also connected to the gate of the second biasing transistor M B2 , the gate of the seventh transistor M a3 , the gate of the eighth transistor M a4 , the gate of the eleventh transistor Mb3 The gate of the twelfth transistor M b4 The gate of the first bias transistor M; B1 The source of the transistor is grounded, wherein the first bias transistor M B1 The gate provides the bias voltage.

[0035] In one embodiment, such as Figure 2 As shown, the output of the bandgap reference module is connected to the gate of the first transistor M1, the gate of the second transistor M2, and the gate of the thirteenth transistor M... 01 The gate provides the reference voltage V. REF The bandgap reference module can use a conventional bandgap reference circuit; the specific circuit structure is not limited here.

[0036] In one embodiment, such as Figure 2 As shown, the voltage follower includes a thirteenth transistor M. 01 Fourteenth transistor M 02 The fifteenth transistor M 03 The sixteenth transistor M 04 The seventeenth transistor M 05 The eighteenth transistor M 06 The nineteenth transistor M 07 20th transistor M 08 Second bias transistor M B2 The thirteen transistors M 01 The source, the fourteenth transistor M 02 The source and second bias transistor M B2 Drain connection; Thirteenth transistor M 01 The gate is connected to the reference voltage V REF ; Thirteenth transistor M 01 The drain of the seventeenth transistor M 05 The gate of the fifteenth transistor M 03 The drain and the fifteenth transistor M 03 Gate connection; Fourteenth transistor M 02 The drain of the eighteenth transistor M 06 The gate of the sixteenth transistor M 04 The drain and the sixteenth transistor M 04 Gate connection; Fourteenth transistor M 02 The gate of the seventeenth transistor M 05 The drain of the nineteenth transistor M 07 The drain of the sixth transistor M a2 The source and the first bias transistor M b1 The source connection; the fifteenth transistor M 03 The source, the sixteenth transistor M 04The source of the seventeenth transistor M 05 The source, the eighteenth transistor M 06 The source and power supply voltage V IN Connection; Eighteenth transistor M 06 The drain of the nineteenth transistor M 07 The gate of the twentieth transistor M 08 The drain and the twentieth transistor M 08 Gate connection; second bias transistor M B2 The source of the nineteenth transistor M 07 The source and the twentieth transistor M 08 The source of the transistor is grounded; the second bias transistor M B2 The gate, the first bias transistor M B1 The gate and the first bias transistor M B1 The drain connection.

[0037] In one embodiment, such as Figure 2 As shown, the source-coupled error amplifier includes a fifth transistor M. a1 The sixth transistor M a2 The seventh transistor M a3 Eighth transistor M a4 Ninth transistor M b1 10th transistor M b2 11th transistor M b3 Twelfth transistor M b4 The fifth transistor M a1 The gate, the sixth transistor M a2 The gate of the sixth transistor M a2 The drain and the eighth transistor M a4 Drain connection; fifth transistor M a1 The source and power transistor M P The drain of the second bias transistor M b2 The source and compensation capacitor C m One end is connected; the fifth transistor M a1 The drain of the seventh transistor M a3 The drain of transistor M1 is connected to the source of transistor M2; the sixth transistor M2 is connected to the source of transistor M3. a2 The source, the fourteenth transistor M 02 The gate of the seventeenth transistor M 05 The drain of the nineteenth transistor M 07 The drain and the first bias transistor M b1 The source connection; the seventh transistor M a3 The source, the eighth transistor M a4 The source of the eleventh transistor M b3 The source and the twelfth transistor Mb4 The source is grounded; the seventh transistor M a3 The gate of the eighth transistor M a4 The gate of the eleventh transistor M b3 The gate and the twelfth transistor M b4 The gate, the second bias transistor M B1 The drain and second bias transistor M B1 Gate connection; Ninth transistor M b1 The drain of the eleventh transistor M b3 The drain of the ninth transistor M1 is connected to the source of the first transistor M1; b1 The gate of the tenth transistor M b2 The gate of the tenth transistor M b2 The drain and the twelfth transistor M b4 The drain connection.

[0038] In one embodiment, such as Figure 2 As shown, the common gate transistor includes a first transistor M1 and a third transistor M3. The source of the first transistor M1 and the first bias transistor M3 are... b1 The drain and the eleventh transistor M b3 The drain of the first transistor M1 is connected; the gate of the first transistor M1 is connected to the reference voltage V. REF The drain of the first transistor M1, the drain of the third transistor M3, the gate of the third transistor M3, and the twenty-first transistor M... 21 The gate of transistor M1 is connected to the gate of transistor M4; the source of transistor M3 is connected to the power supply voltage V. IN .

[0039] In one embodiment, such as Figure 2 As shown, the pseudo-differential common gate includes a second transistor M2 and a fourth transistor M4, the source of the second transistor M2, and the fifth transistor M4. a1 The drain and the seventh transistor M a3 The drain of the first transistor M2 is connected; the gate of the second transistor M2 is connected to the reference voltage V. REF The drain of the second transistor M2, the drain of the fourth transistor M4, and the twenty-second transistor M 22 The gate and compensation capacitor C m The other end is connected to: the gate of the fourth transistor M4, the drain of the first transistor M1, the drain of the third transistor M3, and the twenty-first transistor M... 21 The gate of transistor M1 is connected to the gate of transistor M3; the source of transistor M4 is connected to the power supply voltage V. IN .

[0040] In one embodiment, such as Figure 2 As shown, the dynamic super source follower includes the twenty-first transistor M. 21the gate of the twenty-first transistor M 22 the gate of the twenty-second transistor M 23 the first resistor R b the gate of the twenty-first transistor M 21 , the gate of the fourth transistor M4, the drain of the first transistor Ml, the drain of the third transistor M3 and the gate of the third transistor M3 are connected; the drain of the twenty-first transistor M 21 , the gate of the power transistor M P , the source of the twenty-second transistor M 22 and the drain of the twenty-third transistor M 23 are connected; the source of the twenty-first transistor M 21 is connected to a power supply voltage V IN ; the gate of the twenty-second transistor M 22 , the drain of the second transistor M2, the drain of the fourth transistor M4 and the other end of the compensation capacitor C m are connected; the drain of the twenty-second transistor M 22 , the gate of the twenty-third transistor M 23 and one end of the first resistor R b are connected; the source of the twenty-third transistor M 23 and the other end of the first resistor R b are grounded.

[0041] In an embodiment, as shown in Figure 2 , the frequency compensation module comprises a compensation capacitor C m , one end of the compensation capacitor C m , the source of the fifth transistor M a1 , the drain of the power transistor M P and the source of the tenth transistor M b2 are connected; the other end of the compensation capacitor C m , the drain of the second transistor M2, the drain of the fourth transistor M4 and the gate of the twenty-second transistor M 22 are connected.

[0042] In an embodiment, as shown in Figure 2 , the source of the power transistor M P is connected to a power supply voltage V IN ; the gate of the power transistor M P , the drain of the twenty-first transistor M 21 , the source of the twenty-second transistor M 22 and the drain of the twenty-third transistor M 23 are connected; the drain of the power transistor M P , the source of the fifth transistor M a1 , the source of the tenth transistor M b2 and one end of the compensation capacitor C m are connected.

[0043] As shown in Figure 1-4 , the working principle of the transient response enhanced multi-loop low-dropout linear regulator is as follows:

[0044] As shown in Figure 1 , the power supply voltage V IN is generally 1.5V~1.8V, and 1.5V is usually used as the power supply voltage of the low-dropout linear regulator. If the load capacitor C L is set to 100pF, the corresponding load driving current can be 1~50mA, so that the output voltage V OUT of the low-dropout linear regulator is stabilized at 1.2V.

[0045] As shown in Figure 1 , the power supply voltage V IN supplies power to the bias module, the bandgap reference module, the voltage follower, the common gate, the pseudo-differential common gate, the dynamic super source follower and the power tube M P . The bias module generates a bias voltage V bias , the source-coupled error amplifier differentially processes the control voltage V set and the output voltage V OUT input by the voltage follower to generate gain voltages V EA1 and V EA2 ; the common gate receives the V EA1 voltage signal and generates the voltage V CG1 after amplification; the pseudo-differential common gate receives the V EA2 and V CG1 voltage signals and generates the voltage V CG2 after differential processing; the dynamic super source follower receives the V CG1 and V CG2 voltage signals and generates a second gain voltage V P after differential processing, and the second gain voltage V P pushes and pulls the gate of the power tube M P ; the power tube M P intelligently completes charging or discharging under the push-pull of the dynamic super source follower and outputs a stable output voltage V OUT .

[0046] The current source in the bias module provides a reference current I bias , which generates a bias voltage V bias at the gate of the bias transistor M B1 , and differentially processes the gate of the seventh transistor M a3 , the gate of the eighth transistor M a4 and the gate of the eleventh transistor M b3gate of the twelfth transistor M b4 gate of the second bias transistor M in the voltage follower B2 gate of the twelfth transistor M bias .

[0047] gate of the twenty-first transistor M in the dynamic super source follower 21 and the twenty-third transistor M 23 constitute a push-pull structure, based on the received V CG1 and V CG2 voltage signals, the gate voltage of the twenty-first transistor M 21 is adjusted, the gate voltage of the twenty-third transistor M 23 is adjusted, the drain current of the twenty-first transistor M 21 is further adjusted, the drain current of the twenty-third transistor M 23 is further adjusted, and the gate of the power transistor M P is driven to charge or discharge rapidly, so as to improve the transient response performance, thereby ensuring that the drain current of the power transistor M P can be adjusted rapidly, so as to improve the transient response speed of the regulator.

[0048] As shown in Figure 1 , the regulator comprises a plurality of feedback loops, such as feedback loop 1, feedback loop 2, and feedback loop 3, so that the regulator has low output ripple, high gain, large bandwidth, and high stability.

[0049] As shown in Figure 3 , Figure 3 the frequency characteristic curve of the transient response enhanced multi-loop low-dropout linear regulator is shown. The plurality of feedback loops and the supplementary capacitor C m inside the regulator make the regulator have high low-frequency gain of 72.95 dB, large bandwidth of 5.16 MHz, and high stability of phase margin of 76.1° under the worst stability condition of 1 mA of load current and 100 pF of load capacitance.

[0050] As shown in Figure 4 , Figure 4 the transient response curve of the transient response enhanced multi-loop low-dropout linear regulator is shown. The dynamic super source follower with the push-pull structure performs push-pull processing on the gate of the power transistor M P , so as to improve the transient response performance; as Figure 4As shown, under the conditions of a static current of 33.7 μA, an edge time of 100 ns, and a load capacitance of 100 pF, when the load current jumps from 1 mA to 50 mA, the undershoot voltage is 146.9 mV and the recovery time is less than 0.23 μs. When the load current jumps from 50 mA to 1 mA, the overshoot voltage is 106.4 mV and the recovery time is also less than 0.27 μs. The overshoot and undershoot voltages are small and the recovery time is extremely short, which effectively improves the transient response speed.

[0051] This application relates to a transient response-enhanced multi-loop low-dropout linear regulator, which includes a bias module, a bandgap reference module, a voltage follower, a source-coupled error amplifier, a common-gate amplifier, a pseudo-differential common-gate amplifier, a dynamic super source follower, a frequency compensation module, and a power transistor M. P The bias module provides bias voltages for some transistors in the voltage follower and source-coupled error amplifier; the bandgap reference module provides a reference voltage V for some transistors in the voltage follower, common-gate, and pseudo-differential common-gate amplifiers. REF The source-coupled error amplifier consists of two common-gate transconductors and is based on the output voltage V. OUT and the control voltage V output by the voltage follower set A gain voltage is generated and transmitted to the common-gate and pseudo-differential common-gate transistors. The output signals of the common-gate and pseudo-differential common-gate transistors are respectively connected to the inverting and non-inverting inputs of the dynamic super source follower, enabling the dynamic super source follower to perform push-pull processing at the gate of the power transistor. The frequency compensation module is connected to the output of the low-dropout linear regulator and the non-inverting input of the dynamic super source follower. The regulator involved in this application uses a dynamic super source follower based on a multi-feedback loop at the gate of the power transistor M... P The gate of the regulator is push-pull, improving the transient response performance of the regulator under low power consumption conditions. Three feedback loops are formed internally to ensure low output ripple, high gain, wide bandwidth, and high stability. This regulator not only achieves on-chip integration, supports a wide load current range, provides high-precision output voltage, and possesses fast transient response capability, but also efficiently utilizes power transistor area, maintaining high gain, wide bandwidth, high stability, and low output ripple. Furthermore, it optimizes thermal management and space utilization. These features make it an ideal choice for high-performance electronic products, especially suitable for applications with stringent requirements for reliability, energy efficiency, and performance, such as smartphones, tablets, and other portable devices.

[0052] The above embodiments are only illustrative of the principles of the present application and its efficacy, and are not intended to limit the present application. Any modification or change made by any person skilled in the art without departing from the spirit and scope of the present application shall be covered by the claims of the present application.

Claims

1. A transient response enhanced multi-loop low dropout linear regulator, characterized in that, include: The bias module is used to provide bias voltage; Bandgap reference module, used to provide a reference voltage; Power transistors are used to provide output voltage; A voltage follower for generating a control voltage and a drive current based on the bias voltage and the reference voltage; A source-coupled error amplifier for generating a gain voltage based on the output voltage and the control voltage; A common gate is used to generate a first voltage based on the reference voltage and the gain voltage; A pseudo-differential common gate is used to generate a second voltage based on the reference voltage and the gain voltage; A dynamic super source follower is used to form a push-pull structure at the gate of the power transistor according to the first voltage and the second voltage; The dynamic super source follower includes: a 21st transistor, a 22nd transistor, a 23rd transistor, and a first resistor; the gate of the 21st transistor serves as the inverting input of the dynamic super source follower and is connected to the common-gate output; the gate of the 22nd transistor serves as the non-inverting input of the dynamic super source follower and is connected to the pseudo-differential common-gate output; the source of the 21st transistor is connected to the power supply voltage, and its drain is connected to the source of the 22nd transistor and the drain of the 23rd transistor, respectively, serving as the output of the dynamic super source follower; the drain of the 22nd transistor is connected to the gate of the 23rd transistor and grounded through the first resistor; the source of the 23rd transistor is grounded. The source-coupled error amplifier includes: a first common-gate transconductance and a second common-gate transconductance; the non-inverting input terminal of the first common-gate transconductance is connected to the inverting input terminal of the second common-gate transconductance as the non-inverting input terminal of the source-coupled error amplifier; the inverting input terminal of the first common-gate transconductance is connected to the non-inverting input terminal of the second common-gate transconductance as the inverting input terminal of the source-coupled error amplifier; the output terminal of the first common-gate transconductance is connected to the non-inverting input terminal of the pseudo-differential common-gate amplifier; the output terminal of the second common-gate transconductance is connected to the input terminal of the common-gate amplifier. Wherein, the source of the power transistor is connected to the power supply voltage, the gate is connected to the output terminal of the dynamic super source follower, and the drain outputs the output voltage; The common gate includes a first transistor and a third transistor; the gate of the first transistor is connected to the reference voltage, the drain is connected to the drain of the third transistor, and the source serves as the input terminal of the common gate; the source of the third transistor is connected to the power supply voltage, and the gate and drain are shorted together to serve as the output terminal of the common gate. The pseudo-differential common gate includes a second transistor and a fourth transistor; the gate of the second transistor is connected to the reference voltage, the source serves as the non-inverting input terminal of the pseudo-differential common gate, and the drain is connected to the drain of the fourth transistor as the output terminal of the pseudo-differential common gate; the source of the fourth transistor is connected to the power supply voltage, the gate serves as the inverting input terminal of the pseudo-differential common gate, and is connected to the output terminal of the common gate. The first common-gate transconductance has the same circuit structure as the second common-gate transconductance. The first common-gate transconductance includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The source of the fifth transistor serves as the non-inverting input terminal of the first common-gate transconductance and is connected to the output voltage. Its drain is connected to the drain of the seventh transistor and serves as the output terminal of the first common-gate transconductance. Its gate is connected to the gate of the sixth transistor. The source of the sixth transistor serves as the inverting input terminal of the first common-gate transconductance. Its gate is connected to the drain and is also connected to the drain of the eighth transistor. The gates of the seventh transistor and the eighth transistor are connected to the bias voltage. The sources of the seventh transistor and the eighth transistor are grounded. The second common-gate transconductance includes: a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor; the source of the ninth transistor serves as the non-inverting input terminal of the second common-gate transconductance and is connected to the control voltage, its drain is connected to the drain of the eleventh transistor and serves as the output terminal of the second common-gate transconductance, and its gate is connected to the gate of the tenth transistor; the source of the tenth transistor serves as the inverting input terminal of the second common-gate transconductance, its gate is connected to its drain and is connected to the drain of the twelfth transistor; the gates of the eleventh transistor and the twelfth transistor are connected to the bias voltage; the sources of the eleventh transistor and the twelfth transistor are grounded; The voltage follower includes: a second bias transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, and a twentieth transistor; the sources of the second bias transistor, the nineteenth transistor, and the twentieth transistor are respectively grounded; the sources of the fifteenth transistor, the sixteenth transistor, the seventeenth transistor, and the eighteenth transistor are connected to the power supply voltage; the gate of the thirteenth transistor is connected to the reference voltage, and its source is connected to the source of the fourteenth transistor and the drain of the second bias transistor, respectively, and its drain is connected to the tenth transistor. The drain of the fifth transistor; the gate of the second bias transistor is connected to the bias voltage; the gate of the fourteenth transistor is connected to the drain of the nineteenth transistor and the drain of the seventeenth transistor to output the control voltage; the drain of the thirteenth transistor is connected to the drain of the fifteenth transistor, the gate of the fifteenth transistor, and the gate of the seventeenth transistor; the drain of the fourteenth transistor is connected to the drain of the sixteenth transistor, the gate of the sixteenth transistor, and the gate of the eighteenth transistor; the drain of the eighteenth transistor is connected to the gate of the nineteenth transistor, the gate of the twentieth transistor, and the drain of the twentieth transistor.

2. The transient response enhanced multi-loop low-dropout linear regulator according to claim 1, characterized in that, The bias module includes a current source and a first bias transistor; the input terminal of the current source is connected to the power supply voltage, and the output terminal is connected to the drain of the first bias transistor; the source of the first bias transistor is grounded, and the gate and drain are shorted to serve as the output terminal of the bias module to output the bias voltage.

3. The transient response enhanced multi-loop low dropout linear regulator according to claim 1, characterized in that, Also includes: A frequency compensation module is disposed between the drain of the power transistor and the non-inverting input terminal of the dynamic super source follower.

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