System and method for minimizing insertion loss and loop inductance in PCB layouts

Abstract

Systems and methods involve considering insertion loss and / or loop inductance during design and layout phases of a PCB. The insertion loss is measured along the signal path and / or the loop inductance is measured along the current loop, and if the measured value is above a predefined maximum value, the PCB designer is prompted to redesign the PCB layout.

Description

BACKGROUND

[0001] The strong growth in demand for portable consumer electronics has driven the demand for high-capacity storage devices. Non-volatile semiconductor memory devices, such as flash memory storage cards, are widely used to meet the ever-growing demand for digital information storage and exchange. Their portability, versatility, and rugged design, coupled with their high reliability and large capacity, make such memory devices well suited for use in a variety of electronic devices, including, for example, digital cameras, digital music players, video game controllers, PDAs, cellular telephones, and solid-state drives.

[0002] Semiconductor packages are typically mounted on a printed circuit board (PCB) along with a controller, a capacitor, and other electronic components. The package, controller, and / or other components can be electrically connected to solder balls on a bottom surface of the PCB, or to gold-plated fingers along an edge of the PCB. The PCB can have multiple conductive layers, each having a pattern of conductive traces, each such layer separated by an electrically insulating dielectric layer. Different conductive layers can be electrically coupled to one another by conductive vias formed through the PCB.

[0003] Current high-speed memory devices use PCIe (Peripheral Component Interconnect Express) or other high-speed serial interface standards for communicating signals. These serial interfaces can be implemented using SERDES (serializer / deserializer) technology as the physical layer to serialize data at the transmitting end and deserialize it at the receiving end. It is important in high-speed signal communication through a PCB to minimize noise and insertion loss as the electrical signal travels through the signal path of traces and vias on the PCB. Insertion loss refers to the reduction in signal amplitude or power as the signal travels along the signal path of traces and vias on the PCB. Generally, insertion loss increases with the length of the signal path of traces and vias through the PCB.

[0004] As mentioned, the PCB can include a capacitor, which can take the form of a decoupling capacitor. Decoupling capacitors are used to stabilize the power supply of a memory device on the PCB by filtering out noise, minimizing voltage fluctuations, and ensuring nearly instantaneous delivery of power during transient load conditions of the memory device. Ideally, the decoupling capacitor is physically placed near the associated memory device on the PCB.

[0005] However, physical proximity does not guarantee electrical proximity. It is possible that while the decoupling capacitor is in the vicinity of the associated memory device, the current path can involve long distances through various traces and / or vias. Long current paths between the decoupling capacitor and its associated memory device can result in high loop inductance, especially in high-speed interfaces. Loop inductance refers to the inductance that is generated in the PCB by the current path between the decoupling capacitor and its associated memory device. It is desirable to minimize loop inductance because it can cause noise and interference, voltage droop from the decoupling capacitor, and voltage spikes, and can degrade signal integrity.

[0006] Design and layout of a PCB involves multiple steps, including, for example, a high-level schematic design phase, component selection and placement, and electrical routing that defines electrical connections of traces and vias. These phases are performed by a PCB designer using CAD or other electronic design automation software platforms. While signal loss and loop inductance are known parameters that degrade operation of high-speed PCB memory devices, there is currently no automated system or method for measuring or otherwise accounting for these parameters during the PCB design and layout phases. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a schematic block diagram of a computing system for implementing embodiments of the present technology.

[0008] Figure 2 is a top view of a graphical user interface displaying a PCB being designed in accordance with an embodiment of the present technology.

[0009] Figure 3 is a cross-sectional edge view of a graphical user interface displaying a PCB being designed in accordance with an embodiment of the present technology.

[0010] Figure 4 is a flowchart of the operation of an insertion loss tool in accordance with an embodiment of the present technology.

[0011] Figure 5 is a top view of a graphical user interface displaying a PCB being designed in accordance with an embodiment of the present technology.

[0012] Figure 6 is a cross-sectional edge view of a graphical user interface displaying a PCB being designed in accordance with an embodiment of the present technology.

[0013] Figure 7 is another cross-sectional edge view of a graphical user interface displaying a PCB being designed in accordance with an embodiment of the present technology.

[0014] Figure 8 is a flowchart of the operation of a loop inductance tool in accordance with an embodiment of the present technology.

[0015] Figure 9 FIG. 4 is a plot showing inductance loss versus frequency for two different decoupling capacitor PCB designs according to embodiments of the present technology.

[0016] Figure 10 FIG. 5 is a schematic block diagram of a computing environment according to embodiments of the present technology. DETAILED DESCRIPTION

[0017] The present technology will now be described with reference to the drawings, which in embodiments relate to systems and methods for considering insertion loss and / or loop inductance during the design and layout phase of a PCB. In one example, an insertion loss software tool can be integrated into an electronic design automation software platform. The insertion loss software tool analyzes a signal path of traces and vias proposed by a PCB designer and determines whether that signal path can result in insertion loss above some predefined threshold. If so, the PCB designer is alerted so that the designer can re-design the electrical signal routing within the PCB to reduce insertion loss.

[0018] In another example, a loop inductance software tool can be integrated into an electronic design automation software platform. The loop inductance software tool analyzes a current path of traces and vias proposed by a PCB designer and determines whether that current path can result in loop inductance above some predefined threshold. If so, the PCB designer is alerted so that the designer can move or remove decoupling capacitors, or otherwise re-design the power and / or ground paths within the PCB to reduce loop inductance.

[0019] As used herein, a “PCB designer” refers to any of a variety of technical personnel associated with the design and / or verification of a PCB to be used to electrically interconnect various semiconductor dies and other components. In addition to those traditionally referred to as PCB designers, the term as used herein can additionally or alternatively refer to other technical personnel associated with PCB design, layout, or testing, including, for example, hardware engineers, electrical engineers, embedded systems engineers, manufacturing engineers, quality assurance / test engineers, and firmware engineers.

[0020] It should be understood that the application can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the application to those skilled in the art. Indeed, the application is intended to cover alternatives, modifications and equivalents of these embodiments, which are included within the scope and spirit of the application as defined by the appended claims. Furthermore, in the following detailed description of the application, numerous specific details are set forth in order to provide a thorough understanding of the application. However, it will be clear to those of ordinary skill in the art that the application can be practiced without such specific details.

[0021] The terms "top" and "bottom", "upper" and "lower", "vertical" and "horizontal" and forms thereof as can be used herein are by way of example and illustrative purposes only and are not meant to limit the technical description as the referenced items can be exchanged in position and orientation. Additionally, as used herein, the terms "substantially" and / or "about" mean that the specified dimension or parameter can vary within an acceptable manufacturing tolerance for a given application. In one embodiment, the acceptable manufacturing tolerance is ±0.15 mm or alternatively ±2.5% of a given dimension.

[0022] For purposes of this disclosure, a physical connection or an electrical connection can be either a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when a first element is referred to as being connected, attached, mounted, or coupled to a second element (physically or electrically), it can be directly connected, attached, mounted, or coupled to the second element or indirectly connected, attached, mounted, or coupled to the second element (physically or electrically) via one or more other parts. When a first element is referred to as being directly connected, attached, mounted, or coupled to a second element, then there are no intervening elements (other than possibly an adhesive or a molten metal used to connect, attach, mount, or couple the first element and the second element) between the first element and the second element.

[0023] Figure 1 is a schematic block diagram of a sample computing device 100 for implementing an embodiment of the technology. Reference is made below to Figure 1 A more detailed explanation of the sample computing device 100 is provided, but generally the computing device 100 can be a desktop, laptop, mobile handheld computing device, or other processing device. The computing device 100 can include a processor 102 configured to control the operation of the device 100 and to facilitate communication between various components within the device 100. The processor 102 can include a standardized processor, an application-specific processor, a microprocessor, or similar processor that can execute instructions for controlling the computing device 100.

[0024] The computing device 100 can also include a memory 104 that can store algorithms that can be executed by the processor 102. According to example embodiments, the memory 104 can include RAM, ROM, cache, flash memory, hard disks, and / or any other suitable storage components. As Figure 1 shown, in one embodiment, the memory 104 can be a separate component in communication with the processor 102, but in other embodiments, the memory 104 can be integrated into the processor 102.

[0025] The memory 104 can store various data stores and / or software applications executed by the processor 102 for controlling the operation of the computing device 100. For example, the memory 104 can store an electronic design automation (EDA) software program 106 that, when executed by the processor 102, allows a PCB designer to design and layout all aspects of a PCB for use as a memory device. According to aspects of the present technology, the EDA software program 106 can include an insertion loss software tool 108 and an inductance loop software tool 110, each of which are explained in greater detail below. In addition to the tools 108 and 110 of the present technology, the EDA software program 106 can implement a variety of other functions associated with the design and layout of a PCB that are beyond the scope of the present technology, but are known in the art. While the insertion loss software tool 108 and the inductance loop software tool 110 can be integrated into the EDA software program 106, in other embodiments, the insertion loss software tool 108 and / or the inductance loop software tool 110 can operate independently of the EDA software program 106. The computing device 100 can also include a display 112 for displaying a graphical user interface, as explained below.

[0026] The operation of the insertion loss software tool 108 will now be explained with reference to Figures 2 to 4 The insertion loss software tool 108 is an algorithm that is capable of taking into account insertion loss during the design and layout of a PCB. The PCB can be used to implement memory storage, for example, and when complete, can have any of a variety of electronic components mounted thereon, including, for example, processors, non-volatile memory, volatile memory, and passive components including resistors, capacitors, and / or inductors. The PCB can also include a network of electrical traces and vias to carry signals between the electronic components, and between the electronic components and a host device. The insertion loss software tool 108 of the present embodiment is particularly concerned with ensuring that insertion loss in the PCB due to the length of the traces and / or vias is maintained below some predefined maximum value in the completed PCB.

[0027] Figure 2 and Figure 3An example is shown of a graphical user interface (GUI) 120 displayed on a display 112 of a computing device 100 while running an EDA software program 106. Figure 2 The GUI display 120 illustrates a top view of PCB122, and Figure 3 The GUI display 120 illustrates a cross-sectional side view of PCB 122. Figure 2 The graphic illustration of PCB 122 shows the top surface 124 of PCB 122, including contact pads 126, traces 128, and vias 130 (some of which are in...). Figure 2 The layout is numbered in the diagram. Contact pads 126 are configured to receive electronic components (such as control and / or memory dies) or passive components (such as capacitors, resistors, and / or inductors). Traces 128 are configured to carry signals to and from the contact pads 126 in the top surface 124 of the PCB 122. Vias 130 are configured to pass through the thickness of the PCB 122 to carry signals to and from the contact pads 126 and traces 128, as described below. Figure 3 The pattern of pads 126, traces 128, and vias 130 is created by the PCB designer using EDA software program 106. Figure 2 The GUI display 102 shown is by way of example only. Using EDA software programs, PCB designers can provide the GUI display 102 with any of a variety of other layouts for contact pads 126, traces 128, and / or vias 130 on the top surface 124 of the PCB 122 in other embodiments.

[0028] Figure 3 The GUI display 120 illustrates a cross-sectional side view of PCB 122. Figure 3 The display 120 shows a top surface 124 including contact pads 126, traces 128 and vias 130 visible at a selected cross-section. Figure 3 The GUI display 120 also shows multiple internal layers of the PCB 122, including a ground plane 134 (shown as dotted lines), a power plane 136 (shown without shading), and a signal plane 138 (shown with slight shading). Each of the ground plane 134, power plane 136, and signal plane 138 is separated by electrically insulating dielectric layers 140 (some of which are numbered). Figure 3 The GUI display 120 also illustrates multiple solder balls 142 that are to be mounted on the bottom surface 144 of the PCB 122. Figure 3The GUI display 120 shown is by way of example only. The patterns of pads 126, traces 128, vias 130, ground planes 134, power planes 136, signal planes 138, and solder balls 142 are created by the PCB designer using the EDA software program 106. Using the EDA software program, the PCB designer can provide the GUI display 120 with any of a variety of other layouts of contact pads 126, traces 128, vias 130, ground planes 114, power planes 116, signal planes 118, and solder balls 142 in a cross-sectional edge view of a PCB 122 in other embodiments.

[0029] While Figure 2 And Figure 3 A large number of traces 128 and vias 130 are shown, but a relatively small number of these are used to carry data signals between the contact pads 126 on the top surface 124 of the PCB 122 and the solder balls 142 on the bottom surface 144. Figure 3 A dashed line is shown highlighting one such signal path 150 between a contact pad 126 on the surface 124 and a solder ball 142 on the surface 144. Figure 3 The signal path 150 shown includes a trace 128 on the top surface 144, a via 130a extending between the top surface 144 and the signal plane 138, an electrical trace 128 (not shown) in the signal plane 138, and a via 130b extending from the signal plane 138 to the solder ball 142. It will be appreciated that the PCB designer can provide the signal path 150 with a variety of other traces 128, vias 130, signal planes 138, and routing through the PCB 122 in other examples. In general, a signal path can have a starting point at one of the first and second surfaces 124, 144 of the PCB 122 and an ending point at one of the first and second surfaces 124, 144 of the PCB. Further, it will be appreciated that the PCB designer can include 2, 3, 4, 5, 6, 7, 8, or more such signal paths between contact pads 126 on the surface 124 and solder balls 142 on the surface 144.

[0030] According to aspects of the present technology, as (or after) the PCB designer provides a layout of one or more signal paths 150, the insertion loss software tool 108 analyzes the layout and provides a warning when one or more signal paths 150 can result in an insertion loss higher than some predefined maximum. The insertion loss can be calculated by the tool 108 using the following formula, the Nyquist frequency, and a predefined maximum allowable insertion loss limit, which can be fed into the tool as a constraint input by the PCB designer. The signal attenuation factor of a signal path 150 of length, L, is:

[0031]

[0032] Attenuation or signal loss factor can be expressed in dB:

[0033] dB loss = 20 log 10 (attenuation factor) (2)

[0034] Thus:

[0035]

[0036] The dB loss is proportional to the length of the signal path line. Thus, the above can be expressed as the dB loss per unit length:

[0037]

[0038] The negative sign can be omitted (it is the dB loss, always subtracted from the signal strength in dB. Thus, the total insertion loss per unit length of the signal path transmission line can be given as:

[0039]

[0040] The R / z0component of this loss is proportional to the resistance R per unit length of length and is referred to as conductor loss and I. It is represented by a C The G / z0component of this loss is proportional to the conductivity G of the dielectric material and is referred to as dielectric loss. It is represented by a d Thus:

[0041]

[0042] All of the required data for the above are known and can be input to the EDA software program 106. The trace width and spacing between the P and N signals are also known and can be input to the EDA software program 106. The maximum allowable insertion loss data can also be predefined and input into the EDA software program 106.

[0043] Figure 5 is a flowchart showing the operation of the insertion loss tool 108. In step 200, the tool can receive all trace and via parameters from the PCB designer based on the PCB manufacturing shop specifications. These include the cross-sectional dimensions of the traces 128 and vias 130, the properties of the traces 128 and vias 130 such as the dielectric constant (Dk) and loss tangent (Df) which indicate the loss per unit length, the trace spacing for controlled impedance, the added thickness of the layers of the PCB 122.

[0044] In step 202, the tool can also receive the Nyquist frequency of the signal path. The Nyquist frequency is defined as half the sampling rate of the signal passing through the traces 128 and vias 130. The Nyquist frequency is the highest frequency that the PCB 122 can reliably measure at a given sampling rate or half of a given sampling rate. In step 204, the tool can also receive the maximum allowable insertion loss of the signal path. The maximum allowable insertion loss can be predefined based on a manufacturing plant or a standard specification, and can be, for example, 36 dB. This is a total sum across all signal paths 150. Other maximum allowable insertion loss values are possible. Alternatively, each individual signal path can have a predefined maximum allowable insertion loss. For example, if there are four signal paths 150 for transmitting a signal, the total insertion loss for each signal path 150 can be the total signal loss across all signal paths divided by 4. Other properties of the PCB can be stored in step 200.

[0045] In step 208, the tool 108 receives the layout of the PCB from the PCB designer, including all defined signal paths 150, as shown in the GUI display of, for example, Figure 2 and Figure 3 In step 210, the tool sums the lengths of all signal paths, including the signal paths 150 in, for example, Figure 3

[0046] In step 214, the tool 108 uses the determined signal path lengths and the above equations (1)-(6) to calculate the insertion loss for each signal path. In an embodiment, the traces 128 and vias 130 can be treated the same for the purpose of calculating the insertion loss for a given signal path. However, the traces 128 and vias 130 can have different electrical properties per unit length, and thus different insertion losses. Therefore, in other embodiments, the lengths of the traces in a given signal path can be summed and the insertion loss for the traces can be calculated using values specific to the traces, and the lengths of the vias in a given signal path can be summed and the insertion loss for the vias can be calculated using values specific to the vias. Thereafter, the determined trace insertion loss and the determined via insertion loss for a signal path can be added together to give the total insertion loss for the entire signal path.

[0047] ​In step 214, tool 108 determines whether the insertion loss exceeds a predetermined maximum value. Again, this can be calculated on each signal path 150 or together on all signal paths 150. If it is determined in step 214 that the insertion loss for a single signal path or the entire signal path exceeds the predetermined maximum value, the PCB designer is notified in step 216, and a suggestion is made to redesign the signal paths in a way that reduces signal path length and insertion loss. In an embodiment, insertion loss tool 108 may suggest how to reduce one or more signal paths exceeding the predetermined maximum value, for example, by analyzing suggested signal paths and identifying paths with shorter trace lengths and / or via lengths. The process then returns to step 208, where the PCB designer can make changes to one or more signal paths in the signal paths 150. On the other hand, if it is determined in step 214 that the insertion loss for a single signal path or the entire signal path is within the predetermined maximum value, the process continues to step 218 for the signal designer to complete the layout of PCB 122.

[0048] As mentioned above, in addition to or instead of the insertion loss tool 108, this technique can implement the loop inductor tool 110 in a PCB layout of 120\2. The implementation scheme of the loop inductor tool 110 will now be referred to... Figures 5 to 8 To describe. For example... Figure 5 As shown in the top view, a PCB designer may include multiple semiconductor dies 154 on PCB 122 (e.g., on surface 124 of PCB 122). These semiconductor dies 154 may include, for example, memory dies, such as non-volatile memory dies and volatile memory dies. Non-volatile memory dies may be, for example, NAND memory dies or so-called bit-cost scaling (or BiCS) memory dies. Other types of non-volatile memory dies are possible. Volatile memory dies may be, for example, random access memory (such as DRAM or SRAM). Other types of volatile memory are possible.

[0049] High-frequency PCBs (such as those anticipated by this technology) typically use capacitors as a source of stable and near-instantaneous current for the semiconductor die 154. Ideally, these capacitors, referred to as decoupling capacitors 156, should be placed close to the semiconductor die 154 they serve. Figure 5 The top view shows several sample decoupling capacitors 156, but more capacitors could exist to serve each semiconductor die 154.

[0050] The proximity of decoupling capacitors 156 to current sink ends, such as semiconductor dies 154, can affect the impedance of the power distribution network (PDN) of PCB 122. The impedance of the PDN determines how effectively it can supply a stable and low-noise power supply to semiconductor dies 154 and other electronic components on PCB 122. By placing decoupling capacitors 156 close to their associated semiconductor dies 155, they can provide a low-impedance path for high-frequency current loops. High-frequency currents generated by the switching activity of semiconductor dies 154 can flow in loops between the power supply and the ground pins of semiconductor dies 154. Figure 6 A cross-sectional edge view of one such loop 160 is shown. Decoupling capacitors 156 placed near semiconductor dies 154 act as local charge reservoirs to supply high-frequency current demand with minimal impedance. This reduces voltage drop and noise on the power supply lines, ensuring fast and stable power delivery to semiconductor dies 154.

[0051] The close proximity of decoupling capacitors 156 to their associated current sink ends can also reduce the loop inductance of the high-frequency current path. Inductance in the power distribution network can cause voltage spikes and ringing, degrading the performance of semiconductor dies 154 and causing electromagnetic interference (EMI). By minimizing loop inductance, decoupling capacitors 156 help maintain a lower-impedance path for high-frequency currents, improving the overall integrity of the power distribution system.

[0052] Therefore, PCB designers typically place decoupling capacitors 156 close to their associated semiconductor dies 154. However, a problem that is often overlooked by PCB designers is that physical proximity is not necessarily equivalent to electrical proximity. Figure 5 A cross-sectional edge view of one such loop 160 is shown. Decoupling capacitors 156 placed near semiconductor dies 154 act as local charge reservoirs to supply high-frequency current demand with minimal impedance. This reduces voltage drop and noise on the power supply lines, ensuring fast and stable power delivery to semiconductor dies 154. Figure 6 is a cross-sectional edge view of decoupling capacitors 156 and their associated semiconductor dies 154. As seen, while physically close to each other, physical proximity is not necessarily equivalent to a short path for current travel, referred to herein as a current loop 160. Figure 7 is another cross-sectional edge view in which decoupling capacitors 156 and their associated semiconductor dies 154 are close to each other, aligned with each other on opposite surfaces of PCB 122. However, again, physical proximity does not mean that the current loop 160 between decoupling capacitors 156 and semiconductor 154 is optimized.

[0053] According to aspects of the present technology, the loop inductance tool 110 measures the loop inductance of each current loop between a decoupling capacitor 156 and the semiconductor die 154 with which it is associated to determine whether the loop inductance is above some predefined threshold. If so, the PCB designer is notified so that he or she can re-design the PCB layout to reduce the length of the current loop between a given decoupling capacitor 156 and the semiconductor die 154 with which it is associated.

[0054] The loop inductance for a decoupling capacitor 156 is calculated by using the following equation:

[0055]

[0056] where L eff is the effective loop inductance, Z(decap (decoupling capacitor) supply, GND pad) represents the Z parameter of the port defined across the supply and ground pads of the corresponding decoupling capacitor 156. A 1 MHz frequency can be used in the loop inductance extraction, although other frequencies are possible.

[0057] The operation of the loop inductance tool 110 will now be explained with reference to the flowchart of Figure 8 The PCB designer inputs a value for the maximum allowable loop inductance for each decoupling capacitor inductance loop 160, which is stored in step 230. The maximum allowable loop inductance can be, for example, 0.3 nH, although other values are possible. In step 232, the tool 110 receives the layout of the PCB from the PCB designer, including all semiconductor dies 154, decoupling capacitors, all vias defining the inductance loop for each decoupling capacitor and its associated semiconductor die, ground planes, and supply planes. Figures 5 to 7 An example of such a layout is shown.

[0058] In step 234, the tool determines the length of all current loops 160, including, for example, the current loops 160 shown in Figure 6 and Figure 7 In step 236, the tool 110 uses the determined current loop lengths and the above equation 7 for determining the loop inductance to calculate the inductance for each current loop 160.

[0059] In step 238, the tool 110 determines whether the loop inductance for a given current loop 160 exceeds a predetermined maximum value. If it is determined in step 238 that the loop inductance for one or more of the current loops exceeds the predetermined maximum value, this is communicated to the PCB designer in step 240, and the PCB designer is invited to redesign the current loops in a manner that reduces the length of the current loops and thus the loop inductance. In embodiments, the loop inductance tool 110 can make recommendations on how to reduce the loop inductance in one or more current loops that exceed the predetermined maximum value, for example by analyzing the proposed current loops and identifying loops with shorter total distance through one or more vias 130 and / or one or more ground planes 134 / power planes 136. The flow then returns to step 232, in which the PCB designer can make changes to one or more of the current loops 160. If, on the other hand, it is determined in step 238 that the loop inductance for each of the current loops 160 is within the predetermined maximum value, the flow continues to step 242, as explained below.

[0060] It is possible that any redesign of the PCB 122 will result in a change in the direct current (DC) voltage drop across the circuit of the PCB 122. The DC voltage drop refers to the reduction in voltage experienced across a circuit or interconnect path when DC current flows through it. In the PCB 122, such a drop occurs due to the electrical resistance encountered by the current as it passes through electrically conductive material, such as the vias 130, ground planes 134 and power planes 136 and other interconnects. There needs to be a sufficient number of vias and traces in the ground planes and power planes with sufficient cross-section to prevent the voltage drop from being above a predefined minimum value. This predefined minimum value can be provided by a specification and known to the PCB designer.

[0061] In step 242, the loop inductance tool 110 measures the voltage drop resulting from any redesign necessitated by steps 234-240 (or by the circuit as it was without redesign in steps 234-240). In step 244, the tool 110 determines whether the voltage drop exceeds a predetermined maximum value. If it is determined in step 244 that the voltage drop through the PCB exceeds the predetermined maximum value, this is communicated to the PCB designer in step 246, and the PCB designer is invited to redesign the circuit of the PCB 122 in a manner that reduces the current drop. The flow then returns to step 232, in which the PCB designer can make changes to the circuit.

[0062] Any redesign of the circuit in response to step 244 should still take into account loop inductance. Thus, when changes are made to the circuit in step 232, the loop inductance tool 110 again performs steps 234-240 as described above to ensure that the loop inductance of the current loop 160 remains below the predetermined maximum. Steps 234-246 are performed (possibly multiple times) allowing the PCB designer to make changes until the loop inductance of the current loop 160 is below the predetermined maximum and the voltage drop is above the predetermined maximum. When this goal is reached, the loop inductance engine moves to step 248 for decoupling capacitor and PDN (power distribution network) optimization as explained in the following paragraphs.

[0063] In step 248, after capacitor loop inductance and DC analysis, capacitor and PDN optimization is performed using the capacitor loop inductance data. This data is calculated in steps 234-236. In step 248, the loop inductance tool 110 optimizes the number and type of decoupling capacitors used and the PDN impedance. At a high level, this is done by performing an alternating current (AC) frequency domain simulation to ensure that the AC ripple is within the limits set by the AC specification. This AC analysis ensures the required PDN impedance to reduce / suppress the voltage ripple caused by different frequencies of current. This can be represented as the equation:

[0064] V(f) = I AC (f) * Z(f), (8)

[0065] where I AC (f) is the alternating current at a given frequency; Z = impedance of the PDN at a given frequency; and V(f) is the voltage ripple. All parameters are functions of frequency.

[0066] To reduce / suppress the voltage ripple (V(f)), the PCB designer can remove or change the location of decoupling capacitors to optimize both decoupling capacitor usage and PDN impedance. One process for performing the optimization of decoupling capacitors and PDN impedance uses the following steps. First, the loop inductance data for all decoupling capacitors is sorted in descending order. Again, this data is collected in steps 234-236. Next, the PCB designer can remove one or more of the highest loop inductance decoupling capacitors and run the AC frequency domain simulation given by equation (8) for the circuit before and after removing the one or more highest loop inductance capacitors.

[0067] If as Figure 9The illustrated overlapping raw and modified frequency domain curves appear similar in the high frequency region and the PDN impedance (Zpdn) is less than or equal to the predefined target impedance (Ztarget), the PCB designer can remove the first set of one or more high loop inductance capacitors. Figure 9 The example of FIG. 6 illustrates the raw frequency domain curve (solid line) and the modified frequency domain curve (dashed line) with the first set of decoupling capacitors removed. As seen, in the high frequency region (> 0.01 GHz), the raw and modified frequency domain curves appear identical. This indicates that the first set of one or more high loop inductance capacitors can be removed. The PCB designer can then successively perform the above steps on the next lower loop inductance decoupling capacitors until all decoupling capacitors have been analyzed and removed if allowed by the above steps.

[0068] In the above comparison of the PDN impedance (Zpdn) and the target impedance (Ztarget), the target impedance can be given by a specification. Alternatively, the target impedance can be calculated using the following formula:

[0069]

[0070] Using the above steps, high impedance loop inductance capacitors can be removed from a PCB design. Alternatively, instead of removing a given decoupling capacitor, it can be replaced with a small value decoupling capacitor, for example changing a capacitor from 0.1 uF to 1 uF. Other alternatives to decoupling capacitor values are possible.

[0071] Figure 10 An example computing system 300 is illustrated, which can be a computing device 100 or other device for implementing embodiments of the present technology. Figure 10 The computing system 300 of FIG. 3 includes one or more processors 310 and a main memory 320. The main memory 320 stores, in part, instructions and data for execution by the processor unit 310. The main memory 320 can store the executable code when the computing system 300 is in operation. Figure 10 The computing system 300 can further include a mass storage device 330, a portable storage medium drive 340, an output device 350, user input devices 360, a display system 370, and other peripheral devices 380.

[0072] Figure 10The illustrated components are connected via the single bus 390. The components can be connected by one or more data transport means. The processor unit 310 and the main memory 320 can be connected via a local microprocessor bus, and the mass storage device 330, peripheral device(s) 380, portable storage medium drive(s) 340, and display system 370 can be connected via one or more input / output (I / O) buses.

[0073] The mass storage device 330 embodied as a magnetic or optical disk drive is a non-volatile storage device for storing data and instructions for use by the processor unit 310. The mass storage device 330 can store the system software used to implement embodiments of the present application to load that software into the main memory 320.

[0074] The portable storage medium drive 340 operates in conjunction with a portable non-volatile storage medium, such as a floppy disk, compact disk or digital video disk, to input and output data and code to and from the computing system 300. The system software used to implement embodiments of the present application can be stored on such a portable medium and input to the computing system 300 via the portable storage medium drive 340. Figure 10

[0075] The input devices 360 provide a portion of the user interface. The input devices 360 can include an alphanumeric keypad, such as a keyboard, for inputting alphanumeric and other information, or a pointing device, such as a mouse, trackball, stylus, or cursor direction keys. Additionally, the input devices 360 can include a microphone for inputting voice commands. Figure 10 The system 300 as illustrated includes output devices 350. Suitable output devices include speakers, printers, network interfaces, and monitors. Where the computing system 300 is part of a mechanical client device, the output devices 350 can also include servo controls for motors within the mechanical device.

[0076] The display system 370 can include a liquid crystal display (LCD) or other suitable display device. The display system 370 receives textual and graphical information, and processes that information for output to the display device.

[0077] The peripheral devices 380 can include any type of computer support device, to add additional functionality to the computing system. The peripheral devices 380 can include a modem or a router.

[0078] The components contained in the computing system 300 are those typically found in computing systems of this type. However, other components can be used in addition to, or instead of, those shown here. For example, a Figure 10 ​The components of computing system 300 are those typically found in computing systems that can be suitable for use with embodiments of the application and are intended to represent a broad category of such computer components. The above-described components (hardware and software) are not intended to be exhaustive, but rather are among the various components that can be suitable for use with embodiments of the application. The disclosure is not intended to be limited to the contexts shown, but is intended to extend to any number of other components, layouts, and configurations within the scope of the embodiments of the application. ​ Computing system 300 can be a personal computer, hand-held computing device, telephone, mobile computing device, workstation, server, minicomputer, mainframe computer, or any other computing device. The computer can also include different bus configurations, networked platforms, multi-processor platforms, etc. Various operating systems can be used including UNIX, Linux, Windows, Macintosh OS, Palm OS, and other suitable operating systems.

[0079] Some of the above-described functions can be comprised of instructions that are stored on a storage medium (e.g., computer readable medium). The instructions can be retrieved and executed by a processor. Some examples of storage media are memory devices, tapes, disks, and the like. The instructions, when executed by the processor, are operable to direct the processor to perform the functions described herein. Those skilled in the art are familiar with instructions, processors, and storage media.

[0080] It is noted that any hardware platform suitable for performing the processing described herein is suitable for use with the present application. The terms "computer readable storage medium" and "computer readable storage media" as used herein refer to any one or more media that participate in providing instructions to a CPU for execution. Such media can take many forms, including but not limited to, non-volatile media, volatile media, and transmission media. Non-volatile media includes, for example, optical or magnetic disks, such as a fixed disk. Volatile media includes dynamic memory, such as system RAM. Transmission media includes coaxial cables, copper wire, and fiber optics, among others, including the wires that comprise a bus that is one embodiment of the transmission medium. Transmission media can also take the form of acoustic or light waves, such as those generated during radio frequency (RF) and infrared (IR) data communications. Common forms of computer readable media include, for example, floppy disk, flexible disk, hard disk, magnetic tape, any other magnetic medium, CD-ROM, digital video disk (DVD), any other optical medium, punch cards, paper tape, any other physical medium with patterns of holes, RAM, PROM, EPROM, FLASH-EPROM, any other memory chip or cartridge, a carrier wave, or any other medium from which a computer can read.

[0081] Various forms of computer-readable media can be involved in carrying one or more sequences of one or more instructions to the CPU for execution. A bus carries the data to system RAM, from which the CPU retrieves and executes the instructions. The instructions received by system RAM can optionally be stored on a fixed disk, either before or after execution by the CPU.

[0082] In general, examples of the present technology relate to a system for design of a printed circuit board (PCB), the system comprising: one or more processors; a memory storing: an insertion loss tool that, when executed by the one or more processors, measures insertion loss along one or more signal paths in a layout of the PCB; and an inductance loop tool that, when executed by the one or more processors, measures inductance loss along a current loop connecting a proposed location of a semiconductor die in the layout of the PCB and a decoupling capacitor associated with the semiconductor die in the layout of the PCB.

[0083] In another example, the present technology relates to a method of designing a PCB having insertion loss within predefined limits, the method comprising the steps of: storing trace and via parameters for traces and vias to be used in design of the PCB; storing a maximum allowable insertion loss for a signal path having a start point at one of a first surface and a second surface of the PCB and an end point at one of the first surface and the second surface of the PCB; receiving a proposed layout of the PCB, including a layout of vias and traces; analyzing the proposed layout to determine insertion loss along one or more signal paths; and generating a message that one or more signal paths need to be redesigned in the case that the one or more signal paths have insertion loss above a predefined maximum value.

[0084] In another example, the present technology relates to a method of designing a PCB having loop inductance along a current path within predefined limits, the method comprising the steps of: storing a maximum allowable loop inductance for a current loop to electrically couple a proposed semiconductor die to a proposed decoupling capacitor; receiving a proposed layout of the PCB, including a layout of via ground planes, signal planes, the proposed semiconductor die, and the proposed decoupling capacitor; analyzing the proposed layout to determine loop inductance along one or more current loops; and generating a message that one or more current loops need to be redesigned in the case that the one or more current loops have loop inductance above a predefined maximum value.

[0085] The foregoing detailed description of the application has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the application to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best illustrate the principles of the application and its practical application to thereby enable others skilled in the art to best utilize the application in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the application be defined by the claims appended hereto.

Claims

1. A system for designing printed circuit boards (PCBs), the system comprising: One or more processors; The memory stores: An insertion loss tool, which, when executed by the one or more processors, measures the insertion loss along one or more signal paths in the layout of the PCB; and An inductor loop tool, when executed by the one or more processors, measures the inductance loss along a current loop that connects the suggested locations of semiconductor dies in the layout of the PCB and decoupling capacitors associated with the semiconductor dies in the layout of the PCB.

2. The system according to claim 1, wherein, The insertion loss tool receives a proposed layout of the PCB, including vias and traces, and determines the insertion loss along a subset of signal paths that include vias and traces.

3. The system according to claim 2, wherein, The insertion loss tool measures and sums the lengths of vias and traces in the signal path, and determines the insertion loss along the signal path in part based on the summed lengths of the vias and traces.

4. The system according to claim 1, wherein, The insertion loss tool recommends a redesign of the PCB layout if the insertion loss along the signal path exceeds a predefined maximum value.

5. The system according to claim 4, wherein, The insertion loss tool proposes recommendations on how to redesign the PCB layout to reduce insertion loss along the signal path.

6. The system according to claim 5, wherein, The recommendation made by the insertion loss tool is based on an analysis of the current suggested layout of the PCB and finds a shorter signal path consisting of one or more of a shorter path through traces on the PCB and a shorter path through vias on the PCB.

7. The system according to claim 1, wherein, The loop inductor tool receives a proposed layout of the PCB including a semiconductor die, decoupling capacitors, vias, a power plane, and a ground plane, and determines a loop inductor along a current path including a subset of vias between the semiconductor die and the decoupling capacitors, the power plane, and the ground plane.

8. The system according to claim 7, wherein, The loop inductance is partly based on the distance the current travels along the current path.

9. The system according to claim 1, wherein, The loop inductance tool recommends a redesign of the suggested PCB layout if the loop inductance along the current loop exceeds a predefined maximum value.

10. The system according to claim 9, wherein, The loop inductance tool suggests how to redesign the PCB layout to reduce loop inductance along the current loop.

11. The system according to claim 10, wherein, The recommendation made by the loop inductance tool is based on an analysis of the current suggested layout of the PCB and finds a shorter current loop consisting of one or more of the following: a shorter path through the ground plane on the PCB, a shorter path through the power plane on the PCB, and a shorter path through the vias on the PCB.

12. A method for designing a PCB with insertion loss within a predefined limit, the method comprising the following steps: (a) Store trace and via parameters for use in the design of the PCB; (b) Store the maximum allowable insertion loss for a signal path having a start point at one of the first and second surfaces of the PCB and an end point at one of the first and second surfaces of the PCB. (c) Receive the proposed layout of the PCB, including the layout of vias and traces; (d) Analyze the proposed layout to determine the insertion loss along one or more signal paths; as well as (e) Generate one or more signal paths in the signal path that require redesign if one or more signal paths in the signal path have an insertion loss higher than a predefined maximum value.

13. The method according to claim 12, further comprising the following steps: Store the Nyquist frequency of the signal path in the proposed layout of the PCB.

14. The method according to claim 12, further comprising the following step: One or more signal paths, indicated to have insertion loss higher than the predefined maximum value, are redesigned by shortening the length of one or more of the vias and traces in one or more signal paths that are indicated to have insertion loss higher than the predefined maximum value.

15. A method for designing a PCB having a loop inductance along a current path within predefined limits, the method comprising the steps of: (a) Store the maximum permissible loop inductance for a current loop that electrically couples the proposed semiconductor die to the proposed decoupling capacitor; (b) Receive the proposed layout of the PCB, including the layout of via ground plane, signal plane, proposed semiconductor die and proposed decoupling capacitor; (c) Analyze the proposed layout to determine the loop inductance along one or more current loops; and (d) A message indicating that one or more current loops of the current loop need to be redesigned if one or more current loops of the current loop have a loop inductance higher than a predefined maximum value.

16. The method of claim 15, further comprising the step of: Redesign one or more current loops that are instructed to have a loop inductance higher than the predefined maximum value.

17. The method according to claim 16, wherein, The step of redesigning the one or more current loops includes the step of shortening the length of the one or more current loops, wherein one or more of the vias and traces in the one or more signal paths are indicated to have an insertion loss higher than the predefined maximum value.

18. The method according to claim 16, wherein, The steps of redesigning the one or more current loops include the following steps: removing or changing the value of the decoupling capacitor.

19. The method of claim 15, further comprising the step of: Measure the DC voltage drop across the proposed circuit on the layout of the PCB, and if the DC voltage drop is higher than a predefined maximum value, redesign the proposed circuit.

20. The method of claim 15, further comprising the step of: The recommended number and type of decoupling capacitors and the overall power distribution network (PDN) impedance are optimized by performing AC frequency domain simulations to ensure that AC ripple is within the limits set by predefined AC specifications.

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