A high speed analog multiplier circuit

Abstract

This invention discloses a high-speed analog multiplier circuit, belonging to the field of integrated circuit signal processing. It improves high-frequency performance by dynamically adjusting the tail current through a frequency detection network. This network amplifies the differential signal V2 via a differential-to-single-ended converter, then attenuates high-frequency components through a low-pass RC filter. The comparator output controls the substrate bias voltage of the tail current source. As the frequency of V2 increases, the substrate bias voltage increases, utilizing the NMOS substrate bias effect to lower the threshold voltage, thereby increasing the tail current and compensating for high-frequency gain attenuation. Two alternative solutions are provided: a parallel transistor and a self-biased tail current source. This circuit has a simple structure, significantly extends the multiplier bandwidth, and is suitable for high-speed communication and signal processing systems.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit signal processing technology, and more specifically to a high-speed analog multiplier circuit. Background Technology

[0002] Analog multipliers can multiply two uncorrelated analog signals and are widely used in analog operations such as multiplication, division, square root, and squaring, as well as in analog signal processing such as mixing, modulation, frequency discrimination, and phase discrimination. As a core module of mixed-signal processing systems, the performance of analog multipliers directly affects the bandwidth and linearity of applications such as communication systems, radar signal processing, and high-speed data converters. Especially in scenarios like 5G millimeter-wave communication and automotive 77GHz millimeter-wave radar, multipliers face high demands. Traditional Gilbert units suffer from high-frequency gain attenuation due to fixed tail currents, becoming a bottleneck limiting system performance. The classic Gilbert four-quadrant multiplier, composed of differential pairs, switching pairs, and tail current sources, suffers from pole limitations, tail current nonlinearity, and dynamic range collapse at high frequencies. Researchers have proposed using a common-source cascode structure to improve output impedance and modify the position of the dominant pole, but this sacrifices voltage margin and exacerbates nonlinear distortion. Another approach is a transconductance compensation circuit based on envelope detection, which detects the signal envelope. However, this scheme cannot distinguish between frequency and amplitude. When the second input voltage signal V2 of the multiplier is a high-amplitude, low-frequency signal such as an AM-modulated carrier, it mistakenly increases the current value I of the tail current source. EE This leads to a surge in power consumption and an inability to track transient changes in signals above 5GHz, resulting in delayed response. Researchers also attempted to adjust the threshold voltage V using the bias effect. th It is applied directly to the switching transistor, but this will cause a change in the substrate bias V. th Causes the difference pair ΔV th Mismatch and substrate noise coupling increase the output noise spectral density and degrade the noise. In summary, existing technologies improve bandwidth by optimizing transistor size or cascade structure, but do not solve the linearity degradation problem caused by fixed tail current. Especially when the input voltage signals V1 and V2 of the multiplier are high-frequency signals, the dynamic range of the output current is limited, affecting the performance of applications such as radar signal processing.

[0003] Therefore, there is an urgent need for a high-speed analog multiplier circuit in existing technologies. Summary of the Invention

[0004] The purpose of this invention is to provide a high-speed analog multiplier circuit to solve the problem that existing technologies cannot boost I only for high-frequency signals. EE This results in wasted power consumption under low-frequency large signals. The mismatch and noise introduced by the substrate bias modulation have a significant impact, and it is difficult to maintain the dynamic range of output current ΔIpp≥1mA in the >20GHz frequency band.

[0005] To solve the above-mentioned technical problems, the present invention specifically provides the following technical solution:

[0006] A high-speed analog multiplier circuit includes a four-quadrant multiplier, a tail current source, and a frequency detection network module;

[0007] The core of the four-quadrant multiplier is the Gilbert unit. The first differential input terminal of the Gilbert unit is connected to the differential signal V1, the second differential input terminal is connected to the differential signal V2, and the tail current input terminal of the Gilbert unit is connected to the output terminal of the tail current source.

[0008] The tail current source uses an NMOS transistor. The drain of the NMOS transistor is connected to the tail current input terminal of the Gilbert cell, the source of the NMOS transistor is grounded, and the substrate of the NMOS transistor is connected to the output terminal of the frequency detection network module.

[0009] The frequency detection network module receives a differential signal V2 at its input and outputs a control voltage Vctl to the substrate of the NMOS transistor to adjust the tail current output by the tail current source.

[0010] Furthermore, the frequency detection network module includes a differential-to-single-ended amplifier, an RC low-pass filter, and a comparator. The input of the differential-to-single-ended amplifier is connected to the differential signal V2, and the output is connected to the input of the RC low-pass filter. The tail current source uses an NMOS transistor, and the substrate of the NMOS transistor is connected to the output of the comparator. The substrate bias voltage is adjusted by the control voltage Vctl output by the comparator. The threshold voltage of the NMOS transistor is changed through the substrate bias effect to adjust the tail current value.

[0011] Furthermore, the tail current source uses an NMOS transistor, whose substrate bias voltage is controlled by the comparator output based on the comparison result, and the threshold voltage is changed by utilizing the substrate bias effect to adjust the current value.

[0012] Furthermore, the aforementioned bias effect satisfies Where V th V is the NMOS threshold voltage. TH0 γ is the threshold voltage at zero substrate bias, and γ is the bulk effect coefficient. V is the surface potential. SB The source-substrate voltage is given by V. ctl control.

[0013] Furthermore, the transfer function of the RC low-pass filter is H(s) = 1 / (1+sRC), where s is the complex frequency, R is the resistance, and C is the capacitance, used to attenuate the high-frequency components of the input differential signal V2.

[0014] Furthermore, the tail current source employs two parallel transistors, one of which is connected in series with an NMOS current-limiting transistor. The gate and substrate of the NMOS transistor are connected to the output control voltage V of the frequency detection network module. ctl .

[0015] Furthermore, when V ctl When the voltage increases, the threshold voltage V of the NMOS current limiting transistor... th The decrease causes the current in that branch to increase.

[0016] Furthermore, the high-speed analog multiplier circuit also includes a self-biased tail current regulation circuit. This circuit dynamically stabilizes the operating point through a negative feedback mechanism. The self-biased tail current regulation circuit includes npn bipolar transistors Q1 and Q2 forming a 1:1 current mirror, a negative feedback loop actuator, and a negative feedback loop controller. The negative feedback loop actuator is an NMOS transistor M1, with its gate connected to the collector node of Q1. The negative feedback loop controller is a resistor R1 connected to the power supply voltage V. DD Between the collector and Q1.

[0017] Furthermore, the output current I of the self-biased structure tail Stability is achieved by the negative feedback loop, satisfying ΔI tail / ΔV th <0.

[0018] Furthermore, the core of the four-quadrant multiplier is a Gilbert unit.

[0019] The beneficial effects of this invention are as follows: by using a differential-to-single-ended amplifier for signal conversion, an RC low-pass filter for high-frequency attenuation, and a comparator for generating a substrate bias control voltage to dynamically adjust the tail current, high-frequency gain compensation and bandwidth expansion are achieved. The tail current adaptively increases, compensating for the high-frequency gain attenuation caused by the core pole of the multiplier. Moreover, the circuit is simple and easy to implement, and supports multiple schemes such as substrate bias adjustment, parallel transistors, and self-biased tail current sources. It is suitable for high-speed scenarios such as 5G millimeter-wave communication. Attached Figure Description

[0020] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely exemplary, and those skilled in the art can derive other embodiments based on the provided drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the overall circuit structure as described in Embodiment 1 of the present invention;

[0022] Figure 2This is a circuit diagram of the adaptive tail current source for current limiting control as described in Embodiment 2 of the present invention;

[0023] Figure 3 This is the self-biased adjustable tail current source circuit described in Embodiment 3 of the present invention;

[0024] Figure 4 This is a circuit diagram of a conventional Gilbert four-quadrant analog multiplier as described in Comparative Example 1 of the present invention.

[0025] Figure 5 This is a schematic diagram illustrating the increased bandwidth of the analog multiplier described in this invention. The horizontal axis in the figure represents the frequency f, and the vertical axis represents the transconductance Gm2. It includes two curves: the "improved gain curve" and the "original gain curve," which are used to demonstrate the effect of this circuit on expanding the bandwidth of the multiplier. Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] The concepts involved in this application will first be described with reference to the accompanying drawings. It should be noted that the following descriptions of various concepts are only for the purpose of making the content of this application easier to understand and do not constitute a limitation on the scope of protection of this application; furthermore, the embodiments and features in the embodiments of this application can be combined with each other unless otherwise specified. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0028] Example 1

[0029] This invention provides a high-speed analog multiplier circuit, including a four-quadrant multiplier, a tail current source, and a frequency detection network module, such as... Figure 1 As shown, the four-quadrant multiplier is used to receive differential signals V1 and V2, where V1 = U1cos(w1t) and V2 = U2cos(w2t), respectively, and U1 and U2 are the signal amplitudes of differential signals V1 and V2, respectively, and w1 and w2 are the angular frequencies of differential signals V1 and V2, respectively. The frequency detection network module includes a differential-to-single-ended amplifier, an RC low-pass filter, and a comparator.

[0030] The differential-to-single-ended amplifier is used to convert the input differential signal V2 into a single-ended signal and amplify it by a factor of A1, outputting an AC signal V with DC bias. Where A1 is the amplification factor of the first-stage amplifier, U2 is the signal amplitude of the differential signal V2, and w2 is the angular frequency of the differential signal V2. V represents the phase shift of the op-amp output. CM The DC output voltage of the operational amplifier ensures that the signal level is compatible with subsequent circuits. The differential-to-single-ended amplifier solves the compatibility problem of the differential signal of the multiplier, ensuring that high-frequency signals can be effectively detected and amplified.

[0031] An RC low-pass filter is used to attenuate high-frequency signal components, causing the signal amplitude to decrease as the frequency increases. Its transfer function is H(s) = 1 / (1 + sRC), where s is the complex frequency, R is the resistance, and C is the capacitance. The output signal V′ contains DC and AC components, where the DC component is equal to the DC output voltage V of the operational amplifier. CM After the AC component passes through an RC low-pass filter, its amplitude and phase change. The expression for signal V′ is:

[0032]

[0033] Where w2 is the angular frequency of the differential signal V2. Let V' be the phase shift of the RC filter output. Let the amplitude of the AC component of the filtered signal V' be V. AC Then V AC It can be represented as:

[0034]

[0035] When w2 increases, V AC As the frequency decreases, the amplitude of the AC signal V' attenuates, thus generating a signal that attenuates with frequency, which serves as the input to the comparator to achieve frequency-amplitude mapping.

[0036] The comparator is used to compare the filtered signal V' with the reference voltage V. ref The comparison is performed, and the substrate bias voltage of the tail current source is dynamically adjusted based on the comparison result. Specifically, the comparator output controls V. SB The change, through the substrate bias effect of NMOS, reduces the threshold voltage V. th This increases the tail current I. EE This improves the overall bandwidth; the formula used for the NMOS substrate bias effect is... Where V TH0 γ is the threshold voltage at zero substrate bias, and γ is the bulk effect coefficient. It is the surface potential, V SB It is the source-substrate voltage; when the substrate voltage rises, the threshold voltage V of the NMOS... th As the frequency of V2 decreases, the current increases. Therefore, as the frequency w2 increases, a larger bias current can be provided.

[0037] The effect of the above technical solution is as follows: The frequency detection network proposed in this invention dynamically adjusts the substrate bias voltage of the tail current source by monitoring the frequency characteristics of the differential signal V2 in real time. When the frequency ω2 of V2 increases, the network automatically increases the tail current I. EE This compensates for the gain drop of the multiplier at high frequencies caused by the circuit poles, effectively expanding the bandwidth.

[0038] Example 2

[0039] like Figure 2 As shown, this embodiment provides an improved scheme to enhance high-frequency characteristics by controlling the number of parallel tail current sources. The tail current sources employ dual npn transistors QA and QB in parallel high-speed analog multiplier circuits. The QB high-speed analog multiplier circuit path is connected in series with an NMOS current-limiting transistor M2, whose gate and substrate are both connected to the Vctl high-speed analog multiplier circuit. When the ω2 high-speed analog multiplier circuit increases, the Vctl high-speed analog multiplier circuit increases, the Vth high-speed analog multiplier circuit of the M2 high-speed analog multiplier circuit decreases, the branch current of the QB high-speed analog multiplier circuit increases, and the total tail current enhances the high-frequency gain.

[0040] Example 3

[0041] like Figure 3 As shown, this embodiment provides a self-biased tail current regulation circuit. Q1 and Q2 adopt a 1:1 current mirror structure, and the structure of Q1 and M1 forms a negative feedback loop, resulting in a stable operating point for the circuit. When Vctl increases, the VBE of Q1 and Q2 increases, leading to an increase in the output current. The output current Itail satisfies:

[0042]

[0043] Through ΔI tail / ΔV th <0 enables adaptive current regulation.

[0044] The above formula shows that the output current is related to V th They are negatively correlated. When V ctl When increased, the bias effect leads to V th The output current is reduced, thus increasing the output current, which can improve the high-frequency gain of the multiplier.

[0045] Specifically, the collector current of Q1 is determined by the current equations for Q1, M1, and R1:

[0046]

[0047] Since it's a 1:1 current mirror, the current flowing through Q1 and Q2 is the same, and the output current is ultimately determined by the following formula:

[0048]

[0049] Taking the difference between both sides, we get:

[0050]

[0051] After sorting, we get:

[0052]

[0053] Specifically, when V1 and V2 are small signals, the transconductance of the analog multiplier from the Q1 and Q2 terminals to the output terminal is:

[0054]

[0055] like Figure 5 The schematic diagram of increasing the bandwidth of the analog multiplier is shown. The multiplier circuit is regarded as a common-emitter-common-base amplifier with high-frequency poles. In the high-frequency range, the increase in tail current can compensate for the decrease in gain, thereby increasing the bandwidth of the multiplier.

[0056] Comparative Example 1

[0057] like Figure 4 As shown, the traditional Gilbert four-quadrant analog multiplier circuit structure includes transistors Q1-Q6. The collector currents Ic of Q3 and Q5, Q4 and Q6 are summed and then subtracted to obtain the output differential current, which is approximately proportional to V1 and V2.

[0058] The collector current of each transistor is as follows:

[0059]

[0060] The differential output current is given by the following formula:

[0061]

[0062] When V1 and V2 are much smaller than V T At that time, the output current is proportional to V1 and V2.

[0063]

[0064] Among them I c1 I is the collector current of transistor Q1. EE The tail current (bias current), V T For thermal voltage, I c3 ΔI is the collector current of Q3, μn is the output differential current, Cox is the gate oxide capacitance density, W / L is the width-to-length ratio of the MOSFET, and V is the voltage. G1 V is the gate voltage of M1. BE1This is the base-emitter voltage of Q1.

[0065] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. The above descriptions are only preferred embodiments of this application. It should be noted that due to the limitations of written expression, while there are objectively infinite specific structures, those skilled in the art can make several improvements, modifications, or changes without departing from the principles of this application, and can also combine the above technical features in an appropriate manner. These improvements, modifications, changes, or combinations, or the direct application of the concept and technical solution of this application to other occasions without modification, should all be considered within the scope of protection of this application.

Claims

1. A high speed analog multiplier circuit, characterized by, The four-quadrant multiplier, the tail current source and the frequency detection network module are included. The first differential input end of the Gilbert unit is connected with the differential signal V1, the second differential input end is connected with the differential signal V2, and the tail current input end of the Gilbert unit is connected with the output end of the tail current source. The drain of the NMOS tube is connected with the tail current input end of the Gilbert unit, the source is grounded, and the substrate is connected with the output end of the frequency detection network module. The input end of the frequency detection network module is connected with the differential signal V2, and the output end outputs the control voltage Vctl to the substrate of the NMOS tube to adjust the tail current output by the tail current source. The frequency detection network module includes a differential-to-single-ended amplifier, an RC low-pass filter and a comparator. The tail current source further includes at least two parallel current branches, the input end of each current branch is connected with the power supply voltage VDD, the output ends are connected with the tail current input end of the four-quadrant multiplier after being merged, and the total tail current output by the tail current source is adjusted by controlling the number of turned-on parallel current branches.

2. The high-speed analog multiplier circuit of claim 1, wherein, The input end of the differential-to-single-ended amplifier is connected with the differential signal of the differential signal V2, and the output end is connected with the input end of the RC low-pass filter.

3. The high-speed analog multiplier circuit of claim 1, wherein, The transfer function of the RC low-pass filter is H(s) = 1 / (1+sRC), wherein s is a complex frequency, R is the resistance in the RC low-pass filter, and C is the capacitance in the RC low-pass filter.

4. The high-speed analog multiplier circuit of claim 1, wherein, The first input end of the comparator is connected with the output end of the RC low-pass filter, the second input end is connected with the reference voltage Vref, and the output end is connected with the substrate of the NMOS tube of the tail current source to output the control voltage Vctl to adjust the substrate bias voltage of the tail current source.

5. The high-speed analog multiplier circuit of claim 1, wherein, The tail current source includes an NMOS current mirror, the drain of the input stage NMOS tube of the NMOS current mirror is connected with the power supply voltage VDD, the gate of the input stage NMOS tube is connected with the gate of the output stage NMOS tube, the drain of the output stage NMOS tube is connected with the tail current input end of the four-quadrant multiplier as the output end of the tail current source, and the substrate is connected with the output end of the frequency detection network module.

6. The high-speed analog multiplier circuit of claim 1, wherein, The tail current output by the tail current source flows into the tail current input end of the Gilbert unit of the four-quadrant multiplier, the tail current size of the tail current source is adjusted by the frequency detection network module to compensate for the gain attenuation of the Gilbert unit at high frequency, and the high-frequency gain of the four-quadrant multiplier is improved.

7. The high-speed analog multiplier circuit of claim 1, wherein, The two parallel current branches of the tail current source are respectively a first npn transistor branch and a second npn transistor branch; the input end of the first npn transistor branch is connected with a power supply voltage VDD, and the output end is connected with the tail current input end of the four-quadrant multiplier; the input end of the second npn transistor branch is connected with the power supply voltage VDD, and the output end is connected with the tail current input end of the four-quadrant multiplier in series with an NMOS current limiting tube, the gate and the substrate of the NMOS current limiting tube are connected with the output end of the frequency detection network module to receive a control voltage Vctl to limit the current of the second npn transistor branch.

8. The high-speed analog multiplier circuit of any of claims 1-7, wherein, The self-biased tail current adjusting circuit comprises Q1, Q2, M1 and R1, Q1 and Q2 are npn bipolar transistors in a 1:1 current mirror structure, the collector of Q1 is connected with a power supply voltage VDD through R1, the base of Q1 is connected with the base of Q2, the emitter of Q1 is connected with the drain of M1, the source of M1 is grounded, and the gate of M1 is connected with the collector of Q1; the collector of Q2 is connected with the input end of the tail current source.

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