Management method and device of dynamic multi-thread access memory

Abstract

The invention discloses a dynamic multi-thread memory access management method, and relates to the technical field of computers, in particular to a dynamic multi-thread memory access management method and device.The method comprises the following steps that a plurality of memory access requests outside a processor and / or inside the processor are obtained, and a first request queue is formed; wherein the memory access request comprises a thread identifier, an access type and a target memory address; dynamically sequencing the memory access requests in the request queue according to a preset priority rule, and calculating the memory access request with the highest priority; wherein the priority rule comprises at least one of a thread priority rule, a request source priority rule and a memory address priority rule; obtaining and executing the memory access request with the highest priority; the memory resource allocation efficiency can be effectively improved, the system adaptability and flexibility are enhanced, the hardware implementation complexity is simplified, and the response delay is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of processor architecture, and in particular to a management method and device for dynamic multi-threaded memory access. BACKGROUND

[0002] In a chip, the memory management unit of the chip core is responsible for managing the mapping of all instructions from the core inside and outside the core to the physical memory, memory access permission control, and memory management functions. The main functions of the memory management unit include: (1) mapping of virtual addresses and physical memory; (2) memory protection and permission control; (3) translation lookaside buffer (TLB).

[0003] In the prior art, the Chinese invention with publication number CN105824605B discloses:

[0004] "A controllable dynamic multi-threading method and processor, the processor adopts a multi-threaded pipeline structure, and a mark is added in the instruction structure of the processor, the mark includes a thread to which the mark corresponds to an instruction and priority information of the mark corresponding to the instruction. The processor controls the corresponding instruction according to the mark, and transmits and executes the instruction according to the thread and priority information in the mark. The processor includes an instruction system containing the mark, a program execution control unit (Branch) for identifying and tracking the mark, an instruction decoding circuit for identifying and decoding the mark, an arithmetic operation unit for identifying and decoding the mark, and a corresponding memory unit, which can dynamically schedule all operation hardware resources of a processor to improve the operation capacity of the processor without the need to increase many complex hardware. Unlike other multi-threading schemes, registers and processors are divided and bound according to the number of threads. The controllable dynamic multi-threading technology can flexibly define the number of threads and the priority of the instruction by modifying the instruction."

[0005] However, although the above-mentioned patent achieves good dynamic control in instruction-level scheduling, it does not provide a matching memory access management mechanism, resulting in resource contention problems when multiple threads concurrently access shared memory, which limits the overall performance. Therefore, in order to better apply the dynamic multi-threading scheduling mechanism proposed in CN105824605B, it is necessary to build a memory management unit structure that matches it to achieve efficient coordination and dynamic resource allocation of memory access between threads.

[0006] Although, in the prior art, the US patent with publication number US9223709 also proposes a solution for dynamically allocating memory units based on the number of active threads, the memory management unit divides the physical memory into multiple independent parallel access units, and when the number of active threads reaches the maximum, each thread is allocated an independent memory unit, and when the number of active threads is less, multiple memory units are allocated to a single thread. However, this solution constructs a shared network of memory resources through a hardware circuit, although it can achieve dynamic allocation of memory capacity, but has the following defects:

[0007] (1) Resource allocation depends on the hard division mechanism of physical memory units, which is difficult to respond to dynamic priority changes at the thread level in a timely manner;

[0008] (2) The resource sharing mechanism based on complex hardware circuit implementation leads to an increase in the number of routing path pointers, especially in the multi-core scenario, which leads to signal integrity problems and significantly increases the difficulty of timing convergence;

[0009] (3) There may be sudden situations during operation that require high memory throughput from the request source. If this memory resource needs to be met, the thread binding relationship needs to be restructured, which will cause configuration resource overhead and reduce efficiency.

[0010] In summary, the memory management scheme in the prior art generally has the problems of insufficient resource scheduling flexibility, high hardware complexity, and poor burst load adaptability when facing multi-thread parallel computing scenarios. Therefore, it is urgent to provide a new memory management unit and a design method to solve the above problems, to realize efficient, flexible, and low-latency multi-thread memory access control, and to better support the dynamic multi-thread scheduling mechanism as described in CN105824605B. SUMMARY

[0011] The purpose of the present application is to avoid the shortcomings of the prior art and provide a dynamic multi-thread access memory management technology, aiming to solve the problems of unreasonable memory resource allocation, high response delay, high hardware complexity, and difficulty in adapting to dynamic changes in thread priority in the prior art. By introducing a memory management architecture with an intelligent arbitration mechanism, efficient scheduling and conflict coordination of multi-thread access requests are realized, thereby improving the overall performance and energy efficiency of the processor in parallel computing scenarios.

[0012] The purpose of the present application is achieved by the following technical solutions:

[0013] According to one aspect of the present application, a dynamic multi-thread access memory management method is provided, comprising the following steps:

[0014] Step one: obtaining a plurality of memory access requests outside the processor and / or inside the processor and forming a first request queue; wherein the memory access request comprises a thread identifier, an access type, and a target memory address;

[0015] Step two: dynamically sorting each memory access request in the request queue according to a preset priority rule to calculate a memory access request with the highest priority; wherein the priority rule comprises at least one of a thread priority rule, a request source priority rule, and a memory address priority rule.

[0016] Step three: obtaining and executing the memory access request with the highest priority.

[0017] Specifically, between step one and step two, the following steps are further included: judging whether the number of memory access requests in the first request queue is greater than 1; if yes, entering step two; if no, directly entering step three.

[0018] The above step three further includes: judging whether the memory access request with the highest priority exists instruction conflict; if no, accessing the corresponding storage location in the memory unit according to the address information in the memory access request with the highest priority.

[0019] Another specific, in step three, obtaining and executing the memory access request with the highest priority, while returning the remaining unexecuted access requests in the first request queue to a failure result.

[0020] Another specific, in step two, after dynamically sorting each memory access request in the request queue according to the preset priority rule, a second request queue is formed.

[0021] In step three, obtaining and executing the memory access request with the highest priority in the second request queue, while returning the remaining unexecuted access requests in the second request queue to step one to form a new first request queue.

[0022] Another specific, in step three, when judging whether the memory access request with the highest priority exists instruction conflict, if there is conflict, returning to step one.

[0023] According to another aspect of the present application, a dynamic multi-thread memory access management device is provided, which adopts the above-mentioned dynamic multi-thread memory access management method, and comprises an arbitration module, a first bus interface and a second bus interface; the arbitration module is connected to the first bus interface and the second bus interface respectively; the first bus interface is used for connecting each thread calculation unit, and the second bus interface is used for connecting a memory unit; the thread calculation unit comprises a calculation unit inside and / or outside a processor; the arbitration module comprises a priority determination unit and an execution unit; the priority determination unit is used for dynamically sorting each memory access request in a request queue according to a preset priority rule; the execution unit is used for obtaining and executing a memory access request with the highest priority, and performing conflict detection on the obtained memory request; wherein the conflict detection comprises at least one of unified address access conflict, resource contention conflict and concurrent request number overflow conflict.

[0024] Specifically, the arbitration module further comprises a queue determination unit, which is used for receiving each memory access request and counting the corresponding thread number.

[0025] More specifically, the arbitration module further comprises a queue storage unit, which is used for storing the memory access request queue.

[0026] According to still another aspect of the present application, a processor is provided, which comprises a plurality of thread calculation units and the above-mentioned dynamic multi-thread memory access management device.

[0027] The present application has the following advantages:

[0028] The memory resource allocation efficiency is improved: by introducing an intelligent arbitration mechanism, the access order can be dynamically adjusted according to the thread number, priority and request characteristics, avoiding the resource contention and idle waste problems that may occur in the traditional static scheduling strategy, thereby significantly improving the memory bandwidth utilization.

[0029] The system adaptability and flexibility are enhanced: the present application supports dynamic changes of thread priority, and can flexibly adjust the scheduling strategy according to the runtime environment, adapts to the load characteristics in different application scenarios, and improves the robustness and scalability of the processor in complex parallel computing tasks.

[0030] The hardware implementation complexity is simplified: by integrating the conflict detection and control signal generation module into the arbitration logic, the hardware overhead caused by the need to additionally set multiple mutual exclusion locks or synchronization mechanisms in the traditional scheme is avoided, the chip area and power consumption are reduced, and the system integration is improved.

[0031] Reducing response delay: directly skipping the ordering process when a single thread requests, reducing unnecessary processing overhead; while in the case of multi-thread concurrency, a dynamic priority determination mechanism based on multi-dimensional rules (such as thread information, request source, address information) is adopted to ensure that high-priority tasks obtain fast response and effectively shorten the overall response time. BRIEF DESCRIPTION OF DRAWINGS

[0032] The present application can be better understood by describing the exemplary embodiments disclosed herein with reference to the accompanying drawings, in which:

[0033] Figure 1 Fig. 1 shows a schematic flow chart of a dynamic multi-thread access memory management method according to the first disclosed embodiment of the present application;

[0034] Figure 2 Fig. 2 shows an electrical module block schematic diagram of a dynamic multi-thread access memory management device and processor according to the first disclosed embodiment of the present application;

[0035] Figure 3 Fig. 3 shows a schematic flow chart of a dynamic multi-thread access memory management method according to the second disclosed embodiment of the present application;

[0036] Figure 4 Fig. 4 shows a schematic flow chart of a dynamic multi-thread access memory management method according to the third disclosed embodiment of the present application;

[0037] Figure 5 Fig. 5 shows an electrical module block schematic diagram of a dynamic multi-thread access memory management device and processor according to the third disclosed embodiment of the present application;

[0038] Figure 6 Fig. 6 shows a schematic flow chart of a dynamic multi-thread access memory management method according to the fourth disclosed embodiment of the present application. DETAILED DESCRIPTION

[0039] In this respect, before explaining at least one embodiment of the application in detail, it is to be understood that the application is not limited in its application to the details of construction and the arrangement of the components set forth in the following description or illustrated in the drawings. The application is capable of other embodiments or of being practiced or carried out in various ways. Also, it is to be understood that the phraseology and terminology employed herein are for the purpose of description and should not be regarded as limiting. As such, the use of "including" and "comprising" and variations thereof herein is intended to be broad and encompass the occurrence of zero, one or more of the stated features. Furthermore, the use of letters to identify elements in the figures is intended to represent any and all possible components, whether currently known or from the future, and is not meant to limit the application.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The use of the terms "first", "second" and "like" in the specification and claims are not meant to denote any order, quantity, or importance, but are used to distinguish one element from another. The use of the terms "a" and "an" and "the" and "at least one" are intended to include both singular and plural, unless the context clearly indicates otherwise. The use of the term "including" or "comprising" is meant to encompass the elements listed thereafter and equivalents thereof as well as additional elements not recited. The use of the term "connected" or "coupled" is meant to include both direct and indirect connections or couplings between elements.

[0041] Embodiment One

[0042] One of the embodiments of the method for managing dynamic multi-threaded memory access according to the present application, as shown in FIG. 1, comprises the following steps S101-S132: Figure 1

[0043] S101: Obtain a plurality of memory access requests from outside and / or inside the processor and form a first request queue.

[0044] In this embodiment, memory access requests from a plurality of threads are accepted, and each memory access request comprises a thread identifier, an access type, and a target memory address.

[0045] ​S102: Queue state judgment, judge whether the number of memory access requests in the first request queue is greater than 1. If there is only one thread request, skip the priority judgment process and directly enter the instruction reading stage S120; if there are multiple thread requests, enter step S110 for dynamic priority sorting.

[0046] Among them, in the case of single thread request, the sorting process is directly skipped, reducing unnecessary processing overhead; while in the case of multi-thread concurrency, a dynamic priority judgment mechanism based on multi-dimensional rules (such as thread information, request source, address information) is adopted to ensure that high-priority tasks are quickly responded and the overall response time is effectively shortened.

[0047] S110: Dynamic priority sorting, dynamically sorting each memory access request in the request queue according to the preset priority rules to calculate the highest priority memory access request.

[0048] Among them, the priority rules include at least one of thread priority rules, request source priority rules and memory address priority rules.

[0049] By introducing an intelligent arbitration mechanism, the access order can be dynamically adjusted according to the number of threads, priority and request characteristics, avoiding the resource contention and idle waste problems that may occur in traditional static scheduling strategies, thereby significantly improving the memory bandwidth utilization.

[0050] S120: Get and execute the highest priority memory access request. No matter how many requests are in the queue, the arbitration module always gets and reads the most optimal memory access request in the queue first, and prepares to execute the next operation; at the same time, the remaining unexecuted memory access requests in the first request queue are also transmitted to step S121.

[0051] S121: Judge whether the highest priority memory access request has instruction conflict; if not, generate read-write control signal and execute request operation S132; if there is conflict, return failure result S131.

[0052] Among them, the conflict detection includes at least one of unified address access conflict, resource competition conflict and concurrent request number overflow conflict.

[0053] S131: Return execution failure result.

[0054] S132: According to the address information in the highest priority memory access request, access the corresponding storage location in the memory unit.

[0055] Please continue to refer to Figure 2, show a specific implementation of a dynamic multi-threaded memory access management device, for dynamic arbitration and scheduling of memory access requests from multiple thread computing units in a multi-threaded concurrent execution environment, thereby improving memory access efficiency and reducing conflict probability. The memory management device is managed by a bus from the computing processor. And in the memory management unit by an arbitration module unified management request queue.

[0056] Specifically, the memory management device includes: arbitration module, first bus interface and second bus interface; arbitration module is connected with first bus interface and second bus interface respectively; the first bus interface is used for connecting the multiple thread computing units (such as multiple threads in CPU core, thread computing unit 1 to thread computing unit 6) inside the processor and external computing units, receiving the memory access requests sent by them.

[0057] The arbitration module is connected with the first bus interface and the second bus interface respectively, responsible for queue determination, priority sorting and execution control of the multiple memory access requests received.

[0058] The second bus interface is used for connecting the memory unit, and sending the finally determined memory access request to the target memory address to execute read-write operation.

[0059] Further, the arbitration module consists of three sub-modules: queue determination unit, priority determination unit and execution unit.

[0060] The queue determination unit is used for receiving memory access requests from different threads and counting the number of threads. If there is only one thread request in the queue, the memory access request is directly sent to the execution unit; if there are multiple thread requests in the queue, the memory access request is sent to the priority determination unit for priority determination.

[0061] The priority determination unit is used for priority sorting of multiple requests based on preset rules. Among them, the priority rules include at least one of thread priority rules, request source priority rules and memory address priority rules.

[0062] The execution unit is used for reading and executing one or more access requests, and detecting conflicts of the obtained memory requests.

[0063] Specifically, in the case of multiple access requests, the execution unit will execute the access request with the highest priority first.

[0064] More specifically, if there is no conflict, the arbitration module generates read-write control signal to execute access operation; if there is conflict, the execution module returns failure result.

[0065] The conflict detection includes at least one of a uniform address access conflict, a resource contention conflict, and a concurrent request number over-limit conflict.

[0066] By integrating the conflict detection and the control signal generation module into the arbitration logic, hardware overhead caused by additional setting of multiple mutual exclusion locks or synchronization mechanisms in the traditional scheme is avoided, chip area and power consumption are reduced, and system integration is improved.

[0067] According to still another aspect of the present application, a processor is provided, comprising a plurality of thread calculation units, and the dynamic multi-thread memory access management device.

[0068] Embodiment two

[0069] One of the implementation methods of the dynamic multi-thread memory access management method of the present application, as shown in the figure, comprises the following steps S201 to S232: Figure 3

[0070] S201: Obtain a plurality of memory access requests outside and / or inside the processor, and form a first request queue.

[0071] In the present embodiment, memory access requests from multiple threads can be accepted, and each memory access request comprises a thread identifier, an access type, and a target memory address.

[0072] S202: Queue state judgment, judge whether the number of memory access requests in the first request queue is greater than 1. If there is only one thread request, skip the priority judgment process and directly enter the instruction reading stage S220; if there are multiple thread requests, enter step S210 for dynamic priority sorting.

[0073] S210: Dynamic priority sorting, dynamically sort each memory access request in the request queue according to a preset priority rule, and calculate the memory access request with the highest priority.

[0074] The priority rule comprises at least one of a thread priority rule, a request source priority rule, and a memory address priority rule.

[0075] S220: Obtain and execute the memory access request with the highest priority. Regardless of the number of requests in the queue, the arbitration module always obtains and reads the most priority memory access request in the queue first, and prepares to perform the next operation; at the same time, returns the remaining unexecuted memory access requests in the first request queue to the execution failure result (i.e. corresponding step S231).

[0076] ​S221: Determine if there is an instruction conflict in the highest priority memory access request; if there is no conflict, generate a read / write control signal and execute the request operation S232; if there is a conflict, return a failure result S231.

[0077] The conflict detection includes at least one of the following: unified address access conflict, resource contention conflict, and concurrent request limit exceeding conflict.

[0078] S231: Returns a result indicating execution failure.

[0079] S232: Access the corresponding storage location in the memory unit based on the address information in the highest priority memory access request.

[0080] Example 3

[0081] One implementation method of the present invention is a dynamic multi-threaded memory access management method, such as... Figure 4 As shown, the process includes the following steps S301 to S332:

[0082] S301: Obtain several memory access requests from outside and / or inside the processor, and form a first request queue.

[0083] In this embodiment, memory access requests from multiple threads can be accepted, and each memory access request includes: thread identifier, access type, and target memory address.

[0084] S302: Queue status judgment, determine whether the number of existing memory access requests in the first request queue is greater than 1. If there is only one thread request, skip the priority determination process and directly enter the instruction reading stage S320; if there are multiple thread requests, proceed to step S310 for dynamic priority sorting.

[0085] S310: Dynamic priority sorting, dynamically sorts each memory access request in the request queue according to the preset priority rules, forms a second request queue, and calculates the memory access request with the highest priority.

[0086] The priority rules include at least one of the following: thread priority rules, request source priority rules, and memory address priority rules.

[0087] S320: Obtain and execute the highest priority memory access request. Regardless of the number of requests in the queue, the arbitration module always prioritizes obtaining and reading the highest priority memory access request in the queue, preparing to execute the next operation; at the same time, the remaining unexecuted access requests in the second request queue are returned to step S301, and the process is re-executed to form a new first request queue.

[0088] S321: judging whether the memory access request with the highest priority exists instruction conflict; if not, generating read-write control signal to execute the request operation S332; if yes, returning failure result S331.

[0089] The conflict detection includes at least one of unified address access conflict, resource competition conflict and concurrent request number over-limit conflict.

[0090] S331: returning execution failure result.

[0091] S332: accessing the corresponding storage location in the memory unit according to the address information in the memory access request with the highest priority.

[0092] Please continue to refer to Figure 5 , which shows a specific implementation of a dynamic multi-thread memory access management device, which is used to dynamically arbitrate and schedule memory access requests from multiple thread computing units in a multi-thread concurrent execution environment, thereby improving memory access efficiency and reducing conflict probability. The memory management device is managed by a bus to receive memory access from a computing processor. And in the memory management unit, an arbitration module is used to manage the request queue.

[0093] Specifically, the memory management device includes an arbitration module, a first bus interface and a second bus interface; the arbitration module is connected to the first bus interface and the second bus interface; the first bus interface is used to connect multiple thread computing units (such as multiple threads in CPU core, thread computing unit 1 to thread computing unit 6) inside the processor and external computing units, and receive memory access requests sent by them.

[0094] The arbitration module is connected to the first bus interface and the second bus interface, and is responsible for queue determination, priority sorting and execution control of the received multiple memory access requests.

[0095] The second bus interface is used to connect the memory unit and send the finally determined memory access request to the target memory address to perform read-write operation.

[0096] Further, the arbitration module is composed of four sub-modules: queue registration unit, queue determination unit, priority determination unit and execution unit.

[0097] The queue registration unit is used to store the memory access request queue, and this unit is connected to the first bus interface and the execution unit, and receives and stores memory access requests from the above units.

[0098] The queue determination unit is used to receive memory access requests from different threads and count the number of threads. If there is only one thread request in the queue, the memory access request is sent directly to the execution unit; if there are multiple thread requests in the queue, the memory access request is sent to the priority determination unit for priority determination.

[0099] The priority determination unit is used to prioritize multiple requests based on preset rules. These priority rules include at least one of the following: thread priority rules, request source priority rules, and memory address priority rules.

[0100] The execution unit is used to read and execute one or more access requests, as well as to perform conflict detection on the acquired memory requests.

[0101] Specifically, in the case of multiple access requests, the execution unit will prioritize the highest priority access request and return the remaining access requests to the queue storage unit.

[0102] More specifically, if no conflict is detected, the arbitration module generates a read / write control signal and executes the access operation; if a conflict exists, the execution module returns a failure result.

[0103] In this embodiment, dynamic changes in thread priority can be further supported, and the scheduling strategy can be flexibly adjusted according to the runtime environment to adapt to the load characteristics under different application scenarios, thereby improving the robustness and scalability of the processor in complex parallel computing tasks.

[0104] Example 4

[0105] One implementation method of the present invention is a dynamic multi-threaded memory access management method, such as... Figure 6 As shown, the process includes the following steps S401 to S432:

[0106] S401: Obtain several memory access requests from outside and / or inside the processor, and form a first request queue.

[0107] In this embodiment, memory access requests from multiple threads can be accepted, and each memory access request includes: thread identifier, access type, and target memory address.

[0108] S402: Queue status judgment, determine whether the number of existing memory access requests in the first request queue is greater than 1. If there is only one thread request, skip the priority determination process and directly enter the instruction reading stage S220; if there are multiple thread requests, proceed to step S210 for dynamic priority sorting.

[0109] S410: Dynamic priority ranking, dynamically ranking each memory access request in the request queue according to a preset priority rule to form a second request queue, and calculating a memory access request with the highest priority.

[0110] The priority rule includes at least one of a thread priority rule, a request source priority rule, and a memory address priority rule.

[0111] S420: Obtain and execute the memory access request with the highest priority. Regardless of the number of requests in the queue, the arbitration module always obtains and reads the most priority memory access request in the queue first, and prepares to perform the next operation; at the same time, returns the remaining unexecuted access requests in the second request queue to step S401 and re-executes the process to form a new first request queue.

[0112] S421: Determine whether the memory access request with the highest priority has instruction conflict; if not, generate a read-write control signal to execute the request operation S432; if yes, return to step S431.

[0113] The conflict detection includes at least one of a unified address access conflict, a resource competition conflict, and a concurrent request number overflow conflict.

[0114] S431: Return the memory request to step S401 and re-execute the process.

[0115] S432: Access the corresponding storage location in the memory unit according to the address information in the memory access request with the highest priority.

[0116] Note that the above is only the preferred embodiment of the present application and the technical principle applied. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and those skilled in the art can make various obvious changes, re-adjustments and substitutions without departing from the scope of the present application. Therefore, although the present application has been described in detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. A method for managing dynamic multithreading access to memory, the method comprising: The method comprises the following steps: Step 1: obtaining a plurality of memory access requests outside the processor and / or inside the processor, and forming a first request queue; wherein the memory access request comprises a thread identifier, an access type, and a target memory address; Step 2: dynamically sorting each memory access request in the request queue according to a preset priority rule, and calculating a memory access request with the highest priority; wherein the priority rule comprises at least one of a thread priority rule, a request source priority rule, and a memory address priority rule; Step 3: obtaining and executing the memory access request with the highest priority.

2. The management method of claim 1, wherein, Between the step 1 and the step 2, the following steps are further included: determining whether the number of memory access requests in the first request queue is greater than 1; if yes, entering the step 2; if no, directly entering the step 3.

3. The management method of claim 1 or 2, wherein, The step 3 further includes: determining whether the memory access request with the highest priority exists instruction conflict; if no, accessing the corresponding storage location in the memory unit according to the address information in the memory access request with the highest priority.

4. The method of claim 3, wherein: In the step 3, while obtaining and executing the memory access request with the highest priority, the remaining unexecuted access requests in the first request queue are returned with a failure result.

5. The method according to claim 3, wherein: in the step 2, after dynamically sorting each memory access request in the request queue according to the preset priority rule, a second request queue is formed; in the step 3, while obtaining and executing the memory access request with the highest priority in the second request queue, the remaining unexecuted access requests in the second request queue are returned to the step 1 to form a new first request queue.

6. The method of claim 3, wherein the number of threads is dynamically changed according to the number of the memory blocks. In the step 3, when determining whether the memory access request with the highest priority exists instruction conflict, if there is conflict, the step 1 is returned.

7. A dynamic multithreaded memory access management apparatus using the dynamic multithreaded memory access management method according to any one of claims 1 to 6, characterized by The memory management device comprises an arbitration module, a first bus interface, and a second bus interface; the arbitration module is connected to the first bus interface and the second bus interface respectively; the first bus interface is used to connect each thread calculation unit, and the second bus interface is used to connect a memory unit; the thread calculation unit comprises a calculation unit inside and / or outside the processor; the arbitration module comprises a priority determination unit and an execution unit; the priority determination unit is used to dynamically sort each memory access request in the request queue according to a preset priority rule; the execution unit is used to obtain and execute the memory access request with the highest priority, and to detect the obtained memory request for conflict; wherein the conflict detection comprises at least one of unified address access conflict, resource competition conflict, and concurrent request number overflow conflict.

8. The device according to claim 7, wherein: the arbitration module further comprises a queue determination unit, which is used to receive each memory access request and count the corresponding thread number.

9. The device according to claim 8, wherein: The arbitration module further comprises a queue register unit for storing the memory access request queue.

10. A processor, comprising: The application further provides a dynamic multi-thread memory access management device. The application further provides a dynamic multi-thread memory access management device.

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