Transmission circuit, transmission method and transmission receiving system
By introducing a variable output impedance and a transition detection circuit into the transmission circuit, the output impedance and drive current are adjusted according to the transition of the data signal, thus solving the problem of excessive power consumption of the sequencer/desequencer circuit at high frequencies and achieving the effect of low power consumption and constant signal amplitude.
Patent Information
- Application Number
- CN202410631988.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-05-07
- Filing Date
- 2024-05-21
- Publication Date
- 2025-11-07
AI Technical Summary
The sequencer/deserializer circuit consumes too much power at high frequencies, making it difficult to apply effectively in low-power mobile devices.
By introducing a variable output impedance circuit and a transition detection circuit into the transmission circuit, the output impedance and drive current are adjusted according to the transition status of the data signal to achieve impedance matching and power optimization.
By reducing the power consumption of the transmission circuit when the data signal is in a constant state, while keeping the amplitude of the received signal constant, the energy efficiency of the system is improved.
Smart Images
Figure CN120915321A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present invention relates to a transmission circuit, a transmission method and a transmission / reception system, and more particularly to a transmission circuit, a transmission method and a transmission / reception system for reducing power consumption by judging whether a data signal is in transition. BACKGROUND
[0002] A serializer / deserializer (SerDes) circuit is a circuit for converting a single-ended bus of a large bit width into one or more differential signals, and the switching frequency of the differential signals is greater than that of the single-ended bus of the large bit width. The SerDes circuit can enable point-to-point transmission of a large amount of data while reducing the complexity, cost and circuit board space of a parallel bus. However, as the processing capability of a computer system increases, the operating frequency of the parallel bus is increasingly high, so that the SerDes circuit consumes a large amount of power. In this case, if the SerDes circuit is used in a mobile device requiring low power, how to improve the power consumption of the SerDes circuit becomes one of the goals of the industry. SUMMARY
[0003] One of the main objects of the present invention is to provide a transmission circuit, a transmission method and a transmission / reception system to solve the above problems.
[0004] The present invention provides a transmission circuit for transmitting with a receiving circuit through a positive channel and a negative channel, the transmission circuit comprising an output stage circuit, comprising: a variable output impedance circuit coupled to the positive channel and the negative channel; and a driving circuit comprising a positive output terminal and a negative output terminal for outputting a second data signal according to a first data signal through the variable output impedance circuit, wherein the positive output terminal and the negative output terminal drive the positive channel and the negative channel, respectively, through the variable output impedance circuit; and a transition detection circuit coupled to the output stage circuit for detecting whether the first data signal is in transition according to a clock signal having a unit period, and generating a detection result to adjust the variable output impedance circuit.
[0005] The present application provides a transmission-reception system, comprising a channel, comprising a positive channel and a negative channel; a transmission circuit, comprising: an output stage circuit, comprising: a variable output impedance circuit, coupled to the positive channel and the negative channel; and a driving circuit, comprising a positive output terminal and a negative output terminal, for outputting a second data signal according to a first data signal through the variable output impedance circuit, wherein the positive output terminal and the negative output terminal drive the positive channel and the negative channel respectively through the variable output impedance circuit; and a transition detection circuit, coupled to the output stage circuit, for detecting whether the first data signal is in transition according to a clock signal having a unit period, and generating a detection result to adjust the variable output impedance circuit; and a reception circuit, for receiving a third data signal according to the second data signal through the channel.
[0006] The present application provides a transmission method for a transmission circuit, wherein the transmission circuit transmits signals with a reception circuit through a positive channel and a negative channel, the transmission method comprising: receiving a first data signal and a clock signal having a unit period; detecting whether the first data signal is in transition according to the clock signal, and generating a detection result; adjusting characteristics of the transmission circuit according to the detection result; and outputting a second data signal according to the first data signal, and transmitting the second data signal to the reception circuit as a third data signal through the positive channel and the negative channel. BRIEF DESCRIPTION OF DRAWINGS
[0007] Figure 1 A schematic diagram of a conventional serializer / deserializer system.
[0008] Figure 2A A schematic diagram of a conventional serializer / deserializer system. Figure 1
[0009] Figure 2B A waveform diagram of the second data signal and the third data signal. Figure 2A
[0010] A schematic diagram of a transmission-reception system according to an embodiment of the present application. Figure 3
[0011] A schematic diagram of a transition detection circuit according to an embodiment of the present application. Figure 4
[0012] A schematic diagram of a transmission-reception system according to an embodiment of the present application. Figure 5A Figure 5B A schematic diagram of a transmission-reception system according to another embodiment of the present application.
[0013] Figure 6A Figure 6B A schematic diagram of a transmission-reception system according to another embodiment of the present application.
[0014] Figure 7 Flowchart of the transmission method of the embodiment of the present application.
[0015] Wherein, the reference numerals are explained as follows:
[0016] 1: sequencer / de-sequencer system
[0017] 2, 3, 4: transmission receiving system
[0018] 5: flowchart
[0019] 10: sequencer
[0020] 12, PLL: phase-locked loop
[0021] TX1, TX2, TX3, TX4: transmission circuit
[0022] RX1, RX2, RX3, RX4: receiving circuit
[0023] 14: de-sequencer
[0024] 16, CDR: clock data recovery circuit
[0025] 20: output stage circuit
[0026] 22: transition detection circuit
[0027] Z TX1 ,Z TX2 ,Z TX3 ,Z RX1 ,Z RX2 ,Z RX3 : impedance
[0028] R D_WT ,R D_WOT ,R S : resistance
[0029] I RD_WT ,I RD_WOT ,I LOAD ,I WT ,I WOT ,I RS : current
[0030] V OD : voltage
[0031] Z0: channel impedance
[0032] DET, DETB: detection result
[0033] DFF: D-type flip-flop
[0034] XOR: exclusive OR gate DETAILED DESCRIPTION
[0035] In this description and the following claims, certain terms have been used for brevity, clarity and understanding. An artisan will recognize that each term has a meaning that can be understood by those skilled in the art. The description and claims should not be taken as constraining the application to the terms used, but rather the application encompasses all modifications and alterations within the scope and equivalence of the appended claims. In the description and the following claims, "comprising," "including" or "containing" does not exclude other elements. Also, the use of "or" means "and / or" unless stated otherwise. Furthermore, "coupled" means either a direct connection or an indirect connection via one or more intermediaries.
[0036] Referring to Figure 1 , Figure 1 is a schematic diagram of a conventional serializer / deserializer (SerDes) system 1. The SerDes system 1 includes a serializer 10, a phase-locked loop (PLL) circuit 12, a transmission circuit TX1, a receiving circuit RX1, a deserializer 14, and a clock data recovery (CDR) circuit 16. The serializer 10 is coupled to the transmission circuit TX1 and the PLL circuit 12 for converting a parallel data signal into a serial data signal according to a clock signal having a unit time period provided by the PLL circuit 12. The transmission circuit TX1 transmits the serial data signal through a channel to the receiving circuit RX1. The receiving circuit RX1 is coupled to the CDR circuit 16 and the deserializer 14 for converting the serial data signal into the parallel data signal according to a clock signal recovered by the CDR circuit 16. The operation principle of the SerDes system 1 is well known in the art, and thus is not described in detail. It is noted that impedance matching is usually required between the transmission circuit TX1, the channel, and the receiving circuit RX1 so that the transmission of the serial data signal is not excessively attenuated. For example, refer to Figure 2A , Figure 2A is a schematic diagram of an equivalent circuit of the transmission circuit TX1, the channel, and the receiving circuit RX1. As shown in Figure 2A , a first data signal (serial data signal) passes through an output impedance Z TX1 of the transmission circuit TX1 and becomes a second data signal. The second data signal passes through a channel impedance Z0and is received by an input impedance Z RX1Received a third data signal. Please continue to refer to [the documentation / reference]. Figure 2B , Figure 2B This is a waveform diagram of the second and third data signals. For example... Figure 2B As shown, when the output impedance Z TX1 Channel impedance Z0, input impedance Z RX1 When impedance matching is achieved (i.e., the channel has the same impedance as the transmission circuit TX1 and the receiving circuit RX1, such as characteristic impedance, thus preventing data signal reflection), the third data signal has almost no attenuation compared to the second data signal. On the other hand, when the output impedance Z... TX1 Channel impedance Z0, input impedance Z RX1 When impedance matching is not achieved, the third data signal will exhibit significant attenuation during state transitions. In short, when the second data signal is transmitted to the input of the receiving circuit RX1 through the channel, impedance matching must be considered. As described above, under impedance matching, the input of the receiving circuit RX1 will experience minimal signal attenuation; in other words, the third data signal is essentially the same as the second data signal. However, under impedance mismatch, the data signal received at the input of RX1 will experience significant attenuation. It should be noted that, for simplicity, the following embodiments and accompanying drawings only illustrate the characteristics and waveform of the third data signal.
[0037] It should be noted that, such as Figure 2B As shown, even when the signal has no transition state, the output impedance Z TX1 Channel impedance Z0, input impedance Z RX1 Impedance matching was not achieved, and the third data signal did not attenuate. Therefore, this invention utilizes the output impedance Z... TX1 Channel impedance Z0, input impedance Z RX1 The matching relationship between them is used to reduce the power consumption of the transmission circuit TX.
[0038] Please refer to Figure 3 , Figure 3This is a schematic diagram of a transmission and reception system 2 according to an embodiment of the present invention. The transmission and reception system 2 includes a channel, a receiving circuit RX2, and a transmission circuit TX2. It should be noted that in some embodiments, the transmission and reception system 2 may be, but is not limited to, a sequencer / deserializer system. For simplicity, the sequencer and deserializer are not shown in the following embodiments and figures. The transmission circuit TX2 is used to transmit data signals to the receiving circuit RX2 through the channel. The transmission circuit TX2 includes an output stage circuit 20 and a transition detection circuit 22. The output stage circuit 20 includes a variable output impedance circuit and a driving circuit, wherein the variable output impedance circuit is coupled to the channel, and the driving circuit is coupled to the variable output impedance circuit. Specifically, when the transmission circuit TX2 receives a first data signal, the transition detection circuit 22 detects whether the first data signal has transitioned according to a clock signal and generates a detection result DET to adjust the variable output impedance circuit. It should be noted that the first data signal is related to the clock signal, for example, as... Figure 1 As shown, the clock signal can be generated by the phase-locked loop circuit 12, and the sequencer 10 can convert the parallel data signal into a serial first data signal according to the clock signal, but this is not a limitation. In this way, the drive circuit can output a second data signal according to the first data signal through the adjusted variable output impedance circuit. Specifically, when the detection result DET indicates that the first data signal has a transition state, the transition detection circuit can adjust the variable output impedance circuit to match the channel impedance Z0 and the input impedance Z of the receiving circuit RX2. RX1 Impedance matching is achieved; at this point, the output stage circuit 20 outputs the second data signal in a standard mode, ensuring that the third data signal is not attenuated. Conversely, if... Figure 2B As shown, due to the output impedance Z TX1 Channel impedance Z0, input impedance Z RX1 When impedance matching is not achieved, the third data signal does not attenuate when there is no transition. Therefore, when the detection result DET indicates that the first data signal has not transitioned, the transition detection circuit can adjust the variable output impedance circuit to reduce the power consumption of the output stage circuit; at this time, the output stage circuit 20 outputs the second data signal in a power-saving mode.
[0039] In short, in the transmission and reception system 2, when the transition detection circuit 22 detects that the first data signal has not transitioned, the embodiment of the present invention can optimize the variable output impedance circuit to reduce the power consumption of the output stage circuit 20 of the transmission circuit TX2.
[0040] It is noted that the detection result DET represents a signal generated by the transition detection circuit 22 to indicate whether there is a transition in the first data signal, and the form thereof is not limited, and those skilled in the art can adjust it according to the needs of the system. For example, the transition detection circuit 22 can be implemented by a D flip-flop DFF and an XOR gate, as shown in Figure 4 The D flip-flop DFF detects the first data signal at each unit period of the clock signal, and the XOR gate determines whether there is a transition in the first data signal at each unit period, for example, from a logic high state to a logic low state, or from a logic low state to a logic high state. It is noted that the operation principles of the D flip-flop DFF and the XOR gate are well known in the art, and thus are not described in detail.
[0041] Further, Figure 4 The detection result DET output by the transition detection circuit 22 is a digital signal, and thus the variable output impedance circuit can be implemented by a plurality of resistors and corresponding switches. The detection result DET can control whether the plurality of switches are turned on or off to determine whether the output stage circuit 20 outputs the second data signal in the standard mode or the power saving mode.
[0042] In an embodiment, please refer to Figure 5A and Figure 5B , Figure 5A and Figure 5B is a schematic diagram of an equivalent circuit of a transmission circuit TX3, a channel and a reception circuit RX3 of a transmission and reception system 3 according to an embodiment of the present application. As shown in Figure 5A and Figure 5B , the variable output impedance circuit is implemented by a standard mode resistor R D_WT , a power saving mode resistor R D_WOT , a matching resistor R S and corresponding switches. It is noted that the channel includes a positive channel and a negative channel, and the driving circuit includes a positive output terminal and a negative output terminal to drive the positive channel and the negative channel, respectively. In other words, the transmission and reception system 3 transmits differential signals. The operation of the differential signals is well known in the art, and thus is not described in detail. Specifically, the matching resistor R S and the corresponding switches are coupled in series between the positive channel and the negative channel, the standard mode resistor R D_WT (connected in series with the corresponding switches) and the power saving mode resistor R D_WOT (connected in series with the corresponding switches) are coupled in parallel between the positive output terminal and the positive channel and between the negative output terminal and the negative channel, so that the variable output impedance circuit can control the on or off of the switches according to the detection result DET to operate the transmission circuit TX3 in the standard mode or the power saving mode. AsFigure 5A As shown, when the transmission circuit TX3 outputs the second data signal in standard mode (the first data signal has a transition state), the detection result DET control switch turns on the standard mode resistor R. D_WT and matching resistor R S And disconnect the power saving mode resistor R D_WOT In other words, the positive and negative output terminals of the drive circuit are respectively connected to the standard mode resistor R. D_WT Drive the positive and negative channels. In this way, the transmit / receive system 3 can select the standard mode resistor R. D_WT and matching resistor R S The resistance value is related to the channel impedance Z0 and the input impedance Z. RX3 Impedance matching is achieved. At this point, the amplitudes of the second and third data signals are essentially the same. On the other hand, as... Figure 5B As shown, when the transmission circuit TX3 outputs the second data signal in power-saving mode (the first data signal has no state change), the detection result DET control switch disconnects the standard mode resistor R. D_WT and matching resistor R S And turn on the power-saving mode resistor R D_WOT In other words, the positive and negative output terminals of the drive circuit are respectively connected to the power-saving mode resistor R. D_WOT Drive the positive and negative channels; at this time, even the power-saving mode resistor R D_WOT and channel impedance Z0, input impedance Z RX3 Impedance matching was not achieved, and the third data signal experienced almost no attenuation. It should be noted that when the transmission circuit TX3 outputs the second data signal in standard mode, the drive current I provided by the transmission circuit TX3... RD_WT They will flow into the matching resistor R respectively. S and input impedance Z RX3 When the transmission circuit TX3 outputs the second data signal in power-saving mode, the drive current I provided by the transmission circuit TX3 is... RD_WOT Only the input impedance Z will flow. RX3 In this way, the present invention can be achieved by appropriately selecting the standard mode resistor R. D_WT Power saving mode resistor R D_WOT and matching resistor R S The resistance value causes the drive current I of the transmission circuit TX3 to operate in power-saving mode. RD_WOT Drive current I below standard mode RD_WT To achieve power saving, the power saving mode resistor R... D_WOT The resistance value is greater than the standard mode resistance R. D_WT The resistance value. Furthermore, regardless of whether the transmission circuit TX3 outputs the second data signal in standard mode or power-saving mode, the input impedance Z flowing into the receiving circuit RX3... RX3the current I LOAD must be maintained constant so that the amplitude V OD of the received signal of the receiving circuit RX3 is kept substantially the same.
[0043] For example, in one embodiment, it is assumed that the input impedance Z RX3 is 50 ohms (Ω), the driving voltage of the transmission circuit TX3 is 0.9 volts (V), and the requirement of the amplitude V OD of the received signal of the receiving circuit RX2 is 200 millivolts (mV). In this case, when the transmission circuit TX3 outputs the second data in the standard mode, the embodiment of the present application can determine that the standard mode resistance R D_WT is 112 ohms (Ω) and the matching resistance R S is 90 ohms (Ω), so that the variable output impedance circuit reaches impedance matching with the channel impedance Z0, the input impedance Z RX3 . At this time, the current I LOAD is 2 milliamps (mA) and the current flowing into the matching resistance R S is 1.11 milliamps (mA). In other words, the driving current I RD_WT provided when the transmission circuit TX3 outputs the second data in the standard mode is 3.11 milliamps (mA). On the other hand, when the transmission circuit TX3 outputs the second data in the power saving mode, the embodiment of the present application can determine that the power saving mode resistance R D_WOT is 175 ohms (Ω). At this time, since the standard mode resistance R D_WT and the matching resistance R S have been disconnected, the driving current I RD_WOT provided when the transmission circuit TX3 outputs the second data in the power saving mode is 2 milliamps (mA) and flows into the input impedance Z RX3 , that is, both the driving current I RD_WOT and the current I LOAD are 2 milliamps (mA). In short, compared with the transmission circuit TX1 of the conventional serializer / deserializer system 1 which always transmits the data signal in the standard mode, the transmission / receiving system 3 of the embodiment of the present application transmits the first data signal in the power saving mode when there is no transition of the first data signal, and at the same time maintains the amplitude V OD of the received signal substantially the same. Therefore, the driving current of the transmission circuit TX3 is reduced from 3.11 milliamps (mA) to 2 milliamps (mA), that is, by 35%, when there is no transition of the first data signal. It should be noted that the channel impedance has little effect at low frequencies, so the above embodiment ignores the channel impedance for the sake of clear illustration. However, in actual situations, one skilled in the art can adjust the impedance values as required by the system.
[0044] It should be noted that, Figure 5A and Figure 5BFor the embodiments of the present application, those skilled in the art can make appropriate adjustments according to the needs of the system. For example, Figure 5A and Figure 5B The driving circuit of the voltage type is suitable for the driving circuit of the present application, which can also be a current-based driving circuit. Please refer to Figure 6A and Figure 6B , Figure 6A and Figure 6B is a schematic diagram of a transmission circuit TX4, a channel and an equivalent circuit of a receiving circuit RX4 of another embodiment of the present application. The variable output impedance circuit includes a matching resistor R S and a corresponding switch; the current-based driving circuit includes a standard mode current source I WT , a power saving mode current source I WOT and a corresponding switch. The channel includes a positive channel and a negative channel. Specifically, the matching resistor R S and the corresponding switch are coupled in series between the positive channel and the negative channel, and the standard mode current source I WT (connected in series with the corresponding switch) and the power saving mode current source I WOT (connected in series with the corresponding switch) are coupled in parallel to provide driving current to the positive channel and the negative channel, so that the variable output impedance circuit can control the on or off of the switch according to the detection result DET to operate the transmission circuit TX3 in the standard mode or the power saving mode. As shown in Figure 6A , when the transmission circuit TX4 outputs the second data signal (the first data signal has a transition) in the standard mode, the detection result DET controls the switch to turn on the standard mode current source I WT and the matching resistor R S , and turn off the power saving mode current source I WOT , in other words, the positive output terminal and the negative output terminal of the driving circuit provide driving current through the standard mode current source I WT to drive the positive channel and the negative channel. In this way, the transmission-receiving system 4 can select the resistance value of the matching resistor R S to achieve impedance matching with the channel impedance Z0, the input impedance Z RX4 . At this time, the amplitude of the second data signal and the amplitude of the third data signal are substantially the same. On the other hand, as shown in Figure 6B , when the transmission circuit TX4 outputs the second data signal (the first data signal has no transition) in the power saving mode, the detection result DET controls the switch to turn off the standard mode current source I WT and the matching resistor R S , and turn on the power saving mode current source I WOT , in other words, the positive output terminal and the negative output terminal of the driving circuit provide driving current through the power saving mode current source I WOTa current is provided to drive the positive channel and the negative channel; at this time, even if the transmission circuit TX4 and the channel impedance Z0, the input impedance Z RX4 impedance matching is not reached, and the third data signal is hardly attenuated. It is noted that when the transmission circuit TX4 outputs the second data signal in the standard mode, the standard mode current source I WT will flow into the matching resistance R S and the input impedance Z RX4 respectively; when the transmission circuit TX4 outputs the second data signal in the power saving mode, the driving current I WOT provided by the transmission circuit TX4 will only flow into the input impedance Z RX4 . In this way, the present application can achieve the power saving effect by properly selecting the resistance values of the standard mode current source I WT , the power saving mode current source I WOT , and the matching resistance R S , so that the current source I WOT operating in the power saving mode of the transmission circuit TX4 is lower than the standard mode current source I WT , where the current value of the power saving mode current source I WOT is less than the current value of the standard mode current source I WT . In addition, in order to maintain the amplitude V OD of the received signal of the receiving circuit RX4, the current I RX4 flowing into the input impedance Z LOAD will remain unchanged when the transmission circuit TX4 outputs the second data in the standard mode and the power saving mode.
[0045] For example, in an embodiment, assuming that the input impedance Z RX4 is 50 ohms (Ω) and the requirement of the amplitude V OD of the received signal of the receiving circuit RX4 is 200 millivolts (mV), the embodiment of the present application can decide that the driving current provided by the standard mode current source I WT is 4 milliamperes (mA) and the matching resistance R S is 50 ohms (Ω) when the transmission circuit TX4 outputs the second data in the standard mode, so that the variable output impedance circuit and the channel impedance Z0, the input impedance Z RX4 reach impedance matching; at this time, the current I LOAD is 2 milliamperes (mA) and the current flowing into the matching resistance R S is also 2 milliamperes (mA). On the other hand, when the transmission circuit TX4 outputs the second data in the power saving mode, since the matching resistance R S has been disconnected, the embodiment of the present application can decide that the driving current provided by the power saving mode current source I WOT is 2 milliamperes (mA). At this time, the power saving mode current source I WOTThe driving current provided flows into the input impedance Z RX4 , i.e. the power saving mode current source I WOT The driving current provided and the current I LOAD are both 2 milliampere (mA). In short, compared to the transmission circuit TX1 of the conventional serializer / deserializer system 1 which transmits the data signal in the standard mode all the time, the transmission / reception system 4 of the embodiment of the present application, if using the current-driven circuit, transmits the first data signal in the power saving mode when there is no transition in the first data signal, while maintaining the amplitude V OD of the received signal substantially the same. Therefore, the driving current of the current-driven circuit is reduced from 4 milliampere (mA) to 2 milliampere (mA), i.e. 50% reduction, when there is no transition in the first data signal.
[0046] It is noted that the transmission / reception systems 2-4 are different embodiments of the present application, and those skilled in the art can make different modifications accordingly without being limited thereto. In particular, the transition detector circuit 22 of the present application can be used to detect when there is no transition in one or consecutive unit periods, and adjust the variable output impedance circuit to reduce the power consumption of the output stage circuit of the transmission circuit TX2. For example, as shown in Figure 2B , when the output impedance Z TX1 , the channel impedance Z0, and the input impedance Z RX1 reach impedance matching, the third data signal has no transition in the first unit period (1st TP) of the clock signal, and also has no transition in the second unit period (2nd TP) following the first unit period. Therefore, the transition detector circuit 22 of the present application can be implemented with other logic gates to detect when there is no transition in the first data signal in two consecutive unit periods, and adjust the variable output impedance circuit in the second unit period to reduce the power consumption of the output stage circuit of the transmission circuit TX2. In addition, when the driving circuit is a current-driven circuit, the transition detector circuit 22 can also detect when there is no transition in the first data signal in two consecutive unit periods, and adjust the driving current of the current-driven circuit in the second unit period to reduce the power consumption. In short, the transition detector circuit 22 of the present application detects when there is no transition in any unit period, and controls the transmission / reception systems 2-4 to enter the power saving mode after one more unit period. In addition, if the transition detector circuit 22 detects that there is a transition in any unit period, it immediately controls the transmission / reception systems 2-4 to enter the standard mode to avoid data signal attenuation. It is noted that the transition detector circuit 22 of the present application can detect when there is no transition in two consecutive unit periods, but those skilled in the art can make appropriate adjustments according to the needs of the system.
[0047] Please refer to Figure 7 which shows a transmission method 5 which can be used in the above-mentioned transmission method 1. Figures 3-6BThe transmission and receiving systems 2 to 4 shown are not limited to these. Transmission method 5 includes the following steps:
[0048] Step S500: Receive a first data signal and a clock signal with a unit cycle. For example, the first data signal and the clock signal can be received using a transmission circuit TX2.
[0049] Step S502: Detect whether the first data signal has changed state based on the clock signal and generate a detection result. This detection result can be used to indicate the operating mode. For example, the present invention can utilize the state change detection circuit 22 to detect whether the first data signal has changed state based on the clock signal and generate a detection result DET. That is, the detection result DET is a signal used to indicate whether the first data signal has changed state. Specifically, when the detection result DET indicates that the first data signal has changed state (e.g., logic high state), the transmission circuit TX2 operates in standard mode; when the detection result DET indicates that the first data signal has not changed state (e.g., logic low state), the transmission circuit TX2 operates in power-saving mode. In one embodiment, when it is detected that the first data signal has not changed state in any unit cycle of the clock signal, it is determined that the power-saving mode has been entered. In another embodiment, it is determined that the power-saving mode has been entered only when it is detected that the first data signal has not changed state in multiple consecutive unit cycles of the clock signal. However, it should be noted that when it is detected that the first data signal has changed state, it is determined that the standard mode has been entered.
[0050] Step S504: Based on the detection results, adjust the variable output impedance circuit and / or adjust the drive current of the drive circuit, i.e., adjust the characteristics of the transmission circuit. In standard mode, ensure that the equivalent output impedance of the transmission circuit is impedance-matched with the channel impedance and the input impedance of the receiving circuit; while in power-saving mode, reduce the drive current of the transmission circuit. Furthermore, in both standard and power-saving modes, keep the amplitude of the output signal of the transmission circuit substantially constant. For example, in... Figure 5A , Figure 5B In the voltage-driven mode shown, when the detection result DET indicates a change in the first data signal (standard mode), the variable output impedance circuit is adjusted so that the equivalent output impedance of the variable output impedance circuit is equal to the channel impedance Z0 and the input impedance Z0. RX3 Impedance matching is achieved. Furthermore, when the detection result DET indicates that the first data signal has no transition state (power-saving mode), the variable output impedance circuit is adjusted to reduce the drive current of the transmission circuit TX3. Specifically, in, for example... Figure 5B In the power-saving mode shown, the standard mode resistor R can be disconnected. D_WT and matching resistor R S And turn on the power-saving mode resistor R D_WOT Among them, the power saving mode resistor R D_WOT The resistance value is greater than the standard mode resistance R.D_WT The resistance value. On the other hand, for example in Figure 6A , Figure 6B In the current-driven mode shown, when the detection result DET indicates a change in the first data signal (standard mode), the variable output impedance circuit and the drive current of the drive circuit are adjusted so that the equivalent output impedance of the variable output impedance circuit is equal to the channel impedance Z0 and the input impedance Z0. RX4 Impedance matching is achieved. Furthermore, when the detection result DET indicates that the first data signal has no transition state (power-saving mode), the variable output impedance circuit and the drive current of the drive circuit are adjusted to reduce the drive current of the transmission circuit TX4. Specifically, in, for example... Figure 6B In the power-saving mode shown, the standard mode current source I can be disconnected. WT and matching resistor R S And turn on the power-saving mode current source I. WOT Among them, the power-saving mode current source I WOT The current is less than that of the standard mode current source I. WT The current.
[0051] Step S506: Generate a corresponding second data signal based on the first data signal, and transmit the second data signal to the receiving circuit via the channel as a third data signal. That is, the input terminal of the receiving circuit receives the third data signal corresponding to the second data signal. Specifically, as follows... Figure 5A , Figure 5B The voltage-driven method shown and Figure 6A , Figure 6B In the current-driven mode shown, the second data signal generated by the transmission circuits TX3 and TX4 is transmitted through the channel to the corresponding receiving circuits RX3 and RX4 to become the third data signal without attenuation. Therefore, the amplitudes of the second and third data signals are essentially the same. Furthermore, regardless of whether the transmission circuits TX3 and TX4 operate in standard or power-saving mode, the amplitude of the second data signal remains essentially unchanged. Therefore, the amplitude V of the third data signal received by the corresponding receiving circuits RX3 and RX4 is also constant. OD They are essentially the same and are not affected by the operating mode.
[0052] In short, in the aforementioned voltage-driven and current-driven signal transmission methods, the operating mode of the transmission circuit can be determined based on whether the first data signal (input signal) undergoes a state transition. When the transmission circuit operates in standard mode, the equivalent output impedance of the transmission circuit can be impedance matched with the channel impedance and the input impedance of the receiving circuit to avoid signal attenuation. When the transmission circuit operates in power-saving mode, the drive current of the transmission circuit can be adjusted to reduce power consumption. Furthermore, regardless of whether the transmission circuit operates in standard mode or power-saving mode, the amplitude V of the signal received by the receiving circuit... ODThe same can be maintained substantially, so as to meet the application requirements.
[0053] In summary, the transmission circuit, the transmission method and the transmission-reception system of the present application can adjust the impedance value of the variable output impedance circuit and / or the driving current of the driving circuit when no transition of the data signal is detected, and can maintain the amplitude of the received signal of the receiving circuit at the same time. In this way, compared with the prior art, the adjustment function of the present application can reduce the power consumption of the transmission-reception system while maintaining the amplitude of the received signal.
[0054] The above is only the preferred embodiment of the present application, and any equivalent changes and modifications made within the scope of the patent application of the present application shall be covered by the present application.
Claims
1. A transmitting circuit for transmitting with a receiving circuit via a positive channel and a negative channel, characterized in that, The transmission circuit comprises: an output stage circuit comprising: a variable output impedance circuit coupled to the positive terminal channel and the negative terminal channel; and a driving circuit comprising a positive output terminal and a negative output terminal for outputting a second data signal according to a first data signal through the variable output impedance circuit, wherein the positive output terminal and the negative output terminal drive the positive terminal channel and the negative terminal channel respectively through the variable output impedance circuit; and a transition detection circuit coupled to the output stage circuit for detecting whether the first data signal has a transition according to a clock signal having a unit period and generating a detection result for adjusting the variable output impedance circuit.
2. The transmission circuit of claim 1, wherein, The variable output impedance circuit comprises a matching resistor and a first switch, the matching resistor and the first switch are coupled in series between the positive terminal channel and the negative terminal channel, the variable output impedance circuit controls the first switch to be on or off according to the detection result; and when the detection result indicates that the first data signal has a transition, the first switch is on; when the detection result indicates that the first data signal has no transition, the first switch is off.
3. The transmission circuit of claim 2, wherein, The variable output impedance circuit further comprises a first standard mode resistor, a second standard mode resistor, a first power saving mode resistor and a second power saving mode resistor, the first standard mode resistor and the first power saving mode resistor are coupled in parallel between the positive output terminal and the positive terminal channel, the second standard mode resistor and the second power saving mode resistor are coupled in parallel between the negative output terminal and the negative terminal channel; and when the detection result indicates that the first data signal has a transition, the transition detection circuit controls the positive output terminal to drive the positive terminal channel through the first standard mode resistor, and the negative output terminal to drive the negative terminal channel through the second standard mode resistor; and when the detection result indicates that the first data signal has no transition, the transition detection circuit controls the positive output terminal to drive the positive terminal channel through the first power saving mode resistor, and the negative output terminal to drive the negative terminal channel through the second power saving mode resistor.
4. The transmission circuit of claim 3, wherein, The first standard mode resistor and the second standard mode resistor both have a first resistance value, the first power saving mode resistor and the second power saving mode resistor both have a second resistance value, and the second resistance value is greater than the first resistance value.
5. The transmission circuit of claim 2, wherein, The driving circuit further comprises a standard mode current source and a power saving mode current source, the standard mode current source and the power saving mode current source are coupled in parallel to provide a driving current to the positive terminal channel and the negative terminal channel; and when the detection result indicates that the first data signal has a transition, the driving circuit controls the path of the standard mode current source to be on and the path of the power saving mode current source to be off, so that the driving circuit provides the driving current with the standard mode current source; and When the detection result indicates that the first data signal has no transition, the driving circuit controls the standard mode current source to be turned off and the power saving mode current source to be turned on, so that the driving circuit provides the driving current with the power saving mode current source.
6. The transmission circuit of claim 5, wherein, The standard mode current source has a first current value, and the power saving mode current source has a second current value, and the second current value is less than the first current value.
7. The transmission circuit according to any one of claims 1-6, wherein, When the first data signal has a transition during any unit period, the transition detection circuit causes the detection result to be in a first state to indicate that the transmission circuit operates in a standard mode. and When the first data signal has no transition during any unit period, the transition detection circuit causes the detection result to be in a second state to indicate that the transmission circuit operates in a power saving mode.
8. Transmission circuit according to any one of claims 1 to 6, characterized in that, When the first data signal has a transition during any unit period, the transition detection circuit causes the detection result to be in a first state to indicate that the transmission circuit operates in a standard mode. and When the first data signal has no transition during consecutive unit periods, the transition detection circuit causes the detection result to be in a second state to indicate that the transmission circuit operates in a power saving mode.
9. The transmission circuit of claim 7, wherein, The amplitude of the second data signal is substantially the same when the transmission circuit operates in the standard mode and the power saving mode.
10. The transmission circuit of claim 8, wherein, The amplitude of the second data signal is substantially the same when the transmission circuit operates in the standard mode and the power saving mode.
11. A transmission-reception system, characterized in that comprising: a transmission circuit according to any one of claims 1-10, for outputting a second data signal; a receiving circuit, for receiving a third data signal; and a channel, comprising a positive terminal channel and a negative terminal channel, coupled between the transmission circuit and the receiving circuit, for transmitting the second data signal outputted by the transmission circuit to the receiving circuit as the third data signal.
12. The transmission receiver system of claim 11, wherein, The amplitude of the second data signal is substantially the same as the amplitude of the third data signal.
13. A transmission method for a transmission circuit, wherein the transmission circuit transmits signals with a receiving circuit through a positive terminal channel and a negative terminal channel, characterized in that, The transmission method comprises: receiving a first data signal and a clock signal having a unit period; detecting whether the first data signal has a transition according to the clock signal, and generating a detection result; adjusting the characteristics of the transmission circuit according to the detection result; and outputting a second data signal according to the first data signal, and transmitting the second data signal to the receiving circuit as a third data signal through the positive terminal channel and the negative terminal channel.
14. The transmission method of claim 13, wherein, The step of adjusting the characteristics of the transmission circuit according to the detection result comprises: when the detection result indicates that the first data signal has a transition, adjusting the equivalent output impedance of the transmission circuit, so that the transmission circuit, the positive terminal channel, the negative terminal channel and the receiving circuit are impedance matched; and when the detection result indicates that the first data signal has no transition, reducing the driving current of the transmission circuit.
15. The transmission method according to any one of claims 13 to 14, characterized in that, The step of detecting whether the first data signal transitions according to the clock signal and generating a detection result further comprises: when the first data signal has a transition during any unit period, the detection result is in a first state to indicate that the transmission circuit operates in a standard mode; and when the first data signal has no transition during any unit period, the detection result is in a second state to indicate that the transmission circuit operates in a power saving mode.
16. The transmission method according to any one of claims 13 to 14, characterized in that, The step of detecting whether the first data signal transitions according to the clock signal and generating a detection result further comprises: when the first data signal has a transition during any unit period, the detection result is in a first state to indicate that the transmission circuit operates in a standard mode; and when the first data signal has no transition during any unit period, the detection result is in a second state to indicate that the transmission circuit operates in a power saving mode.
17. The transmission method of claim 15, wherein, The amplitude of the second data signal is substantially the same in the case that the transmission circuit operates in the standard mode and the power saving mode; and The amplitude of the second data signal is substantially the same as the amplitude of the third data signal.
18. The transmission method of claim 16, wherein, The amplitude of the second data signal is substantially the same in the case that the transmission circuit operates in the standard mode and the power saving mode; and The amplitude of the second data signal is substantially the same as the amplitude of the third data signal.