Semiconductor device

Abstract

An example semiconductor device includes a lower wiring including a lower wiring line; an upper wiring layer including an upper wiring line; and a power gating unit between the lower wiring layer and the upper wiring layer. The power gating unit includes: a first active region on the substrate and including first and second lower source / drain patterns and a first channel pattern connecting the first and second lower source / drain patterns to each other; a second active region on the first active region and including a first upper source / drain pattern and a second upper source / drain pattern; and a power gate electrode surrounding the first channel pattern and extending in a first direction parallel to the top surface of the substrate. The lower wiring layer includes: a global power line connected to the first lower source / drain pattern; and a local power line connected to the second lower source / drain pattern.

Description

TECHNICAL FIELD

[0001] The disclosure relates to a semiconductor device. BACKGROUND

[0002] A semiconductor device includes an integrated circuit composed of a metal oxide semiconductor field effect transistor (MOSFET). As the size and design rule of the semiconductor device gradually decrease, the size of the MOSFET is also increasingly small. The miniaturization of the MOSFET deteriorates the operating characteristics of the semiconductor device. Therefore, various studies have been made to manufacture a semiconductor device with improved performance while overcoming the limitations caused by the integration of the semiconductor device. SUMMARY

[0003] The disclosure relates to a semiconductor device with improved electrical characteristics and increased integration.

[0004] The objects of the disclosure are not limited to the above, and other objects not mentioned above will become apparent to those skilled in the art from the following description.

[0005] In some embodiments, a semiconductor device can include a lower wiring layer including a plurality of lower wiring lines, an upper wiring layer including a plurality of upper wiring lines, and a power gate unit between the lower wiring layer and the upper wiring layer. The power gate unit can include a first active region on a substrate, wherein the first active region includes a first lower source / drain pattern, a second lower source / drain pattern, and a first channel pattern connecting the first lower source / drain pattern and the second lower source / drain pattern to each other, a second active region on the first active region, wherein the second active region includes a first upper source / drain pattern and a second upper source / drain pattern, and a power gate electrode surrounding the first channel pattern and extending in a first direction parallel to a top surface of the substrate. The lower wiring layer can include a global power line connected to the first lower source / drain pattern, and a local power line connected to the second lower source / drain pattern.

[0006] In some embodiments, a semiconductor device can include: a first active region on a substrate, wherein the first active region includes a first lower source / drain pattern, a second lower source / drain pattern, and a first channel pattern connecting the first lower source / drain pattern and the second lower source / drain pattern to each other; a second active region on the first active region, wherein the second active region includes a first upper source / drain pattern and a second upper source / drain pattern; a power gate electrode extending in a first direction parallel to a top surface of the substrate and surrounding the first channel pattern; a global power line on a bottom surface of the substrate and connected to the first lower source / drain pattern; a first local power line on the bottom surface of the substrate and connected to the second lower source / drain pattern; a through-active contact connecting the second lower source / drain pattern and the second upper source / drain pattern; and a second local power line on the top surface of the substrate and connected to the through-active contact.

[0007] In some embodiments, a semiconductor device can include: a first active region on a substrate, wherein the first active region includes a first lower source / drain pattern, a second lower source / drain pattern, and a first channel pattern connecting the first lower source / drain pattern and the second lower source / drain pattern to each other; a second active region on the first active region, wherein the second active region includes a first upper source / drain pattern and a second upper source / drain pattern; a power gate electrode extending in a first direction parallel to a top surface of the substrate and surrounding the first channel pattern; a first separation pattern spaced apart from the power gate electrode in a second direction and contacting the first lower source / drain pattern; a second separation pattern spaced apart from the power gate electrode in the second direction and contacting the second lower source / drain pattern and the second upper source / drain pattern; a third separation pattern between the first upper source / drain pattern and the second upper source / drain pattern and overlapping the power gate electrode; a dummy gate electrode extending in the first direction and surrounding a second channel pattern on the first separation pattern; a global power line on a bottom surface of the substrate and connected to the first lower source / drain pattern; a first local power line on the bottom surface of the substrate and connected to the second lower source / drain pattern; a first lower active contact between the global power line and the first lower source / drain pattern; a second lower active contact between the first local power line and the second lower source / drain pattern; a through active contact connecting the second lower source / drain pattern to the second upper source / drain pattern; and a second local power line on the top surface of the substrate and connected to the through active contact.

[0008] Details of other embodiments are included in the description and the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 and Figure 2 An example conceptual diagram depicting a logic cell of a semiconductor device is shown.

[0010] Figure 3 A block diagram depicting an example of a semiconductor device including a power gating circuit is shown.

[0011] Figure 4A A top view depicting an example of a semiconductor device including a power gating cell is shown.

[0012] Figure 4B A bottom view of an example depicting a semiconductor device including a power gating cell is shown.

[0013] Figure 5A An example cross-sectional view taken along line A-A' of Figure 4A and Figure 4B is shown.

[0014] Figure 5B An example cross-sectional view taken along line B-B' of Figure 4A and Figure 4B is shown.

[0015] Figure 5C An example cross-sectional view taken along line C-C' of Figure 4A and Figure 4B is shown.

[0016] Figure 5D An example cross-sectional view taken along line D-D' of Figure 4A and Figure 4B is shown.

[0017] Figure 5E An example cross-sectional view taken along line E-E' of Figure 4A and Figure 4B is shown.

[0018] Figure 6 A block diagram of an example depicting a semiconductor device including a power gating circuit is shown.

[0019] Figure 7A A top view of an example depicting a semiconductor device including a power gating cell is shown.

[0020] Figure 7B A bottom view of an example depicting a semiconductor device including a power gating cell is shown.

[0021] Figure 8A An example cross-sectional view taken along line A-A' of Figure 7A and Figure 7B is shown.

[0022] Figure 8B An example cross-sectional view taken along line B-B' of Figure 7A and Figure 7B is shown.

[0023] Figure 8C An example cross-sectional view taken along line C-C' of Figure 7A and Figure 7B is shown.

[0024] Figure 8D An example cross-sectional view taken along line D-D' of Figure 7A andFigure 7B Example cross-sectional view taken along line D-D' of

[0025] Figure 8E Example cross-sectional view taken along line D-D' of Figure 7A and Figure 7B Example cross-sectional view taken along line E-E' of

[0026] Figure 9A Example top view depicting an example of a semiconductor device including a power gating cell.

[0027] Figure 9B Example bottom view depicting an example of a semiconductor device including a power gating cell.

[0028] Figure 10A Example cross-sectional view taken along line A-A' of Figure 9A and Figure 9B Example cross-sectional view taken along line B-B' of

[0029] Figure 10B Example cross-sectional view taken along line B-B' of Figure 9A and Figure 9B Example cross-sectional view taken along line C-C' of

[0030] Figure 10C Example cross-sectional view taken along line C-C' of Figure 9A and Figure 9B Example cross-sectional view taken along line D-D' of

[0031] Figure 10D Example cross-sectional view taken along line D-D' of Figure 9A and Figure 9B Example cross-sectional view taken along line E-E' of

[0032] Figure 10E Example cross-sectional view taken along line E-E' of Figure 9A and Figure 9B Example cross-sectional view taken along line E-E' of

[0033] Figure 11 Example bottom view depicting an example of a semiconductor device including a power gating cell.

[0034] Figure 12 Example cross-sectional view taken along line E-E' of Figure 11

[0035] Example top view depicting an example of a semiconductor device including a power gating cell. Figure 13

[0036] Example cross-sectional view taken along line E-E' of Figure 14 Figure 13 Example bottom view depicting an example of a semiconductor device including a power gating cell.

[0037] Figure 15 ​A top view illustrating an example of a semiconductor device including a power gating unit is shown.

[0038] Figure 16 An example cross-sectional view taken along line B-B' of Figure 15 is shown.

[0039] Figure 17 An example cross-sectional view taken along line E-E' of Figure 15 is shown.

[0040] Figure 18A A top view illustrating an example of a semiconductor device including a power gating unit is shown.

[0041] Figure 18B A bottom view illustrating an example of a semiconductor device including a power gating unit is shown.

[0042] Figure 19A An example cross-sectional view taken along line A-A' of Figure 18A and Figure 18B is shown.

[0043] Figure 19B An example cross-sectional view taken along line B-B' of Figure 18A and Figure 18B is shown. DETAILED DESCRIPTION

[0044] Referring to the drawings, a semiconductor device according to some embodiments of the disclosure will be described in detail below.

[0045] Figure 1 and Figure 2 An example conceptual diagram illustrating a logic cell of a semiconductor device is shown.

[0046] In some embodiments, a logic cell can be a unit cell of a layout included in a semiconductor device, can be designed to perform a preset function, and can be referred to as a standard cell. A semiconductor device can include logic cells having various functions. A logic cell can refer to a logic device that performs a specific function, such as AND, OR, XOR, XNOR, and an inverter. For example, a logic cell can include transistors for constituting a logic device, and can also include a wiring line connecting the transistors to each other.

[0047] A logic cell can include a single-height cell SHC and a double-height cell DHC.

[0048] Referring to Figure 1 , a single-height cell SHC including a stacked transistor can be provided.

[0049] For example, a first power line POR1 and a second power line POR2 can be provided on the substrate 100. A single-height cell SHC can be defined between the first power line POR1 and the second power line POR2. The first power line POR1 can be a path to which a source voltage (e.g., a ground voltage (VSS)) is supplied. The second power line POR2 can be a path to which a drain voltage (e.g., a power supply voltage (VDD)) is supplied. The first power line POR1 and the second power line POR2 can extend along a first direction D1 parallel to a top surface of the substrate 100. The first power line POR1 and the second power line POR2 can be spaced apart from each other in a second direction D2 parallel to the top surface of the substrate 100 and crossing the first direction D1.

[0050] The single-height cell SHC can include a lower active region LAR and an upper active region UAR. One of the lower active region LAR and the upper active region UAR can be a PMOSFET region, and the other of the lower active region LAR and the upper active region UAR can be an NMOSFET region.

[0051] The semiconductor device can be a three-dimensional device in which transistors are vertically stacked on a front-end-of-line (FEOL) layer.

[0052] The upper active region UAR can be stacked on the lower active region LAR in a third direction D3 perpendicular to the top surface of the substrate 100. For example, when viewed in a top view, the upper active region UAR can overlap the lower active region LAR.

[0053] According to some embodiments, a first height HE1 can be defined as indicating a length of the single-height cell SHC in the second direction D2. The first height HE1 can be substantially the same as a distance (e.g., a pitch) between the first power line POR1 and the second power line POR2. Each of the lower active region LAR and the upper active region UAR can have a first width W1 in the second direction D2. The first width W1 can be less than the first height HE1.

[0054] The single-height cell SHC according to some embodiments can integrate all NMOSFETs and PMOSFETs in a limited area of the first height HE1. Accordingly, the semiconductor device can have increased integration.

[0055] Reference Figure 2A double-height cell DHC can be provided. For example, a first power line POR1, a second power line POR2, and a third power line POR3 can be disposed on the substrate 100. The first power line POR1 can be disposed between the second power line POR2 and the third power line POR3. The first power line POR1 can be a path to which a source voltage (e.g., a ground voltage (VSS)) is supplied. The second power line POR2 and the third power line POR3 can be paths to which a drain voltage (e.g., a power supply voltage (VDD)) is supplied. The first power line POR1, the second power line POR2, and the third power line POR3 can extend along a first direction D1 parallel to a top surface of the substrate 100, and can be spaced apart from each other in a second direction D2 parallel to the top surface of the substrate 100 and intersecting the first direction D1.

[0056] A double-height cell DHC can be defined between the second power line POR2 and the third power line POR3. The double-height cell DHC can include first and second lower active regions LAR1 and LAR2, and first and second upper active regions UAR1 and UAR2.

[0057] The first upper active region UAR1 can be disposed on the first lower active region LAR1, and the second upper active region UAR2 can be disposed on the second lower active region LAR2. For example, the first lower active region LAR1 can overlap the first upper active region UAR1, and the second lower active region LAR2 can overlap the second upper active region UAR2 when viewed in a top view. The first lower active region LAR1 can be spaced apart from the second lower active region LAR2 in the second direction D2 parallel to the top surface of the substrate 100.

[0058] A double-height cell DHC according to some embodiments can have a second height HE2 in the second direction D2. The second height HE2 can be substantially the same as a distance between the second power line POR2 and the third power line POR3. The second height HE2 can be about twice a first height HE1 in the single-height cell SHC. Figure 1 Each of the first and second upper active regions UAR1 and UAR2 can have a second width W2 in the second direction D2. The second width W2 can be less than half of the second height HE2.

[0059] In the present disclosure, Figure 2 The double-height cell DHC shown can be defined as a multi-height cell. Although not shown, the multi-height cell can include a triple-height cell having a cell height that is about three times a cell height of the single-height cell SHC.

[0060] Figure 3 A block diagram depicting an example of a semiconductor device including a power gating circuit is shown.

[0061] Reference Figure 3 The semiconductor device can include a power gating circuit 10 and a logic circuit 20.

[0062] The power gating circuit 10 can include a PMOS power gate transistor PG connected between a first global power line VDDG and a first power line VDD.

[0063] The power gating circuit 10 can be turned on to provide a power supply voltage to the logic circuit 20 when the logic circuit 20 is in an active state.

[0064] The power gating circuit 10 can selectively connect the first global power line VDDG to the first power line VDD in response to a control signal applied to a power gate electrode PGE to adjust the power supply voltage provided to the logic circuit 20 and adjust a power mode of the logic circuit 20.

[0065] In the power-on mode, the power gating circuit 10 can connect the first power line VDD and the first global power line VDDG to each other, thereby providing a power supply voltage to the logic circuit 20.

[0066] In the power-off mode, the power gating circuit 10 can disconnect the first power line VDD and the first global power line VDDG from each other, thereby electrically floating the first power line VDD.

[0067] The power gating circuit 10 can further include a control circuit that provides the control signal applied to the power gate electrode PGE to the power gate transistor PG.

[0068] The logic circuit 20 can include an arbitrary circuit connected to the first power line VDD. For example, the logic circuit 20 can be implemented as an inverter, a NAND gate, an AND gate, a NOR gate, an OR gate, an XOR gate, an XNOR gate, a multiplexer, an adder, a latch, or a flip-flop.

[0069] The logic circuit 20 can be selectively provided with a power supply voltage through the first power line VDD. The logic circuit 20 can be provided with a driving voltage having a level different depending on the power mode. For example, the logic circuit 20 can be provided with a power supply voltage in the power-on mode and not supplied with power in the power-off mode. The semiconductor device according to some embodiments can be configured to operate in one or more retention modes in addition to the power-on mode and the power-off mode.

[0070] Figure 4A A top view illustrating an example of a semiconductor device including a power gating unit is shown. Figure 4B A bottom view illustrating an example of a semiconductor device including a power gating unit is shown.Figure 5A 、 Figure 5B 、 Figure 5C 、 Figure 5D and Figure 5E shows example cross-sectional views taken along lines A-A’, lines B-B’, lines C-C’, lines D-D’, and lines E-E’ of Figure 4A and Figure 4B .

[0071] Referring to Figure 4A 、 Figure 4B 、 Figure 5A 、 Figure 5B 、 Figure 5C 、 Figure 5D and Figure 5E , a semiconductor device according to some embodiments can include, when viewed in a direction normal to a top surface of a substrate 100: a lower wiring layer LMS including lower wiring lines, an upper wiring layer UMS including upper wiring lines, and a device layer DS disposed between the lower wiring layer LMS and the upper wiring layer UMS.

[0072] The substrate 100 can have a top surface and a bottom surface opposite each other. The substrate 100 can be a dielectric substrate including silicon-based dielectric materials (e.g., silicon oxide and / or silicon nitride). Alternatively, the substrate 100 can be a semiconductor substrate including silicon, germanium, or silicon germanium.

[0073] The device layer DS can include logic cells LC and power-gating cells PGC disposed on the substrate 100. The logic cells LC and the power-gating cells PGC can each be single-height cells discussed above with reference to Figure 1 .

[0074] The device layer DS can include a first lower active region LAR1 located on the substrate 100 and a first upper active region UAR1 stacked on the first lower active region LAR1.

[0075] For example, the first lower active region LAR1 can be a PMOSFET region, and the first upper active region UAR1 can be an NMOSFET region. Alternatively, the first lower active region LAR1 can be an NMOSFET region, and the first upper active region UAR1 can be a PMOSFET region. Each of the first lower active region LAR1 and the first upper active region UAR1 can have a strip shape or a linear shape extending in a first direction D1.

[0076] According to some embodiments, the power-gating cell PGC can be disposed on the first lower active region LAR1 and can be formed of a PMOS transistor. The power-gating cell PGC can include a three-dimensional field effect transistor (e.g., MBCFET or GAAFET) with a power gate electrode PGE three-dimensionally surrounding a first channel pattern SP1.

[0077] The first lower active region LAR1 can include a first lower source / drain pattern LSD1, a second lower source / drain pattern LSD2, and a first channel pattern SP1 connecting the first lower source / drain pattern LSD1 to the second lower source / drain pattern LSD2.

[0078] The first channel pattern SP1 can be stacked apart from each other in a third direction D3 perpendicular to the top surface of the substrate 100. The first channel pattern SP1 can include silicon (Si), germanium (Ge), or silicon germanium (SiGe). For example, the first channel pattern SP1 can include crystalline silicon. Each of the first channel patterns SP1 can be a nanosheet.

[0079] The first lower source / drain pattern LSD1 and the second lower source / drain pattern LSD2 can be disposed on the substrate 100. The first lower source / drain pattern LSD1 and the second lower source / drain pattern LSD2 can be spaced apart from each other in a first direction D1 parallel to the top surface of the substrate 100. The first lower source / drain pattern LSD1 and the second lower source / drain pattern LSD2 can be epitaxial patterns formed by a selective epitaxial growth (SEG) process. The first lower source / drain pattern LSD1 and the second lower source / drain pattern LSD2 can include an impurity having a first conductivity type. For example, the first lower source / drain pattern LSD1 and the second lower source / drain pattern LSD2 can include a p-type impurity. The first lower source / drain pattern LSD1 and the second lower source / drain pattern LSD2 can include one or more of silicon (Si) and silicon germanium (SiGe).

[0080] The first interlayer dielectric layer 110 can be disposed on the first lower source / drain pattern LSD1 and the second lower source / drain pattern LSD2. The first interlayer dielectric layer 110 can cover the first lower source / drain pattern LSD1 and the second lower source / drain pattern LSD2.

[0081] The first upper active region UAR1 can include a first upper source / drain pattern USD1 and a second upper source / drain pattern USD2. The first upper source / drain pattern USD1 and the second upper source / drain pattern USD2 can be spaced apart from each other in the first direction D1 parallel to the top surface of the substrate 100. The first interlayer dielectric layer 110 can separate the first upper source / drain pattern USD1 and the second upper source / drain pattern USD2 from the first lower source / drain pattern LSD1 and the second lower source / drain pattern LSD2.

[0082] A first upper source / drain pattern USD1 and a second upper source / drain pattern USD2 can be disposed on the first interlayer dielectric layer 110. The first upper source / drain pattern USD1 and the second upper source / drain pattern USD2 can include impurities of a second conductivity type. For example, the first upper source / drain pattern USD1 and the second upper source / drain pattern USD2 can include n-type impurities. The first upper source / drain pattern USD1 and the second upper source / drain pattern USD2 can include one or more of silicon (Si) and silicon germanium (SiGe). A second interlayer dielectric layer 120 can be disposed on the first upper source / drain pattern USD1 and the second upper source / drain pattern USD2. The second interlayer dielectric layer 120 can cover the first upper source / drain pattern USD1 and the second upper source / drain pattern USD2.

[0083] The power gate structure PGS can extend in the second direction D2 and cross the first lower active region LAR1 and the first upper active region UAR1. The power gate structure PGS can include a power gate electrode PGE, an upper division pattern UDB on the power gate electrode PGE, a dummy pattern DSP between the power gate electrode PGE and the upper division pattern UDB, and a gate dielectric layer GI.

[0084] The power gate electrode PGE can extend along the second direction D2 parallel to a top surface of the substrate 100 and can surround the first channel pattern SP1 vertically stacked on the substrate 100. For example, portions of the power gate electrode PGE can be interposed between the first channel pattern SP1. The power gate electrode PGE can include a first inner electrode PO1 interposed between the substrate 100 and the first channel pattern SP1, a second inner electrode PO2 interposed between adjacent first channel patterns SP1, and a third inner electrode PO3 interposed between the first channel pattern SP1 and the dummy pattern DSP.

[0085] The dummy pattern DSP can be vertically spaced apart from and overlapping the first channel pattern SP1. The dummy pattern DSP can include a semiconductor material such as silicon (Si), germanium (Ge), or silicon germanium (SiGe), or a silicon-based dielectric material such as silicon oxide or silicon nitride. In some embodiments, the dummy pattern DSP can include a silicon-based dielectric material.

[0086] The upper separation pattern UDB can extend on the dummy pattern DSP in the second direction D2. The upper separation pattern UDB can overlap the power gate electrode PGE. The upper separation pattern UDB can be disposed between the first upper source / drain pattern USD1 and the second upper source / drain pattern USD2. Opposing sidewalls of the upper separation pattern UDB can be in contact with the first upper source / drain pattern USD1 and the second upper source / drain pattern USD2. The upper separation pattern UDB can include a dielectric material, such as at least one selected from silicon oxide, silicon oxycarbide, silicon nitride, and combinations thereof.

[0087] The gate dielectric layer GI can be between the power gate electrode PGE and the first channel pattern SP1. In addition, a portion of the gate dielectric layer GI can be between the power gate electrode PGE and the dummy pattern DSP. The gate dielectric layer GI can include one or more of a silicon oxide layer, a silicon oxynitride layer, and a high-k dielectric layer. In some embodiments, the gate dielectric layer GI can include a silicon oxide layer directly covering a surface of the first channel pattern SP1 and a high-k dielectric layer on the silicon oxide layer. For example, the gate dielectric layer GI can include multiple layers of a silicon oxide layer and a high-k dielectric layer.

[0088] The high-k dielectric layer can include a high-k dielectric material having a dielectric constant greater than a dielectric constant of a silicon oxide layer. For example, the high-k dielectric material can include at least one selected from hafnium oxide, hafnium silicon oxide, zirconium hafnium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, scandium tantalum

[0089] On a top surface of the substrate 100, the lower separation pattern LDB can be in contact with the first lower source / drain pattern LSD1. The lower separation pattern LDB can be spaced apart from the power gate electrode PGE in the first direction D1 and can be parallel to the power gate electrode PGE in the second direction D2. The lower separation pattern LDB can include a dielectric material, such as at least one selected from silicon oxide, silicon oxycarbide, silicon nitride, and combinations thereof.

[0090] The third channel patterns SP3 can be stacked apart from each other on the lower separation pattern LDB in a third direction D3. The third channel patterns SP3 can include silicon (Si), germanium (Ge), or silicon germanium (SiGe). For example, the third channel patterns SP3 can include crystalline silicon. Each of the third channel patterns SP3 can be a nanosheet.

[0091] Dummy gate electrodes DGE can be disposed on the lower separation pattern LDB. The dummy gate electrodes DGE can surround the third channel pattern SP3 and can overlap the lower separation pattern LDB. A portion of the dummy gate electrodes DGE can be between the dummy pattern DSP and the third channel pattern SP3 and between adjacent third channel patterns SP3. An upper portion of the dummy gate electrodes DGE can be disposed on the uppermost third channel pattern SP3.

[0092] The dummy pattern DSP can be disposed between the lower separation pattern LDB and the dummy gate electrodes DGE.

[0093] Pairs of gate spacers can be disposed on opposite sidewalls of the dummy gate electrodes DGE. The gate spacers can extend along the dummy gate electrodes DGE in the first direction D1. The gate spacers can include at least one selected from SiCN, SiCON, and SiN. Optionally, the gate spacers can include a multilayer formed from at least two selected from SiCN, SiCON, and SiN.

[0094] A gate cover pattern GP can be disposed on a top surface of the dummy gate electrodes DGE. The gate cover pattern GP can extend along the dummy gate electrodes DGE in the first direction D1. For example, the gate cover pattern GP can include at least one selected from SiON, SiCN, SiCON, and SiN.

[0095] On a top surface of the substrate 100, a through separation pattern TDB can be in contact with the second lower source / drain pattern LSD2. The through separation pattern TDB can be spaced apart from the power gate electrode PGE in the first direction D1 and can be parallel to the power gate electrode PGE in the second direction D2. The through separation pattern TDB can extend in the third direction D3 and can be in contact with the second upper source / drain pattern USD2. The through separation pattern TDB can include a dielectric material such as at least one selected from silicon oxide, silicon carbon oxide, silicon nitride, and combinations thereof.

[0096] A third interlayer dielectric layer 130 can be disposed on the second interlayer dielectric layer 120. The through-active contact TAC can vertically penetrate the third interlayer dielectric layer 130, the second interlayer dielectric layer 120, the second upper source / drain pattern USD2, and the first interlayer dielectric layer 110, and can be connected to the second lower source / drain pattern LSD2. The through-active contact TAC can electrically connect the second upper source / drain pattern USD2 to the second lower source / drain pattern LSD2. The second upper source / drain pattern USD2 can be partially in direct contact with a sidewall of the through-active contact TAC. The through-active contact TAC can be disposed between the upper division pattern UDB and the through-division pattern TDB. The through-active contact TAC can include a metal selected from copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo).

[0097] A device isolation layer ST can be disposed in the substrate 100. The device isolation layer ST can define the lower active areas LAR1, LAR2, and the upper active areas UAR1 and UAR2. For example, the device isolation layer ST can include a silicon-based dielectric material (e.g., silicon oxide, silicon oxynitride, or silicon nitride).

[0098] The first and second lower active contacts LAC1 and LAC2 can penetrate the substrate 100 to be coupled to the first and second lower source / drain patterns LSD1 and LSD2, respectively. The first and second lower active contacts LAC1 and LAC2 can be buried in the substrate 100. The first and second lower active contacts LAC1 and LAC2 can include a metal selected from copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo).

[0099] The lower metal wiring layer LMS can be disposed on the bottom surface of the substrate 100, and can include the first and second lower power lines VSS and VDD, the first global power line VDDG, and the first local power line VDD1.

[0100] The first and second lower power lines VSS and VDD can extend in parallel along the first direction D1. The first global power line VDDG and the first local power line VDD1 can extend along the first direction D1. When viewed in a top-down view, the first global power line VDDG and the first local power line VDD1 can be spaced apart from each other in the first direction D1 across the power gate structure PGS.

[0101] The lower metal wiring layer LMS can further include the first and second lower interlayer dielectric layers 210 and 220 stacked on the bottom surface of the substrate 100, the first and second lower connection patterns LCM1 and LCM2.

[0102] The first lower connection pattern LCM1 and the second lower connection pattern LCM2 can be disposed in the first lower interlayer dielectric layer 210 and can have a bar shape with a long axis in the second direction D2.

[0103] The first lower connection pattern LCM1 can be coupled to the first lower active contact LAC1, and the second lower connection pattern LCM2 can be coupled to the second lower active contact LAC2.

[0104] The first global power line VDDG can extend in the first direction D1 on the second lower interlayer dielectric layer 220 and can be connected to the first lower connection pattern LCM1 through a lower via LV.

[0105] On the second lower interlayer dielectric layer 220, the first local power line VDD1 can be disposed to be spaced apart from the first global power line VDDG in the first direction D1 and can extend in the first direction D1. The first local power line VDD1 can be connected to the second lower connection pattern LCM2 through a lower via LV.

[0106] The upper wiring layer UMS can be disposed on the second interlayer dielectric layer 120, the power gate structure PGS, and the gate structure GS and can include an upper wiring line UM and a second local power line VDD2. The upper wiring layer UMS can include a third interlayer dielectric layer 130, a fourth interlayer dielectric layer 140, and a fifth interlayer dielectric layer 150, an upper connection pattern UCM, an upper via UV, an upper wiring line UM, and a second local power line VDD2, which are sequentially stacked.

[0107] The upper connection pattern UCM can be disposed in the fourth interlayer dielectric layer 140 and can be connected to the through active contact TAC. The upper connection pattern UCM can have a bar shape with a long axis in the second direction D2.

[0108] The upper via UV can be disposed in the fifth interlayer dielectric layer 150 and can be coupled to the upper connection pattern UCM.

[0109] The upper wiring line UM can be disposed on the fifth interlayer dielectric layer 150 at a regular pitch. When viewed in a top view, the upper wiring line UM can be disposed between the first lower power line VSS and the second lower power line VDD.

[0110] The second local power line VDD2 can have the same line width as the upper wiring line UM, and can be spaced apart from the upper wiring line UM in the first direction D1 and the second direction D2. The second local power line VDD2 can be electrically connected to the upper connection pattern UCM through the upper via UV. For example, the second local power line VDD2 can be electrically connected to the second lower source / drain pattern LSD2 of the power gating unit PGC through the upper via UV, the upper connection pattern UCM, and the through active contact TAC.

[0111] The logic unit LC can be disposed to be spaced apart from the power gating unit PGC in the second direction D2.

[0112] The cut pattern CT can separate the power gating unit PGC and the logic unit LC adjacent in the second direction D2. Adjacent cut patterns CT can have a bar shape or a linear shape extending in the first direction D1.

[0113] The logic unit LC can include a second lower active region LAR2 on the substrate 100, a second upper active region UAR2 stacked on the second lower active region LAR2, and a gate electrode GE.

[0114] The logic unit LC can include a three-dimensional field effect transistor (e.g., MBCFET or GAAFET) in which the gate electrode GE three-dimensionally surrounds the third channel pattern SP3 and the fourth channel pattern SP4.

[0115] For example, the second lower active region LAR2 can be a PMOSFET region, and the second upper active region UAR2 can be an NMOSFET region. Alternatively, the second lower active region LAR2 can be an NMOSFET region, and the second upper active region UAR2 can be a PMOSFET region. Each of the second lower active region LAR2 and the second upper active region UAR2 can have a bar shape or a linear shape extending in the first direction D1.

[0116] The second lower active region LAR2 can include third lower source / drain patterns LSD3 spaced apart from each other in the first direction D1, and can further include third channel patterns SP3 connecting the third lower source / drain patterns LSD3 to each other.

[0117] The second upper active region UAR2 can include third upper source / drain patterns USD3 spaced apart from each other in the first direction D1, and can further include fourth channel patterns SP4 connecting the third upper source / drain patterns USD3 to each other. A dummy pattern DSP can be disposed between the lowermost fourth channel pattern SP4 and the uppermost third channel pattern SP3.

[0118] The gate electrode GE can extend in the second direction D2 while surrounding the third channel pattern SP3 and the fourth channel pattern SP4.

[0119] The gate electrode GE can include a first inner electrode PO1 between the third channel pattern SP3 and the substrate 100, a second inner electrode PO2 between the third channel patterns SP3, a third inner electrode PO3 between the third channel pattern SP3 and the dummy pattern DSP, a fourth inner electrode PO4 between the dummy pattern DSP and the fourth channel pattern SP4, a fifth inner electrode PO5 between the fourth channel patterns SP4, and an outer electrode PO6 on the fourth channel pattern SP4.

[0120] The gate electrode GE can extend in the second direction D2 while surrounding the third channel pattern SP3 and the fourth channel pattern SP4.

[0121] Figure 6 A block diagram illustrating an example of a semiconductor device including a power gating circuit is shown.

[0122] Reference Figure 6 The semiconductor device can include a power gating circuit 10 and a logic circuit 20. Unlike the embodiments discussed with reference to Figure 3 the power gating circuit 10 shown can include an NMOS power gate transistor PG connected between a second global power line VSSG and a second power line VSS. Figure 6

[0123] When the logic circuit 20 is in an active state, the power gating circuit 10 can be turned on to provide a power supply voltage to the logic circuit 20. In response to a control signal applied to a power gate electrode PGE, the power gating circuit 10 can selectively connect the second global power line VSSG to the second power line VSS to adjust a ground voltage provided to the logic circuit 20 and adjust a power mode of the logic circuit 20.

[0124] In the power-on mode, the power gating circuit 10 can connect the second global power line VSSG to the second power line VSS, thereby providing a ground voltage to the logic circuit 20.

[0125] In the power-off mode, the power gating circuit 10 can disconnect the second global power line VSSG from the second power line VSS, thereby electrically floating the second power line VSS.

[0126] The power gating circuit 10 can further include a control circuit that provides the control signal applied to the power gate electrode PGE to the power gate transistor PG. ​

[0127] The logic circuit 20 can include any circuit connected to the second power line VSS. For example, the logic circuit 20 can be implemented as an inverter, a NAND gate, an AND gate, a NOR gate, an OR gate, an XOR gate, an XNOR gate, a multiplexer, an adder, a latch, or a flip-flop.

[0128] In some embodiments, the power gating circuit 10 is shown to be formed of PMOS or NMOS transistors, in other embodiments, the power gating circuit 10 can include both PMOS power gating transistors and NMOS power gating transistors.

[0129] Figure 7A A top view depicting an example of a semiconductor device including a power gating cell is shown. Figure 7B A bottom view depicting an example of a semiconductor device including a power gating cell is shown. Figure 8A 、 Figure 8B 、 Figure 8C 、 Figure 8D and Figure 8E An example cross-sectional view taken along line A-A’, line B-B’, line C-C’, line D-D’, and line E-E’ of Figure 7A and Figure 7B will be assigned the same reference numerals, and a detailed description of its related technical features will be omitted. Figure 4A 、 Figure 4B and Figures 5A-5E will be assigned the same reference numerals, and a detailed description of its related technical features will be omitted.

[0130] Referring to Figure 7A 、 Figure 7B and Figures 8A-8E , a power gating cell PGC can be disposed between logic cells LC. The power gating cell PGC can include a first lower active region LAR1 located on the substrate 100, a first upper active region UAR1 stacked on the first lower active region LAR1, and a power gate electrode PGE. For example, the first lower active region LAR1 can be a PMOSFET region, while the first upper active region UAR1 can be an NMOSFET region. According to some embodiments, the power gating cell PGC can be disposed on the first upper active region UAR1 and can be formed of an NMOS transistor.

[0131] The first lower active region LAR1 can include a first lower source / drain pattern LSD1, a second lower source / drain pattern LSD2, and a lower division pattern LDB located between the first lower source / drain pattern LSD1 and the second lower source / drain pattern LSD2.

[0132] The first lower source / drain pattern LSD1 and the second lower source / drain pattern LSD2 can be spaced apart from each other in a first direction D1 parallel to the top surface of the substrate 100, and can be in contact with sidewalls of the lower separation pattern LDB.

[0133] The first upper active region UAR1 can include a first upper source / drain pattern USD1, a second upper source / drain pattern USD2, a second channel pattern SP2 connecting the first upper source / drain pattern USD1 and the second upper source / drain pattern USD2 to each other, and a power gate electrode PGE.

[0134] The second channel pattern SP2 can be stacked apart from each other in a third direction D3 on the dummy pattern DSP. The second channel pattern SP2 can include silicon (Si), germanium (Ge), or silicon germanium (SiGe). For example, the second channel pattern SP2 can include crystalline silicon. Each of the second channel patterns SP2 can be a nanosheet.

[0135] The first interlayer dielectric layer 110 can separate the first upper source / drain pattern USD1 and the second upper source / drain pattern USD2 from the first lower source / drain pattern LSD1 and the second lower source / drain pattern LSD2.

[0136] For example, the first lower source / drain pattern LSD1 and the second lower source / drain pattern LSD2 can include p-type impurities. The first upper source / drain pattern USD1 and the second upper source / drain pattern USD2 can include n-type impurities.

[0137] The power gate structure PGS can extend in a second direction D2 and cross the first lower active region LAR1 and the first upper active region UAR1. The power gate structure PGS can include the power gate electrode PGE on the lower separation pattern LDB.

[0138] The power gate electrode PGE can extend along the second direction D2 parallel to the top surface of the substrate 100, and can surround the second channel patterns SP2 vertically stacked on the substrate 100. For example, the power gate electrode PGE can include an inner electrode interposed between the second channel patterns SP2 and an outer electrode on the uppermost second channel pattern SP2. A pair of gate spacers can be disposed on opposite sidewalls of the power gate electrode PGE. The gate spacers can extend in the first direction D1 along the dummy gate electrode DGE.

[0139] A gate dielectric layer GI can be interposed between the power gate electrode PGE and the second channel patterns SP2. The gate dielectric layer GI can include one or more of a silicon oxide layer, a silicon oxynitride layer, and a high-k dielectric layer.

[0140] A lower separation pattern LDB can extend on the substrate 100 in the second direction D2. The lower separation pattern LDB can overlap the power grid electrode PGE. The lower separation pattern LDB can be disposed between the first lower source / drain pattern LSD1 and the second lower source / drain pattern LSD2. The lower separation pattern LDB can include a dielectric material, such as at least one selected from silicon oxide, silicon oxycarbide, silicon nitride, and combinations thereof.

[0141] A dummy pattern DSP can be disposed between the lower separation pattern LDB and the power grid electrode PGE.

[0142] On the substrate 100, a dummy gate electrode DGE can be disposed spaced apart from the lower separation pattern LDB in the first direction D1.

[0143] The third channel pattern SP3 can be vertically stacked on the substrate 100, and the dummy gate electrode DGE can surround the third channel pattern SP3. A portion of the dummy gate electrode DGE can be between the substrate 100 and the third channel pattern SP3 and between adjacent third channel patterns SP3.

[0144] The third channel pattern SP3 can include silicon (Si), germanium (Ge), or silicon germanium (SiGe). For example, the third channel pattern SP3 can include crystalline silicon. Each third channel pattern SP3 can be a nanosheet.

[0145] An upper separation pattern UDB can be spaced apart from the power grid electrode PGE in the first direction D1, thereby being disposed on the dummy pattern DSP. The upper separation pattern UDB can extend in the second direction D2 parallel to the power grid electrode PGE. The upper separation pattern UDB can overlap the dummy gate electrode DGE. The upper separation pattern UDB can be in contact with the first upper source / drain pattern USD1. The upper separation pattern UDB can include a dielectric material, such as at least one selected from silicon oxide, silicon oxycarbide, silicon nitride, and combinations thereof.

[0146] The dummy pattern DSP can be disposed between the upper separation pattern UDB and the dummy gate electrode DGE.

[0147] The first upper active contact UAC1 can penetrate the second interlayer dielectric layer 120 and the third interlayer dielectric layer 130 to be coupled to the first upper source / drain pattern USD1, and the second upper active contact UAC2 can penetrate the second interlayer dielectric layer 120 and the third interlayer dielectric layer 130 to be coupled to the second upper source / drain pattern USD2.

[0148] The upper wiring layer UMS can be disposed on the second interlayer dielectric layer 120, the power gate structure PGS, and the gate structure GS, and can include a second global power line VSSG and a first local power line VSS1. The second global power line VSSG and the first local power line VSS1 can extend along the first direction D1 and can be spaced apart from each other in the first direction D1.

[0149] The second global power line VSSG can be connected to the first upper active contact UAC1 through an upper via UV and a first upper connection pattern UCM1. The first local power line VSS1 can be connected to the second upper active contact UAC2 through an upper via UV and a second upper connection pattern UCM2. The first upper connection pattern UCM1 and the second upper connection pattern UCM2 can be disposed in the fourth interlayer dielectric layer 140 and can have a bar shape with a long axis in the second direction D2.

[0150] The through active contact TAC can penetrate the substrate 100, the second lower source / drain pattern LSD2, and the first interlayer dielectric layer 110, thereby being coupled to the second upper source / drain pattern USD2. The through active contact TAC can electrically connect the second upper source / drain pattern USD2 to the second lower source / drain pattern LSD2.

[0151] The second lower source / drain pattern LSD2 can be partially in direct contact with a sidewall of the through active contact TAC. The through active contact TAC can be disposed between the lower division pattern LDB and the through division pattern TDB. The through active contact TAC can include a metal selected from copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo).

[0152] The lower wiring layer LMS can include a lower wiring line LM and a second local power line VSS2. The lower wiring layer LMS can include the first lower interlayer dielectric layer 210 and the second lower interlayer dielectric layer 220 stacked on the bottom surface of the substrate 100, the lower wiring line LM, and the second local power line VSS2.

[0153] The lower wiring line LM and the second local power line VSS2 can extend in the first direction D1 on the second lower interlayer dielectric layer 220.

[0154] The lower wiring line LM and the second local power line VSS2 can be disposed at a regular pitch along the second direction D2. The second local power line VSS2 can be connected to the through active contact TAC through a lower via LV and a lower connection pattern LCM.

[0155] Some embodiments of the present disclosure will be described below with reference to the accompanying drawings. As described above with reference to FIGS. 1 to 3, the present disclosure can be applied to a semiconductor device including a substrate 100, a gate structure GS, a power gate structure PGS, an upper wiring layer UMS, and a lower wiring layer LMS. Figure 4A 、 Figure 4B and Figures 5A-5EComponents that are repeated in the discussion will be assigned the same reference numerals, and detailed descriptions of their related technical features will be omitted.

[0156] Figure 9A A top view depicting an example of a semiconductor device including a power gating unit is shown. Figure 9B A bottom view depicting an example of a semiconductor device including a power gating unit is shown. Figure 10A , Figure 10B , Figure 10C , Figure 10D and Figure 10E It shows along Figure 9A and Figure 9B Example cross-sectional views of lines A-A', B-B', C-C', D-D', and E-E'.

[0157] refer to Figure 9A , Figure 9B and Figures 10A-10E The logic unit LC can be set on the power gating unit PGC. For example, the power gating unit PGC and the logic unit LC can overlap each other and can be perpendicularly separated from each other by a dummy pattern DSP.

[0158] On substrate 100, a power gate electrode PGE may be disposed between a first lower separator pattern LDB1 and a second lower separator pattern LDB2. As described above, the power gate electrode PGE may extend along the second direction D2 while surrounding the first channel pattern SP1.

[0159] The first lower source / drain pattern LSD1 can be disposed between the first lower separator pattern LDB1 and the power gate electrode PGE, and the second lower source / drain pattern LSD2 can be disposed between the second lower separator pattern LDB2 and the power gate electrode PGE. As described above, the first lower source / drain pattern LSD1 and the second lower source / drain pattern LSD2 can be connected to the first channel pattern SP1.

[0160] The second channel pattern SP2 can be vertically stacked on the first channel pattern SP1. The second channel pattern SP2 can overlap with the first channel pattern SP1. In addition, the second channel pattern SP2 can be vertically stacked on the first lower separator pattern LDB1 and the second lower separator pattern LDB2.

[0161] The upper gate electrodes UGE can be spaced apart from each other along a first direction D1 on the first active region UAR1. Each upper gate electrode UGE can extend along a second direction D2 while surrounding the second channel pattern SP2.

[0162] A portion of the upper gate electrode UGE can overlap the power gate electrode PGE and can be electrically separated from each other by a dummy pattern DSP. A portion of the upper gate electrode UGE can overlap the first lower division pattern LDB1 and the second lower division pattern LDB2.

[0163] The first lower active contact LAC1 and the second lower active contact LAC2 can penetrate the substrate 100 to be coupled to the first lower source / drain pattern LSD1 and the second lower source / drain pattern LSD2, respectively. The first lower active contact LAC1 and the second lower active contact LAC2 can be buried in the substrate 100.

[0164] In the first lower interlayer dielectric layer 210, the first lower connection pattern LCM1 can be coupled to the first lower active contact LAC1, and in the first lower interlayer dielectric layer 210, the second lower connection pattern LCM2 can be coupled to the second lower active contact LAC2.

[0165] The first global power line VDDG can extend in the first direction D1 on the second lower interlayer dielectric layer 220 and can be connected to the first lower connection pattern LCM1 through a lower via LV.

[0166] On the second lower interlayer dielectric layer 220, the first local power line VDD1 can be disposed to be spaced apart from the first global power line VDDG in the first direction D1 and can extend in the first direction D1. The first local power line VDD1 can be connected to the second lower connection pattern LCM2 through a lower via LV.

[0167] The upper active contact UAC can be coupled to the first upper source / drain pattern USD1 and the second upper source / drain pattern USD2, respectively. The upper active contact UAC can be electrically connected to an upper wiring line UM disposed on an upper wiring layer UMS.

[0168] Figure 11 A bottom view illustrating an example of a semiconductor device including a power gating unit is shown. Figure 12 An example cross-sectional view taken along the line E-E’ of Figure 11

[0169] Referring to Figure 11 and Figure 12 The logic unit LC can be disposed adjacent to the power gating unit PGC in the second direction D2.

[0170] On the substrate 100, the second lower connection pattern LCM2 can extend in the second direction D2 and cross the first lower active region LAR1 and the second lower active region LAR2.

[0171] ​The second lower connection pattern LCM2 can be electrically connected to the second lower source / drain pattern LSD2 of the logic cell LC and the second lower source / drain pattern LSD2 of the power gating cell PGC through the second lower active contact LAC2. For example, the logic cell LC can be provided with a power supply voltage from the power gating cell PGC adjacent thereto in the second direction D2.

[0172] Figure 13 A top view illustrating an example of a semiconductor device including a power gating cell is shown. Figure 14 An example cross-sectional view taken along line E-E’ of Figure 13

[0173] Referring to Figure 13 and Figure 14 , the semiconductor device can include a lower metal layer LMS including lower metal lines, an upper metal layer UMS including upper metal lines, and a device layer DS disposed between the lower metal layer LMS and the upper metal layer UMS.

[0174] The upper metal layer UMS can be disposed on the second interlayer dielectric layer 120, the power gate structure PGS, and the gate structure GS, and can include upper metal lines UM and a second local power line VDD2.

[0175] The upper metal lines UM can be disposed on the fifth interlayer dielectric layer 150 at a regular pitch. When viewed in a top view, the upper metal lines UM can be disposed between the first lower power line VSS and the second lower power line VDD.

[0176] The second local power line VDD2 can have a line width greater than a line width of the upper metal lines UM, and can be spaced apart from the upper metal lines UM in the first direction D1 and the second direction D2. Since the line width of the second local power line VDD2 is greater than the line width of the upper metal lines UM, transmission delay of a power supply voltage can be reduced.

[0177] The second local power line VDD2 can be electrically connected to the upper connection pattern UCM through the upper via UV. For example, the second local power line VDD2 can be electrically connected to the second lower source / drain pattern LSD2 through the upper via UV, the upper connection pattern UCM, and the through active contact TAC.

[0178] Figure 15 A top view illustrating an example of a semiconductor device including a power gating cell is shown. Figure 16 An example cross-sectional view taken along line B-B’ of Figure 15 Figure 17 An example cross-sectional view taken along line E-E’ of Figure 15

[0179] Referring to​​​Figure 15 、 Figure 16 and Figure 17 The semiconductor device can include a lower wiring layer LMS including lower wiring lines, an upper wiring layer UMS including upper wiring lines, and a device layer DS disposed between the lower wiring layer LMS and the upper wiring layer UMS.

[0180] The lower wiring layer LMS can include a first lower power line VSS, a second lower power line VDD, a first global power line VDDG, and a first local power line VDD1. The upper wiring layer UMS can include upper wiring lines UMs and a second local power line VDD2. As described above, the device layer DS can include logic cells LC and power gating cells PGC.

[0181] On the upper wiring layer UMS, the second local power line VDD2 can have a line width that is the same as a line width of the upper wiring layer UMs, and can continuously extend along the first direction D1. The upper wiring lines UMs can be spaced apart from each other in the first direction D1, and can be arranged along the second direction D2 at a regular pitch. The second local power line VDD2 can be connected to the through- active contacts TACs through upper vias UV and upper connection patterns UCM.

[0182] Figure 18A A top view illustrating an example of a semiconductor device including power gating cells is shown. Figure 18B A bottom view illustrating an example of a semiconductor device including power gating cells is shown. Figure 19A An example cross-sectional view taken along line A-A’ and line B-B’ of Figure 19B An example cross-sectional view taken along line A-A’ and line B-B’ of Figure 18A An example cross-sectional view taken along line A-A’ and line B-B’ of Figure 18B An example cross-sectional view taken along line A-A’ and line B-B’ of

[0183] Referring to Figure 18A 、 Figure 18B 、 Figure 19A and Figure 19B The semiconductor device can include a lower wiring layer LMS including lower wiring lines, an upper wiring layer UMS including upper wiring lines, and a device layer DS disposed between the lower wiring layer LMS and the upper wiring layer UMS, when viewed in a direction (or, a third direction D3) perpendicular to a top surface of the substrate 100.

[0184] According to some embodiments, the semiconductor device can include a first region R1, a second region R2, and a third region R3, when viewed in the first direction D1 parallel to the top surface of the substrate 100.

[0185] On the first region R1, the power gating unit PGC can be disposed between the logic units LC adjacent to each other in the second direction D2. On the second region R2, the logic units LC can be disposed along the first direction D1 and the second direction D2. On the third region R3, the first local power line VDD1 can be disposed to be connected to the power gating unit PGC on the first region R1.

[0186] According to some embodiments, the lower wiring layer LMS can include: the global power line VDDG on the first region R1, the lower wiring line LM on the second region R2, and the first local power line VDD1 on the third region R3. The global power line VDDG, the lower wiring line LM, and the first local power line VDD1 can extend along the first direction D1 and can be spaced apart from each other in the first direction D1.

[0187] The upper wiring layer UMS can include the upper wiring line UM and the second local power line VDD2. The upper wiring line UM and the second local power line VDD2 can extend along the first direction D1. The second local power line VDD2 can extend continuously from the first region R1 to the third region R3 along the first direction D1.

[0188] On the first region R1, the device layer DS can include the logic unit LC and the power gating unit PGC. The power gating unit PGC can include: a first lower active region LAR1 on the substrate 100, a first upper active region UAR1 stacked on the first lower active region LAR1, and a power gate electrode PGE. The power gating unit PGC can be disposed on the first lower active region LAR1 and can be formed of a PMOS transistor.

[0189] The first lower active region LAR1 can include: a first lower source / drain pattern LSD1, a second lower source / drain pattern LSD2, and a first channel pattern SP1 connecting the first lower source / drain pattern LSD1 to the second lower source / drain pattern LSD2. The power gate electrode PGE can extend along the first direction D1 parallel to the top surface of the substrate 100 and can surround the first channel pattern SP1.

[0190] The first upper active region UAR1 can include a first upper source / drain pattern USD1 and a second upper source / drain pattern USD2. An upper division pattern UDB can be disposed between the first upper source / drain pattern USD1 and the second upper source / drain pattern USD2.

[0191] The first lower active contact LAC1 can penetrate the substrate 100 to couple to a first lower source / drain pattern LSD1 of the power-gating cell PGC. The first lower active contact LAC1 can be connected to a global power line VDDG through a first lower connection pattern LCM1 and a lower via LV.

[0192] The second lower source / drain pattern LSD2 of the power-gating cell PGC can be electrically connected to a second local power line VDD2 of the upper metal layer UMS through the first through active contact TAC1, a first upper connection pattern UCM1, and an upper via UV.

[0193] The second local power line VDD2 on the fifth interlayer dielectric layer 150 can extend continuously along the first direction D1 through a plurality of logic cells LC disposed on the second region R2 when viewed in a top view. The second local power line VDD2 can be coupled to the second through active contact TAC2 through a second upper connection pattern UCM2 and an upper via UV located on the third region R3.

[0194] On the second region R2, a plurality of gate structures GS can be arranged along the first direction D1 at a regular pitch.

[0195] Each gate structure GS can include a gate electrode GE surrounding a lower channel pattern LSP and an upper channel pattern USP, a gate dielectric layer GI, a gate spacer, and a gate cap pattern GP. The lower channel pattern LSP and the upper channel pattern USP can be stacked apart from each other in a third direction D3. Each gate structure GS can be disposed between upper source / drain patterns USD and between lower source / drain patterns LSD.

[0196] On the second region R2, a lower metal line LM can be disposed on the second lower interlayer dielectric layer 220. On the third region R3, a first local power line VDD1 can be disposed on the second lower interlayer dielectric layer 220.

[0197] On the third region R3, the second through active contact TAC2 can electrically connect an upper source / drain pattern USDa to a lower source / drain pattern LSDa.

[0198] On the third region R3, a second lower active contact LAC2 can penetrate the substrate 100 to couple to the lower source / drain pattern LSDa. The second lower active contact LAC2 can be connected to the first local power line VDD1 through a second lower connection pattern LCM2 and a lower via LV.

[0199] On the third region R3, the upper source / drain pattern USDa and the lower source / drain pattern LSDa can be disposed between through-deck patterns TDB along the first direction D1.

[0200] According to some implementations, power gating units can be set in a structure where PMOS transistors and NMOS transistors are stacked vertically, so that semiconductor devices can reduce power consumption and improve performance.

[0201] By utilizing through-active contacts, local power lines can be placed on the top and bottom of semiconductor devices, increasing the flexibility of wiring for connecting logic units and power gating units.

[0202] While this specification contains numerous specific implementation details, these should not be construed as limiting the scope of any invention or the scope that may be claimed, but rather as descriptions of features characteristic of particular embodiments of a particular invention. Certain features described in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately in multiple embodiments or in any suitable sub-combination. Furthermore, although features may be described above as functioning in certain combinations, in some cases, one or more features from a combination may be removed from that combination, and the combination may refer to a sub-combination or a variation of a sub-combination.

[0203] Although this disclosure has been described in conjunction with some embodiments shown in the accompanying drawings, those skilled in the art will understand that various changes and modifications can be made without departing from the technical spirit and essential characteristics of this disclosure. It will be apparent to those skilled in the art that various substitutions, modifications, and alterations can be made without departing from the scope and spirit of this disclosure.

Claims

1. A semiconductor device comprising: a lower wiring layer including a plurality of lower wiring lines; an upper wiring layer including a plurality of upper wiring lines; and a power gate cell located between the lower wiring layer and the upper wiring layer, wherein the power gate cell includes: a first active region on a substrate, wherein the first active region includes a first lower source / drain pattern, a second lower source / drain pattern, and a first channel pattern connecting the first lower source / drain pattern and the second lower source / drain pattern to each other; a second active region on the first active region, wherein the second active region includes a first upper source / drain pattern and a second upper source / drain pattern; and a power gate electrode surrounding the first channel pattern and extending in a first direction parallel to a top surface of the substrate, wherein the lower wiring layer includes: a global power line connected to the first lower source / drain pattern; and a local power line connected to the second lower source / drain pattern.

2. The semiconductor device of claim 1, wherein the global power line and the local power line extend in a second direction parallel to the top surface of the substrate and intersecting the first direction, and in a top view, the global power line is spaced apart from the local power line in the second direction, and the power gate electrode is disposed between the global power line and the local power line.

3. The semiconductor device of claim 1, further comprising a through active contact connecting the second lower source / drain pattern and the second upper source / drain pattern. the upper wiring layer includes an upper local power line connected to the through active contact.

4. The semiconductor device of claim 3, wherein, a line width of the upper local power line is greater than a line width of the upper wiring lines.

5. The semiconductor device of claim 4, wherein, 6. The semiconductor device of claim 1, further comprising: a first separation pattern extending in the first direction parallel to the power gate electrode and contacting the first lower source / drain pattern; and a second separation pattern extending in the first direction parallel to the power gate electrode and contacting the second lower source / drain pattern. the second separation pattern extends perpendicularly and contacts the second upper source / drain pattern. the second active region includes a third separation pattern between the first upper source / drain pattern and the second upper source / drain pattern, and 7. The semiconductor device of claim 6, wherein, wherein the third separation pattern overlaps the power gate electrode.

8. The semiconductor device of claim 7, wherein, 9. The semiconductor device of claim 8, further comprising a through active contact connecting the second lower source / drain pattern and the second upper source / drain pattern, and the through active contact is located between the second separation pattern and the third separation pattern. the first separation pattern, the second separation pattern, and the third separation pattern include a dielectric material. wherein, 11. The semiconductor device of claim 1, further comprising:

10. The semiconductor device of claim 9, wherein, ​ ​ an upper gate electrode extending in the first direction and surrounding a second channel pattern connecting the first and second upper source / drain patterns to each other over the power gate electrode; and a dummy pattern between the power gate electrode and the upper gate electrode.

12. The semiconductor device of claim 1, further comprising: a logic cell adjacent to the power gate cell in the first direction, wherein the logic cell includes: a third channel pattern on the substrate; a fourth channel pattern on the third channel pattern; a plurality of third lower source / drain patterns on opposite sides of the third channel pattern; a plurality of fourth upper source / drain patterns on opposite sides of the fourth channel pattern; and a gate electrode extending in the first direction and surrounding the third and fourth channel patterns.

13. The semiconductor device of claim 12, wherein, the local power line is connected to one of the plurality of third lower source / drain patterns.

14. A semiconductor device, comprising: a first active region on a substrate, wherein the first active region includes a first lower source / drain pattern, a second lower source / drain pattern, and a first channel pattern connecting the first and second lower source / drain patterns to each other; a second active region on the first active region, wherein the second active region includes a first upper source / drain pattern and a second upper source / drain pattern; a power gate electrode extending in a first direction parallel to a top surface of the substrate and surrounding the first channel pattern; a global power line on a bottom surface of the substrate and connected to the first lower source / drain pattern; a first local power line on the bottom surface of the substrate and connected to the second lower source / drain pattern; a through active contact connecting the second lower source / drain pattern and the second upper source / drain pattern; and a second local power line on the top surface of the substrate and connected to the through active contact.

15. The semiconductor device of claim 14, further comprising: a first separation pattern extending in the first direction parallel to the power gate electrode and contacting the first lower source / drain pattern; a second separation pattern extending in the first direction parallel to the power gate electrode and contacting the second lower source / drain pattern and the second upper source / drain pattern; and a third separation pattern between the first and second upper source / drain patterns, the third separation pattern overlapping the power gate electrode. the through active contact is between the second and third separation patterns.

16. The semiconductor device of claim 15, wherein, ​ 17. The semiconductor device of claim 14, wherein, In a top view, the global power line is spaced apart from the first local power line, and the power supply gate electrode is disposed between the global power line and the first local power line.

18. The semiconductor device of claim 17, further comprising a plurality of gate electrodes between the global power line and the first local power line. wherein, The second local power line extends in a second direction that intersects the first direction, and crosses the plurality of gate electrodes.

19. The semiconductor device of claim 14, further comprising: a first lower active contact between the global power line and the first lower source / drain pattern; and a second lower active contact between the first local power line and the second lower source / drain pattern.

20. A semiconductor device, comprising: a first active region on a substrate, wherein the first active region includes a first lower source / drain pattern, a second lower source / drain pattern, and a first channel pattern connecting the first lower source / drain pattern and the second lower source / drain pattern to each other; a second active region on the first active region, wherein the second active region includes a first upper source / drain pattern and a second upper source / drain pattern; a power supply gate electrode extending in a first direction parallel to a top surface of the substrate, and surrounding the first channel pattern; a first separation pattern spaced apart from the power supply gate electrode in a second direction, and contacting the first lower source / drain pattern; a second separation pattern spaced apart from the power supply gate electrode in the second direction, and contacting the second lower source / drain pattern and the second upper source / drain pattern; a third separation pattern between the first upper source / drain pattern and the second upper source / drain pattern, and overlapping the power supply gate electrode; a dummy gate electrode extending in the first direction, and surrounding a second channel pattern on the first separation pattern; a global power line on a bottom surface of the substrate and connected to the first lower source / drain pattern; a first local power line on the bottom surface of the substrate and connected to the second lower source / drain pattern; a first lower active contact between the global power line and the first lower source / drain pattern; a second lower active contact between the first local power line and the second lower source / drain pattern; a through active contact connecting the second lower source / drain pattern and the second upper source / drain pattern; and a second local power line on the top surface of the substrate and connected to the through active contact.

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