Extended double-side asymmetric phase shift modulation method of dual active bridge converter

Abstract

The invention discloses an extended double-side asymmetric phase shift modulation method for a dual-active bridge converter, and belongs to the technical field of isolated high-frequency power conversion in a power electronic technology. According to the symmetric phase shift modulation method, under the condition that the voltage conversion ratio is not matched, the zero voltage switching range of a switching tube is small, the light load efficiency is low, and variable abrupt change can occur during mode switching to cause the uncontrollable oscillation problem of inductive current. The invention provides an extended double-side asymmetric phase shift modulation method for a dual-active bridge converter in a wide voltage range. A multi-objective optimization scheme is established based on the provided modulation method, and an approximation method is provided to solve a full power range analytical solution. A smooth switching method between modes is realized, and uncontrollable oscillation of inductive current can be effectively avoided. And the conversion efficiency in a full-power range is improved.

Description

Technical Field

[0001] This invention belongs to the field of isolated high-frequency power conversion technology in power electronics, specifically relating to an extended dual-sided asymmetric phase-shift modulation method for dual active bridge converters. Background Technology

[0002] DC microgrids consist of distributed generation, loads, energy storage units, and grid-connected units. In recent years, they have received increasing attention due to their high energy efficiency, high system reliability, and high power quality. Isolated DC / DC converters serve as a crucial power interface between distributed energy storage units and the DC bus. When distributed generation (photovoltaics, wind turbines) outputs power, the energy transfer to the load side or the charging and discharging of distributed energy storage units (batteries, supercapacitors) needs to be managed through the isolated DC / DC converter. Therefore, isolated DC / DC converters play a vital role. Furthermore, dual active bridge (DAB) converters are widely used in DC microgrids due to their numerous advantages, including electrical isolation, zero-voltage switching, bidirectional power flow, wide voltage ratio range, high efficiency, and high power density.

[0003] To address the issues of narrow zero-voltage switching (ZVS) range, high return power, and low efficiency in traditional modulation methods when voltage conversion ratio mismatch exists, existing improvement methods can be divided into two aspects. Firstly, improvements are made from a hardware perspective. A DC blocking capacitor is connected in series on the secondary side of the DAB converter, and a hybrid extended phase-shift modulation strategy is used to achieve dual voltage matching points through full-bridge and half-bridge mode switching. However, this method is limited by the selection of the DC blocking capacitor capacity, leading to increased size and cost of the DAB converter (Xu Guo, Li Liting, Chen Xiaoying, Su Mei, Sun Yao, Wang Hui, Han Hua, Liu Yonglu, Dan Hanbing, Xiong Wenjing, Liu Zhangjie. Soft-switching control method for full load range of dual active bridge converters [P]. Hunan Province: CN114142732A, 2024-10-08). Secondly, improvements are made from a software perspective at the phase-shift level. (Luo Quanming, Li Jia, Mou Di. A Comprehensive Optimization Modulation Method for DAB Converters [P]. Guangdong Province: CN112953245A, 2023-09-15) This paper uses a time-domain analysis method to optimize the minimum inductor current peak. By modeling the switching process of the switching transistors in detail, the ZVS current value required for the switching process is obtained. The dead time is dynamically adjusted by utilizing the voltage conversion ratio and output power to ensure the ZVS of the switching transistors and improve the overall efficiency of the DAB converter. However, during the mode switching process, two switching transistors still cannot achieve ZVS, and the smooth switching of modes cannot be guaranteed. Currently, a large number of studies are beginning to consider increasing the control degrees of freedom by changing the duty cycle of the switching transistors to further improve the efficiency of the DAB converter. (Luo Quanming, Mou Di, Li Jia, Sun Pengju, Du Xiong. An Asymmetric Duty Cycle Optimization Modulation Method for Dual Active Bridges [P]. Chongqing: CN112054693B, 2022-03-08) proposes asymmetric duty cycle modulation (ADM). Based on SPS modulation, it changes the duty cycle of the primary and secondary full-bridge switches by 50%, enabling a wider ZVS range with a smaller effective inductor current, thus improving the efficiency of the DAB converter under light load. However, it only considers the buck process and does not discuss the boost process, i.e., the wide voltage range, in detail. Summary of the Invention

[0004] To address the shortcomings of existing technologies, the present invention aims to provide an extended dual-sided asymmetric phase-shift modulation method for dual active bridge converters, solving the problem of uncontrollable oscillations in the inductor current. Using the method described in this invention, the RMS value of the inductor current can be effectively reduced, thereby decreasing the converter's conduction and copper losses and improving the conversion efficiency across the entire power range.

[0005] To achieve the above objectives, the present invention provides an extended dual-sided asymmetric phase-shift modulation method for a dual active bridge converter, comprising the following steps:

[0006] S1. The modes of extended double-sided asymmetric phase-shift modulation are classified and their steady-state characteristics are analyzed.

[0007] S2. Establish a mathematical model of the switching transistor commutation process and derive the accurate current value required for the switching transistor to achieve ZVS.

[0008] S3. For power ranges without analytical solutions, approximate solutions are obtained by adding constraints.

[0009] S4. Unify the current value for ZVS for different switches to achieve smooth switching between modes.

[0010] Further preferred embodiments include deriving the steady-state characteristics of extended bilateral asymmetric phase-shift modulation, including:

[0011] The conduction time of primary-side switches S2 and S4 is defined as d1T. s (The value of d1 ranges from [0, 0.5]), and the conduction time of the secondary-side switches Q2 and Q4 is defined as d3T. s (The value of d3 ranges from [0, 0.5]). Under step-down operation, the shift ratio between the primary-side switching transistors S1 and S4 is defined as d2T. s (The value of d2 ranges from [0,1]). Under boost operation, the shift ratio between the secondary-side switching transistors Q1 and Q4 is defined as d2T. s The shift ratio between the primary-side switch S1 and the secondary-side switch Q1 is defined as... ( The value range is [0, 0.5]. In the time domain analysis, the DAB converter's transmission power P and the effective value of the inductor current I can be obtained using piecewise linearization of the inductor current and the volt-second balance principle of the inductor. rms Taking EDAPSM mode A as an example for derivation, the transmission power is normalized to a per-unit value for ease of expression. I b =v ab T s / 2πL. The normalized transmission power P of the DAB converter in steady state is obtained. n As shown in the formula.

[0012]

[0013] In EDAPSM mode A, the peak-to-peak value of the inductor current I p_p The square of the effective value is shown in the formula.

[0014]

[0015] Further, a mathematical model of the switching transistor's commutation process is established to derive the accurate current value required for the switching transistor to achieve ZVS; including:

[0016] When switching transistors Q1 (Q4) are switched at the commutation point, the following equation holds true.

[0017]

[0018] During the dead time, the junction capacitance C of switching transistors Q1 and Q4 Q1 and C Q4 Discharge begins, and simultaneously, the junction capacitance C of switching transistors Q2 and Q3... Q2 and C Q3 Charging begins. The primary inductance is transferred to the secondary side via a transformer. The junction capacitance and inductance form a resonant network. Therefore, according to the KVL equation and the initial conditions above, the inductor current i during the dead time can be calculated. L (t) and junction capacitance C Q1 voltage u CQ1 (t) can be represented as:

[0019]

[0020] Using the same analysis method, the inductor current i during the dead time can be obtained from switch S3. L (t) and junction capacitance C S3 voltage u CS3 (t) is shown below:

[0021]

[0022] When the direction of the ZVS current value is satisfied, different ZVS current values ​​will also affect the dead time. Taking the commutation process of switch S3 as an example, under ideal conditions, when C S3 When the voltage across the transistor is 0, switching transistor S3 is turned on, thus achieving efficient ZVS. The minimum current value for the switching transistor to achieve ZVS is defined as I. minZVS t3' is the start time of commutation of switch S3, and t3 is the end time of commutation of switch S3. During the commutation process, the junction capacitance C of switch S4... S4 The voltage on it is fully charged from 0V to V. in The junction capacitance C of the switching transistor S3 S3 The voltage on is determined by V in It is completely discharged to 0V. During this time, the junction capacitance C... S3 All the stored energy was transferred to the junction capacitance C. S4 Above, i.e., E t3'_CS3 =E t3_CS4According to the law of conservation of energy, the energy before commutation is the same as the energy after commutation.

[0023]

[0024] At time t3', the inductance L and junction capacitance C S3 The stored energy is:

[0025]

[0026] At time t3, the junction capacitance C S4 The stored energy and the dead time are controlled by the input voltage V in and output voltage V out Energy consumed E c for:

[0027]

[0028] The minimum current value I required for switch S3 to achieve ZVS can be obtained. minZVS As shown in the formula:

[0029]

[0030] Therefore, the ZVS current value of switch S3 at the commutation moment should be greater than the minimum ZVS current value I. minZVS Then the ZVS current value at the commutation moment can be expressed as:

[0031]

[0032] A further preferred approach is to approximate the power range without analytical solutions by adding constraints:

[0033] In EDAPSM mode A, an analytical solution cannot be obtained due to the equality constraints on transmission power, the equality constraints on switches Q2 and Q3, and the inequality constraints on switch S4 implementing ZVS. However, to make the EDAPSM method real-time, this paper proposes an approximate solution method, which adds switch Q1 (Q4) to the original constraints to implement the ZVS inequality constraints.

[0034] Further optimization involves unifying the current values ​​for ZVS across different switches to achieve smooth switching between modes.

[0035] Because the minimum current values ​​required for switches Q2 and Q3 to achieve ZVS differ in the two modes, in practical applications, as power increases, uncontrollable oscillations in the inductor current can occur, leading to system instability. The minimum current values ​​required for switches Q2 and Q3 to achieve ZVS in EDAPSMmode A are shown in the equation.

[0036]

[0037] In EDAPSM mode B, the minimum current required for switches Q2 and Q3 to achieve ZVS is shown in the equation.

[0038]

[0039] I ZVSQ2Q3_B The absolute value is always greater than I. ZVSQ2Q3_A Analysis of Section IIB shows that a larger ZVS current value at commutation time is more conducive to the ZVS of the switching transistors. Therefore, in order to ensure smooth mode switching and ZVS of switching transistors Q2 and Q3 in EDAPSMmode A mode, the ZVS current values ​​of switching transistors Q2 and Q3 at commutation time are set as shown in the equation.

[0040]

[0041] Compared with the prior art, the extended dual-sided asymmetric phase-shift modulation method for dual active bridge converters disclosed in this application has the following advantages:

[0042] 1. The commutation process of the switching transistor is discussed in detail, and the correct ZVS current value is obtained. Based on the proposed modulation method, the ZVS range of the switching transistor is expanded with the minimum peak-to-peak value of the inductor current and the return power is reduced as the optimization objectives, thus forming a multi-objective efficiency optimization method.

[0043] 2. An analytical solution for the full power range was obtained using an approximation method, revealing the essential reason for the sudden change in variables during mode switching and realizing smooth mode switching. This effectively improved the efficiency of the DAB converter over a wide voltage range, especially under light load conditions. Attached Figure Description

[0044] Figure 1 A flowchart illustrating the steps of an extended dual-side asymmetric phase-shift modulation method for a dual active bridge converter;

[0045] Figure 2 DAB converter topology;

[0046] Figure 3 EDAPSM mode classification. (a) EDAPSM mode A. (b) EDAPSM mode B. (c) EDAPSM mode C. (d) EDAPSM mode D;

[0047] Figure 4 The equivalent circuit of the commutation process of switching transistors S3, Q1 (Q4);

[0048] Figure 5Comparison of peak-to-peak currents between approximate and optimized solutions;

[0049] Figure 6 The graphs showing the changes in the optimization variables when M = 0.6 are as follows: (a) Global graph; (b) Zoom-in local graph.

[0050] Figure 7 The graph showing the change of the optimization variables after applying the proposed method when M=0.6;

[0051] Figure 8 Steady-state waveform when M=0.6. (a) EDAPSM mode A. (b) EDAPSM mode A before mode switching. (c) EDAPSM mode B after mode switching. (d) EDAPSM mode B;

[0052] Figure 9 Steady-state waveform when M=1.25. (a) EDAPSM mode C. (b) EDAPSM mode C before mode switching. (c) EDAPSM mode D after mode switching. (d) EDAPSM mode D. Detailed Implementation

[0053] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0054] like Figure 1 As shown, the extended dual-sided asymmetric phase-shift modulation method for the dual active bridge converter of the present invention includes the following steps:

[0055] S1. The modes of extended double-sided asymmetric phase-shift modulation are classified and their steady-state characteristics are analyzed.

[0056] like Figure 2 As shown, the primary-side full-bridge H1 is composed of power switches S1 to S4, and the secondary-side full-bridge H2 is composed of power switches Q1 to Q4. Where D... Si and D Qi These represent the power switching transistors S and S, respectively. i and Q i The anti-parallel diode, C Si and C Qi These represent the power switching transistors S and S, respectively. i and Q i The junction capacitance is given. C1 and C2 represent the filter capacitors on the input and output sides, respectively. The turns ratio of the high-frequency transformer is N. ab and v cd These represent the midpoint voltages of the primary and secondary sides of the full-bridge circuit, respectively. The DAB converter modifies the midpoint voltage v of the primary and secondary sides of the full-bridge circuit. ab and v cd The relative position of the inductor to change the inductor current i LThe waveform is used to control energy. The voltage conversion ratio M = NV is defined. out / V in To enable the DAB converter to achieve stable operation over a wide voltage range under the proposed EDAPSM, Figure 3 The steady-state waveform of the proposed modulation method is shown. The conduction time of the primary-side switches S2 and S4 is defined as d1T. s (The value of d1 ranges from [0, 0.5]), and the conduction time of the secondary-side switches Q2 and Q4 is defined as d3T. s (The value of d3 ranges from [0, 0.5]). Under step-down operation, the shift ratio between the primary-side switching transistors S1 and S4 is defined as d2T. s (The value of d2 ranges from [0,1]), as shown in Fig. 2(a) and (b). Under boost operation, the shift ratio between the secondary-side switching transistors Q1 and Q4 is defined as d2T. s As shown in Fig. 2(c) and (d), the shift ratio between the primary-side switch S1 and the secondary-side switch Q1 is defined as... ( The value range is [0, 0.5].

[0057] In the time domain, the transmission power P and the effective value I of the inductor current can be obtained by using piecewise linearization of the inductor current and the volt-second balance principle of the inductor. rms Taking EDAPSM mode A as an example for derivation, the transmission power is normalized to a per-unit value for ease of expression. I b =v ab T s / 2πL. The normalized transmission power P of the DAB converter in steady state is obtained. n As shown in the formula.

[0058]

[0059] In EDAPSM mode A, the peak-to-peak value of the inductor current I p_p The square of the effective value is shown in the formula.

[0060]

[0061] S2. Establish a mathematical model of the switching transistor commutation process and derive the accurate current value required for the switching transistor to achieve ZVS.

[0062] Specifically as follows:

[0063] Taking the commutation process of switches S3 and Q1 (Q4) in EDAPSM mode A as an example, the mathematical model takes into account the junction capacitance C of the switches. Si(C Qi And dead time. To simplify the model, the junction capacitance of the switching transistor as a function of the drain-source voltage V of the switching transistor is ignored. DS The factors that change along with the junction capacitance of all switching transistors are the same, i.e., C. Si =C Qi =C oss . Figure 4 The equivalent circuit diagrams of switching transistors S3 and Q1 (Q4) before commutation, during the dead time, and after commutation are given. The equivalent circuit diagram of the commutation process of switching transistor Q1 (Q4) is shown below. Figure 4 As shown in (a)-(c), the following holds true at the commutation point.

[0064]

[0065] During the dead time, the junction capacitance C of switching transistors Q1 and Q4 Q1 and C Q4 Discharge begins, and simultaneously, the junction capacitance C of switching transistors Q2 and Q3... Q2 and C Q3 Charging begins. The primary inductance is transferred to the secondary side via a transformer. The junction capacitance and inductance form a resonant network. Therefore, according to the KVL equation and the initial conditions above, the inductor current i during the dead time can be calculated. L (t) and junction capacitance C Q1 voltage u CQ1 (t) can be represented as:

[0066]

[0067] The equivalent circuit diagrams of switching transistor S3 before and after commutation are as follows: Figure 4 As shown in (d)-(f). Using the same analysis method, the inductor current i during the dead time can be obtained. L (t) and junction capacitance C S3 voltage u CS3 (t) is shown below:

[0068]

[0069] When the direction of the ZVS current value is satisfied, different ZVS current values ​​will also affect the dead time. Taking the commutation process of switch S3 as an example, under ideal conditions, when C S3 When the voltage across the transistor is 0, switching transistor S3 is turned on, thus achieving efficient ZVS. The minimum current value for the switching transistor to achieve ZVS is defined as I. minZVS t3' is the start time of commutation of switch S3, and t3 is the end time of commutation of switch S3. During the commutation process, the junction capacitance C of switch S4... S4 The voltage on it is fully charged from 0V to V. inThe junction capacitance C of the switching transistor S3 S3 The voltage on is determined by V in It is completely discharged to 0V. During this time, the junction capacitance C... S3 All the stored energy was transferred to the junction capacitance C. S4 Above, i.e., E t3'_CS3 =E t3_CS4 According to the law of conservation of energy, the energy before commutation is the same as the energy after commutation.

[0070]

[0071] At time t3', the inductance L and junction capacitance C S3 The stored energy is:

[0072]

[0073] At time t3, the junction capacitance C S4 The stored energy and the dead time are controlled by the input voltage V in and output voltage V out Energy consumed E c for:

[0074]

[0075] The minimum current value I required for switch S3 to achieve ZVS can be obtained. minZVS As shown in the formula:

[0076]

[0077] Therefore, the ZVS current value of switch S3 at the commutation moment should be greater than the minimum ZVS current value I. minZVS Then the ZVS current value at the commutation moment can be expressed as:

[0078]

[0079] S3. For power ranges without analytical solutions, approximate solutions are obtained by adding constraints.

[0080] In the low-power range of EDAPSM mode A, an analytical solution cannot be obtained due to the equality constraints on transmission power, the equality constraints on switches Q2 and Q3, and the inequality constraints on ZVS implementation by switch S4. To make the EDAPSM method real-time, this paper proposes an approximate solution method, which adds the inequality constraints on ZVS implementation by switches Q1 (Q4) to the original constraints. The approximate analytical solution and the optimized solution are quantized by substituting them into the expressions for the peak-to-peak value of the inductor current and the square of the inductor current RMS value. The quantized results are as follows: Figure 5 As shown, Figure 5(a) compares the peak-to-peak inductor current of the two solutions, showing that in the low power range, the peak-to-peak current of the optimized solution is smaller than that of the approximate analytical solution. However, in... Figure 5 (b) compares the squares of the RMS inductor current values ​​for the two solutions, where the approximate analytical solution is smaller than the optimal solution. This is because, in the multi-objective optimization process, to obtain an analytical solution across the entire power range, a simple peak-to-peak inductor current value is used instead of the complex RMS inductor current value as the optimization objective. Therefore, the optimized solution guarantees the minimum peak-to-peak current. Conduction loss is related to the RMS inductor current value. Using the proposed approximate solution method, not only can an analytical solution across the entire power range be obtained, but the conduction loss in the low-power range can also be reduced. Therefore, it is reasonable to use the proposed approximation method and KKT conditions to obtain analytical solutions for the optimization variables across the entire power range.

[0081] S4. Unify the current value for ZVS for different switches to achieve smooth switching between modes.

[0082] The changes in the optimization variables obtained are as follows Figure 6 As shown in (a). Figure 6 (b) is a magnified view of the mode switching process, showing a sudden change in variables during mode switching. This is because the minimum current values ​​required for switches Q2 and Q3 to achieve ZVS differ between the two modes. In practical applications, as power increases, uncontrollable oscillations in the inductor current can occur, leading to system instability. The minimum current values ​​required for switches Q2 and Q3 to achieve ZVS in EDAPSM mode A are shown in the equation.

[0083]

[0084] In EDAPSM mode B, the minimum current required for switches Q2 and Q3 to achieve ZVS is shown in the equation.

[0085]

[0086] I ZVSQ2Q3_B The absolute value is always greater than I. ZVSQ2Q3_A Analysis shows that a larger ZVS current value at commutation time is more conducive to the ZVS of the switching transistors. Therefore, in order to ensure smooth mode switching and ZVS of switching transistors Q2 and Q3 in EDAPSM mode A, the ZVS current values ​​of switching transistors Q2 and Q3 at commutation time are set as shown in the equation.

[0087]

[0088] Figure 7The graph shows the changes in optimization variables after applying the proposed mode-smoothing switching method. As can be seen from the graph, all optimization variables change continuously, and no abrupt changes occur at the mode-switching points, verifying the effectiveness of the proposed method.

[0089] To verify that the proposed EDAPSM method can operate stably across a wide voltage range under all operating conditions, experiments were conducted under buck conditions, with a voltage conversion ratio M of 0.6, to present the steady-state waveforms of EDAPSM mode A and EDAPSM mode B, as well as before and after mode switching. Simultaneously, under boost conditions, experiments were conducted to present the steady-state waveforms of EDAPSM mode C and EDAPSM mode D, with a voltage conversion ratio M of 1.25, as well as before and after mode switching. At M = 0.6, the input voltage was set to 200V, and the output voltage was controlled to 120V via closed-loop control. The results are as follows: Figure 8 As shown. Figure 8 (a) is the steady-state waveform of EDAPSM mode A, where the drive pulse of switch S2 lags behind the drive pulse of switch Q2. Figure 8 (b) is the steady-state waveform of EDAPSM mode A before mode switching. At this time, the drive pulses of switching transistors Q2 and Q3 coincide. Since it is still in EDAPSM mode A, the drive pulse of switching transistor S2 is still lagging behind the drive pulse of switching transistors Q2 (Q3). Figure 8 (c) is the steady-state waveform of EDAPSM mode B after mode switching. The drive pulse of switch S2 leads the drive pulse of switch Q2 (Q3). Figure 8 (d) is the steady-state waveform of EDAPSM mode B, where the drive pulse of switch S2 leads the drive pulse of switch Q2 (Q3).

[0090] When M=1.25, the experimental setup was to set the input voltage to 160V and the output voltage to 200V via closed-loop control. The results are as follows. Figure 9 As shown. Figure 9 (a) is the steady-state waveform of EDAPSM mode C, where the drive pulse of switch S3 lags behind the drive pulse of switch Q3. Figure 9 (b) is the steady-state waveform of EDAPSM mode C before mode switching. Since the drive pulses of switches S2 and S3 coincide, the drive pulse of switch S2 (S3) lags behind the drive pulse of switch Q2 (Q3). Figure 9 (c) is the steady-state waveform of EDAPSMmode D after mode switching. At this time, the drive pulse of switch S2 (S3) leads the drive pulse of switch Q3. Figure 9(d) is the steady-state waveform of EDAPSM mode D, where the drive pulse of switch S2 (S3) leads the drive pulse of switch Q3.

[0091] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. An extended dual-sided asymmetric phase-shift modulation method for a dual active bridge converter, characterized in that, Includes the following steps: S1. The modes of extended double-sided asymmetric phase-shift modulation are classified and their steady-state characteristics are analyzed. S2. Establish a mathematical model of the switching transistor commutation process and derive the accurate current value required for the switching transistor to achieve ZVS. S3. For power ranges without analytical solutions, approximate solutions are obtained by adding constraints. S4. Unify the current value for ZVS for different switches to achieve smooth switching between modes.

2. The extended dual-sided asymmetric phase-shift modulation method for a dual active bridge converter as described in claim 1, characterized in that, In S1, the conduction time of primary-side switches S2 and S4 is defined as d1T. s The value of d1 ranges from 0 to 0.5, and the conduction time of the secondary switching transistors Q2 and Q4 is defined as d3T. s The value of d3 ranges from 0 to 0.5; under step-down operation, the shift ratio between primary-side switching transistors S1 and S4 is defined as d2T. s The value of d2 ranges from 0 to 1; under boost operation, the shift ratio between secondary switching transistors Q1 and Q4 is defined as d2T. s The shift ratio between the primary-side switch S1 and the secondary-side switch Q1 is defined as The value ranges from 0 to 0.5; under time-domain analysis, the transmission power P and the effective value I of the DAB converter can be obtained by using piecewise linearization of the inductor current and the volt-second balance principle of the inductor. rms Taking EDAPSM mode A as an example, the derivation is performed. For ease of expression, the transmission power is normalized to per unit, let... I b =v ab T s / 2πL, the normalized transmission power P of the DAB converter under steady state is obtained. n As shown in the formula: In EDAPSM mode A, the peak-to-peak value of the inductor current I p_p The sum of the squares of the effective values ​​is shown in the formula:

3. The extended dual-sided asymmetric phase-shift modulation method for a dual active bridge converter as described in claim 1, characterized in that, In S2, a mathematical model of the switching transistor's commutation process is established, and the accurate current value required for the switching transistor to achieve ZVS is derived; including: With the switching transistor Q1 (Q4) at the commutation point, the following equation holds: During the dead time, the junction capacitance C of switching transistors Q1 and Q4 Q1 and C Q4 Discharge begins, and simultaneously, the junction capacitance C of switching transistors Q2 and Q3... Q2 and C Q3 When charging begins, the primary inductance is transferred to the secondary side via a transformer. The junction capacitance and inductance form a resonant network. Therefore, based on the KVL equations and the initial conditions above, the inductor current *i* during the dead time can be calculated. L (t) and junction capacitance C Q1 voltage u CQ1 (t) can be represented as: Using the same analysis method, the inductor current i during the dead time can be obtained from switch S3. L (t) and junction capacitance C S3 voltage u CS3 (t) is shown below: When the direction of the ZVS current is satisfied, different ZVS current values ​​will also affect the dead time. Taking the commutation process of switch S3 as an example, under ideal conditions, when C S3 When the voltage across the circuit is 0, switching transistor S3 is turned on, thus achieving efficient ZVS. The minimum current value for the switching transistor to achieve ZVS is defined as I. minZVS t3' is the start time of commutation of switch S3, and t3 is the end time of commutation of switch S3. During the commutation process, the junction capacitance C of switch S4 is... S4 The voltage on it is fully charged from 0V to V. in The junction capacitance C of the switching transistor S3 S3 The voltage on is determined by V in When fully discharged to 0V, during this period, the junction capacitance C S3 All the stored energy was transferred to the junction capacitance C. S4 Above, i.e., E t3'_CS3 =E t3_CS4 According to the law of conservation of energy, the energy before commutation is the same as the energy after commutation. At time t3', the inductance L and junction capacitance C S3 The stored energy is: At time t3, the junction capacitance C S4 The stored energy and the dead time are controlled by the input voltage V in and output voltage V out Energy consumed E c for: The minimum current value I required for switch S3 to achieve ZVS can be obtained. minZVS As shown in the formula: Therefore, the ZVS current value of switch S3 at the commutation moment should be greater than the minimum ZVS current value I. minZVS Then the ZVS current value at the commutation moment can be expressed as:

4. The extended dual-sided asymmetric phase-shift modulation method for a dual active bridge converter as described in claim 1, characterized in that, In S3, the power range without analytical solutions is approximated by adding constraints; In EDAPSM mode A, since an analytical solution cannot be obtained under the equality constraints of transmission power, the equality constraints of switches Q2 and Q3, and the inequality constraints of switch S4 implementing ZVS, an inequality constraint of switch Q1 (Q4) implementing ZVS is added to the original constraints to ensure that the EDAPSM method has real-time performance.

5. The extended dual-sided asymmetric phase-shift modulation method for a dual active bridge converter as described in claim 1, characterized in that, In S4, the current value for ZVS is unified for different switches to achieve smooth switching between modes; Because the minimum current values ​​required for switches Q2 and Q3 to achieve ZVS differ in the two modes, in practical applications, as power increases, uncontrollable oscillations in the inductor current can occur, leading to system instability. In EDAPSM mode A, the minimum current values ​​required for switches Q2 and Q3 to achieve ZVS are shown in the equation: In EDAPSM mode B, the minimum current required for switches Q2 and Q3 to achieve ZVS is shown in the following equation: I ZVSQ2Q3_B The absolute value is always greater than I. ZVSQ2Q3_A As analyzed above, a larger ZVS current value at commutation time is more conducive to the ZVS of the switching transistors. Therefore, in order to ensure smooth mode switching and ZVS of switching transistors Q2 and Q3 in EDAPSM mode A, the ZVS current values ​​of switching transistors Q2 and Q3 at commutation time are set as shown in the following formula:

Images