Efficiency optimization method of DAB converter, electronic equipment and storage medium

Abstract

The invention relates to the technical field of new energy, in particular to an efficiency optimization method of a DAB converter, electronic equipment and a storage medium. The method comprises the following steps: calculating a staggered ratio coefficient and a first phase shift parameter in a heavy load mode and a first phase shift parameter in a light load mode according to an output power reference value, a battery side voltage sampling value and a bus side voltage sampling value; determining a second phase shift parameter and a switching frequency in the heavy load mode according to the staggered proportion coefficient and the first phase shift parameter in the heavy load mode, and determining a second phase shift parameter in the light load mode according to the first phase shift parameter in the light load mode; and determining a current working mode based on the staggered proportion coefficient in the heavy load mode and a preset dead zone proportion, and generating a driving signal of each power switch based on the first phase shift parameter, the second phase shift parameter and the switching frequency corresponding to the current working mode. According to the method, the overall efficiency of the DAB converter under different load conditions is improved.

Description

Technical Field

[0001] This application relates to the field of new energy technology, and in particular to an efficiency optimization method for a DAB converter, an electronic device, and a storage medium. Background Technology

[0002] In recent years, low-voltage, high-capacity single-cell battery energy storage systems (BESS) have gradually gained a dominant position in the market due to their significant advantages such as high cost-effectiveness and simple battery management system design. To achieve efficient energy exchange with the grid, single-cell BESS requires a high boost ratio DC-DC converter and sophisticated control strategies to boost its output voltage to a grid-compatible level, meeting grid connection requirements.

[0003] Dual active bridge (DAB) converters have attracted much attention in modern energy conversion systems due to their excellent bidirectional power transfer capability and inherent soft-switching characteristics. However, in practical applications, DAB converters still face many challenges in maintaining high efficiency when subjected to extreme voltage ratio operating conditions.

[0004] Existing control strategies have significant limitations when handling partial load operation of DAB converters. On one hand, a large amount of reactive power circulates in the circuit, increasing system energy loss and reducing power transfer efficiency. On the other hand, the narrowing of the soft-switching window makes it difficult for switching devices to switch under ideal zero-voltage conditions, leading to increased switching losses. These two factors combined cause a significant performance degradation of DAB converters under partial load conditions, failing to meet the growing demand for efficient and stable energy conversion. Summary of the Invention

[0005] This application aims to provide an efficiency optimization method, electronic device, and storage medium for DAB converters to solve the problem of high energy loss in the control strategies of existing DAB converters.

[0006] To address the aforementioned technical problems, the embodiments of this application provide the following technical solutions: According to a first aspect of this application, an efficiency optimization method for a DAB converter is provided. The DAB converter employs dual-phase-shift control, and a first phase-shift parameter and a second phase-shift parameter are defined based on the dual-phase-shift control method. The first phase-shift parameter is the ratio of the nVp pulse width to the switching period, and the second phase-shift parameter is the ratio of the difference between the midpoint of the high-level pulses of Vs and nVp to the switching period. nVp is the primary-side normalized voltage, and Vs is the transformer output voltage. The method includes: Step A: Obtain the output power reference value, battery-side voltage sample value, and bus-side voltage sample value; Step B: Calculate the offset ratio coefficient and the first phase shift parameter to achieve the first optimization target under heavy load mode, and the first phase shift parameter to achieve the second optimization target under light load mode, based on the output power reference value, the battery side voltage sampling value and the bus side voltage sampling value. The offset ratio coefficient is the ratio of the difference between the high-level pulse start point of Vs and nVp to the pulse width of nVp. Step C: Determine the second phase shift parameter and switching frequency in the heavy load mode based on the staggered ratio coefficient and the first phase shift parameter in the heavy load mode; determine the second phase shift parameter in the light load mode based on the first phase shift parameter in the light load mode. Step D: Determine the current working mode based on the staggered ratio coefficient and the preset dead zone ratio in the overload mode; Step E: Generate drive signals for each power switch based on the first phase shift parameter, the second phase shift parameter, and the switching frequency corresponding to the current operating mode, wherein the switching frequency of the DAB converter in light load mode is a preset value.

[0007] Optionally, when the DAB converter is in heavy load mode, the nVp high level and the Vs high level are partially staggered and partially overlapped; when the DAB converter is in light load mode, the nVp high level and the Vs high level are completely overlapped.

[0008] Optionally, the first optimization objective is to minimize the return reactive power while ensuring that all power switches achieve zero-voltage switching, and the second optimization objective is to ensure that all power switches achieve zero-voltage switching.

[0009] Optionally, the formula for calculating the first phase shift parameter to achieve the first optimization objective in heavy-load mode is:

[0010] The formula for calculating the first phase shift parameter to achieve the second optimization objective under light load mode is:

[0011] in, This refers to the first phase shift parameter in heavy-load mode. This refers to the first phase shift parameter under light load mode. The output power reference value is... The sampled value of the battery-side voltage. Voltage conversion ratio, For power transfer ratio, The sampled value of the bus-side voltage. This refers to the turns ratio of a high-frequency transformer. This is the reference switching frequency in heavy-load mode. For the magnitude of leakage inductance on the secondary side, This refers to the switching frequency in light-load mode.

[0012] Optionally, the formula for calculating the staggered ratio coefficient to achieve the first optimization objective in overload mode is:

[0013] in, The staggered ratio coefficient is used to achieve the first optimization objective in heavy-load mode.

[0014] Optionally, determining the current working mode based on the staggered ratio coefficient and the preset dead zone ratio under heavy load mode includes: Multiplying the offset ratio coefficient in the heavy load mode with the first phase shift parameter in the heavy load mode yields the high-level offset ratio between Vs and nVp in the heavy load mode. Determine whether the high-level offset ratio is greater than twice the preset dead zone ratio. If yes, determine that the current working mode is heavy load mode; otherwise, determine that the current working mode is light load mode.

[0015] Optionally, the formula for calculating the second phase shift parameter in heavy-load mode is:

[0016] The formula for calculating the switching frequency in heavy-load mode is:

[0017] The formula for calculating the second phase shift parameter in light load mode is:

[0018] in, This refers to the second phase shift parameter in heavy-load mode. This refers to the second phase shift parameter in the light load mode.

[0019] Optionally, after step B and before step C, the method further includes: Obtain the bus-side current sampling value, and calculate the current error value based on the output power reference value, the bus-side voltage sampling value, and the bus-side current sampling value; The correction value of the first phase shift parameter is obtained by using a proportional-integral controller based on the current error value; The first phase shift parameter in heavy load mode and light load mode is corrected based on the correction value.

[0020] According to a second aspect of this application, an electronic device is provided, including at least one processor and a memory communicatively connected to the at least one processor, the memory storing instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the method described above.

[0021] According to a third aspect of this application, a computer storage medium is provided, the computer storage medium storing instructions or programs that, when executed by at least one processor, cause the at least one processor to perform the method described above.

[0022] The beneficial effects of this application embodiment are as follows: Unlike the prior art, this application embodiment provides an efficiency optimization method for a DAB converter. This DAB converter employs dual-phase-shift control, and a first phase-shift parameter and a second phase-shift parameter are pre-defined based on the dual-phase-shift control method. The efficiency optimization method includes: firstly, calculating the offset ratio coefficient and the first phase-shift parameter to achieve the first optimization objective under heavy load mode, and the first phase-shift parameter to achieve the second optimization objective under light load mode, based on the output power reference value, battery-side voltage sampling value, and bus-side voltage sampling value; then, calculating the second phase-shift parameter and the switching frequency under heavy load mode based on the offset ratio coefficient and the first phase-shift parameter under heavy load mode; and finally, determining the current operating mode based on the offset ratio coefficient and the preset dead-zone ratio under heavy load mode, and generating drive signals for each power switch based on the first phase-shift parameter, the second phase-shift parameter, and the switching frequency corresponding to the current operating mode. This application proposes a full-range efficiency optimization control strategy for high boost ratio DAB converters. Under heavy load mode, it improves system efficiency by jointly optimizing zero-voltage switching and minimizing return current power. Under light load mode, it focuses on optimizing the zero-voltage switching effect across the entire range to ensure high performance. Overall, this method not only improves the overall performance of the DAB converter under different load conditions but also ensures the system's economy and practicality. Attached Figure Description

[0023] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0024] Figure 1 This is a topology diagram of a high boost ratio DAB converter provided in an embodiment of this application; Figure 2 These are schematic diagrams illustrating the six working modes provided in the embodiments of this application; Figure 3 This is a typical waveform diagram of mode B1 provided in the embodiments of this application; Figure 4 This is a typical waveform diagram of mode C1 provided in the embodiments of this application; Figure 5 This is a flowchart of an efficiency optimization method for a DAB converter provided in an embodiment of this application; Figure 6 This is a block diagram of the optimized control strategy for the DAB converter provided in the embodiments of this application; Figure 7 These are simulation waveforms of the efficiency optimization method of this application under various working conditions; Figure 8 yes Figure 7 ZVS performance diagrams for various operating conditions; Figure 9 This is a structural diagram of the electronic device provided in the embodiments of this application. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] Furthermore, the technical features involved in the various embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0027] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0028] Please refer to Figure 1 , Figure 1 This is a topology diagram of a high boost ratio DAB converter provided in an embodiment of this application. For example... Figure 1As shown, this high boost ratio DAB converter employs a symmetrical configuration, containing six power switches (S1-S6) to achieve bidirectional energy conversion between the low-voltage battery terminal and the high-voltage DC bus terminal. Specifically, the primary-side full-bridge circuit composed of power switches S1, S2, S3, and S4 is connected to the battery via an input capacitor (Cin), while the secondary-side hybrid network composed of power switches S5, S6, and capacitors C1 and C2 achieves voltage multiplication through capacitor switching operation. The drain-source voltages of power switches S1, S2, S3, S4, S5, and S6 are represented as Vds1, Vds2, Vds3, Vds4, Vds5, and Vds6, respectively. A high-frequency voltage converter with a turns ratio of 1:n is used to achieve electrical isolation and voltage conversion, wherein the magnetizing inductor ( The primary magnetic core excitation dynamics, secondary leakage inductance ( This DAB converter exhibits dominant power transfer characteristics. Compared to a symmetrical DAB converter with a full-bridge secondary side, its boost ratio is doubled. Figure 1 In this context, the reference directions of voltage and current indicate that power is transmitted from the current meter to the bus side, meaning the power transmission direction is positive.

[0029] Based on the topology of the DAB converter, its current equivalent circuit consists of nVp, A first-order linear circuit is formed by connecting Vp and Vs in series, where nVp is the normalized primary voltage, i.e., n times the primary voltage Vp of the transformer, and Vs is the transformer output voltage. In the embodiments of this application, the DAB converter adopts dual phase-shift control, which controls the shape and relative timing of the transformer primary voltage Vp and transformer secondary voltage Vs by controlling the inner phase shift angle between the primary leading bridge arm (i.e., S1 and S2) and the primary lagging bridge arm (i.e., S3 and S4), and the outer phase shift angle between the primary leading bridge arm and the secondary bridge arm (i.e., S5 and S6), thereby regulating the power flow.

[0030] Please refer to Figure 2 , Figure 2 These are schematic diagrams illustrating the six working modes provided in the embodiments of this application. For example... Figure 2As shown, based on the relative alignment of the midpoints of the high-level pulses of nVp (blue three-level waveform) and Vs (red two-level waveform), the operating modes of the DAB converter are divided into six modes: A1, B1, C1, A2, B2, and C2. Specifically, (a1) corresponds to mode A1; (b1) corresponds to mode B1; (c1) corresponds to mode C1; (a2) corresponds to mode A2; (b2) corresponds to mode B2; and (c2) corresponds to mode C2. In particular, in modes A1 and A2, the high-level pulses of nVp and Vs are completely staggered; in modes B1 and B2, the high-level pulses of nVp and Vs are partially staggered and partially overlapped; and in modes C1 and C2, the high-level pulses of nVp and Vs completely overlap. Furthermore, in modes A1 / B1 / C1, the midpoint of the nVp high-level pulse leads the midpoint of the Vs high-level pulse, the voltage difference is positive, and power is transferred in the forward direction, i.e., energy is transferred from the low-voltage battery side to the high-voltage bus side; in modes A2 / B2 / C2, the midpoint of the nVp high-level pulse lags the midpoint of the Vs high-level pulse, the voltage difference is reverse, and power is transferred in the reverse direction, i.e., energy is transferred from the high-voltage bus side to the low-voltage battery side. The efficiency optimization method proposed in this application switches between these modes by dynamically adjusting the midpoint offset and the high-level pulse width.

[0031] To facilitate quantitative analysis, two intermediate variables are defined: a first phase-shifting parameter D1 and a second phase-shifting parameter D2. The first phase-shifting parameter D1 is the ratio of the nVp pulse width to the switching period Ts, i.e., D1*Ts equals the duration of the nVp high-level pulse. The second phase-shifting parameter D2 is the ratio of the difference between the midpoint of the Vs high-level pulse and the midpoint of the nVp high-level pulse, to the switching period, i.e., D2*Ts equals the time by which the midpoint of the nVp high-level pulse precedes the midpoint of the Vs high-level pulse. If the midpoint of the nVp high-level pulse lags behind the midpoint of the Vs high-level pulse, then D2*Ts takes a negative value. Figure 2 It can be seen that the value range of D1 is from 0 to 0.5, and the value range of D2 is from -0.5 to 0.5. The relationship between D1 and D2 under the six modes is shown in Table 1 below: Table 1

[0032] Experiments show that modes A1 and A2 have the same output power range as modes C1 and C2, but modes A1 and A2 have higher current stress. Therefore, in practical control, modes A1 and A2 are usually avoided, and switching is only performed between modes B1, B2, C1, and C2. The following analysis uses modes B1 and C1 corresponding to forward power transmission as an example. Since the power transmission of the DAB converter is controlled by the outward phase shift angle of the primary and secondary voltages, when the DAB converter operates under heavy load conditions, in order to transmit more power, the high level of nVp must be offset from the high level of Vs to increase the outward phase shift angle; that is, under heavy load conditions, the DAB converter operates in mode B1. Conversely, when the DAB converter operates under light load conditions, the transmitted power is smaller, so the high level of nVp must overlap with the high level of Vs to reduce the outward phase shift angle; that is, under light load conditions, the DAB converter operates in mode C1. For ease of understanding, mode B1 is also called heavy load mode, and mode C1 is also called light load mode.

[0033] Please refer to Figure 3 , Figure 3 This is a typical waveform diagram of mode B1 provided in the embodiments of this application. For example... Figure 3 As shown, the first three sets of waveforms are the conduction waveforms of power switches S1-S6, where S1, S4, and S5 correspond to red waveforms, and S2, S3, and S6 correspond to blue waveforms. The fourth set of waveforms are the waveforms of nVp and Vs (nVp is the blue waveform, and Vs is the red waveform). The fifth set is the instantaneous transmission current of the high-frequency transformer. The waveforms in the sixth group represent the instantaneous power transmission of the high-frequency transformer. The waveform. It should be noted that... Figure 3 The dead time between the turn-on and turn-off times of two power switches in the same bridge arm is ignored. Based on Figure 3 Time stamps in (e.g., When S1 is turned on, When S4 is turned on, When S5 is turned on, When S2 is turned on, When S3 is turned on, When S6 is turned on, (This refers to the S1 turn-on time of the next switching cycle). The correspondence between D1, D2 and the power switch switching time in mode B1 is as follows: (1) in, The switching cycle, i.e. arrive Duration.

[0034] Considering instantaneous transmission current The symmetry of the waveform within one switching cycle, then the switching moments in mode B1 The calculation formula is as follows: (2) in, This is the low-voltage battery side voltage. This refers to the voltage on the high-voltage bus side. For the magnitude of leakage inductance on the secondary side, The turns ratio of a high-frequency transformer. This refers to the switching frequency in B1 mode.

[0035] Instantaneous transmission power of high frequency transformers Average output power in the next switching cycle of mode B1 for: (3) According to the value ranges of D1 and D2 under mode B1 described in Table 1, when D1=1 / 2 and D2=1 / 4, the output power is... Reaching its maximum value Under heavy load conditions, the transformer experiences high-frequency current stress and large return reactive power. Therefore, the first optimization objective of mode B1 is to jointly optimize based on zero voltage switching (ZVS) and return reactive power, specifically to minimize return reactive power while ensuring that all power switches achieve ZVS.

[0036] To achieve ZVS, the direction of the transformer current must be sufficient to discharge the parasitic capacitances of the power switch (i.e., Coss1, Coss2, Coss3, and Coss4) during the dead time before the power switch is turned on. According to Figure 3 The waveform and formula (2), the ZVS conditions for S1 and S2 are: ,Right now (4) The ZVS conditions for S3 and S4 are: ,Right now (5) The ZVS conditions for S5 and S6 are: ,Right now (6) Furthermore, under ZVS conditions, the return reactive power is minimized. Return reactive power is the reactive power that circulates within the circuit but does not contribute to effective power transfer; it corresponds to... Figure 3The shaded triangle area in the bottommost sub-figure illustrates this. While a certain level of return power is necessary to achieve ZVS, excessive return power leads to additional conduction losses, thus reducing overall efficiency. To suppress return reactive power, it must be minimized. Figure 3 The geometric area of ​​the shaded region. According to... Figure 3 And formula (2), return reactive power The calculation formula is: (7) Under heavy load conditions, the joint optimization of ZVS and cyclic reactive power aims to balance the benefits of ZVS with the associated losses. By optimizing the hardware parameter design of DAB, the dominant constraint in ZVS conditions (4), (5), and (6) becomes the ZVS condition of the lagging arm switch. Specifically, satisfying inequality (5) automatically guarantees the validity of inequalities (4) and (6). The first optimization objective can be transformed into minimizing formula (7) under the premise of satisfying inequality (5). Re-examining Figure 3 , The value transitions from negative to positive between t1 and t2. To model this behavior, a staggered percentage coefficient is introduced. ,satisfy = * * Combining formula (1), we can obtain: (8) Therefore, inequality (5) and formula (7) are transformed into the following inequality (9) and formula (10), respectively: (9) (10) From this, we can deduce that... Relationship between ZVS condition and return reactive power: When At that time, the ZVS condition is satisfied, and hour, The smaller the value, the smaller the reactive power of the return flow. Based on By definition, equation (3) can be rewritten as: (11) Furthermore, a reference switching frequency is introduced. Actual switching frequency Follow The changes are as follows: (12) Therefore, formula (11) can be simplified to: ,Right now (13) Equation (13) shows that when the variable switching frequency defined by equation (12) is applied, the output power There is a linear relationship between D1 and D2. This simplifies the parameter tuning process of the feedback controller. Based on equation (13), the minimum reactive power used to optimize the return flow is... The formula for calculating the value is: (14) Please refer to Figure 4 , Figure 4 This is a typical waveform diagram of mode C1 provided in the embodiments of this application. For example... Figure 4 As shown, the first three sets of waveforms are the conduction waveforms of power switches S1-S6, where S1, S4, and S5 correspond to red waveforms, and S2, S3, and S6 correspond to blue waveforms. The fourth set of waveforms are the waveforms of nVp and Vs (nVp is the blue waveform, and Vs is the red waveform). The fifth set is the instantaneous transmission current of the high-frequency transformer. The waveforms in the sixth group represent the instantaneous power transmission of the high-frequency transformer. The waveform. Similarly, Figure 4 The dead time between the turn-on and turn-off times of two switches in the same bridge arm is also ignored. Based on Figure 4 Time stamps in (e.g., When S1 is turned on, When S5 is turned on, When S4 is turned on, When S2 is turned on, When S6 is turned on, When S3 is turned on, (This refers to the S1 turn-on time of the next switching cycle). The correspondence between D1, D2 and the power switch switching time in mode C1 is as follows: (15) in, The switching cycle, i.e. arrive Duration.

[0037] At each switching moment in mode C1 The calculation formula is as follows: (16) in, This refers to the switching frequency in C1 mode.

[0038] Furthermore, the average output power of mode C1 in the next switching cycle for: (17) According to the value ranges of D1 and D2 under mode C1 described in Table 1, when D1=1 / 4 and D2=1 / 8, the output power is... Reaching its maximum value It is worth noting that the maximum output power in mode C1 is half that in mode B1. Therefore, the DAB converter operates in mode C1 under light load conditions. Under light load conditions, the high-frequency current stress on the transformer is low, and both return reactive power and conduction losses are at low levels. In this case, power loss is mainly dominated by switching losses. Therefore, the second optimization objective corresponding to mode C1 is to ensure that all power switches achieve ZVS.

[0039] according to Figure 4 The waveform and formula (16), the ZVS conditions for S1 and S2 are: ,Right now (18) The ZVS conditions for S3 and S4 are: ,Right now (19) The ZVS conditions for S5 and S6 are: ,Right now (20) To simplify the derivation of the ZVS condition, a voltage conversion ratio is introduced. and power transfer ratio The definition is as follows: (twenty one) By optimizing the hardware parameter design of the DAB converter, the ZVS condition (18) can be made to hold naturally. Combining equations (19), (20), and (17), the ZVS condition can be reformulated as... , And the form of D1: (twenty two) In the control, in order to simultaneously satisfy the two ZVS conditions, D1 is set as the average of the upper and lower limits of equation (22): (twenty three) Please refer to Figure 5 , Figure 5 This is a flowchart of an efficiency optimization method for a DAB converter provided in an embodiment of this application. The method is applied to... Figure 1 The DAB converter with the topology shown employs dual phase-shift control, and the method includes: Step S501: Obtain the output power reference value, battery side voltage sample value, and bus side voltage sample value.

[0040] In one embodiment, a first voltage sampling device is installed on the battery side of the DAB converter, and a second voltage sampling device is installed on the bus side of the DAB converter. The first voltage sampling device is used to collect low-voltage battery side voltage sampling values ​​in real time to obtain battery side voltage sampling values, and the second voltage sampling device is used to collect high-voltage bus side voltage sampling values ​​in real time to obtain bus side voltage sampling values.

[0041] Step S502: Calculate the staggered ratio coefficient, the first phase shift parameter, and the first phase shift parameter for achieving the first optimization objective under heavy load mode, based on the output power reference value, battery side voltage sampling value, and bus side voltage sampling value.

[0042] The control methods of DAB converters include single-phase-shift control, dual-phase-shift control, and three-phase-shift control. Among them, dual-phase-shift control controls the shape and relative timing of the transformer primary voltage vp and transformer secondary voltage vs by controlling the inner phase shift angle between the primary leading arm and the primary lagging arm, and the outer phase shift angle between the primary leading arm and the secondary arm.

[0043] To facilitate quantitative analysis, two intermediate variables are defined: a first phase-shifting parameter D1 and a second phase-shifting parameter D2. The first phase-shifting parameter D1 is the ratio of the nVp pulse width to the switching period Ts, i.e., D1*Ts equals the nVp pulse width. The second phase-shifting parameter D2 is the ratio of the difference between the midpoints of the high-level pulses of Vs and nVp to the switching period, i.e., D2*Ts equals the duration by which the midpoint of the nVp high-level pulse leads the midpoint of the Vs high-level pulse.

[0044] Based on the foregoing analysis, during forward power transmission, the candidate operating modes of the DAB converter are B1 mode (i.e., heavy load mode) and C1 mode (i.e., light load mode). In heavy load mode, the high levels of nVp and Vs are partially offset and partially overlap; in light load mode, the high levels of nVp and Vs completely overlap. The offset ratio is the ratio of the difference in the starting points of the high-level pulses of Vs and nVp to the pulse width of nVp. Figure 3 For example, let the staggered ratio coefficient be... Then there is = * * .

[0045] Under heavy load conditions, the transformer experiences significant high-frequency current stress and a large amount of return reactive power. In one embodiment, the first optimization objective is to perform joint optimization based on ZVS and return reactive power, specifically minimizing return reactive power while ensuring that all power switches achieve ZVS.

[0046] Under light load conditions, the transformer experiences lower high-frequency current stress, resulting in lower return reactive power and conduction losses. In this scenario, power loss is primarily driven by switching losses. In one embodiment, the second optimization objective is to ensure that all power switches achieve zero-voltage switching (ZVS).

[0047] Based on the foregoing Figure 3 The analysis shows that the output power of formula (14) is... Replacing it with the output power reference value, we can obtain the formula for calculating the staggered ratio coefficient to achieve the first optimization objective in heavy-load mode: (twenty four) in, The staggered ratio coefficient is used to achieve the first optimization objective in heavy-load mode. This is the output power reference value. The equivalent leakage inductance of the secondary side, This is the sampled value of the battery-side voltage. This is the sampled value of the bus-side voltage. This refers to the turns ratio of a high-frequency transformer. This is the reference switching frequency in heavy-load mode (a preset value).

[0048] Based on the foregoing Figure 4 The analysis shows that the output power of formula (13) is... By replacing the output power reference value, the first phase shift parameter that achieves the first optimization objective in heavy-load mode can be obtained. The calculation formula is as follows: (25) Furthermore, the output power of formula (21) By replacing the output power reference value with formula (23), the first phase shift parameter for achieving the second optimization objective under light load mode can be obtained. The calculation formula is: (26) in, This is the switching frequency in light load mode (a preset value). Voltage conversion ratio, This represents the power transfer ratio.

[0049] Step S503: Calculate the second phase shift parameter and switching frequency under heavy load mode based on the staggered ratio coefficient and the first phase shift parameter under heavy load mode, and calculate the second phase shift parameter under light load mode based on the first phase shift parameter under light load mode.

[0050] Specifically, the second phase shift parameter under heavy load mode is obtained based on the aforementioned formula (8). The calculation formula is as follows: (27) Based on the aforementioned formula (12), the switching frequency in heavy-load mode is obtained. The calculation formula is as follows: (28) Based on the foregoing Figure 4 The analysis shows that the output power of formula (17) is... By replacing the output power reference value, the second phase shift parameter in light load mode can be obtained. The calculation formula is as follows: (29) Step S504: Determine the current working mode based on the staggered ratio coefficient and the preset dead zone ratio in the heavy load mode.

[0051] Specifically, the high-level offset ratio of Vs and nVp in heavy-load mode is obtained by multiplying the offset ratio coefficient in heavy-load mode with the first phase shift parameter in heavy-load mode, i.e., high-level offset ratio = Next, determine whether the high-level offset ratio is greater than twice the preset dead zone ratio. If so, determine that the current working mode is heavy load mode; otherwise, determine that the current working mode is light load mode.

[0052] Step S505: Generate drive signals for each power switch based on the first phase shift parameter, the second phase shift parameter, and the switching frequency corresponding to the current operating mode.

[0053] In one embodiment, step S505 specifically includes: firstly calculating the inner phase shift angle and outer phase shift angle in the current operating mode based on the first phase shift parameter and the second phase shift parameter in the current operating mode; and then generating drive signals for each power switch based on the inner phase shift angle, outer phase shift angle, and switching frequency in the current operating mode. Specifically, according to... Figure 3 and Figure 4 The formulas for calculating the inner and outer phase shift angles in the current operating mode are as follows: (28) in, This is the inward phase angle. For the outward phase angle, , These are the first and second phase shift parameters, respectively, in the current operating mode.

[0054] In one embodiment, after step S502 and before step S503, the method further includes: acquiring bus-side current sampling values; calculating a current error value based on the output power reference value, the bus-side voltage sampling value, and the bus-side current sampling value; obtaining a correction value for the first phase-shifting parameter using a proportional-integral controller based on the current error value; and correcting the first phase-shifting parameter under heavy-load and light-load modes respectively based on the correction value. Specifically, firstly, bus-side current sampling values ​​are acquired; a current reference value is calculated based on the output power reference value and the bus-side voltage sampling value; a current error value can be calculated based on the current reference value and the bus-side current sampling value; then, a correction value for the first phase-shifting parameter is obtained using a proportional-integral controller based on the current error value; finally, the correction value is added to the first phase-shifting parameters calculated in step S502 under heavy-load and light-load modes respectively to obtain the corrected first phase-shifting parameters under heavy-load and light-load modes.

[0055] In practical applications of control strategies, maintaining system stability and optimizing performance under varying load conditions is crucial. To prevent instability caused by switching between different feedback control loops, a unified feedback control strategy is proposed. This strategy is based on an output power reference value. and the sampled values ​​of the battery side voltage Bus side voltage sampling value and bus side current sampling value Real-time measurement and dynamic parameter adjustment ensure optimal performance in all operating modes without altering the structure of the basic control loop.

[0056] Please refer to Figure 6 , Figure 6 This is a block diagram of the DAB converter optimization control strategy provided in an embodiment of this application. Figure 6 As shown, the optimized control strategy includes the following steps: Step 1, based on the output power reference value... Battery-side voltage sampling value Bus side voltage sampling value The staggered ratio coefficient under heavy load mode is calculated using formula (24). According to the output power reference value Battery-side voltage sampling value Bus side voltage sampling value The feedforward control output under heavy load mode is calculated using formula (25). (i.e., the feedforward output of the first phase shift parameter in heavy load mode); based on the output power reference value Battery-side voltage sampling value Bus side voltage sampling value The feedforward control output under light load mode is calculated using formula (26). (i.e., the feedforward output of the first phase shift parameter in light load mode). Step 2, based on the output power reference value. High-voltage bus side voltage sampling value Bus current sampling value Calculate the bus current error Feedback output is obtained through a PI controller. (That is, the correction value of the first phase shift parameter). Step 3, output the feedforward control in heavy load mode. With feedback output Adding them together yields the compensated first phase shift parameter in the overload mode. ; the feedforward control output in light load mode With feedback output Adding them together, we obtain the compensated first phase shift parameter in the light load mode. Step 4, based on the compensated first phase shift parameters Formulas (27) and (28) are used to calculate the second phase shift parameter under heavy load mode. Switching frequency Based on the compensated first phase shift parameters The second phase shift parameter under light load mode is calculated using formula (29). Step 5, Determine Whether it holds true, and if so, then based on the first phase shift parameter in overload mode. Second phase shift parameters and switching frequency Generate drive signals for each power switch; otherwise, based on the first phase shift parameter in light load mode. Second phase shift parameters and switching frequency Generate drive signals for each power switch. Among them, The switching frequency in light load mode is set to the preset dead zone percentage. This is the default value.

[0057] Please refer to Figure 7 , Figure 7 These are typical waveform diagrams of the efficiency optimization method provided in this application under various operating conditions. For example... Figure 7 As shown, (a1), (a2), and (a3) ​​respectively display the sampled values ​​of the low-voltage battery side voltage. =20V, Output Power Reference Value Waveforms for 100W, 300W, and 500W are shown; (b1), (b2), and (b3) respectively display the sampled values ​​of the low-voltage battery side voltage. =25V, Output Power Reference Value Waveforms for 100W, 300W, and 500W. From Figure 7 As can be seen, the waveforms exhibit stable operation under all conditions, with minimal voltage and current ripple at lower power levels. The ripple increases slightly with increasing output power reference value, indicating that the system maintains stability even under high load conditions.

[0058] In light load mode (mode C1), a constant frequency of 50 kHz is maintained; in heavy load mode (mode B1), the reference switching frequency is set to 600 kHz. According to equation (12), when k=0.2, the effective switching frequency range is 300 kHz to 400 kHz.

[0059] In the simulation experiment, DAB at the output power reference value When the power is 100W and 300W, it runs in light load mode (corresponding to...). Figure 7 In (a1), (a2), (b1), and (b2), a constant frequency of 50 kHz is maintained, and the return reactive power is relatively high to ensure that all switches achieve complete ZVS. The DAB operates at the output power reference value. When the power is 500W, it runs in heavy load mode (corresponding to) Figure 7 In equations (a3) ​​and (b3), the reference switching frequency is set to 600 kHz. According to equation (12), when k=0.2, the effective switching frequency range is 300 kHz to 400 kHz. By jointly optimizing ZVS and return reactive power, the return reactive power in heavy load mode is controlled within a low range, significantly improving the efficiency of DAB.

[0060] Please refer to Figure 8 , Figure 8 yes Figure 7 ZVS performance diagrams for various operating conditions. (Example) Figure 8 As shown, (a1), (a2), and (a3) ​​respectively display the sampled values ​​of the low-voltage battery side voltage. =20V, Output Power Reference Value The waveforms of the drive signals of switches S1, S4, and S5 and their drain-source voltage (Vds) are shown for 100W, 300W, and 500W respectively; (b1), (b2), and (b3) show the sampled values ​​of the low-voltage battery side voltage respectively. =25V, Output Power Reference Value The waveforms of the drive signals for switches S1, S4, and S5 and their drain-source voltage (Vds) are shown for 100W, 300W, and 500W. ZVS was achieved stably in all test scenarios, demonstrating that Vds drops to zero before the switch is turned on, effectively reducing switching losses. This performance remained stable regardless of changes in battery voltage or output power reference values.

[0061] The efficiency optimization method for the DAB converter provided in this application adopts dual-phase-shift control, and pre-defines a first phase-shift parameter and a second phase-shift parameter based on the dual-phase-shift control method. The efficiency optimization method includes: firstly, calculating the offset ratio coefficient and the first phase-shift parameter to achieve the first optimization target in heavy-load mode and the first phase-shift parameter to achieve the second optimization target in light-load mode based on the output power reference value, battery-side voltage sampling value and bus-side voltage sampling value; secondly, calculating the second phase-shift parameter and the switching frequency in heavy-load mode based on the offset ratio coefficient and the first phase-shift parameter in heavy-load mode; and thirdly, calculating the second phase-shift parameter in light-load mode based on the first phase-shift parameter in light-load mode; finally, determining the current operating mode based on the offset ratio coefficient and the preset dead-zone ratio in heavy-load mode, and generating drive signals for each power switch based on the first phase-shift parameter, the second phase-shift parameter and the switching frequency corresponding to the current operating mode. This application proposes a full-range efficiency optimization control strategy for high boost ratio DAB converters. Under heavy load mode, it improves system efficiency by jointly optimizing zero-voltage switching and minimizing return current power. Under light load mode, it focuses on optimizing the zero-voltage switching effect across the entire range to ensure high performance. Overall, this method not only improves the overall performance of the DAB converter under different load conditions but also ensures the system's economy and practicality.

[0062] According to an embodiment of this application, an electronic device is provided, such as... Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. The electronic device 100 may include a processor 10, a communication interface 30, a memory 20, and a communication bus. The processor 10, the communication interface 30, and the memory 20 communicate with each other through the communication bus. The processor 10 can call logical instructions in the memory 20 to execute the efficiency optimization method of the DAB converter described above.

[0063] Furthermore, the logical instructions in the aforementioned memory 20 can be implemented as software functional units and sold or used as independent products, and can be stored in several computer-readable storage media. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the efficiency optimization method of the DAB converter of this application. The aforementioned storage media include: USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, optical disks, and other media capable of storing program code.

[0064] According to an embodiment of this application, a computer-readable storage medium of the type described above is provided. The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the processor performs the steps of the efficiency optimization method for the DAB converter described above.

[0065] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a general-purpose hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the related technology, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., including several instructions to enable a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in various embodiments or some parts of the embodiments.

[0066] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of variations or substitutions within the technical scope disclosed in this application. Therefore, any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. An efficiency optimization method for a DAB converter, characterized in that, The DAB converter employs dual-phase-shift control, and defines a first phase-shift parameter and a second phase-shift parameter based on this dual-phase-shift control method. The first phase-shift parameter is the ratio of the nVp pulse width to the switching period, and the second phase-shift parameter is the ratio of the difference between the midpoints of the high-level pulses of Vs and nVp to the switching period. nVp is the normalized primary-side voltage, and Vs is the transformer output voltage. The method includes: Step A: Obtain the output power reference value, battery-side voltage sample value, and bus-side voltage sample value; Step B: Calculate the offset ratio coefficient and the first phase shift parameter to achieve the first optimization target under heavy load mode, and the first phase shift parameter to achieve the second optimization target under light load mode, based on the output power reference value, the battery side voltage sampling value and the bus side voltage sampling value. The offset ratio coefficient is the ratio of the difference between the high-level pulse start point of Vs and nVp to the pulse width of nVp. Step C: Determine the second phase shift parameter and switching frequency in the heavy load mode based on the staggered ratio coefficient and the first phase shift parameter in the heavy load mode; determine the second phase shift parameter in the light load mode based on the first phase shift parameter in the light load mode. Step D: Determine the current working mode based on the staggered ratio coefficient and the preset dead zone ratio in the overload mode; Step E: Generate drive signals for each power switch based on the first phase shift parameter, the second phase shift parameter, and the switching frequency corresponding to the current operating mode, wherein the switching frequency of the DAB converter in light load mode is a preset value.

2. The method according to claim 1, characterized in that, When the DAB converter is in heavy load mode, the nVp high level and the Vs high level are partially staggered and partially overlapped. When the DAB converter is in light load mode, the nVp high level and the Vs high level are completely overlapped.

3. The method according to claim 1, characterized in that, The first optimization objective is to minimize the return reactive power while ensuring that all power switches achieve zero-voltage switching. The second optimization objective is to ensure that all power switches achieve zero-voltage switching.

4. The method according to claim 1, characterized in that, The formula for calculating the first phase shift parameter to achieve the first optimization objective in heavy-load mode is: The formula for calculating the first phase shift parameter to achieve the second optimization objective under light load mode is: in, This refers to the first phase shift parameter in heavy-load mode. This refers to the first phase shift parameter under light load mode. The output power reference value is... The sampled value of the battery-side voltage. Voltage conversion ratio, For power transfer ratio, The sampled value of the bus-side voltage. This refers to the turns ratio of a high-frequency transformer. This is the reference switching frequency in heavy-load mode. The magnitude of leakage inductance on the secondary side. This refers to the switching frequency in light-load mode.

5. The method according to claim 4, characterized in that, The formula for calculating the staggered ratio coefficient to achieve the first optimization objective in heavy-load mode is as follows: in, The staggered ratio coefficient is used to achieve the first optimization objective in heavy-load mode.

6. The method according to claim 5, characterized in that, The determination of the current working mode based on the staggered ratio coefficient and the preset dead zone ratio under heavy load mode includes: Multiplying the offset ratio coefficient in the heavy load mode with the first phase shift parameter in the heavy load mode yields the high-level offset ratio between Vs and nVp in the heavy load mode. Determine whether the high-level offset ratio is greater than twice the preset dead zone ratio. If yes, determine that the current working mode is heavy load mode; otherwise, determine that the current working mode is light load mode.

7. The method according to claim 5, characterized in that, The formula for calculating the second phase shift parameter in heavy-load mode is: The formula for calculating the switching frequency in heavy-load mode is: The formula for calculating the second phase shift parameter in light load mode is: in, This refers to the second phase shift parameter in heavy-load mode. This refers to the second phase shift parameter in the light load mode.

8. The method according to any one of claims 1 to 7, characterized in that, After step B and before step C, the following is also included: Obtain the bus-side current sampling value, and calculate the current error value based on the output power reference value, the bus-side voltage sampling value, and the bus-side current sampling value; The correction value of the first phase shift parameter is obtained by using a proportional-integral controller based on the current error value; The first phase shift parameter in heavy load mode and light load mode is corrected based on the correction value.

9. An electronic device, characterized in that, The method includes at least one processor and a memory communicatively connected to the at least one processor, the memory storing instructions executable by the at least one processor to enable the at least one processor to perform the method as described in any one of claims 1 to 8.

10. A computer storage medium, characterized in that, The computer storage medium stores instructions or programs that, when executed by at least one processor, cause the at least one processor to perform the method as described in any one of claims 1 to 8.

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