Inter-core-particle interconnection 5b-6b crosstalk elimination transceiver, chip and equipment

Abstract

The invention discloses an inter-core-particle interconnection 5b-6b crosstalk cancellation transceiver, a chip and equipment, the inter-core-particle interconnection 5b-6b crosstalk cancellation transceiver comprises a transmitter, a receiver and a clock module, the transmitter comprises an encoder used for realizing inter-channel bit smooth coding, the receiver comprises a clock module, and the clock module comprises a clock module. The receiver comprises a decoder used for realizing inter-channel bit smooth decoding, inter-channel bit smooth coding refers to performing inter-channel bit smooth coding on 5-bit binary data to obtain 6-bit coded data, and inter-channel bit smooth decoding refers to performing inter-channel bit smooth decoding on the 6-bit coded data to obtain 5-bit binary data. The present invention is directed to combining crosstalk cancellation coding with channel characteristics to maximize bandwidth and edge density while maintaining signal integrity, improving the ability to maintain signal integrity in high density interconnects by reducing bit transitions between channels to reduce far-end crosstalk (FEXT) between lines and to improve crosstalk suppression performance.

Description

Technical Field

[0001] This invention relates to the field of chip interconnect technology, specifically to a chip-to-chip 5b-6b crosstalk cancellation transceiver, chip, and device. Background Technology

[0002] The exponential growth of data-centric computing paradigms necessitates the development of high-speed, high-precision data center interconnects, imposing stringent requirements on linearity and noise suppression. Simultaneously, advancements in information technology continue to drive the demand for scalable bandwidth solutions. However, traditional methods have inherent limitations in terms of physical size, power consumption, and cost efficiency, hindering their ability to meet evolving performance requirements. Therefore, increasing bandwidth density without compromising signal integrity has become a core focus of advancements in modern interconnect architecture technology.

[0003] To address this challenge, researchers have explored various strategies, including novel architectural designs, significant adjustments to the linewidth / spacing ratio, and directly increasing the data rate. However, with the substantial reduction in channel spacing, the enhanced electromagnetic coupling between adjacent conductors significantly exacerbates crosstalk impairment. This necessitates the development of advanced crosstalk cancellation (XTC) coding.

[0004] Current solutions for high-density bare D2D (Die-to-Die) interfaces fall into two categories: package-level engineering and circuit-level technology. Package-level methods involve spacing strategies, swing optimization to reduce worst-case coupling delays in long parallel lines, and serpentine protection routing, among others. However, these methods introduce significant area overhead and routing complexity, contradicting the cost-efficiency requirements of high-density applications. Circuit-level solutions, such as unit-interval pulse shaping and multi-valued signaling, mitigate crosstalk but impose stringent accuracy requirements on the analog front-end. Therefore, XTC encoding emerged to meet these needs. Commonly used encoding methods include Fibonacci encoding (FC), bit-inverted encoding (BI), special increment encoding, non-adjacent transformation codes (NATs), SDT-free encoding, and JCI encoding. Among these, Fibonacci encoding exhibits excellent crosstalk suppression capabilities. However, a key limitation is that an n-bit Fibonacci code can only represent decimal values ​​up to F(n+2)-1, where F(n+2) represents the (n+2)th term of the Fibonacci sequence. For example, Fibonacci encoding of 5-bit binary data requires at least 7 bits, which means two redundant bits are needed. Therefore, challenges remain regarding XTC ratio and pin efficiency. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a 5b-6b crosstalk cancellation transceiver, chip and device for inter-chip interconnection, which addresses the above-mentioned problems of the prior art. The present invention aims to combine crosstalk cancellation coding with channel characteristics to maximize bandwidth and edge density while maintaining signal integrity. By reducing inter-channel bit conversion, it reduces far-end crosstalk (FEXT) between lines and improves crosstalk suppression performance, thereby enhancing the ability to maintain signal integrity in high-density interconnection.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: A 5b-6b crosstalk cancellation transceiver for inter-chip interconnection includes a transmitter, a receiver, and a clock module. The transmitter and receiver are interconnected, and the clock input is connected to the output of the clock module. The transmitter includes an encoder for implementing inter-channel bit smoothing encoding, and the receiver includes a decoder for implementing inter-channel bit smoothing decoding. Inter-channel bit smoothing encoding refers to smoothly encoding 5-bit binary data into 6-bit encoded data, and inter-channel bit smoothing decoding refers to smoothly decoding 6-bit encoded data into 5-bit binary data. The conversion relationship between 5-bit binary data and 6-bit encoded data during inter-channel bit smoothing encoding and decoding is as follows: 00000 corresponds to 000000; 00001 corresponds to 000001; 00010 corresponds to 000011; 00011 corresponds to 000110; 00100 corresponds to 000111; 00101 corresponds to 001100; 00110 corresponds to 001110; 00111 corresponds to 001111; 01000 corresponds to 011000; 01001 corresponds to 011001; 01010 corresponds to 011100; 01011 corresponds to 011110; 01100 corresponds to 011111; 01101 corresponds to 100000; 01110 corresponds to 100001; 01111 corresponds to 100011; 10000 corresponds to 100110; 10001 corresponds to 100111; 10010 corresponds to 110000; 10011 corresponds to 110001; 10100 corresponds to 110011; 10101 corresponds to 111000; 10110 corresponds to 111001; 10111 corresponds to 111011; 11000 corresponds to 111110; 11001 corresponds to 111111; 11010 corresponds to 000010; 11011 corresponds to 000100; 11100 corresponds to 001000; 11101 corresponds to 001001; 11110 corresponds to 001101; 11111 corresponds to 010000.

[0007] Optionally, the transmitter includes two encoders and six data multiplexing and amplification circuits. The 10-bit raw data input to the transmitter is encoded by the two encoders to obtain 12-bit encoded data. The 12-bit encoded data is multiplexed and amplified by the six data multiplexing and amplification circuits to obtain a 6-bit parallel data signal for output to the receiver. The clock input terminal of the data multiplexing and amplification circuit is connected to the output terminal of the clock module.

[0008] Optionally, the data multiplexing and amplification circuit includes a 2:1 multiplexer, a pre-driver, and an SST driver connected in sequence, wherein the clock input of the 2:1 multiplexer is connected to the output of the clock module.

[0009] Optionally, the receiver includes a buffer amplifier (BUF), a comparator array, and two decoders. The input 6-bit parallel data signal is first stabilized by the buffer amplifier (BUF) to obtain a voltage level, then the comparator array performs analog-to-digital conversion to obtain 12-bit encoded data, and finally the two decoders recover the 10-bit original data. The clock input of the comparator array is connected to the output of the clock module.

[0010] Optionally, the comparator array consists of multiple parallel comparators, each including transistors M1 to M10. Transistors M1 to M6 are PMOS transistors, and transistors M7 to M10 are NMOS transistors. Transistors M7 and M9 are connected in parallel, their sources connected to the power supply VDD, and their drains are grounded sequentially through transistors M5, M3, and M1. Transistors M8 and M10 are connected in parallel, their sources connected to the power supply VDD, and their drains are grounded sequentially through transistors M6, M4, and M2. The gates of transistors M9 and M10 are both connected to the clock signal CLK. The gate of transistor M7 is connected to the drain of transistor M8, and the gate of transistor M8 is connected to the drain of transistor M7. The gates of transistors M5 and M6 are both connected to the clock signal CLK. The gate of transistor M3 is connected to the drain of transistor M6, and the gate of transistor M4 is connected to the drain of transistor M5. The gate of transistor M1 is connected to the first input signal V. in1 The gate of transistor M2 is connected to the second input signal V. in2 Connected.

[0011] Optionally, the transmitter and receiver are connected via an on-chip channel, which includes six signal transmission lines for transmitting 6-bit parallel data signals.

[0012] Optionally, the line width of the six signal transmission lines is 0.5 µm, and the spacing between adjacent signal transmission lines is 0.5 µm.

[0013] Optionally, the length of the six signal transmission lines is 4 mm.

[0014] The present invention also provides a chip comprising a plurality of chips, wherein adjacent chips are provided with the aforementioned 5b-6b inter-chip interconnect crosstalk cancellation transceiver.

[0015] The present invention also provides an electronic device including a processor and a memory interconnected thereto, wherein the processor includes the aforementioned 5b-6b crosstalk cancellation transceiver for inter-chip interconnection.

[0016] Compared with the prior art, the present invention mainly has the following beneficial effects: The 5b-6b crosstalk cancellation transceiver for inter-chip interconnection of the present invention includes a transmitter, a receiver and a clock module. The transmitter includes an encoder for implementing inter-channel bit smoothing encoding, and the receiver includes a decoder for implementing inter-channel bit smoothing decoding. Inter-channel bit smoothing encoding refers to smoothly encoding 5-bit binary data into 6-bit encoded data, and inter-channel bit smoothing decoding refers to smoothly decoding 6-bit encoded data into 5-bit binary data. The present invention combines crosstalk cancellation encoding with channel characteristics to maximize bandwidth and edge density while maintaining signal integrity. By reducing inter-channel bit conversion, it reduces far-end crosstalk (FEXT) between lines and improves crosstalk suppression performance, thereby enhancing the ability to maintain signal integrity in high-density interconnection. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the 5b-6b crosstalk cancellation transceiver for inter-chip interconnection in an embodiment of the present invention.

[0018] Figure 2 This is a schematic diagram of the crosstalk interaction between the interfering line and the victim line in an embodiment of the present invention.

[0019] Figure 3 This is a comparison of signal waveforms with and without ICBS encoding under 0D crosstalk conditions in this embodiment of the invention.

[0020] Figure 4 This is a comparison of signal waveforms with and without ICBS encoding under 4D crosstalk conditions in this embodiment of the invention.

[0021] Figure 5 This is the crosstalk suppression performance of the encoding in the 5-bit binary data transmission embodiment of the present invention, where (a) is the complete crosstalk distribution observed on the victim line during 5-bit data transmission, and (b) is the crosstalk characteristics after ICBS encoding.

[0022] Figure 6 This invention presents a comparison of the crosstalk amplitude characteristics on the victim line before and after ICBS encoding in signal transmission, where (a) represents the crosstalk amplitude characteristics on the victim line before ICBS encoding, and (b) represents the crosstalk amplitude characteristics on the victim line after ICBS encoding.

[0023] Figure 7 The results are the signal timing analysis of the interfering line and the victim line in this embodiment of the invention.

[0024] Figure 8 The present invention provides a comparison of improvements to the comparator in the embodiments of the present invention, wherein (a) is the circuit schematic of the existing comparator and (b) is the circuit schematic of the improved comparator.

[0025] Figure 9 This is a schematic diagram of the principle structure of the on-chip channel in an embodiment of the present invention.

[0026] Figure 10 for Figure 9 The experimental results for the on-chip channel are shown.

[0027] Figure 11 This is a schematic diagram showing the edge density comparison in an embodiment of the present invention.

[0028] Figure 12 The images show eye diagrams before and after ICBS encoding at a data rate of 15 Gbps in this embodiment of the invention, where (a) is the eye diagram before ICBS encoding and (b) is the eye diagram after ICBS encoding.

[0029] Figure 13 The images show eye diagrams before and after ICBS encoding at a data rate of 20 Gbps in this embodiment of the invention, where (a) is the eye diagram before ICBS encoding and (b) is the eye diagram after ICBS encoding. Detailed Implementation

[0030] This invention, a 5b-6b crosstalk cancellation transceiver for inter-chip interconnects, aims to integrate coding techniques to optimize signal integrity and transmission reliability in high-speed interconnects. To enable those skilled in the art to better understand the technical solution of this invention, the following will provide a more detailed description of the technical solution in conjunction with the accompanying drawings of the embodiments of this invention.

[0031] like Figure 1As shown, this embodiment provides a 5b-6b crosstalk cancellation transceiver for inter-chip interconnection, including a transmitter, a receiver, and a clock module. The transmitter and receiver are interconnected, and the clock input is connected to the output of the clock module. The transmitter includes an encoder for implementing inter-channel bit smoothing encoding, and the receiver includes a decoder for implementing inter-channel bit smoothing decoding. Inter-channel bit smoothing encoding refers to smoothly encoding 5-bit binary data into 6-bit encoded data, and inter-channel bit smoothing decoding refers to smoothly decoding 6-bit encoded data into 5-bit binary data. As shown in Table 1, the conversion relationship between 5-bit binary data and 6-bit encoded data during inter-channel bit smoothing encoding and decoding is as follows: 00000 corresponds to 000000; 00001 corresponds to 000001; 00010 corresponds to 000011; 00011 corresponds to 000110; 00100 corresponds to 000111; 00101 corresponds to 001100; 00110 corresponds to 001110; 00111 corresponds to 001111; 01000 corresponds to 011000; 01001 corresponds to 011001; 01010 corresponds to 011100; 01011 corresponds to 011110; 01100 corresponds to 011111; 01101 corresponds to 100000; 01110 corresponds to 100001; 01111 corresponds to 100011; 10000 corresponds to 100110; 10001 corresponds to 100111; 10010 corresponds to 110000; 10011 corresponds to 110001; 10100 corresponds to 110011; 10101 corresponds to 111000; 10110 corresponds to 111001; 10111 corresponds to 111011; 11000 corresponds to 111110; 11001 corresponds to 111111; 11010 corresponds to 000010; 11011 corresponds to 000100; 11100 corresponds to 001000; 11101 corresponds to 001001; 11110 corresponds to 001101; 11111 corresponds to 010000.

[0032] Table 1: Conversion Relationship between 5-bit binary data and 6-bit encoded data

[0033] The following section will explain the technical effects of inter-channel bit smoothing encoding and decoding in this embodiment, based on the principle of crosstalk. Crosstalk not only affects the signal swing by introducing external noise, but also causes a delay in the transition characteristics of the original signal. This interference significantly reduces signal integrity and system performance, especially in high-speed and precision-dependent applications. When an input voltage is applied to the interfering line, the far-end crosstalk induced on the affected line can be expressed as: , in, For the remote crosstalk caused on the affected line, It is a constant. Input voltage, For transfer functions, Indicates the voltage Take the derivative. Since the derivative reflects the rate of change, crosstalk can be standardized in the digital domain. For ease of discussion, we will temporarily ignore the coupling effect between non-adjacent channels. Figure 2 This is a schematic diagram of the crosstalk interaction between the interfering line and the victim line, where C C Indicates the coupling capacitance between channels. Indicates from jump to , As a switching voltage, XT i Let represent the crosstalk of interfering line i to the victim line, where i = 0, 1, ..., N. In this case, the absolute value of the crosstalk of any interfering line i to the victim line during transmission. Defined as: , in, It is a constant related to the coupling capacitance and signal swing. , and This represents the normalized voltage change of the nth channel during transmission (when...). When the value is 0, there is no data transition, so discussing jitter and delay caused by crosstalk is meaningless. In high-speed interconnects, signal degradation caused by crosstalk is a critical issue, manifesting as delay variations and timing jitter. System analysis revealed that in the 010→101 transition mode, the maximum crosstalk amplitude is... The minimum was observed during the data conversion from 000 to 111. Crosstalk.

[0034] Figure 3 and Figure 4 Experimental verification was provided. Figure 3 and Figure 4In the code, w / o coding represents the case without inter-channel bit smoothing coding, w ICBS represents the case with inter-channel bit smoothing coding, and XT free represents the case without crosstalk. For example... Figure 3 As shown, when the 5-bit binary data changes in a unidirectional manner, the crosstalk coupling on the victim line is negligible. Conversely, Figure 4 This indicates that the 010→101 mode is generated during transmission. The peak crosstalk amplitude. It is worth noting that, through advanced coding optimization strategies, this crosstalk amplitude can be effectively reduced to [amount missing]. These results indicate that high-intensity crosstalk modes can be eliminated through mode selection ( and It can significantly improve signal integrity.

[0035] In this embodiment, inter-channel bit smoothing encoding and decoding based on ICBS code-based crosstalk cancellation (XTC) minimize far-end crosstalk (FEXT) while maintaining transmission efficiency. As mentioned earlier, the 010→101 transition pattern can cause severe crosstalk coupling; therefore, the encoding schemes for inter-channel bit smoothing encoding and decoding in this embodiment are specifically designed to suppress such high-impact bit transitions. Experimental results show that by eliminating the 010→101 transition pattern, inter-channel crosstalk is attenuated by 40.07%. Compared with Fibonacci encoding, pin efficiency is improved by 16.67%, while achieving superior crosstalk cancellation performance. Figure 5 (a) in the image visualizes the complete crosstalk distribution observed on the victim line during 5-bit data transmission in blue, showing that the peak crosstalk amplitude reaches 4 D under this configuration. In contrast, Figure 5 (b) in the figure shows the crosstalk characteristics after ICBS encoding, indicating that crosstalk is effectively suppressed in all test scenarios. Figure 6 The crosstalk amplitude characteristics of the victim line before and after encoding were compared during signal transmission. Figure 6 (a) in the figure represents the crosstalk amplitude characteristics on the victim line before ICBS encoding. Figure 6 (b) shows the crosstalk amplitude characteristics on the victim line after ICBS encoding. Experimental results show that the average crosstalk amplitude decreased from 1.335 D to 0.802 D after ICBS encoding, achieving a significant suppression of 40.07%. Figure 7 The timing diagram illustrates the working principle of XTC: the black curve represents the original transmitted signal, and the red waveform represents the distorted signal affected by crosstalk coupling from adjacent interference lines. It is evident that this coding strategy effectively mitigates signal distortion caused by crosstalk, highlighting the robustness of the proposed scheme.

[0036] See Figure 1In this embodiment, the 5b-6b crosstalk cancellation transceiver for inter-chip interconnection mainly consists of a transmitter (TX) and a receiver (RX) subsystem, which are synchronized through a clock module. The clock module has a phase interpolation circuit (PI) and a CML-to-CMOS converter for stabilizing the clock signal conditioning.

[0037] As an optional experimental verification method, this embodiment uses a pseudo-random binary sequence (PRBS) generator as the signal generation module. In practical applications, it can be modified to use the desired signal generation module.

[0038] like Figure 1 As shown, in this embodiment, the transmitter includes two encoders and six data multiplexing and amplification circuits. The 10-bit raw data input to the transmitter is encoded by the two encoders to obtain 12-bit encoded data. The 12-bit encoded data is multiplexed and amplified by the six data multiplexing and amplification circuits to obtain a 6-bit parallel data signal for output to the receiver. The clock input terminal of the data multiplexing and amplification circuit is connected to the output terminal of the clock module.

[0039] In this embodiment, the data multiplexing and amplification circuit includes a 2:1 multiplexer (2:1 MUX), a pre-driver, and an SST driver connected in sequence. The clock input of the 2:1 multiplexer is connected to the output of the clock module. The encoded signal is passed through an inter-channel bit smoothing decoder (2:1 MUX), and then amplified by a cascaded circuit driven by the pre-driver and the inter-channel bit smoothing decoder (SST). This circuit is designed to match the channel impedance characteristics, and six parallel channels transmit the signal to the receiver (RX).

[0040] like Figure 1 As shown, in this embodiment, the receiver includes a buffer amplifier (BUF), a comparator array, and two decoders. The input 6-bit parallel data signal is first stabilized by the buffer amplifier (BUF) to obtain a voltage level, then the comparator array performs analog-to-digital conversion to obtain 12-bit encoded data, and finally the two decoders recover the original 10-bit data. The clock input of the comparator array is connected to the output of the clock module. In this embodiment, the decoder output is sent to a receiver that uses a signal verification module (specifically, a PRBS inter-channel bit smoothing decoder) as the data signal. In practical applications, this can be changed to any desired signal receiving module. The PRBS inter-channel bit smoothing decoder verifies data integrity by monitoring the bit error rate in real time.

[0041] Figure 8 This embodiment presents an improvement and comparison of the comparator, where (a) is the circuit schematic of the existing comparator and (b) is the circuit schematic of the improved comparator. The comparator array consists of multiple comparators in parallel, such as... Figure 8As shown in (b), the comparator in this embodiment includes transistors M1 to M10, where transistors M1 to M6 are PMOS transistors, and transistors M7 to M10 are NMOS transistors. Transistors M7 and M9 are connected in parallel with their sources connected to the power supply VDD, and their drains are grounded sequentially through transistors M5, M3, and M1. Transistors M8 and M10 are connected in parallel with their sources connected to the power supply VDD, and their drains are grounded sequentially through transistors M6, M4, and M2. The gates of transistors M9 and M10 are both connected to the clock signal CLK. The gate of transistor M7 is connected to the drain of transistor M8, and the gate of transistor M8 is connected to the drain of transistor M7. The gates of transistors M5 and M6 are both connected to the clock signal CLK. The gate of transistor M3 is connected to the drain of transistor M6, and the gate of transistor M4 is connected to the drain of transistor M5. The gate of transistor M1 is connected to the first input signal V. in1 The gate of transistor M2 is connected to the second input signal V. in2 Connected. In this embodiment, a novel comparator with a specially designed structure is integrated into the receiver, such as... Figure 8 As shown in (a), in a conventional comparator, the gate of the transistor on the ground side provides the clock for the input device, such as... Figure 8 As shown in (b) of this embodiment, the novel comparator provides a clock to the input device through the drain path (instead of the source path) and uses inter-channel bit smoothing decoding of transistor M5 and inter-channel bit smoothing decoding of transistor M6 to adjust the latching operation, thereby minimizing feedback noise. This topology effectively suppresses feedback noise caused by differential-mode and common-mode interaction during the regeneration stage.

[0042] like Figure 1 and Figure 9 As shown, in this embodiment, the transmitter and receiver are connected via an on-chip channel, which includes six signal transmission lines for transmitting 6-bit parallel data signals. Figure 9 The numbers are denoted as N0 to N5, where C c For the content between signal transmission lines, C g This is the capacitance to ground, and GND is ground. For example... Figure 9 As shown, in this embodiment, the line width of the six signal transmission lines is 0.5 µm, and the spacing between adjacent signal transmission lines is 0.5 µm. In this embodiment, the length of the six signal transmission lines is 4 mm.

[0043] Figure 10 for Figure 9The on-chip channel's signal integrity performance at a 7.5 Gbps Nyquist rate is shown: the insertion loss (IL) is -3.12 dB, and far-end crosstalk (FEXT) exhibits a significant proximity-dependent characteristic—nearest neighbor coupling (FEXT1) is -12.1 dB (IL / XT ratio of -4.14 dB), while the second-nearest neighbor coupling (FEXT2) drops to -18.1 dB (ratio of -9.36 dB). Measurement results show that FEXT1 has 6.0 dB higher crosstalk than FEXT2, confirming that nearest neighbor interference is the main source of crosstalk. These results provide experimental validation for crosstalk modeling and suppression strategies in high-speed, high-density interconnect systems.

[0044] Figure 11 This diagram illustrates the edge density comparison in this embodiment, where the horizontal axis represents the year. The hollow triangle represents the edge density of existing solutions for high-density bare D2D interfaces, and the solid triangle represents the edge density of the 5b-6b crosstalk cancellation transceiver for inter-chip interconnects in this embodiment. Compared to existing technologies, this represents a significant improvement in edge density. Minimizing channel spacing can improve interconnect edge density but exacerbates signal degradation caused by crosstalk. To balance this trade-off, this embodiment simulates high-density channels with integrated ICBS coding to derive the optimal edge density that balances geometric constraints and signal integrity. Simulation results show that a maximum edge density of 9.37 Tb / s / mm can be achieved under conditions of 0.5 µm channel spacing, 15 Gbps data rate, and -4.1 dB crosstalk.

[0045] To verify the 5b-6b crosstalk cancellation transceiver based on inter-channel bit smoothing coding (ICBS) in this embodiment, the robustness of this embodiment to changes in operating conditions was studied through numerical simulation comparing uncoded and ICBS-coded transmission systems. The quantization effect of ICBS was investigated, and different data rates and crosstalk intensities were analyzed.

[0046] In this embodiment, an evaluation of inter-channel bit smoothing coding (ICBS) was conducted using eye diagram measurements at data rates of 15 Gbps and 20 Gbps. Figure 12 The images show the eye diagrams before and after ICBS encoding at a data rate of 15Gbps in this embodiment, where (a) is the eye diagram before ICBS encoding and (b) is the eye diagram after ICBS encoding. Figure 13 The images show the eye diagrams before and after ICBS encoding at a data rate of 20Gbps in this embodiment, where (a) is the eye diagram before ICBS encoding and (b) is the eye diagram after ICBS encoding. (Comparison) Figure 12 and Figure 13 It can be seen that a significant improvement in signal integrity was observed under all test conditions: at a data rate of 15Gbps, such as Figure 12As shown, the eye width of the encoded signal increased by 102.2% (from 27.3 ps to 54.2 ps), the eye height increased by 83.7% (from 146.1 mV to 268.4 mV), and the timing jitter decreased by 69.3% (from 36.8 ps to 11.27 ps). At a data rate of 20 Gbps, as... Figure 13 As shown, the encoding strategy remains effective at high speeds, with eye width increasing by 149.4% (from 67.8 ps to 169.1 ps), eye height improving by 213.6% (from 12.5 mV to 39.2 mV), and overall timing jitter decreasing by 67.7% (from 33.3 ps to 10.77 ps). These results demonstrate that the ICBS encoding scheme can suppress both deterministic and random jitter components under different operating conditions.

[0047] This embodiment implements a 5b-6b crosstalk cancellation transceiver based on Inter-Channel Bit Smoothing (ICBS) inter-chip interconnects on a 28nm process. Its parameters are as follows: Data rate: 12.5Gbps / pin; Signal type: Single-ended NRZ; Architecture: Transmitter + Receiver; Driver: SST; Encoding method: Inter-Channel Bit Smoothing (ICBS); Line efficiency: 83%; Channel type: On-chip; Channel length: 4mm; Channel spacing: 0.5 µm; Channel crosstalk: -4.14dB@10GHz; Eye opening: 0.42U1; Jitter improvement: 69.3%; Edge density: 9.37Tb / s / mm. The transceiver in this embodiment achieves XTC (Extreme Crosstalk Cancellation) encoding and decoding by reducing inter-channel bit transitions through ICBS, suppressing high-impact transition modes and achieving 40.07% far-end crosstalk (FEXT) suppression. Simulation results demonstrate a 69.3% reduction in crosstalk-induced jitter (from 36.8 ps to 11.27 ps) at a 12.5 Gb / s / pin data rate and -4.14 dB crosstalk. The transceiver employs a novel comparator architecture, reducing feedback noise and supporting reliable operation with a 0.5 µm channel pitch. These results validate the ability of this embodiment's 5b-6b crosstalk cancellation transceiver based on Inter-Channel Bit Smoothing Coding (ICBS) to maintain signal integrity in next-generation high-density interconnects, outperforming existing solutions while supporting edge densities up to 9.37 Tb / s / mm.

[0048] In addition, this embodiment also provides a chip including multiple chips, with the aforementioned 5b-6b crosstalk cancellation transceiver provided between adjacent chips.

[0049] In addition, this embodiment also provides an electronic device, including a processor and a memory interconnected with each other, wherein the processor includes the aforementioned 5b-6b crosstalk cancellation transceiver for inter-chip interconnection.

[0050] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A 5b-6b crosstalk cancellation transceiver for inter-chip interconnection, comprising a transmitter, a receiver, and a clock module, wherein the transmitter and receiver are interconnected and the clock input terminal is connected to the output terminal of the clock module, characterized in that, The transmitter includes an encoder for implementing inter-channel bit smoothing encoding, and the receiver includes a decoder for implementing inter-channel bit smoothing decoding. Inter-channel bit smoothing encoding refers to smoothly encoding 5-bit binary data into 6-bit encoded data, and inter-channel bit smoothing decoding refers to smoothly decoding 6-bit encoded data into 5-bit binary data. The conversion relationship between 5-bit binary data and 6-bit encoded data during inter-channel bit smoothing encoding and decoding is as follows: 00000 corresponds to 000000; 00001 corresponds to 000001; 00010 corresponds to 000011; 00011 corresponds to 000110; 00100 corresponds to 000111; 00101 corresponds to 001100; 00110 corresponds to 001110; 00111 corresponds to 001111; 01000 corresponds to 011000; 01001 corresponds to 011001; 01010 corresponds to 011100; 01011 corresponds to 011110; 01100 corresponds to 011111; 01101 corresponds to 100000; 01110 corresponds to 100001; 01111 corresponds to 100011; 10000 corresponds to 100110; 10001 corresponds to 100111; 10010 corresponds to 110000; 10011 corresponds to 110001; 10100 corresponds to 110011; 10101 corresponds to 111000; 10110 corresponds to 111001; 10111 corresponds to 111011; 11000 corresponds to 111110; 11001 corresponds to 111111; 11010 corresponds to 000010; 11011 corresponds to 000100; 11100 corresponds to 001000; 11101 corresponds to 001001; 11110 corresponds to 001101; 11111 corresponds to 010000.

2. The 5b-6b crosstalk cancellation transceiver for inter-chip interconnection according to claim 1, characterized in that, The transmitter includes two encoders and six data multiplexing and amplification circuits. The 10-bit raw data input to the transmitter is encoded by the two encoders to obtain 12-bit encoded data. The 12-bit encoded data is then multiplexed and amplified by the six data multiplexing and amplification circuits to obtain a 6-bit parallel data signal for output to the receiver. The clock input terminal of the data multiplexing and amplification circuit is connected to the output terminal of the clock module.

3. The 5b-6b crosstalk cancellation transceiver for inter-chip interconnection according to claim 2, characterized in that, The data multiplexing and amplification circuit includes a 2:1 multiplexer, a pre-driver, and an SST driver connected in sequence. The clock input of the 2:1 multiplexer is connected to the output of the clock module.

4. The 5b-6b crosstalk cancellation transceiver for inter-chip interconnection according to claim 1, characterized in that, The receiver includes a buffer amplifier (BUF), a comparator array, and two decoders. The input 6-bit parallel data signal is first stabilized by the buffer amplifier (BUF) to obtain a voltage level, then the comparator array performs analog-to-digital conversion to obtain 12-bit encoded data, and finally the two decoders recover the 10-bit original data. The clock input of the comparator array is connected to the output of the clock module.

5. The 5b-6b crosstalk cancellation transceiver for inter-chip interconnection according to claim 4, characterized in that, The comparator array consists of multiple parallel comparators, each including transistors M1 to M10. Transistors M1 to M6 are PMOS transistors, and transistors M7 to M10 are NMOS transistors. Transistors M7 and M9 are connected in parallel, their sources connected to the power supply VDD, and their drains are grounded sequentially through transistors M5, M3, and M1. Transistors M8 and M10 are connected in parallel, their sources connected to the power supply VDD, and their drains are grounded sequentially through transistors M6, M4, and M2. The gates of transistors M9 and M10 are both connected to the clock signal CLK. The gate of transistor M7 is connected to the drain of transistor M8, and the gate of transistor M8 is connected to the drain of transistor M7. The gates of transistors M5 and M6 are both connected to the clock signal CLK. The gate of transistor M3 is connected to the drain of transistor M6, and the gate of transistor M4 is connected to the drain of transistor M5. The gate of transistor M1 is connected to the first input signal V. in1 The gate of transistor M2 is connected to the second input signal V. in2 Connected.

6. The 5b-6b crosstalk cancellation transceiver for inter-chip interconnection according to claim 2, characterized in that, The transmitter and receiver are connected via an on-chip channel, which includes six signal transmission lines for transmitting 6-bit parallel data signals.

7. The 5b-6b crosstalk cancellation transceiver for inter-chip interconnection according to claim 6, characterized in that, The line width of the six signal transmission lines is 0.5 µm, and the spacing between adjacent signal transmission lines is 0.5 µm.

8. The 5b-6b crosstalk cancellation transceiver for inter-chip interconnection according to claim 7, characterized in that, The length of the six signal transmission lines is 4 mm.

9. A chip comprising a plurality of chips, characterized in that, Adjacent cores are provided with a 5b-6b crosstalk cancellation transceiver for inter-core interconnection as described in any one of claims 1 to 8.

10. An electronic device comprising a processor and a memory interconnected, characterized in that, The processor includes the 5b-6b crosstalk cancellation transceiver for inter-chip interconnection as described in any one of claims 1 to 8.

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