Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, and electronic equipment, and belongs to the technical field of semiconductors, and the semiconductor device comprises a plurality of layers of storage units which are stacked in the direction perpendicular to a substrate; the memory cell includes: a transistor; the transistor comprises a grid electrode extending in the direction perpendicular to a substrate, a semiconductor layer surrounding the side wall of the grid electrode, and a transition layer surrounding the side wall of the semiconductor layer and making contact with the semiconductor layer. Wherein the transition layer comprises two conductive contact areas which are isolated from each other, and two insulating areas which are positioned between the two conductive contact areas.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, semiconductor technology, and particularly to a semiconductor device and its manufacturing method, and an electronic device. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a semiconductor device and its manufacturing method, as well as an electronic device, which can reduce contact resistance and improve transistor performance.

[0006] This application provides a semiconductor device including multiple layers of memory cells stacked along a direction perpendicular to the substrate;

[0007] The storage unit includes: a transistor;

[0008] The transistor includes: a gate extending in a direction perpendicular to the substrate, a semiconductor layer surrounding a sidewall of the gate, and a transition layer surrounding a sidewall of the semiconductor layer and in contact with the semiconductor layer.

[0009] The transition layer includes two isolated conductive contact areas and two insulating areas located between the two conductive contact areas.

[0010] In some embodiments, the two conductive contact regions of the transition layer comprise metal conductive regions, and the two insulating regions of the transition layer comprise metal oxide insulating regions, wherein the metal conductive regions and the metal oxide insulating regions contain the same metal element.

[0011] In some embodiments, the metal of the conductive region comprises titanium, and the metal oxide of the insulating region comprises titanium oxide; or,

[0012] The metal in the conductive region contains molybdenum, and the metal oxide in the insulating region contains molybdenum oxide; or...

[0013] The metal in the conductive region contains tantalum, and the metal oxide in the insulating region contains tantalum oxide.

[0014] In some embodiments, the two conductive contact regions include a first conductive contact region and a second conductive contact region; the semiconductor device further includes:

[0015] Bit line, the bit line being in contact with the second conductive contact area;

[0016] A capacitor, the capacitor including a first capacitor electrode, the first capacitor electrode being in contact with the first conductive contact area.

[0017] In some embodiments, the first conductive contact area has a U-shaped cross-section perpendicular to the substrate with an opening facing the first capacitor electrode, and a source / drain electrode is disposed within the opening, the source / drain electrode being in contact with both the first conductive contact area and the first capacitor electrode.

[0018] In some embodiments, the first capacitor electrode is a hollow cylindrical structure with an opening away from the semiconductor layer, and the bottom of the cylindrical structure is connected to the semiconductor layer through the source / drain electrode.

[0019] In some embodiments, the capacitor further includes a second capacitor electrode located within the opening of the cylindrical structure of the first capacitor electrode and connected to the first capacitor electrode through a capacitor dielectric layer.

[0020] In some embodiments, the second conductive contact region is annular in cross-section perpendicular to the substrate, the bit line extends in a direction parallel to the substrate, and the second conductive contact region surrounds the sidewalls of the bit line; the semiconductor layer includes a first region in contact with the first conductive contact region, the first region having the same shape and size as the first conductive contact region.

[0021] In some embodiments, the semiconductor layer includes a second region that contacts the outer surface of the second conductive contact region, the second region surrounding the second conductive contact region, and the second region having the same shape and size as the second conductive contact region.

[0022] In some embodiments, the system further includes multiple rows and columns of memory cells located on the same layer, with a bit line provided between the transistors of two adjacent columns of memory cells, and the second region of the semiconductor layer shared by two adjacent transistors.

[0023] In some embodiments, the semiconductor layer includes a metal oxide semiconductor layer.

[0024] In some embodiments, the system further includes multiple rows and columns of memory cells located on the same layer, with an isolation layer disposed between transistors of two adjacent memory cells in the column direction, and the two insulating regions of the transition layer contacting the isolation layer.

[0025] This application also provides a method for manufacturing a semiconductor device, including:

[0026] A substrate is provided on which insulating thin films and sacrificial thin films are sequentially and alternately deposited to form a stacked structure;

[0027] A plurality of first holes are formed in the stacked structure extending in a direction perpendicular to the substrate, and word line sacrificial layers are filled in the first holes;

[0028] The stacked structure forms a plurality of first trenches, and between the plurality of first trenches are bit line regions extending along the column direction, and a plurality of branch regions that are spaced apart in the column direction and extend in the row direction and intersect the bit line regions, wherein the first hole is located in the branch regions.

[0029] An isolation layer is filled into the first trench;

[0030] The sacrificial film of multiple branch regions is etched away to form a transverse groove extending in the row direction between adjacent isolation layers and adjacent insulating films, and a portion of the sacrificial film layer is retained between the transverse groove and the word line sacrificial layer;

[0031] A first capacitor electrode and a capacitor dielectric layer are sequentially deposited on the inner wall of the transverse groove, and a second capacitor electrode is filled in the transverse groove.

[0032] An opening is formed in the isolation layer of the first trench to vertically substrate the opening, which exposes the sacrificial film between the word line sacrificial layer and the first capacitor electrode, as well as the sacrificial film layer of the bit line region; the sacrificial film is etched away to form a first via corresponding to the word line sacrificial layer and the first capacitor electrode, and a second via corresponding to the bit line region, the first via and the second via being connected and exposing each sidewall of the word line sacrificial layer;

[0033] A gate insulating layer, a semiconductor thin film, a metal thin film, and a conductive thin film filling the first and second vias are sequentially deposited on the inner walls of the first and second vias; the gate insulating layer, the semiconductor thin film, and the metal thin film surround the sidewalls of the exposed word line sacrificial layer;

[0034] Remove the conductive film filling the opening to expose the metal film on the two opposite sidewalls of the word line sacrificial layer in the column direction. Then, oxidize the exposed metal film using an oxidation process to form a metal oxide insulating region.

[0035] In some embodiments, after removing the conductive film filling the opening to expose the metal film on the two opposite sidewalls of the word line sacrificial layer in the column direction, the method further includes:

[0036] Remove the semiconductor thin film within the opening to disconnect the semiconductor thin films of different transistor layers from each other.

[0037] In some embodiments, after the oxidation process is used to oxidize the exposed metal film to form a metal oxide insulating region, the process further includes:

[0038] An insulating layer is filled into the opening;

[0039] An opening is made in the isolation layer to expose each gate insulating layer, semiconductor thin film and metal thin film near the first capacitor electrode. The area in the gate insulating layer that contacts the first capacitor electrode is etched away, and a conductive layer is filled in the area where the gate insulating layer is removed, so that the conductive layer contacts both the first capacitor electrode and the metal thin film.

[0040] The word line sacrificial layer is etched away to expose the inner wall of the first hole, and word lines are formed in the first hole.

[0041] In some embodiments, forming an opening in the isolation layer of the first trench that is perpendicular to the substrate includes:

[0042] Multiple openings are spaced apart along the column direction, the openings being located between adjacent branch regions in the column direction, the sidewalls of the openings exposing each insulating film and each sacrificial film between the word line sacrificial layer and the first capacitor electrode, and the sidewalls of the openings not exposing the word line sacrificial layer.

[0043] In some embodiments, the second via is located between two adjacent word line sacrificial layers in the row direction and exposes a portion of the sidewalls of the two word line sacrificial layers.

[0044] In some embodiments, the etching process removes the region of the gate insulating layer that contacts the first capacitor electrode, and fills the region where the gate insulating layer has been removed with a conductive layer, including:

[0045] The gate insulating layer in contact with the first capacitor electrode and the semiconductor thin film located near the first capacitor electrode are etched away, and a conductive layer is filled in; or, the gate insulating layer in contact with the first capacitor electrode, the semiconductor thin film and a portion of the metal thin film located near the first capacitor electrode are etched away, exposing the conductive thin film, and a conductive layer is filled in.

[0046] This application provides an electronic device that includes the semiconductor device described in any of the above embodiments.

[0047] In the semiconductor device of this disclosure, the region where the semiconductor layer contacts the electrode includes a transition layer, which simultaneously includes a conductive contact region and an insulating layer between the two conductive contact regions, simplifying the device structure and manufacturing process.

[0048] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description and the drawings.

[0049] After reading and understanding the accompanying diagrams and detailed descriptions, other aspects can be understood. Attached Figure Description

[0050] The accompanying drawings are provided to further understand the technical solutions of this disclosure and constitute a part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of the present invention and do not constitute a limitation on the technical solutions.

[0051] Figure 1 A schematic cross-sectional view of a semiconductor device provided in an embodiment of this disclosure, along a direction parallel to the substrate.

[0052] Figure 2a A schematic cross-sectional view of the memory cell of a semiconductor device provided in an embodiment of this disclosure, along the direction parallel to the substrate.

[0053] Figure 2b for Figure 1 A cross-sectional view of the provided semiconductor device along the a-a' direction;

[0054] Figure 2c for Figure 1 A cross-sectional view of the provided semiconductor device along the c-c' direction;

[0055] Figure 2d for Figure 1 A cross-sectional view of the provided semiconductor device in the b-b' direction;

[0056] Figure 2e for Figure 1 A cross-sectional view of the provided semiconductor device in the d-d' direction;

[0057] Figure 3a This is a schematic diagram of the longitudinal section of the stacked structure;

[0058] Figure 3b This is a top view of the stacked structure;

[0059] Figure 4a for Figure 1 A cross-sectional view in the a-a' direction after the word line sacrificial layer is formed during the manufacturing process of the provided semiconductor device;

[0060] Figure 4b for Figure 1 A cross-sectional view in the c-c' direction after the word line sacrificial layer is formed during the manufacturing process of the provided semiconductor device;

[0061] Figure 4c for Figure 1 A schematic diagram showing the formation of a word line sacrificial layer in a direction parallel to the substrate during the manufacturing process of the provided semiconductor device;

[0062] Figure 5a for Figure 1 A cross-sectional view in the c-c' direction after the isolation layer is formed during the manufacturing process of the provided semiconductor device;

[0063] Figure 5b for Figure 1 A cross-sectional view in the b-b' direction after the isolation layer is formed during the manufacturing process of the provided semiconductor device;

[0064] Figure 5c for Figure 1 A cross-sectional view in the d-d' direction after the isolation layer is formed during the manufacturing process of the provided semiconductor device;

[0065] Figure 5d for Figure 1 A schematic diagram showing the formation of an isolation layer parallel to the substrate during the manufacturing process of the provided semiconductor device;

[0066] Figure 6a for Figure 1 A cross-sectional view in the a-a' direction after the lateral trench is formed during the manufacturing process of the provided semiconductor device;

[0067] Figure 6b for Figure 1 A cross-sectional view in the b-b' direction after the lateral trench is formed during the manufacturing process of the provided semiconductor device;

[0068] Figure 6c for Figure 1 A cross-sectional view in the d-d' direction after the lateral trench is formed during the manufacturing process of the provided semiconductor device;

[0069] Figure 6d for Figure 1 A schematic diagram showing the semiconductor device after a lateral trench is formed in the manufacturing process, parallel to the substrate direction;

[0070] Figure 7a for Figure 1 A cross-sectional view in the a-a' direction after the capacitor is formed during the manufacturing process of the provided semiconductor device;

[0071] Figure 7b for Figure 1A cross-sectional view in the b-b' direction after the capacitor is formed during the manufacturing process of the provided semiconductor device;

[0072] Figure 8a for Figure 1 A cross-sectional view in the c-c' direction after an opening is formed during the manufacturing process of the provided semiconductor device;

[0073] Figure 8b for Figure 1 A cross-sectional view in the b-b' direction after an opening is formed during the manufacturing process of the provided semiconductor device;

[0074] Figure 8c for Figure 1 A schematic diagram showing the semiconductor device after an opening is formed during the manufacturing process, in a direction parallel to the substrate;

[0075] Figure 9a for Figure 1 The provided semiconductor device is shown in a cross-sectional view along the a-a' direction after the formation of the gate insulating layer, semiconductor thin film, metal thin film and fourth conductive thin film during the manufacturing process.

[0076] Figure 9b for Figure 1 The provided semiconductor device is shown in a cross-sectional view along the c-c' direction after the formation of the gate insulating layer, semiconductor thin film, metal thin film and fourth conductive thin film during the manufacturing process.

[0077] Figure 9c for Figure 1 The provided semiconductor device is shown in a cross-sectional view in the d-d' direction after the formation of the gate insulating layer, semiconductor thin film, metal thin film and fourth conductive thin film during the manufacturing process.

[0078] Figure 10a for Figure 1 A cross-sectional view in the c-c' direction after the insulating region is formed during the manufacturing process of the provided semiconductor device;

[0079] Figure 10b for Figure 1 A cross-sectional view in the b-b' direction after the insulating region is formed during the manufacturing process of the provided semiconductor device;

[0080] Figure 11a for Figure 1 A cross-sectional view in the a-a' direction after the second hole and semiconductor layer are formed during the manufacturing process of the provided semiconductor device;

[0081] Figure 11b for Figure 1 A cross-sectional view in the b-b' direction after the second hole and semiconductor layer are formed during the manufacturing process of the provided semiconductor device. Detailed Implementation

[0082] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments of this disclosure and the features thereof can be combined arbitrarily with each other.

[0083] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention pertains.

[0084] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values ​​shown in the drawings.

[0085] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0086] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a semiconductor layer region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the semiconductor layer region, and the source electrode. In this disclosure, the semiconductor layer region refers to the region through which current primarily flows.

[0087] In this disclosure, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0088] In this disclosure, the terms "film" and "layer" can be interchanged. For example, "conductive layer" can sometimes be replaced with "conductive film". Similarly, "insulating film" can sometimes be replaced with "insulating film".

[0089] The phrase "A and B are set on the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process. "The orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0090] This disclosure provides a semiconductor device including multiple layers of memory cells stacked in a direction perpendicular to a substrate;

[0091] The storage unit includes: a transistor;

[0092] The transistor includes: a gate extending in a direction perpendicular to the substrate, a semiconductor layer surrounding a sidewall of the gate, and a transition layer surrounding a sidewall of the semiconductor layer and in contact with the semiconductor layer.

[0093] The transition layer includes two isolated conductive contact areas and two insulating areas located between the two conductive contact areas.

[0094] Figure 1 This is a schematic cross-sectional view of a semiconductor device provided in an embodiment of the present disclosure, along a direction parallel to the substrate. Figure 2a This is a schematic cross-sectional view of a memory cell in a semiconductor device provided in an embodiment of the present disclosure, parallel to the substrate direction. In an exemplary embodiment, as shown... Figure 1 and Figure 2a As shown, in the direction parallel to the substrate, the semiconductor device provided in this embodiment may include a multi-layer memory cell array stacked in a direction perpendicular to the substrate. Each layer of the memory cell array includes multiple rows and columns of memory cells, word lines 5, and bit lines 7. The word lines 5 extend in a direction perpendicular to the substrate and penetrate the memory cells in different layers. The bit lines 7 extend in a direction parallel to the substrate and are connected to one or two columns of memory cells in the same layer.

[0095] In one exemplary embodiment, the memory cell includes a transistor, a source / drain 60, and a transition layer 70. The transistor includes a semiconductor layer 3, the main surface of which extends along and surrounds the sidewall of the word line 5, forming a ring extending in a direction perpendicular to the substrate. A gate insulating layer 2 is disposed between the semiconductor layer 3 and the word line 5. The transistor also includes a gate 6 extending in a direction perpendicular to the substrate, the gate 6 being a part of the word line 5, and the gate 6 having sidewalls extending toward the substrate. The main surface of the semiconductor layer 3 can be understood as the main surface of a film layer, where the main surface of the film layer has an area much larger than the thickness of the film layer.

[0096] The semiconductor layer is a ring surrounding the word line or gate. The transition layer also includes a ring-shaped structure surrounding the outer wall of the semiconductor layer. Each region of the transition layer surrounding the semiconductor layer is a continuous, identical film layer, which can be understood as forming the transition layer surrounding the semiconductor layer in a single deposition process. The film thickness is the same in each region of the transition layer.

[0097] In one exemplary embodiment, the gate 6 is part of the word line 5 and its cross-section can be circular, elliptical, etc.

[0098] In an exemplary embodiment, the outer wall of the semiconductor layer 3 is connected to the bit line 7 on one side of the first direction D1, and the outer wall of the semiconductor layer 3 is connected to the source / drain 60 on the other side of the first direction D1.

[0099] In an exemplary embodiment, a transition layer 70 extends along and surrounds the outer wall of the semiconductor layer 3, forming a ring with its main surface extending toward the substrate. The transition layer 70 includes two conductive contact regions 4 that respectively contact the bit line 7 and the source / drain 60, and two insulating regions 1 located between the two conductive contact regions 4. The two conductive contact regions 4 of the transition layer 70 are isolated from each other, and the patterns of the two conductive contact regions 4 and the two insulating regions 1 of the transition layer 70 are complementary, combining to form a ring-shaped structure surrounding the outer wall of the semiconductor layer 3.

[0100] In an exemplary embodiment, the transition layer 70 has a rectangular cross-section parallel to the substrate direction. Two conductive contact regions 4 of the transition layer 70 are located on opposite sides of the outer wall of the semiconductor layer 3 in the first direction D1, and are in direct contact with the outer wall of the semiconductor layer 3. The source / drain electrode 60 and the bit line 7 are connected to the semiconductor layer 3 through the two conductive contact regions 4, respectively. Two insulating regions 1 of the transition layer 70 are located on opposite sides of the outer wall of the semiconductor layer 3 in the second direction D2, and are in direct contact with the outer wall of the semiconductor layer 3 in the second direction D2. Wherein, both the first direction D1 and the second direction D2 are parallel to the substrate, and the first direction D1 and the second direction D2 intersect each other. For example, the first direction D1 can be the row direction of the semiconductor device, and the second direction D2 can be the column direction of the semiconductor device. The first direction D1 and the second direction D2 are perpendicular to each other.

[0101] In an exemplary embodiment, a first conductive contact region 401 and a second conductive contact region 402 in a transition layer are respectively provided on opposite sides of the outer wall of the semiconductor layer 3 in the first direction D1. The first conductive contact region 401 is located between the semiconductor layer 3 and the source / drain electrode 60, and the first conductive contact region 401 is in direct contact with both the outer wall of the semiconductor layer 3 and the source / drain electrode 60. The source / drain electrode 60 is connected to the outer wall of the semiconductor layer 3 through the first conductive contact region 401. The second conductive contact region 402 is located between the semiconductor layer 3 and the bit line 7, and the second conductive contact region 402 is in direct contact with both the outer wall of the semiconductor layer 3 and the bit line 7. The bit line 7 is connected to the outer wall of the semiconductor layer 3 through the second conductive contact region 402.

[0102] In an exemplary embodiment, the semiconductor layer 3 includes two semiconductor contact regions 301 extending along a second direction D2, and a channel region 302 extending along a first direction D1 and located between the two semiconductor contact regions 301. The channel region 302 contacts the insulating region 1 of the transition layer 70. The semiconductor contact regions 301 are in contact with the bit line 7 and the source / drain electrode 60 through the two conductive contact regions 4 of the transition layer, respectively.

[0103] In an exemplary embodiment, the semiconductor layer 3 may be a metal oxide semiconductor material. The metal oxide semiconductor material may be indium gallium zinc oxide (IGZO), InGaO, ITO, IZO, metal oxides containing In and / or Sn, etc. When the metal oxide material is IGZO, the transistor leakage current is relatively small (leakage current less than or equal to 1E). -15 A to 1E -10 A), where 1E -15 A refers to 10 to the power of negative 15 amperes, 1E -10 A refers to 10 to the power of negative 10 amperes, thus ensuring the low refresh rate of the dynamic memory. It should be noted that the metal oxide material can also be IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZOx, etc., as long as the transistor leakage current meets the requirements. Specific adjustments can be made according to the actual situation.

[0104] In one exemplary embodiment, the two conductive contact regions 4 of the transition layer 70 include metal conductive regions, and the insulating region 1 of the transition layer 70 includes metal oxide insulating regions. The metal conductive regions and the metal oxide insulating regions contain the same metal element. The metal has the following characteristics: it satisfies insulation properties when oxidized, or it can become a metal oxide insulating film after oxidation.

[0105] In one exemplary embodiment, the metal of the conductive region comprises titanium, and the metal oxide of the insulating region comprises titanium oxide; or, the metal of the conductive region comprises molybdenum, and the metal oxide of the insulating region comprises molybdenum oxide; or, the metal of the conductive region comprises tantalum, and the metal oxide of the insulating region comprises tantalum oxide.

[0106] In the manufacturing process of the semiconductor device in this application embodiment, a metal thin film (e.g., a titanium thin film) can be formed around the outer sidewall of the semiconductor layer 3. Then, the metal thin film on the opposite sides of the semiconductor layer 3 in the second direction D2 is oxidized to form an insulating region 1. The metal thin film on the opposite sides of the semiconductor layer 3 in the first direction D1 is not oxidized, and the unoxidized metal thin film on the opposite sides of the semiconductor layer 3 in the first direction D1 forms the two conductive contact regions 4.

[0107] In one exemplary embodiment, a plurality of transistors are arranged at intervals in a column direction (second direction D2), and an isolation layer 8 is disposed between adjacent transistors in the column direction, the isolation layer 8 separating adjacent transistors in the column direction. The insulating region 1 of the transition layer 70 is in contact with the isolation layer 8.

[0108] In an exemplary embodiment, the source / drain 60 is disposed on the side of the transistor away from the bit line 7 in the first direction D1, and one end of the source / drain 60 in the first direction D1 is in direct contact with the conductive contact region 4 of the transition layer 70.

[0109] In one exemplary embodiment, the memory cell of the semiconductor device provided in this embodiment can be a structure that does not include a capacitor, such as 1T or 2T0C. Alternatively, it can be a structure that includes a capacitor, such as 1T1C or 2T1C.

[0110] In an exemplary embodiment, the memory cell of the semiconductor device provided in this embodiment further includes a capacitor 50, the capacitor 50 being located on the side of the source / drain 60 away from the bit line 7 in the first direction D1, the capacitor 50 being connected to the other end of the source / drain 60 in the first direction D1, and the capacitor 50 being connected to the conductive contact region 4 of the transition layer 70 through the source / drain 60.

[0111] In an exemplary embodiment, the capacitor 50 includes a first capacitor electrode 51, a second capacitor electrode 52, and a capacitor dielectric layer 53 located between the first capacitor electrode 51 and the second capacitor electrode 52. The first capacitor electrode 51 is located on the side close to the source / drain electrode 60 and is connected to the source / drain electrode 60.

[0112] In an exemplary embodiment, the first capacitor electrode 51 is a hollow cylindrical structure with an opening away from the semiconductor layer. The bottom of the cylindrical structure is connected to the semiconductor layer through the source / drain electrode 60. It can be understood that the first capacitor electrode 51 of the cylindrical structure has a U-shaped cross-section perpendicular to the substrate direction. The first capacitor electrode 51 includes sidewalls, a bottom wall located on opposite sides of the sidewalls in a first direction D1, and an opening (the opening is the opening of the hollow cylindrical structure). The sidewalls of the first capacitor electrode 51 are annular extending along the first direction D1. The bottom wall of the first capacitor electrode 51 is in direct contact with the source / drain electrode 60, and the opening of the first capacitor electrode 51 is away from the source / drain electrode 60.

[0113] In one exemplary embodiment, at least a portion of the second capacitor electrode 52 is located within the opening of the cylindrical structure of the first capacitor electrode 51 and is connected to the first capacitor electrode 51 through the capacitor dielectric layer 52.

[0114] In some embodiments, the second capacitor electrode 52 fills the opening.

[0115] Figure 2b for Figure 1 A cross-sectional view of the provided semiconductor device along the a-a' direction. In an exemplary embodiment, as shown... Figure 2b As shown, in a direction perpendicular to the substrate, the source / drain 60 includes a first sub-electrode 61 and a second sub-electrode 62 connected to each other. The first sub-electrode 61 is located on the side of the second sub-electrode 62 away from the bit line 7. The first sub-electrode 61 is block-shaped, with its first end connected to the first capacitor electrode 51 and its second end connected to the second sub-electrode 62. The second sub-electrode 62 is also block-shaped, with its first end connected to the first sub-electrode 61 and its second end extending along a direction close to the bit line 7. The upper surface, lower surface, and second end of the second sub-electrode 62 are covered by the conductive contact region 4 of the transition layer 70. The second sub-electrode 62 is connected to the inner surface of the semiconductor layer 3 through the conductive contact region 4.

[0116] In an exemplary embodiment, the second sub-electrode 62 may be made of the same conductive material as the bit line 7, such as tungsten, copper, etc.

[0117] In an exemplary embodiment, the transition layer 70 includes a first conductive contact region 401 and a second conductive contact region 402. The first conductive contact region 401 is disposed between the semiconductor layer 3 and the source / drain electrode 60, and contacts the outer surface of the source / drain electrode 60. The inner surface of the semiconductor layer 3 is connected to the outer surface of the source / drain electrode 60 through the first conductive contact region 401. The second conductive contact region 402 is disposed between the semiconductor layer 3 and the bit line 7, and contacts the outer surface of the bit line 7. The inner surface of the semiconductor layer 3 is connected to the outer surface of the bit line 7 through the second conductive contact region 402. The first conductive contact region 401 contacts the upper surface, lower surface, and second end of the second sub-electrode 62.

[0118] In an exemplary embodiment, a first conductive contact region 401 covers the upper surface, lower surface, and second end of the second sub-electrode 62. The cross-section of the first conductive contact region 401 along a first direction D1 perpendicular to the substrate is U-shaped. At least a portion of a source / drain electrode 60 is disposed within the U-shaped opening of the first conductive contact region 401, and the source / drain electrode 60 simultaneously contacts both the first conductive contact region 401 and the first capacitor electrode 51. The first conductive contact region 401 includes sidewalls, a bottom wall located on opposite sides of the sidewalls in the first direction D1, and an opening. The opening of the first conductive contact region 401 faces away from the word line. The first conductive contact region 401 has a first end face facing away from the word line, which contacts the first sub-electrode 61. The bottom wall of the first conductive contact region 401 contacts the bottom wall of the semiconductor layer 3. The sidewalls of the first conductive contact region 401 extend along the sidewalls of the second sub-electrode 62, covering the upper and lower surfaces of the second sub-electrode 62.

[0119] In one exemplary embodiment, the second conductive contact region 402 is annular in cross-section perpendicular to the substrate along the first direction D1. The second conductive contact region 402 surrounds the sidewall of the bit line 7, forming an annulus extending along the second direction D2.

[0120] In an exemplary embodiment, the two semiconductor contact regions 301 of the semiconductor layer 3 include a first region 3011 that contacts the outer surface of the first conductive contact region 401, and a second region 3012 that contacts the outer surface of the second conductive contact region 402. The first region 3011 and the second region 3012 are different regions of the semiconductor layer 3 on opposite sides of the word line 5 in the first direction D1. The first region 3011 is connected to the source / drain 60 through the first conductive contact region 401. The side of the first region 3011 and the second region 3012 closest to the word line 5 is connected to the word line 5 through the gate insulating layer 2.

[0121] In an exemplary embodiment, the shape and size of the first region 3011 are substantially the same as the shape and size of the first conductive contact region 401. The first region 3011 has a U-shaped cross-section along the first direction D1 perpendicular to the substrate. The first region 3011 has a second end face facing away from the word line. The second end face of the first region 3011 contacts the first sub-electrode 61. The second end face of the first region 3011 is substantially flush with the first end face of the first conductive contact region 401 in the direction perpendicular to the substrate. The first region 3011 covers the upper and lower surfaces of the second sub-electrode 62 through the first conductive contact region 401.

[0122] In one exemplary embodiment, the shape and size of the second region 3012 are substantially the same as the shape and size of the second conductive contact region 402. The second region 3012 is annular in cross-section along the first direction D1 perpendicular to the substrate. The second region 3012 surrounds the sidewall of the bit line 7 through the second conductive contact region 402.

[0123] In an exemplary embodiment, a bit line 7 extending along a second direction D2 is provided between two adjacent columns of transistors in the same layer, the second region 3012 of the semiconductor layer 3 of the two adjacent transistors is shared, the two adjacent semiconductor layers 3 are connected through the shared second region 3012, and each transistor in the two adjacent columns of transistors can share a bit line 7.

[0124] In an exemplary embodiment, the gate insulating layer 2 covers the outer surface of the first region 3011 and the outer surface of the second region 3012 of the semiconductor layer 3, and the gate insulating layer 2 is disposed between the first region 3011 and the word line 5, and between the second region 3012 and the word line 5.

[0125] In an exemplary embodiment, the memory cell of the semiconductor device provided in this embodiment further includes a capacitor 50. The capacitor 50 includes a first capacitor electrode 51, a second capacitor electrode 52, and a capacitor dielectric layer 53 located between the first capacitor electrode 51 and the second capacitor electrode 52. The first capacitor electrode 51 has a U-shaped cross-section perpendicular to the substrate along a first direction D1, and the opening of the first capacitor electrode 51 faces away from the word line. The second capacitor electrode 52 includes a main body portion 521 extending along a direction perpendicular to the substrate and at least one protruding portion 522 intersecting and connecting with the main body portion 521. The main body portion 521 is plate-shaped and extends along a second direction D2; the protruding portion 522 is parallel to the substrate, and at least a portion of the protruding portion 522 extends into the first capacitor electrode 51 and is connected to the first capacitor electrode 51 through the capacitor dielectric layer 53.

[0126] In an exemplary embodiment, the semiconductor device provided in this embodiment further includes a trench 9 extending along a direction parallel to the substrate. The trench 9 is located on the side of the gate 6 away from the bit line 7. The trench 9 includes a bottom wall and side walls, and the bottom wall of the trench 9 exposes the gate 6. Along the direction away from the gate 6, a gate insulating layer 2, a first region 3011, a first conductive contact region 401, a second sub-electrode 62, a first sub-electrode 61, a first capacitor electrode 51, a capacitor dielectric layer 53, and a second capacitor electrode 52 are sequentially disposed in the trench 9.

[0127] Figure 2c for Figure 1 A cross-sectional view of the provided semiconductor device along the c-c' direction. In an exemplary embodiment, as shown... Figure 2c As shown, in the direction perpendicular to the substrate, the semiconductor layer 3 is located on opposite sides of the second direction D2. The cross-section of the semiconductor layer 3 along the first direction D1 perpendicular to the substrate is U-shaped. The openings of the semiconductor layer 3 on opposite sides of the second direction D2 are all oriented away from the word line 5. The bottom walls of the semiconductor layer 3 on opposite sides of the second direction D2 are connected to the word line 5 through the gate insulating layer 2.

[0128] In an exemplary embodiment, the insulating region 1 of the transition layer 70 has a U-shaped cross-section along the second direction D2 perpendicular to the substrate. The opening of the insulating region 1 faces away from the word line 5, and the bottom wall of the insulating region 1 is connected to the gate 6 through the semiconductor layer 3 and the gate insulating layer 2. The insulating region 1 covers the channel region of the semiconductor layer 3 and is in direct contact with the channel region of the semiconductor layer 3. The insulating region 1 is configured to protect the channel region of the semiconductor layer 3.

[0129] Figure 2d for Figure 1 A cross-sectional view of the provided semiconductor device along the b-b' direction. In an exemplary embodiment, as shown... Figure 2d As shown, the bit line 7 has a rectangular cross-section along the first direction D1 perpendicular to the substrate, and conductive contact areas 4 are sequentially provided on the upper and lower surfaces of the bit line 7.

[0130] In one exemplary embodiment, an insulating film 10 is provided between adjacent bit lines 7 in a direction perpendicular to the substrate.

[0131] Figure 2e for Figure 1 A cross-sectional view of the provided semiconductor device along the d-d' direction. In an exemplary embodiment, as shown... Figure 2eAs shown, at least a portion of the main body of the second capacitor electrode 52 is disposed in the tank 9, and the cross-section of the main body of the second capacitor electrode 52 in the direction perpendicular to the substrate includes a rectangle. At least a portion of the first capacitor electrode 51 is disposed in the tank 9, and the cross-section of the first capacitor electrode 51 in the direction perpendicular to the substrate includes an annulus extending along a first direction D1. The first capacitor electrode 51 is disposed around the sidewall of the main body of the second capacitor electrode 52 through a capacitor dielectric layer 53.

[0132] In one exemplary embodiment, a plurality of capacitors 50 are arranged at intervals in a second direction D2, with an isolation layer 8 disposed between adjacent capacitors 50, and the first capacitor electrodes 51 of adjacent capacitors 50 are insulated by the isolation layer 8. The plurality of capacitors 50 are arranged at intervals along a direction perpendicular to the substrate, with an insulating film 10 disposed between adjacent capacitors 50, and the first capacitor electrodes 51 of adjacent capacitors 50 are insulated by the insulating film 10.

[0133] The semiconductor device of this disclosure reduces the Schottky barrier between the semiconductor layer and the source / drain by disposing a conductive contact region between the semiconductor layer and the source / drain, thereby reducing the contact resistance between the semiconductor layer and the source / drain.

[0134] The semiconductor device disclosed herein reduces the Schottky barrier between the semiconductor layer and the bit line by disposing a conductive contact region between the semiconductor layer and the bit line, thereby reducing the contact resistance between the semiconductor layer and the bit line.

[0135] The semiconductor device of this disclosure protects the semiconductor layer by disposing an insulating region on at least one side of the semiconductor layer, and the insulating region and the conductive contact region are located in different layers of the semiconductor layer, thereby preventing the external environment from affecting the semiconductor layer and improving the performance of the transistor.

[0136] In the semiconductor device of this disclosure, the region where the semiconductor layer contacts the electrode includes a transition layer. This transition layer simultaneously includes a conductive contact region and an insulating layer between two conductive contact regions, thereby reducing contact resistance and simplifying device structure and manufacturing process.

[0137] The technical solution of this embodiment is further illustrated below through the manufacturing process of the semiconductor device in this embodiment. The "patterning process" mentioned in this embodiment includes deposition of film layers, coating with photoresist, mask exposure, development, etching, and photoresist stripping, which are mature fabrication processes in related technologies. The "photolithography process" mentioned in this embodiment includes coating of film layers, mask exposure, and development, which are mature fabrication processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations. In the description of this embodiment, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or photolithography process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process or photolithography process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or photolithography process contains at least one "pattern."

[0138] In this embodiment, the semiconductor device may include a plurality of memory cells stacked along a direction perpendicular to the substrate.

[0139] In one exemplary embodiment, the manufacturing process of a semiconductor device may include:

[0140] Step 101: Form a stacked structure.

[0141] In one exemplary embodiment, forming the stacked structure includes sequentially and alternately depositing an insulating thin film 10 and a sacrificial thin film 11 on a substrate 101 to form the stacked structure. In some embodiments, both the film layer near the substrate and the film layer away from the substrate in the stacked structure are insulating thin films 10, such as... Figure 3a and Figure 3b As shown. Among them, Figure 3a This is a schematic diagram of the longitudinal section of the stacked structure; Figure 3b This is a top view of the stacked structure.

[0142] In one exemplary embodiment, the sacrificial film 11 and the insulating film 10 have an etching selectivity ratio. For example, the insulating film 10 may be made of silicon oxide, and the sacrificial film 11 may be made of silicon nitride.

[0143] In an exemplary embodiment, the insulating film 10 and the sacrificial film 11 may be deposited using a chemical vapor deposition method or an atomic layer deposition method.

[0144] In one exemplary embodiment, the substrate may comprise a semiconductor substrate, such as a silicon substrate.

[0145] In an exemplary embodiment, the stacked structure includes a bit line region 102 extending along the column direction (second direction D2) and a plurality of branch regions 103 arranged at intervals in the column direction and extending in the row direction (first direction D1) intersecting the bit line region 102. A non-branch region 104 extending in the row direction (corresponding to a groove region between two branch regions) is provided between adjacent branch regions 103 in the column direction. A bit line region 102 is provided between two column branch regions 103 in the row direction. Of course, two adjacent bit line regions 102 can also be provided.

[0146] In one exemplary embodiment, each sacrificial film 11 in the bit line region 102 is etched away in a subsequent process and then filled with a conductive film to form a bit line; each branch region 103 is used to form a transistor, or to form a transistor and a capacitor.

[0147] Step 102: Form the first hole for accommodating the word lines.

[0148] In one exemplary embodiment, forming a first hole for accommodating a word line includes: forming a first hole 12 extending in a direction perpendicular to the substrate 101 and penetrating the stacked structure on a substrate on which the aforementioned pattern is formed, wherein a plurality of first holes 12 are arranged at intervals in a column direction. The first hole 12 is located in the region of each branch region 103 near the bit line region 102, and the first hole 12 is used to accommodate a word line.

[0149] Subsequently, the first hole 12 is filled with a sacrificial material (such as polycrystalline silicon) to form a word line sacrificial layer 13, such as... Figure 4a , 4b and Figure 4c As shown. Among them, Figure 4a for Figure 1 A cross-sectional view in the a-a' direction after the word line sacrificial layer is formed during the manufacturing process of the provided semiconductor device; Figure 4b for Figure 1 A cross-sectional view in the c-c' direction after the word line sacrificial layer is formed during the manufacturing process of the provided semiconductor device; Figure 4c for Figure 1 A schematic diagram showing the formation of a word line sacrificial layer in a direction parallel to the substrate during the manufacturing process of the provided semiconductor device.

[0150] In one exemplary embodiment, the word line sacrificial layer 13 fills each of the first holes 12.

[0151] Step 103: Form an isolation layer between adjacent memory cells in the column direction.

[0152] In an exemplary embodiment, forming an isolation layer between adjacent memory cells in the column direction includes: forming a first trench 14 extending in a direction perpendicular to the substrate 101 on a stacked structure using an etching process on a substrate forming the aforementioned pattern. The first trench 14 penetrates the stacked structure in the thickness direction of the stacked structure, and the bottom of the first trench 14 extends to the substrate 101. The first trench 14 extends in the row direction, and a plurality of first trenches 14 are spaced apart in the column direction. The first trenches 14 are located between adjacent branch regions 103 of each column branch region 103. The sidewalls of any two adjacent first trenches 14 expose each insulating film 10 and each sacrificial film 11 in each branch region 103. The sidewalls of the first trenches 14 do not expose the word line sacrificial layer 13. A portion of each insulating film 10 and each sacrificial film 11 is located between the sidewall of the first trench 14 and the sidewall of the word line sacrificial layer 13.

[0153] Subsequently, the first trenches 14 are filled with insulating material to form an isolation layer 8 corresponding to each first trench 14. The isolation layer 8 extends along the row direction and is located between any adjacent branch areas 103 in a column of branch areas 103, such as... Figure 5a , Figure 5b , Figure 5c and Figure 5d As shown. Among them, Figure 5a for Figure 1 A cross-sectional view in the c-c' direction after the isolation layer is formed during the manufacturing process of the provided semiconductor device; Figure 5b for Figure 1 A cross-sectional view in the b-b' direction after the isolation layer is formed during the manufacturing process of the provided semiconductor device; Figure 5c for Figure 1 A cross-sectional view in the d-d' direction after the isolation layer is formed during the manufacturing process of the provided semiconductor device; Figure 5d for Figure 1 A schematic diagram showing the formation of an isolation layer parallel to the substrate during the manufacturing process of the provided semiconductor device.

[0154] In an exemplary embodiment, the material of the insulating layer 8 may be the same as or different from the material of the insulating film 10. For example, the material of the insulating layer 8 may be silicon oxide.

[0155] Step 104: Form a transverse groove for accommodating the capacitor electrode.

[0156] In an exemplary embodiment, forming a lateral trench for accommodating capacitor electrodes includes: on a substrate having the aforementioned pattern formed, using an etching process to form a second trench 15 extending in a direction perpendicular to the substrate 101 on the stacked structure. This can be understood as the substrate containing a plurality of trenches periodically distributed in the first direction, such as... Figure 6aThe repeating unit is shown. A second groove 15 is formed between two adjacent repeating units. Each repeating unit contains, as shown... Figure 6a The image shows word line sacrificial layers 13 within two rows of first holes and two rows of transistors periodically distributed in the direction perpendicular to the substrate.

[0157] In a direction parallel to the substrate, the second trench 15 extends along the column direction. The second trench 15 is located on opposite sides of the stacked structure in the row direction. The second trench 15 penetrates the stacked structure in the thickness direction of the stacked structure. The bottom of the second trench 15 extends to the substrate 101. The sidewalls of the second trench 15 expose each insulating film 10 and each sacrificial film 11 in each branch region 103.

[0158] Subsequently, each sacrificial film 11 in each branch region 103 exposed by the second trench 15 is etched back and removed in the first direction by wet selective etching. A lateral trench 16 extending parallel to the substrate direction is formed in the area where the sacrificial film 11 has been etched away. The lateral trench 16 is located between adjacent isolation layers 8 in the column direction and adjacent insulating films 10 in the perpendicular substrate direction. The lateral trench 16 does not expose the word line sacrificial layer 13, retaining a portion of the sacrificial film 11 connected to the word line sacrificial layer 13. The first end of the retained sacrificial film 11 is in direct contact with the word line sacrificial layer 13, and the second end of the retained sacrificial film 11 is exposed by the lateral trench 16. The area containing the retained sacrificial film 11 is etched away in subsequent processes to accommodate semiconductor layers, conductive contact areas, insulating areas, and source / drain electrodes, such as... Figure 6a , Figure 6b , Figure 6c and Figure 6d As shown. Among them, Figure 6a for Figure 1 A cross-sectional view in the a-a' direction after the lateral trench is formed during the manufacturing process of the provided semiconductor device; Figure 6b for Figure 1 A cross-sectional view in the b-b' direction after the lateral trench is formed during the manufacturing process of the provided semiconductor device; Figure 6c for Figure 1 A cross-sectional view in the d-d' direction after the lateral trench is formed during the manufacturing process of the provided semiconductor device; Figure 6d for Figure 1 A schematic diagram showing the semiconductor device after a lateral trench is formed in the manufacturing process, parallel to the substrate direction.

[0159] In one exemplary embodiment, the lateral trench 16 includes sidewalls, openings on opposite sides of the sidewalls in a first direction D1, and a bottom wall. The sidewalls of the lateral trench 16 are annular extending along the first direction D1. The openings of the lateral trench 16 face and communicate with the second trench 15. The bottom wall of the lateral trench 16 exposes the second end of the sacrificial film 11. The sidewalls of the lateral trench 16 include sidewalls parallel to the substrate and sidewalls perpendicular to the substrate. The sidewalls of the lateral trench 16 parallel to the substrate are the insulating film 10 exposed by the lateral trench 16, and the sidewalls of the lateral trench 16 perpendicular to the substrate are the isolation layer 8 exposed by the lateral trench 16.

[0160] Step 105: Form a capacitor.

[0161] In an exemplary embodiment, forming a capacitor includes: depositing a first conductive film on a stacked structure by an atomic layer deposition process on a substrate on which the aforementioned pattern is formed, wherein the first conductive film at least covers the inner wall of the second trench, as well as the annular sidewalls and bottom wall of the transverse trench 16, i.e. the first conductive film covers the insulating film 10 exposed in the second trench 15, and the sacrificial film 11, the insulating film 10, and the isolation layer 8 exposed in the transverse trench 16.

[0162] Subsequently, through an etching process, the first conductive film on the surface of the stacked structure and the first conductive film on the insulating film 10 exposed in the second trench are etched away, while the first conductive film on the sidewall and bottom wall of the transverse trench 16 is retained, forming the first capacitor electrode 51 in different transverse trenches 16, and each first capacitor electrode 51 is isolated from each other.

[0163] Subsequently, an atomic layer deposition process is used to deposit a capacitor dielectric film on the stacked structure. The capacitor dielectric film at least covers the sidewalls of the insulating film 10 exposed by the second trench, as well as the first capacitor electrode 51 on the annular sidewalls and bottom wall of the transverse trench 16.

[0164] Subsequently, an atomic layer deposition process is used to deposit a second conductive film on the stacked structure. The second conductive film at least covers the capacitor dielectric film on the sidewalls of the insulating film 10 exposed in the second trench 15, as well as the capacitor dielectric film on the sidewalls and bottom wall of the transverse trench 16. The second conductive film fills the transverse trench 16.

[0165] Subsequently, a third conductive film is deposited on the stacked structure by a deposition process. The third conductive film at least covers the second conductive film on the sidewall of the insulating film 10 exposed by the second trench 15, and fills the transverse trench 16, covering the sidewall and bottom wall of the transverse trench 16.

[0166] Subsequently, through an etching process, the capacitor dielectric film, the second conductive film, and the third conductive film on the surface of the stacked structure are etched away, while the capacitor dielectric film, the second conductive film, and the third conductive film on the insulating film 10 exposed in the second trench are retained. The capacitor dielectric film and the second conductive film on the sidewalls and bottom wall of the transverse trench 16, as well as the third conductive film in the transverse trench 16, are retained. The retained capacitor dielectric film forms a capacitor dielectric layer 53, which covers the sidewalls of the insulating film 10 exposed in the second trench, and the first capacitor electrode 51 on the sidewalls and bottom wall of the transverse trench 16. The retained second and third conductive films form a second capacitor electrode 52, which covers the sidewalls of the insulating film 10 exposed in the second trench, and the capacitor dielectric layer 53 on the sidewalls and bottom wall of the transverse trench 16. At least a portion of the capacitor dielectric layer 53 is disposed between the second capacitor electrode 52 and the first capacitor electrode 51, separating the second capacitor electrode 52 from the first capacitor electrode 51. Figure 7a , Figure 7b and Figure 2e As shown. Among them, Figure 7a for Figure 1 A cross-sectional view in the a-a' direction after the capacitor is formed during the manufacturing process of the provided semiconductor device; Figure 7b for Figure 1 A cross-sectional view in the b-b' direction after the capacitor is formed during the manufacturing process of the provided semiconductor device.

[0167] In an exemplary embodiment, the first capacitor electrode 51 has a single-layer structure, and the material of the first capacitor electrode 51 can be titanium nitride. The second capacitor electrode 52 has a multi-layer structure, including a first conductive layer and a second conductive layer. The first conductive layer is in direct contact with the capacitor dielectric layer 53, and the second conductive layer is located on the side of the first conductive layer away from the capacitor dielectric layer 53, and is connected to the capacitor dielectric layer 53 through the first conductive layer. The material of the first conductive layer can be titanium nitride, and the material of the second conductive layer can be polycrystalline silicon. The capacitor dielectric layer 53 can be a high-k dielectric material, that is, a dielectric material with a dielectric constant K ≥ 3.9. The high-k dielectric material can include, but is not limited to, at least one of the following: silicon oxide, aluminum oxide, hafnium oxide, hafnium aluminum oxide, and hafnium lanthanum oxide.

[0168] In an exemplary embodiment, the first capacitor electrode 51 includes a sidewall, a bottom wall disposed on opposite sides of the sidewall, and an opening. The sidewall is annular and extends along a first direction D1. The sidewall of the first capacitor electrode 51 is disposed on the insulating film 10 and the isolation layer 8 exposed by the transverse groove 16. The bottom wall of the first capacitor electrode 51 is disposed on the bottom wall of the transverse groove 16 and is in direct contact with the corresponding sacrificial film 11. The opening of the first capacitor electrode 51 faces the same direction as the opening of the transverse groove 16. The sidewall of the first capacitor electrode 51 is disposed on the insulating film 10 and the isolation layer 8 exposed by the transverse groove 16.

[0169] In an exemplary embodiment, the second capacitor electrode 52 includes a main body portion 521 extending along a direction perpendicular to the substrate and an extension portion 522 intersecting and connected to the main body portion 521. The main body portion 521 is plate-shaped, fills the second trench, and is located on opposite sides of the stacked structure in the first direction D1. The extension portion 522 is parallel to the substrate, and at least part of the extension portion 522 extends into the first capacitor electrode 51 and is connected to the first capacitor electrode 51 through the capacitor dielectric layer 53.

[0170] In one exemplary embodiment, the main body is provided with a plurality of protruding portions, which are arranged at intervals along a direction perpendicular to the substrate. Each protruding portion is disposed in a corresponding transverse groove 16 and is connected to the first capacitor electrode 51 through a capacitor dielectric layer 53.

[0171] Step 106: Form an opening.

[0172] In an exemplary embodiment, forming an opening includes: on the substrate on which the aforementioned pattern is formed, using an etching process, forming an opening 17 perpendicular to the substrate in the region of the isolation layer 8. The opening 17 penetrates the stacked structure in the thickness direction of the stacked structure, the bottom of the opening 17 extends to the substrate 101, the opening 17 extends along the row direction, and a plurality of openings 17 are arranged at intervals along the column direction. The openings 17 are located between adjacent branch regions in each column branch region. The sidewalls of any two adjacent openings 17 expose each insulating film 10 and each sacrificial film 11 between the word line sacrificial layer 13 and the first capacitor electrode 51. The sidewalls of the plurality of openings 17 do not expose the word line sacrificial layer 13. The opening 17 can also be understood as a hole.

[0173] In one exemplary embodiment, the sidewall of the opening 17 in the column direction exposes each insulating film 10 and each sacrificial film 11 between the word line sacrificial layer 13 and the first capacitor electrode 51, but does not expose the word line sacrificial layer 13; one end of the opening 17 in the row direction exposes each insulating film 10 and each sacrificial film 11 in the bit line region 102, such as Figure 8a , Figure 8b and Figure 8c As shown. Among them, Figure 8a for Figure 1 A cross-sectional view in the c-c' direction after an opening is formed during the manufacturing process of the provided semiconductor device;

[0174] Figure 8b for Figure 1 A cross-sectional view in the b-b' direction after an opening is formed during the manufacturing process of the provided semiconductor device; Figure 8c for Figure 1 A schematic diagram showing the semiconductor device after an opening is formed during the manufacturing process, parallel to the substrate.

[0175] Step 107: Forming a gate insulating layer, a semiconductor thin film, a metal thin film, and a fourth conductive thin film.

[0176] In one exemplary embodiment, forming the gate insulating layer, semiconductor thin film, metal thin film, and fourth conductive thin film includes: on a substrate forming the aforementioned pattern, selectively etching away the sacrificial film surrounding the word line sacrificial layer 13 to form a first via, the first via exposing the sidewalls of the word line sacrificial layer 13; and etching away each sacrificial film layer in the bit line region 102 to form a second via extending along the column direction. The first via and the second via are disposed around the sidewalls of the word line sacrificial layer 13 and communicate through the opening 17, the first via, the second via, and the opening 17 exposing the annular sidewalls of the word line sacrificial layer.

[0177] In an exemplary embodiment, the areas in the bit line region 102 where each sacrificial film layer is etched away form second vias. The second vias are located between two adjacent columns of word line sacrificial layers 13. The sidewalls of the second vias, which are opposite each other in the row direction, expose the sidewalls of each word line sacrificial layer 13 in the two adjacent columns of word line sacrificial layers 13. The two adjacent columns of word line sacrificial layers 13 share a second via.

[0178] Subsequently, using atomic layer deposition (ALD), a gate insulating layer 18, a semiconductor thin film 19, and a metal thin film 20 are sequentially deposited on the inner walls of the first and second vias. At least a portion of the gate insulating layer 18, semiconductor thin film 19, and metal thin film 20 surround the sidewalls of the exposed word line sacrificial layer 13. The conductive thin film in the second via forms the bit line 7. In subsequent processes, the gate insulating layer 18 forms a gate insulating layer, the semiconductor thin film 19 forms a semiconductor layer, and the metal thin film 20 forms an insulating region and a conductive contact region. Subsequently, using chemical deposition (CCD), a fourth conductive thin film 21 is used to fill the first and second vias. Subsequently, using an etch-back process, the fourth conductive thin film 21 on the surface of the stacked structure is etched away to expose the metal thin film 20. Subsequently, the metal thin film 20, semiconductor thin film 19, and gate insulating layer 18 on the surface of the stacked structure are etched away, as shown below. Figure 9a , 9b As shown in 9c. Among them, Figure 9a for Figure 1 The provided semiconductor device is shown in a cross-sectional view along the a-a' direction after the formation of the gate insulating layer, semiconductor thin film, metal thin film and fourth conductive thin film during the manufacturing process. Figure 9b for Figure 1 The provided semiconductor device is shown in a cross-sectional view along the c-c' direction after the formation of the gate insulating layer, semiconductor thin film, metal thin film and fourth conductive thin film during the manufacturing process. Figure 9c for Figure 1The provided semiconductor device is shown in a cross-sectional view in the d-d' direction after the formation of the gate insulating layer, semiconductor thin film, metal thin film and fourth conductive thin film during the manufacturing process.

[0179] In an exemplary embodiment, bit line 7 extends along the column direction and is located between two adjacent column word line sacrificial layers 13, with the two adjacent column word line sacrificial layers 13 sharing a single bit line 7.

[0180] In one exemplary embodiment, the gate insulating layer may be a high-k dielectric material, i.e., a dielectric material with a dielectric constant K ≥ 3.9. The high-k dielectric material may include, but is not limited to, at least one of the following: silicon oxide, aluminum oxide, hafnium oxide, hafnium aluminum oxide, and hafnium lanthanum oxide.

[0181] In one exemplary embodiment, the metal thin film may be a metal, such as titanium.

[0182] In one exemplary embodiment, the fourth conductive film may be a metal, such as tungsten.

[0183] Step 108: Form the conductive contact area and the insulating area.

[0184] In an exemplary embodiment, forming the conductive contact area and the insulating area includes: on the substrate on which the aforementioned pattern is formed, using an etching process to etch away the fourth conductive film within the opening 17; subsequently, using a wet etching process to etch away the metal film on the inner wall of the opening 17 and the fourth conductive film on the two opposite sidewalls of the word line sacrificial layer 13 in the column direction, exposing the metal film on the two opposite sidewalls of the word line sacrificial layer 13 in the column direction; and retaining the fourth conductive film on the two opposite sidewalls of the word line sacrificial layer 13 in the row direction.

[0185] Subsequently, the semiconductor film inside the opening 17 is removed, thereby disconnecting the semiconductor films of the transistors in different layers.

[0186] Subsequently, an oxidation process, such as an oxygen plasma treatment process, is used to oxidize the metal films on the two opposite sidewalls of the exposed word line sacrificial layer 13 in the column direction, so that the metal films on the two opposite sidewalls of the word line sacrificial layer 13 in the column direction form insulating regions 1; the metal films in contact with the retained fourth conductive film form conductive contact regions, and the conductive contact regions are the metal films on the two opposite sidewalls of the word line sacrificial layer 13 in the row direction, such as... Figure 10a and 10b As shown. Among them, Figure 10a for Figure 1 A cross-sectional view in the c-c' direction after the insulating region is formed during the manufacturing process of the provided semiconductor device; Figure 10b for Figure 1 The provided semiconductor device is shown in a cross-sectional view along the b-b' direction after the insulating region is formed during the manufacturing process.

[0187] In an exemplary embodiment, the conductive contact area is a metal, such as titanium. The insulating area 1 is a metal oxide, such as titanium oxide.

[0188] Step 109: Form the second hole and semiconductor layer.

[0189] In an exemplary embodiment, forming the second hole, conductive contact area, and semiconductor layer includes: filling an isolation layer in the opening 17 on a substrate with the aforementioned pattern; subsequently, using an etching process, forming a second hole 23 extending perpendicular to the substrate on the isolation layer, the second hole 23 penetrating the stacked structure in the thickness direction of the stacked structure, the bottom of the second hole 23 extending to the substrate 101, and the sidewalls of the second hole 23 exposing each layer of the gate insulating layer, semiconductor thin film, and metal thin film near the first capacitor electrode; subsequently, using wet selective etching, etching away the gate insulating layer in contact with the first capacitor electrode 51 to form a third via 24 parallel to the substrate; the retained semiconductor thin film forms the semiconductor layer 3, and the fourth conductive thin film retained in the first via forms the second sub-electrode 62, as shown below. Figure 11a and 11b As shown. Among them, Figure 11a for Figure 1 A cross-sectional view in the a-a' direction after the second hole and semiconductor layer are formed during the manufacturing process of the provided semiconductor device; Figure 11b for Figure 1 A cross-sectional view in the b-b' direction after the second hole and semiconductor layer are formed during the manufacturing process of the provided semiconductor device.

[0190] In some embodiments, selective wet etching can be used to remove the gate insulating layer in contact with the first capacitor electrode 51, as well as the semiconductor thin film located near the first capacitor electrode 51; or, etching can remove the gate insulating layer in contact with the first capacitor electrode 51, as well as the semiconductor thin film and part of the metal thin film located near the first capacitor electrode 51, thereby increasing the contact area of ​​the etching solution and improving the etching efficiency of the gate insulating layer and the semiconductor thin film.

[0191] In one exemplary embodiment, in the row direction, the first end of the third through hole 24 exposes the first capacitor electrode 51, and the second end of the third through hole 24 exposes at least the second sub-electrode 62; in the column direction, the third through hole 24 is connected to the adjacent second hole 23 respectively.

[0192] In one exemplary embodiment, the gate insulating layer 2 may be a high-k dielectric material, i.e., a dielectric material with a dielectric constant K ≥ 3.9. The high-k dielectric material may include, but is not limited to, at least one of the following: silicon oxide, aluminum oxide, hafnium oxide, hafnium aluminum oxide, and hafnium lanthanum oxide.

[0193] Step 110: Form the source / drain, gate, and word line.

[0194] In an exemplary embodiment, forming the source / drain, gate, and word line includes: on a substrate forming the aforementioned pattern, using a chemical deposition process, filling the second hole and the third via with a fifth conductive film; subsequently, using an etch-back process, etching away the fifth conductive film on the surface of the stacked structure; subsequently, etching away the fifth conductive film in the second hole, retaining the fifth conductive film in the second via, forming a first sub-electrode 61, the first sub-electrode 61 and the second sub-electrode 62 forming the source / drain 60; subsequently, filling the second hole with an isolation layer; subsequently, etching away the word line sacrificial layer, exposing the inner wall of the first hole, filling the first hole with a conductive material, forming the word line 5, as shown. Figure 2a , Figure 2b , Figure 2c and Figure 2d As shown.

[0195] In an exemplary embodiment, in the row direction, the first end of the first sub-electrode 61 is in direct contact with the first capacitor electrode 51 of the capacitor, and the second end of the first sub-electrode 61 is in direct contact with the side of the second sub-electrode 62 near the capacitor, the side of the conductive contact area 4 near the capacitor, the side of the semiconductor layer 3 near the capacitor, and the side of the gate insulating layer 2 near the capacitor.

[0196] In one exemplary embodiment, both the first insulating film and the second insulating film can be silicon oxide.

[0197] In an exemplary embodiment, a word line 5 extends along a direction perpendicular to the substrate, the word line 5 is linear, the word line 5 passes through a plurality of semiconductor layers 3 stacked along a direction perpendicular to the substrate, and the portion of the word line 5 corresponding to the semiconductor layer 3 forms a gate 6, the gate 6 being a part of the word line 5.

[0198] The manufacturing method of this embodiment has a simple process for forming the transition layer, and it can electrically isolate the two contact areas in the transition layer without the need for an etching process.

[0199] This application also provides a method for manufacturing a semiconductor device, including:

[0200] A substrate is provided on which insulating thin films and sacrificial thin films are sequentially and alternately deposited to form a stacked structure;

[0201] A plurality of first holes are formed in the stacked structure extending in a direction perpendicular to the substrate, and word line sacrificial layers are filled in the first holes;

[0202] The stacked structure forms a plurality of first trenches, and between the plurality of first trenches are bit line regions extending along the column direction, and a plurality of branch regions that are spaced apart in the column direction and extend in the row direction and intersect the bit line regions, wherein the first hole is located in the branch regions.

[0203] An isolation layer is filled into the first trench;

[0204] The sacrificial film of multiple branch regions is etched away to form a transverse groove extending in the row direction between adjacent isolation layers and adjacent insulating films, and a portion of the sacrificial film layer is retained between the transverse groove and the word line sacrificial layer;

[0205] A first capacitor electrode and a capacitor dielectric layer are sequentially deposited on the inner wall of the transverse groove, and a second capacitor electrode is filled in the transverse groove.

[0206] An opening is formed in the isolation layer of the first trench to vertically substrate the opening, which exposes the sacrificial film between the word line sacrificial layer and the first capacitor electrode, as well as the sacrificial film layer of the bit line region; the sacrificial film is etched away to form a first via corresponding to the word line sacrificial layer and the first capacitor electrode, and a second via corresponding to the bit line region, the first via and the second via being connected and exposing each sidewall of the word line sacrificial layer;

[0207] A gate insulating layer, a semiconductor thin film, a metal thin film, and a conductive thin film filling the first and second vias are sequentially deposited on the inner walls of the first and second vias; the gate insulating layer, the semiconductor thin film, and the metal thin film surround the sidewalls of the exposed word line sacrificial layer;

[0208] Remove the conductive film filling the opening to expose the metal film on the two opposite sidewalls of the word line sacrificial layer in the column direction. Then, oxidize the exposed metal film using an oxidation process to form a metal oxide insulating region.

[0209] In some embodiments, after removing the conductive film filling the opening to expose the metal film on the two opposite sidewalls of the word line sacrificial layer in the column direction, the method further includes:

[0210] Remove the semiconductor thin film within the opening to disconnect the semiconductor thin films of different transistor layers from each other.

[0211] In some embodiments, after the oxidation process is used to oxidize the exposed metal film to form a metal oxide insulating region, the process further includes:

[0212] An insulating layer is filled into the opening;

[0213] An opening is made in the isolation layer to expose each gate insulating layer, semiconductor thin film and metal thin film near the first capacitor electrode. The area in the gate insulating layer that contacts the first capacitor electrode is etched away, and a conductive layer is filled in the area where the gate insulating layer is removed, so that the conductive layer contacts both the first capacitor electrode and the metal thin film.

[0214] The word line sacrificial layer is etched away to expose the inner wall of the first hole, and word lines are formed in the first hole.

[0215] In some embodiments, forming an opening in the isolation layer of the first trench that is perpendicular to the substrate includes:

[0216] Multiple openings are spaced apart along the column direction, the openings being located between adjacent branch regions in the column direction, the sidewalls of the openings exposing each insulating film and each sacrificial film between the word line sacrificial layer and the first capacitor electrode, and the sidewalls of the openings not exposing the word line sacrificial layer.

[0217] In some embodiments, the second via is located between two adjacent word line sacrificial layers in the row direction and exposes a portion of the sidewalls of the two word line sacrificial layers.

[0218] In some embodiments, the etching process removes the region of the gate insulating layer that contacts the first capacitor electrode, and fills the region where the gate insulating layer has been removed with a conductive layer, including:

[0219] The gate insulating layer in contact with the first capacitor electrode and the semiconductor thin film located near the first capacitor electrode are etched away, and a conductive layer is filled in; or, the gate insulating layer in contact with the first capacitor electrode, the semiconductor thin film and a portion of the metal thin film located near the first capacitor electrode are etched away, exposing the conductive thin film, and a conductive layer is filled in.

[0220] This disclosure also provides an electronic device, including the semiconductor device described in any of the foregoing embodiments. The electronic device may be a storage device, smartphone, computer, tablet computer, artificial intelligence device, wearable device, or power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0221] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A semiconductor device, characterized in that, It includes multiple layers of memory cells stacked in a direction perpendicular to the substrate; The storage unit includes: a transistor; The transistor includes: a gate extending in a direction perpendicular to the substrate, a semiconductor layer surrounding a sidewall of the gate, and a transition layer surrounding a sidewall of the semiconductor layer and in contact with the semiconductor layer. The transition layer includes two isolated conductive contact areas and two insulating areas located between the two conductive contact areas.

2. The semiconductor device according to claim 1, characterized in that, The two conductive contact regions of the transition layer comprise metal conductive regions, and the two insulating regions of the transition layer comprise metal oxide insulating regions, wherein the metal conductive regions and the metal oxide insulating regions contain the same metal element.

3. The semiconductor device according to claim 2, characterized in that, The metal in the conductive region comprises titanium, and the metal oxide in the insulating region comprises titanium oxide; or... The metal in the conductive region contains molybdenum, and the metal oxide in the insulating region contains molybdenum oxide; or... The metal in the conductive region contains tantalum, and the metal oxide in the insulating region contains tantalum oxide.

4. The semiconductor device according to claim 1, characterized in that, The two conductive contact regions include a first conductive contact region and a second conductive contact region; the semiconductor device further includes: Bit line, the bit line being in contact with the second conductive contact area; A capacitor, the capacitor including a first capacitor electrode, the first capacitor electrode being in contact with the first conductive contact area.

5. The semiconductor device according to claim 4, characterized in that, The first conductive contact area has a U-shaped cross-section perpendicular to the substrate with an opening facing the first capacitor electrode. A source / drain electrode is disposed within the opening, and the source / drain electrode is in contact with both the first conductive contact area and the first capacitor electrode.

6. The semiconductor device according to claim 5, characterized in that, The first capacitor electrode is a hollow cylindrical structure with an opening away from the semiconductor layer, and the bottom of the cylindrical structure is connected to the semiconductor layer through the source / drain electrode.

7. The semiconductor device according to claim 6, characterized in that, The capacitor further includes a second capacitor electrode, which is located inside the opening of the cylindrical structure of the first capacitor electrode and is connected to the first capacitor electrode through a capacitor dielectric layer.

8. The semiconductor device according to claim 4, characterized in that, The second conductive contact area has an annular cross-section perpendicular to the substrate, the bit line extends in a direction parallel to the substrate, and the second conductive contact area surrounds the sidewall of the bit line; the semiconductor layer includes a first region that contacts the first conductive contact area, and the shape and size of the first region are the same as those of the first conductive contact area.

9. The semiconductor device according to claim 4, characterized in that, The semiconductor layer includes a second region that contacts the outer surface of the second conductive contact region, the second region surrounding the second conductive contact region, and the second region having the same shape and size as the second conductive contact region.

10. The semiconductor device according to claim 9, characterized in that, It also includes multiple rows and columns of memory cells located on the same layer, with a bit line provided between the transistors of two adjacent columns of memory cells, and the second region of the semiconductor layer of two adjacent transistors being shared.

11. The semiconductor device according to any one of claims 1 to 10, characterized in that, The semiconductor layer includes a metal oxide semiconductor layer.

12. The semiconductor device according to claim 1, characterized in that, It also includes multiple rows and columns of memory cells located on the same layer, with an isolation layer disposed between the transistors of two adjacent memory cells in the column direction, and the two insulating regions of the transition layer contacting the isolation layer.

13. An electronic device, characterized in that, Includes the semiconductor device as described in any one of claims 1 to 12.

14. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided on which insulating thin films and sacrificial thin films are sequentially and alternately deposited to form a stacked structure; A plurality of first holes are formed in the stacked structure extending in a direction perpendicular to the substrate, and word line sacrificial layers are filled in the first holes; The stacked structure forms a plurality of first trenches, and between the plurality of first trenches are bit line regions extending along the column direction, and a plurality of branch regions that are spaced apart in the column direction and extend in the row direction and intersect the bit line regions, wherein the first hole is located in the branch regions. An isolation layer is filled into the first trench; The sacrificial film of multiple branch regions is etched away to form a transverse groove extending in the row direction between adjacent isolation layers and adjacent insulating films, and a portion of the sacrificial film layer is retained between the transverse groove and the word line sacrificial layer; A first capacitor electrode and a capacitor dielectric layer are sequentially deposited on the inner wall of the transverse groove, and a second capacitor electrode is filled in the transverse groove. An opening is formed in the isolation layer of the first trench to vertically expose the sacrificial film between the word line sacrificial layer and the first capacitor electrode, as well as the sacrificial film layer of the bit line region. The sacrificial film is etched away to form a first via between the word line sacrificial layer and the first capacitor electrode, and a second via corresponding to the bit line region. The first via and the second via are connected and expose each sidewall of the word line sacrificial layer. A gate insulating layer, a semiconductor thin film, a metal thin film, and a conductive thin film filling the first and second vias are sequentially deposited on the inner walls of the first and second vias. A gate insulating layer, a semiconductor thin film, and a metal thin film surround the sidewalls of the exposed word line sacrificial layer; Remove the conductive film filling the opening to expose the metal film on the two opposite sidewalls of the word line sacrificial layer in the column direction. Then, oxidize the exposed metal film using an oxidation process to form a metal oxide insulating region.

15. The method for manufacturing a semiconductor device according to claim 14, characterized in that, After removing the conductive film filling the opening to expose the metal film on the two opposite sidewalls of the word line sacrificial layer in the column direction, the process further includes: Remove the semiconductor thin film within the opening to disconnect the semiconductor thin films of different transistor layers from each other.

16. The method for manufacturing a semiconductor device according to claim 14, characterized in that, After the oxidation process is used to oxidize the exposed metal film to form a metal oxide insulating region, the process further includes: An insulating layer is filled into the opening; An opening is made in the isolation layer to expose each gate insulating layer, semiconductor thin film and metal thin film near the first capacitor electrode. The area in the gate insulating layer that contacts the first capacitor electrode is etched away, and a conductive layer is filled in the area where the gate insulating layer is removed, so that the conductive layer contacts both the first capacitor electrode and the metal thin film. The word line sacrificial layer is etched away to expose the inner wall of the first hole, and word lines are formed in the first hole.

17. The method for manufacturing a semiconductor device according to claim 14, characterized in that, The method of forming an opening perpendicular to the substrate in the isolation layer of the first trench includes: Multiple openings are spaced apart along the column direction, the openings being located between adjacent branch regions in the column direction, the sidewalls of the openings exposing each insulating film and each sacrificial film between the word line sacrificial layer and the first capacitor electrode, and the sidewalls of the openings not exposing the word line sacrificial layer.

18. The method for manufacturing a semiconductor device according to claim 14, characterized in that, The second via is located between two adjacent word line sacrificial layers in the row direction and exposes part of the sidewalls of the two word line sacrificial layers.

19. The method for manufacturing a semiconductor device according to claim 16, characterized in that, The etching process removes the region of the gate insulating layer that contacts the first capacitor electrode, and fills the region where the gate insulating layer is removed with a conductive layer, including: The gate insulating layer in contact with the first capacitor electrode and the semiconductor thin film located near the first capacitor electrode are etched away, and a conductive layer is filled in; or, the gate insulating layer in contact with the first capacitor electrode, the semiconductor thin film and a portion of the metal thin film located near the first capacitor electrode are etched away, exposing the conductive thin film, and a conductive layer is filled in.

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