AlGaInP red-light LED chip structure with polarization-induced tunnel junction and preparation method of AlGaInP red-light LED chip structure

Abstract

The invention discloses an AlGaInP red light LED chip structure with a polarization-induced tunnel junction and a preparation method thereof. The chip structure sequentially comprises a GaAs substrate, an n-type GaAs buffer layer, an n-type etching barrier layer, an n-type GaAs ohmic contact layer, an n-type limiting layer, a non-doped InGaP / quantum well structure, a p-type spacer layer, a p-type AlGaInP polarization-induced doping layer, an insertion layer and an n-type ohmic contact layer from bottom to top. Wherein the p-type AlGaInP polarization induction doping layer introduces a piezoelectric polarization electric field through an Al component gradual change design, high-density two-dimensional hole gas is formed through induction, and the high-Al component insertion layer and the n-type ohmic contact layer form a tunnel junction; according to the invention, the problems of low p-type doping efficiency and high resistivity of the AlGaInP material with high Al component are fundamentally solved, the epitaxial structure and the chip process are simplified, the series resistance of the chip is reduced, the luminous efficiency is improved, the yield is improved, and the method has remarkable technical and commercial values.

Description

Technical Field

[0001] This invention relates to the field of Micro LED display technology, specifically to an AlGaInP red LED chip structure with a polarization-induced tunneling junction and its fabrication method. Background Technology

[0002] AlGaInP red LEDs are widely used in displays, lighting, and optical communications due to their high luminous efficiency, good stability, and long lifespan. However, existing AlGaInP red LEDs still face significant technical bottlenecks in fabrication and performance, mainly in the following aspects: 1. Low p-type doping efficiency: In existing technologies, magnesium (Mg) is commonly used as the p-type doping source for AlGaInP materials. However, in p-type AlGaInP with high aluminum (Al) content, the ionization energy of Mg acceptors is significantly increased, leading to insufficient hole concentration in the p-type region (often insufficient to meet the high conductivity requirements of devices) and high resistivity. Increasing the Mg doping concentration to improve conductivity easily induces a self-compensation effect—forming Mg-related deep-level defects or complexes—while also introducing dislocations and non-radiative recombination centers, damaging crystal quality. This not only fails to effectively improve hole concentration and conductivity but also reduces device luminous efficiency. Furthermore, the inherently low hole mobility of p-type AlGaInP further exacerbates the high resistance problem.

[0003] 2. Complex manufacturing process and high cost: To alleviate the high resistance problem in the p-type region, existing solutions typically design multi-layer p-type epitaxial structures (such as p-type spacer layers, p-type confinement layers, p-type superlattice structures, p-type hole-providing layers, and p-type ohmic contact layers), which leads to cumbersome epitaxial growth steps and increased time consumption. At the same time, in the subsequent chip fabrication, metallization processes are required for the p-type and n-type regions to prepare ohmic contact electrodes. The process involves many steps and has a low tolerance for errors, which not only increases the manufacturing cost but also reduces the chip production yield.

[0004] The aforementioned problems severely restrict the performance improvement and industrialization cost control of AlGaInP red LEDs, and there is an urgent need for an innovative structure and preparation method that can overcome the bottleneck of p-type doping and simplify the process. Summary of the Invention

[0005] The purpose of this invention is to overcome the technical defects of existing red Micro LEDs and provide an AlGaInP red LED chip structure and fabrication method with a polarization-induced tunneling junction. The aim is to: improve the hole concentration and conductivity of the p-type region through a polarization-induced mechanism without relying on high-concentration Mg doping; introduce a tunneling junction to synergistically enhance the conductivity of the p-type region, solving the p-type doping bottleneck of high-Al composition AlGaInP; simplify the epitaxial structure and chip process, reduce manufacturing costs, and improve chip yield and luminous performance.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows: An AlGaInP red LED chip structure with a polarization-induced tunneling junction, comprising, from bottom to top: a GaAs substrate, an n-type GaAs buffer layer, and an n-type... Etching barrier layer, n-type GaAs ohmic contact layer, n-type Confinement layer, undoped InGaP / Quantum well structure, p-type Spacer layer, p-type AlGaInP polarization-induced doped layer, Insertion layer and n-type Ohmic contact layer; The composition of the p-type AlGaInP polarization-induced doped layer is from Gradient to Al component =0.6-0.7、 =0.9-1, component ratio =0.5、 =0.7; The Al components of the insertion layer =0.8-1, and is consistent with n-type The ohmic contact layer forms a tunnel junction; The n-type Al composition of ohmic contact layer =0.8-1, component ratio =0.5.

[0007] In a preferred embodiment, the GaAs substrate has a wafer size of 2-12 inches, a thickness of 350-650 μm, and a bevel angle of 2-15°.

[0008] In a preferred embodiment, the doping source of the n-type GaAs buffer layer is silane, and the doping concentration is [missing information]. The thickness is 100-300 nm; the doping source of the n-type GaAs ohmic contact layer is silane, and the doping concentration is... The thickness is 10-50nm.

[0009] In a preferred embodiment, the undoped InGaP / The quantum well structure has 1-5 quantum well pairs, and the InGaP well layer thickness is 1.5-4.5 nm. Al composition of the barrier layer =0.6-0.9, component ratio =0.5, thickness is 4-10nm.

[0010] In a preferred embodiment, the p-type Al components of the spacer layer =0.8-0.9, component ratio =0.5, the doping source is magnesia-dicenocene, and the doping concentration is The thickness is 30-100nm.

[0011] This application also provides a method for fabricating an AlGaInP red LED chip structure with a polarization-induced tunneling junction, using metal-organic chemical vapor deposition (MOCVD) technology, including the following steps: S1, an n-type GaAs buffer layer is epitaxially grown on a GaAs substrate; S2, epitaxial growth of n-type GaAs buffer layer. Etching barrier layer; S3, in n-type An n-type GaAs ohmic contact layer is epitaxially grown on an etch barrier layer; S4, epitaxial growth of n-type GaAs ohmic contact layer. Constraint layer; S5, in n-type Epitaxial growth of undoped InGaP / on confinement layer Quantum well structure; S6, in undoped InGaP / Epitaxial growth of p-type quantum well structures Spacer layer; S7, in p-type p-type AlGaInP polarization-induced doped layer is epitaxially grown on the spacer layer; S8, high Al composition epitaxially grown on a p-type AlGaInP polarization-induced doped layer. Insertion layer; S9, in Epitaxial growth of n-type on the insertion layer An ohmic contact layer is used to obtain an epitaxial wafer; S10, the epitaxial wafer is bonded, substrate removed, mesa structure prepared, passivated and single-step metallized to obtain a chip.

[0012] In a preferred embodiment, in step S2, the n-type... The etch barrier layer was grown at a temperature of 700-780℃, a growth rate of 0.2-0.7 nm / s, and the doping source was silane with a doping concentration of [missing information]. The thickness is 100-300nm.

[0013] In a preferred embodiment, in step S7, the growth temperature of the p-type AlGaInP polarization-induced doped layer is 700-780℃, the growth rate is 0.2-0.5 nm / s, the dopant source is magnesia-diocene, and the doping concentration is [missing information]. The thickness is 30-100nm; the composition is gradually changed by adjusting the flow ratio of trimethylaluminum to trimethylgallium.

[0014] In a preferred embodiment, in step S8, the high Al component... The growth source for the insertion layer is trimethylaluminum, trimethylgallium and arsenide, the growth temperature is 700-780℃, the growth rate is 0.2-0.5nm / s, and the thickness is 10-40nm.

[0015] In a preferred embodiment, in step S10, the diameter of the mesa structure is 1-50 μm; the passivation layer material is... , or The electrodes are prepared by atomic layer deposition (ALD) or plasma-enhanced chemical vapor deposition (PECVD); single-step metallization is carried out by electron beam evaporation or sputtering to prepare Cr / Au or Ti / Al / Ni / Au electrodes.

[0016] Due to the application of the above technical solution, the beneficial effects of this application compared with the prior art are as follows: 1. Overcoming the bottleneck of p-type doping: By designing the Al composition gradient of the p-type AlGaInP polarization-induced doping layer, a piezoelectric polarization field is introduced to induce the formation of a high-density two-dimensional hole gas (2DHG). This can improve the hole concentration and conductivity of the p-type region without relying on high-concentration Mg doping, and completely solves the self-compensation effect and crystal quality damage problem of high Al composition AlGaInP. At the same time, the tunnel junction effectively increases the net hole concentration of the p-type region through the electron tunneling effect, synergistically enhancing the conductivity. 2. Simplified structure and process: The composite structure of "p-type AlGaInP spacer layer + polarization-induced doping layer + tunnel junction" is adopted to replace the traditional multilayer p-type epitaxial structure (such as superlattice, hole-providing layer, etc.), reducing the number of epitaxial growth layers and time; and both the p-side (connected by tunnel junction) and the n-side ohmic contact layer are n-type doped, so only a single-step metallization is required to prepare the electrodes on both sides, simplifying the chip process and reducing manufacturing costs; 3. Significantly improved performance and yield: Compared with traditional chips, the series resistance of the chip in this invention is significantly improved at 20 ohms. 25% reduction at current density (from 12) Dropped to 9 The luminous efficiency at 625nm wavelength is improved by 18% (from 22lm / W to 26lm / W), and the production yield is improved from 71% to 85%, combining high luminous performance with industrialization advantages. Attached Figure Description

[0017] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the AlGaInP red LED chip structure with polarization-induced tunneling junction of the present invention. Figure 2 This is a flowchart of the fabrication method of the AlGaInP red LED chip structure with polarization-induced tunneling junction of the present invention. Among them, 1. GaAs substrate; 2. n-type GaAs buffer layer; 3. n-type 4. Etching barrier layer; 5. n-type GaAs ohmic contact layer; Confinement layer; 6. Undoped InGaP / Quantum well structure; 7. p-type 8. Spacer layer; 9. p-type AlGaInP polarization-induced doped layer; Insertion layer; 10, n-type Ohmic contact layer. Detailed Implementation

[0019] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0020] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0021] In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," and "longitudinal" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing the invention and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.

[0022] Furthermore, in addition to indicating direction or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in certain situations to indicate a dependency or connection. Those skilled in the art can understand the specific meaning of these terms in this invention based on the specific circumstances.

[0023] Furthermore, the terms "installation," "setup," "equipped with," "connection," "linking," and "socketing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this invention based on the specific circumstances.

[0024] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0025] Example 1 Please see Figure 1 The present invention provides an AlGaInP red LED chip structure with a polarization-induced tunneling junction, which includes the following functional layers from bottom to top: GaAs substrate 1: The wafer size is 2-12 inches, the thickness is 350-650μm, and the bevel angle is 2-15°, which provides stable support for subsequent epitaxial layers; n-type GaAs buffer layer 2: grown on GaAs substrate 1, the doping source is silane, and the doping concentration is [missing information]. With a thickness of 100-300 nm, it is used to provide a flat, low-defect epitaxial growth surface and improve the crystal quality of the epitaxial layer; n-type Etching barrier layer 3: grown on n-type GaAs buffer layer 2, wherein the Al composition x = 0.1-0.4, the composition ratio y = 0.5, the doping source is silane, and the doping concentration is [missing information]. With a thickness of 100-300nm, it is used in subsequent chip manufacturing processes to precisely control substrate removal and etching depth; n-type GaAs ohmic contact layer 4: grown on n-type On the etch barrier layer 3, the doping source is silane, and the doping concentration is [missing information]. The thickness is 10-50nm, which is used to form a low-resistance ohmic contact with the metal electrode later; n-type Confinement layer 5: grown on n-type GaAs ohmic contact layer 4, wherein the Al component =0.7-1, component ratio =0.5, the doping source is silane, and the doping concentration is With a thickness of 150-500 nm, it is used to confine the overflow of charge carriers in the quantum well structure and improve the charge carrier recombination efficiency; Undoped InGaP / Quantum well structure 6: grown in n-type On the confinement layer 5, where the barrier layer Al component =0.6-0.9, component ratio =0.5; the number of quantum well pairs is 1-5, and the InGaP well layer thickness is 1.5-4.5 nm. The barrier layer is 4-10nm thick and is the core light-emitting region of the LED, where charge carriers recombine and radiate red light. p-type Spacer layer 7: grown on undoped InGaP / On quantum well structure 6, where the Al component =0.8-0.9, component ratio =0.5, the doping source is magnesia-dicenocene, and the doping concentration is With a thickness of 30-100nm, it is used to connect the quantum well structure and the polarization-induced doping layer to optimize the carrier transport path; p-type AlGaInP polarization-induced doped layer 8: grown on p-type On spacer layer 7, its components are from Gradient to Al component =0.6-0.7、 =0.9-1, component ratio =0.5、 =0.7; the doping source is magnesia-dicenocene, and the doping concentration is... The thickness is 30-100nm; gradient strain is introduced through the Al composition gradient design to induce the generation of piezoelectric polarization field, thereby forming a high-density two-dimensional hole gas (2DHG) near the interlayer interface, which significantly improves the hole concentration and conductivity of the p-type region. Insertion layer 9: grown on p-type AlGaInP polarization-induced doped layer 8, wherein the Al composition is... =0.8-1, thickness is 10-40nm, with a lower p-type AlGaInP polarization-induced doped layer 8 and an upper n-type The ohmic contact layer 10 forms a tunneling junction, providing a barrier structure for the tunneling effect; n-type Ohmic contact layer 10: grown on high Al composition On the insertion layer 9, where the Al component =0.8-1, component ratio =0.5, the doping source is silane, and the doping concentration is Thickness is 30-100 nm; compared with high Al content The insertion layer 9 together forms a tunnel junction. Under reverse bias, electrons in the p-type region can be injected into this layer through the potential barrier via the quantum tunneling effect, which effectively increases the net hole concentration in the p-type region. At the same time, this layer is n-type doped, which can form a low-resistance ohmic contact with the metal electrode.

[0026] Example 2 Please see Figure 2 This application also provides a method for fabricating an AlGaInP red LED chip structure with a polarization-induced tunneling junction, which uses metal-organic chemical vapor deposition (MOCVD) for epitaxial growth. The specific steps are as follows: S1,n-type GaAs buffer layer 2 growth: GaAs substrate 1 is placed in the MOCVD reaction chamber, and silane is used as the dopant source, trimethylgallium (TMGa) and hydrogen arsenide (… Using hydrogen as the growth source and hydrogen as the carrier gas, an n-type GaAs buffer layer 2 was epitaxially grown at a temperature of 620-700℃ and a growth rate of 0.2-0.7 nm / s, with the doping concentration controlled at [value missing]. Thickness is 100-300nm; S2, n type Etching barrier layer 3 growth: On n-type GaAs buffer layer 2, silane is used as the dopant source, and trimethylaluminum (TMAl), trimethylgallium (TMGa), trimethylindium (TMIn) and phosphine are added. Using α as the growth source and hydrogen as the carrier gas, n-type epitaxial growth was performed at a temperature of 700-780℃ and a growth rate of 0.2-0.7 nm / s. Etch barrier layer 3 (x=0.1-0.4, y=0.5), controlling the doping concentration to be... Thickness is 100-300nm; S3, n-type GaAs ohmic contact layer 4 growth: In n-type On the etch barrier layer 3, silane is used as the dopant source, and trimethylgallium (TMGa) and arsenide ( Using hydrogen as the growth source and hydrogen as the carrier gas, an n-type GaAs ohmic contact layer 4 was epitaxially grown at a temperature of 620-700℃ and a growth rate of 0.1-0.3 nm / s, with the doping concentration controlled at [value missing]. Thickness is 10-50nm; S4, n type Growth of confinement layer 5: On the n-type GaAs ohmic contact layer 4, trimethylaluminum (TMAl), trimethylgallium (TMGa), trimethylindium (TMIn), and phosphine (…) are grown using silane as the dopant source. Using α as the growth source and hydrogen as the carrier gas, n-type epitaxial growth was performed at a temperature of 700-780℃ and a growth rate of 0.2-0.5 nm / s. Restriction layer 5 ( =0.7-1, =0.5), controlling the doping concentration to be Thickness is 150-500nm; S5, undoped InGaP / Quantum well structure 6 growth: in n-type On confinement layer 5, trimethylaluminum (TMAl), trimethylgallium (TMGa), trimethylindium (TMIn) and phosphine ( Using hydrogen as the growth source and hydrogen as the carrier gas, InGaP well layers were epitaxially grown alternately at a growth rate of 0.1-0.2 nm / s at a temperature of 700-780℃. Barrier layer ( =0.6-0.9, =0.5), forming 1-5 pairs of undoped InGaP / Quantum well structure 6, with InGaP well layer thickness controlled to be 1.5-4.5 nm and barrier layer thickness to be 4-10 nm; S6, p type Spacer layer 7 growth: in undoped InGaP / On quantum well structure 6, magnesia-dicyclopentadiene (MgO) The doping source is trimethylaluminum (TMAl), trimethylgallium (TMGa), trimethylindium (TMIn), and phosphine (…). Using hydrogen as the growth source and hydrogen as the carrier gas, p-type epitaxial growth was performed at a temperature of 700-780℃ and a growth rate of 0.2-0.5 nm / s. Spacer layer 7 ( =0.8-0.9, =0.5), controlling the doping concentration to be Thickness is 30-100nm; S7, p-type AlGaInP polarization-induced doped layer 8 growth: In p-type On spacer layer 7, magnesia-diocene (MgO) The doping source is trimethylaluminum (TMAl), trimethylgallium (TMGa), trimethylindium (TMIn), and phosphine (…). Using TMAl as the growth source and hydrogen as the carrier gas, p-type AlGaInP polarization-induced doped layers were epitaxially grown at a temperature of 700-780℃ and a growth rate of 0.2-0.5 nm / s. The layer composition was adjusted by gradually changing the flow rate ratio of TMAl to TMGa. ( =0.6-0.7, =0.5) Gradually change to ( =0.9-1, =0.7), controlling the doping concentration to be Thickness is 30-100nm; S8, Insertion layer 9 growth: On p-type AlGaInP polarization-induced doped layer 8, trimethylaluminum (TMAl), trimethylgallium (TMGa), and arsenide (… Using hydrogen as the growth source and hydrogen as the carrier gas, high-Al composition epitaxial growth was performed at a temperature of 700-780℃ and a growth rate of 0.2-0.5 nm / s. Insertion layer 9 ( =0.8-1), controlling the thickness to be 10-40nm; S9, n-type Ohmic contact layer 10 growth: in high Al composition On insertion layer 9, silane is used as the dopant source, along with trimethylaluminum (TMAl), trimethylgallium (TMGa), trimethylindium (TMIn), and phosphine (… Using α as the growth source and hydrogen as the carrier gas, n-type epitaxial growth was performed at a temperature of 700-780℃ and a growth rate of 0.2-0.5 nm / s. Ohmic contact layer 10 ( =0.8-1, =0.5), controlling the doping concentration to be An epitaxial wafer with a thickness of 30-100 nm is obtained. S10, post-chip processing: The epitaxial wafers described above are bonded to Si-based CMOS driver chips to achieve electrical connection and thermal management. The GaAs substrate 1, the n-type GaAs buffer layer 2, and the n-type GaAs buffer layer 3 were removed by chemical etching. Etch barrier layer 3 to expose n-type GaAs ohmic contact layer 4; Mesa (mesa) structures with diameters of 1-50 μm are formed on the exposed epitaxial layer using photolithography and dry etching processes to define the chip's light-emitting area; Atomic layer deposition (ALD) or plasma-enhanced chemical vapor deposition (PECVD) equipment was used to deposit on the sidewalls of the mesa structure. , or Passivation layer to prevent leakage current and environmental corrosion on the chip surface; Holes were created in the passivation layer using photolithography and etching processes to expose the n-type GaAs ohmic contact layer 4 and the n-type... Ohmic contact layer 10: Metallization is carried out in a single step using electron beam evaporation or sputtering to prepare metal electrodes (such as Cr / Au or Ti / Al / Ni / Au), while forming ohmic contacts between the n-side and p-side (connected by a tunnel junction) to complete chip fabrication.

[0027] Example 3 This application provides a method for fabricating an AlGaInP red LED chip structure with a polarization-induced tunneling junction, comprising the following steps: S1, Substrate preparation and growth of n-type GaAs buffer layer 2: Substrate preparation: A 4-inch GaAs substrate 1, 500 μm thick, with a 10° bevel angle, was selected and cleaned (acetone sonication → ethanol sonication → deionized water rinsing → After drying, place it in the MOCVD reaction chamber; n-type GaAs buffer layer 2 growth: using silane as the dopant source (flow rate 5 sccm), TMGa (flow rate 20 sccm) and (Flow rate 500 sccm) is the growth source, Using a carrier gas (flow rate 10 L / min), a reaction temperature of 650 °C, and a growth rate of 0.5 nm / s, an n-type GaAs buffer layer 2 with a thickness of 200 nm was grown. The doping concentration was... ; S2, n-type Etching barrier layer 3 growth: silane flow rate 5 sccm, TMAl (flow rate 8 sccm), TMGa (flow rate 12 sccm), TMIn (flow rate 15 sccm). (Flow rate 600 sccm) is the growth source. Carrier gas 10 L / min, temperature 750℃, growth rate 0.4 nm / s, growing n-type Etching barrier layer 3 (x=0.2, y=0.5), 200 nm thick, doping concentration... ; S3,n-type GaAs ohmic contact layer 4 growth: silane flow rate 10 sccm, TMGa (flow rate 20 sccm) (Flow rate 500 sccm) Carrier gas 10 L / min, temperature 650℃, growth rate 0.2 nm / s, growth of n-type GaAs ohmic contact layer 4, thickness 30 nm, doping concentration... ; S4, n type Growth of confinement layer 5: silane flow rate 5 sccm, TMAl (flow rate 18 sccm), TMGa (flow rate 2 sccm), TMIn (flow rate 15 sccm). (Flow rate 600 sccm) Carrier gas 10 L / min, temperature 750℃, growth rate 0.3 nm / s, growing n-type Restriction layer 5 ( =0.9, =0.5), thickness 300nm, doping concentration ; S5, undoped InGaP / Quantum well structure 6 growth: TMAl (flux 15 sccm), TMGa (flux 5 sccm), TMIn (flux 15 sccm) (Flow rate 600 sccm) Carrier gas 10 L / min, temperature 750℃, growth rate 0.15 nm / s; alternating growth of 3 pairs of InGaP well layers (3 nm thick) and... Barrier layer ( =0.8, =0.5mm thick (7nm), forming a quantum well structure; S6, p type Spacer layer 7 growth: Magnesium dicerocene flow rate 8 sccm, TMAl (flow rate 16 sccm), TMGa (flow rate 4 sccm), TMIn (flow rate 15 sccm). (Flow rate 600 sccm) Carrier gas 10 L / min, temperature 750℃, growth rate 0.3 nm / s, p-type growth Spacer layer 7 ( =0.85, =0.5), thickness 60nm, doping concentration ; S7,p-type AlGaInP polarization-induced doped layer 8 growth: Magnesium pyrocene flux 8 sccm, TMIn (flux 15 sccm). (Flow rate 600 sccm) Carrier gas flow rate 10 L / min, temperature 750℃, growth rate 0.3 nm / s; initial stage TMAl flow rate 12 sccm, TMGa flow rate 8 sccm (corresponding to...) ( =0.6, =0.5), and gradually increase the TMA1 flow rate to 18 sccm and decrease the TMAGa flow rate to 2 sccm (corresponding to 0.5) over time. ( =0.9, =0.7), total thickness 60nm, doping concentration ; S8, Insertion layer 9 growth: TMAl (flow rate 18 sccm), TMGa (flow rate 2 sccm) (Flow rate 500 sccm) Carrier gas 10 L / min, temperature 750℃, growth rate 0.3 nm / s, growth Insertion layer 9 ( =0.9), thickness 20nm; S9, n-type Ohmic contact layer 10 growth: silane flow rate 10 sccm, TMAl (flow rate 18 sccm), TMGa (flow rate 2 sccm), TMIn (flow rate 15 sccm). (Flow rate 600 sccm) Carrier gas 10 L / min, temperature 750℃, growth rate 0.3 nm / s, growing n-type Ohmic contact layer 10 ( =0.9, =0.5), thickness 60nm, doping concentration ; S10, chip back-end process: The epitaxial wafer and the Si-based CMOS driver are connected by gold-gold bonding (temperature 300℃, pressure 5MPa); use : : An etchant solution with a ratio of 3:1:10 was used to etch and remove GaAs substrate 1, n-type GaAs buffer layer 2, and n-type GaAs buffer layer 3 at 60°C. Etch barrier layer 3 to expose n-type GaAs ohmic contact layer 4; Photolithography defines the mesa pattern, and dry etching ( / Plasma forms a Mesa structure with a diameter of 20 μm; PECVD deposition Passivation layer (100nm thick), photolithography and etching to expose n-type GaAs ohmic contact layer 4 and n-type Ohmic contact layer 10; Cr / Au electrodes (Cr thickness 50 nm, Au thickness 500 nm) are prepared by electron beam evaporation, and ohmic contact on both sides is completed in a single step to obtain the final chip.

[0028] Performance testing and comparison: The performance of the chip prepared in Example 3 and a traditional AlGaInP red LED chip (containing a p-type AlInP confinement layer 5, a p-type AlGaInP superlattice, a p-type GaP hole-providing layer, and a heavily doped p-type GaP ohmic contact layer) were tested under the following conditions: room temperature and a forward current of 20mA. The test results are shown in the table below.

[0029] Test results show that the chip of this invention is significantly superior to traditional chips in terms of resistance, luminous efficiency and yield, verifying the effectiveness of the technical solution.

[0030] Finally, it should be noted that the above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An AlGaInP red LED chip structure with a polarization-induced tunneling junction, characterized in that, From bottom to top, the layers consist of: GaAs substrate, n-type GaAs buffer layer, and n-type... Etching barrier layer, n-type GaAs ohmic contact layer, n-type Confinement layer, undoped InGaP / Quantum well structure, p-type Spacer layer, p-type AlGaInP polarization-induced doped layer, Insertion layer and n-type Ohmic contact layer; The composition of the p-type AlGaInP polarization-induced doped layer is from Gradient to Al component =0.6-0.7、 =0.9-1, component ratio =0.5、 =0.7; The Al components of the insertion layer =0.8-1, and is consistent with n-type The ohmic contact layer forms a tunnel junction; The n-type Al composition of ohmic contact layer =0.8-1, component ratio =0.

5.

2. The AlGaInP red LED chip structure with polarization-induced tunneling junction according to claim 1, characterized in that, The GaAs substrate has a wafer size of 2-12 inches, a thickness of 350-650 μm, and a bevel angle of 2-15°.

3. The AlGaInP red LED chip structure with polarization-induced tunneling junction according to claim 1, characterized in that, The doping source for the n-type GaAs buffer layer is silane, and the doping concentration is [missing information]. The thickness is 100-300 nm; the doping source of the n-type GaAs ohmic contact layer is silane, and the doping concentration is... The thickness is 10-50nm.

4. The AlGaInP red LED chip structure with polarization-induced tunneling junction according to claim 1, characterized in that, The undoped InGaP / The quantum well structure has 1-5 quantum well pairs, and the InGaP well layer thickness is 1.5-4.5 nm. Al composition of the barrier layer =0.6-0.9, component ratio =0.5, thickness is 4-10nm.

5. The AlGaInP red LED chip structure with polarization-induced tunneling junction according to claim 1, characterized in that, The p-type Al components of the spacer layer =0.8-0.9, component ratio =0.5, the doping source is magnesia-dicenocene, and the doping concentration is The thickness is 30-100nm.

6. A method for fabricating an AlGaInP red LED chip structure with a polarization-induced tunneling junction as described in any one of claims 1-5, characterized in that, The metal-organic chemical vapor deposition (MOCVD) technique is employed, including the following steps: S1, an n-type GaAs buffer layer is epitaxially grown on a GaAs substrate; S2, epitaxial growth of n-type GaAs buffer layer. Etching barrier layer; S3, in n-type An n-type GaAs ohmic contact layer is epitaxially grown on an etch barrier layer; S4, epitaxial growth of n-type GaAs ohmic contact layer. Constraint layer; S5, in n-type Epitaxial growth of undoped InGaP / on confinement layer Quantum well structure; S6, in undoped InGaP / Epitaxial growth of p-type quantum well structures Spacer layer; S7, in p-type p-type AlGaInP polarization-induced doped layer is epitaxially grown on the spacer layer; S8, high Al composition epitaxially grown on a p-type AlGaInP polarization-induced doped layer. Insertion layer; S9, in Epitaxial growth of n-type on the insertion layer An ohmic contact layer is used to obtain an epitaxial wafer; S10, the epitaxial wafer is bonded, substrate removed, mesa structure prepared, passivated and single-step metallized to obtain a chip.

7. The preparation method according to claim 6, characterized in that, In step S2, n-type The etch barrier layer was grown at a temperature of 700-780℃, a growth rate of 0.2-0.7 nm / s, and the doping source was silane with a doping concentration of [missing information]. The thickness is 100-300nm.

8. The preparation method according to claim 6, characterized in that, In step S7, the growth temperature of the p-type AlGaInP polarization-induced doped layer is 700-780℃, the growth rate is 0.2-0.5 nm / s, the dopant source is magnesia-diocene, and the doping concentration is [missing information]. The thickness is 30-100nm; the composition is gradually changed by adjusting the flow ratio of trimethylaluminum to trimethylgallium.

9. The preparation method according to claim 6, characterized in that, In step S8, the high-Al component The growth source for the insertion layer is trimethylaluminum, trimethylgallium and arsenide, the growth temperature is 700-780℃, the growth rate is 0.2-0.5nm / s, and the thickness is 10-40nm.

10. The preparation method according to claim 6, characterized in that, In step S10, the diameter of the mesa structure is 1-50 μm; the passivation layer material is... , or It is prepared by atomic layer deposition (ALD) or plasma-enhanced chemical vapor deposition (PECVD); Single-step metallization employs electron beam evaporation or sputtering processes to prepare Cr / Au or Ti / Al / Ni / Au electrodes.

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