Package including optical integrated device

Abstract

A package includes: a package substrate; a first integrated device coupled to the package substrate through a first plurality of solder interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a plurality of pillar interconnects in the encapsulation layer; a metallization portion coupled to the plurality of pillar interconnects; a second integrated device coupled to the metallization portion through a second plurality of solder interconnects; an optical integrated device coupled to the package substrate; and an optical fiber coupled to the optical integrated device.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit from: (i) U.S. non-provisional application No. 18 / 607,170, filed March 15, 2024, with the U.S. Patent and Trademark Office; and (ii) U.S. provisional application No. 63 / 491,982, filed March 24, 2023, with the U.S. Patent and Trademark Office. U.S. non-provisional application No. 18 / 607,170 claims priority and benefit from U.S. provisional application No. 63 / 491,982. The entire contents of both applications are incorporated herein by reference, as fully set forth herein and for all applicable purposes. Technical Field

[0003] Various features involve packages including integrated devices. Background Technology

[0004] A package may include a substrate and integrated devices. These components are coupled together to provide a package capable of performing a variety of functions. The performance of a package and its components can depend on many factors. There is a ongoing demand for packages that offer improved performance. Furthermore, there is a ongoing demand for packages that include a more compact form factor, enabling implementation in smaller devices. Summary of the Invention

[0005] Various features involve packages including integrated devices.

[0006] One example provides a package comprising: a package substrate; a first integrated device coupled to the package substrate via a first plurality of solder interconnects; an encapsulation layer that at least partially encapsulates the first integrated device; a plurality of pillar interconnects located within the encapsulation layer; a metallization portion coupled to the plurality of pillar interconnects; a second integrated device coupled to the metallization portion via a second plurality of solder interconnects; an optical integrated device coupled to the package substrate; and an optical fiber coupled to the optical integrated device.

[0007] Another example provides a package comprising: a metallized portion; a first integrated device coupled to the metallized portion via a first plurality of solder interconnects, wherein the front side of the first integrated device is oriented toward the metallized portion; an encapsulation layer that at least partially encapsulates the first integrated device; a plurality of pillar interconnects located within the encapsulation layer; a second integrated device coupled to the metallized portion via a second plurality of solder interconnects; an optical integrated device coupled to the metallized portion via a third plurality of solder interconnects; an optical fiber coupled to the optical integrated device; and a package substrate coupled to the plurality of pillar interconnects via a fourth plurality of solder interconnects. Attached Figure Description

[0008] Various features, properties and advantages will become apparent from the specific embodiments described below when viewed in conjunction with the accompanying drawings, in which the same reference numerals are used to identify them throughout.

[0009] Figure 1 A cross-sectional view of an exemplary package including optical integrated devices is shown.

[0010] Figure 2 A cross-sectional view of an exemplary package including optical integrated devices is shown.

[0011] Figure 3 A cross-sectional view of an exemplary package including optical integrated devices is shown.

[0012] Figure 4 A cross-sectional view of an exemplary package including optical integrated devices is shown.

[0013] Figure 5 A cross-sectional view of an exemplary package including optical integrated devices is shown.

[0014] Figure 6 A cross-sectional view of an exemplary package including optical integrated devices is shown.

[0015] Figure 7 A cross-sectional view of an exemplary optical integrated device is shown.

[0016] Figure 8 A cross-sectional view of an exemplary optical integrated device is shown.

[0017] Figures 9A-9D An exemplary sequence for manufacturing packages that include optical integrated devices is shown.

[0018] Figure 10 An exemplary flowchart of a method for manufacturing a package including optical integrated devices is shown.

[0019] Figure 11 Various electronic devices that can integrate the dies, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein are shown. Detailed Implementation

[0020] In the following description, specific details are set forth to provide a thorough understanding of various aspects of this disclosure. However, those skilled in the art will understand that these aspects can be practiced without these specific details. For example, circuits may be shown as block diagrams to avoid obscuring these aspects with unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail so as not to obscure various aspects of this disclosure.

[0021] This disclosure describes a package comprising: a package substrate; a first integrated device coupled to the package substrate via a first plurality of solder interconnects; an encapsulation layer that at least partially encapsulates the first integrated device; a plurality of pillar interconnects located within the encapsulation layer; a metallized portion coupled to the plurality of pillar interconnects; a second integrated device coupled to the metallized portion via a second plurality of solder interconnects; an optical integrated device coupled to the package substrate; and an optical fiber coupled to the optical integrated device. The optical integrated device coupled to the package substrate provides a short distance for at least one electrical path to the various integrated devices within the package. Furthermore, the closer proximity of the optical integrated device to the integrated device provides a small IR drop, which contributes to improved performance of the integrated device and / or the package.

[0022] Exemplary package including optical integrated devices

[0023] Figure 1 A cross-sectional view of a package 100 including optical integrated devices is shown. The package 100 includes optical integrated devices 101, a package substrate 102, integrated devices 103, a metallized portion 104, integrated devices 105, integrated devices 109, a connector socket 107, passive devices 111, integrated devices 130, integrated devices 132, integrated devices 134, multiple pillar interconnects 160, and an encapsulation layer 106.

[0024] The packaging substrate 102 includes at least one dielectric layer 120 and a plurality of interconnects 122 (e.g., substrate interconnects). An optical integrated device 101 is coupled to the packaging substrate 102. For example, the optical integrated device 101 may be embedded within the packaging substrate 102. In some implementations, the optical integrated device 101 may be located within a cavity of the packaging substrate 102. The optical integrated device 101 may be coupled to the packaging substrate 102 by an adhesive (not shown). An optical fiber 110 is coupled to the optical integrated device 101. The optical fiber 110 may be considered part of the package 100. The optical fiber 110 may be coupled to another optical integrated device (not shown). This other optical integrated device may be coupled to another package or board. The following... Figure 7 An example of an optical integrated device 101 is shown and described below. The optical integrated device may include the capability to: (i) convert optical signals / energy into electrical signals / energy, and / or (ii) convert electrical signals / energy into optical signals / energy. For example, a signal can be received as an optical signal and can be converted into an electrical signal. Similarly, a signal can be received as an electrical signal and can be converted into an optical signal. The optical integrated device can transmit signals as optical signals and / or electrical signals. Below, at least... Figure 7 and Figure 8 More detailed examples of optical integrated devices are shown and described below. In some implementations, optical integrated device 101 may be implemented as optical integrated device 700 and / or optical integrated device 800.

[0025] Encapsulation layer 106 at least partially encapsulates integrated device 103, integrated device 105, and multiple pillar interconnects 160. Integrated device 103 is coupled to package substrate 102 via solder interconnects from multiple solder interconnects 123. The front side of integrated device 103 faces package substrate 102. For example, the surface of the front side of integrated device 103 may be oriented in a direction toward package substrate 102. Integrated device 105 is coupled to package substrate 102 via solder interconnects from multiple solder interconnects 123. The front side of integrated device 105 faces package substrate 102. For example, the surface of the front side of integrated device 105 may be oriented in a direction toward package substrate 102. Multiple pillar interconnects 160 are coupled to package substrate 102 via other solder interconnects from multiple solder interconnects 123. Underfill 125 exists between package substrate 102 and encapsulation layer 106. Underfill 125 may laterally surround multiple solder interconnects 123. The underfill 125 can be coupled to and contact the package substrate 102, multiple solder interconnects 123, encapsulation layer 106, integrated device 103 and integrated device 105.

[0026] Metallization portion 104 is coupled to encapsulation layer 106 and a plurality of pillar interconnects 160. Metallization portion 104 includes at least one dielectric layer 140 and a plurality of metallization interconnects 142. Metallization portion 104 may be a redistribution portion. The plurality of metallization interconnects 142 may include redistribution interconnects. The plurality of pillar interconnects 160 are coupled to metallization interconnects from the plurality of metallization interconnects 142 of metallization portion 104. The back side of integrated device 103 may face metallization portion 104. For example, the surface of the back side of integrated device 103 may be oriented in a direction toward encapsulation substrate 104. The back side of integrated device 105 may face metallization portion 104. For example, the surface of the back side of integrated device 105 may be oriented in a direction toward metallization portion 104. The bottom surface of metallization portion 104 may be coupled to encapsulation layer 106.

[0027] The passive device 111 can be coupled to the top surface of the metallization portion 104 via multiple solder interconnects 112. For example, the passive device 111 can be coupled to metallization interconnects from multiple metallization interconnects 142 via multiple solder interconnects 112.

[0028] Integrated device 109 can be coupled to the top surface of metallized portion 104 via multiple solder interconnects 190. For example, integrated device 109 can be coupled to metallized interconnects from multiple metallized interconnects 142 via multiple solder interconnects 190. Integrated device 130 can be coupled to the top surface of metallized portion 104 via multiple solder interconnects 131. For example, integrated device 130 can be coupled to metallized interconnects from multiple metallized interconnects 142 via multiple solder interconnects 131.

[0029] Integrated device 132 is coupled to integrated device 130 via multiple solder interconnects 133. Integrated device 134 is coupled to integrated device 132 via multiple solder interconnects 135. Integrated devices 130, 132, and 134 may be stacked integrated devices.

[0030] Connector socket 107 is coupled to the top surface of metallized portion 104 via multiple solder interconnects 170. Connector socket 107 is configured to be electrically coupled to connector socket 113. Connector socket 107 is configured to provide an electrical path for power. Connector socket 107 is configured to provide an electrical path for ground. Connector socket 107 can be coupled to connector socket 113 via one or more wires.

[0031] Package 100 is coupled to board 108 via a plurality of solder interconnects 183. Board 108 includes at least one board dielectric layer 180 and a plurality of board interconnects 182. Connector socket 113 is coupled to board 108 via a plurality of solder interconnects 114. Connector sockets (e.g., 107, 113) may include a plurality of connector interconnects. Connector sockets may include connector housings, wherein the plurality of connector interconnects may be at least partially located within the connector housings. One or more wirings coupled to connector sockets may include wiring interconnects and a dielectric layer surrounding one or more wirings.

[0032] Optical fiber 110 is coupled to optical integrated device 101. Optical fiber 110 may extend through encapsulation substrate 102. Optical fiber 110 may extend through a cavity in encapsulation substrate 102. In some implementations, optical fiber 110 may extend within plate 108. In some implementations, optical fiber 110 may extend between encapsulation substrate 102 and plate 108. One or more optical signals may travel through optical fiber 110 to and / or from optical integrated device 101.

[0033] Integrated device 103 can be configured to be electrically coupled to optical integrated device 101 via electrical path 151, which includes solder interconnects from a plurality of solder interconnects 123. Integrated device 105 can be configured to be electrically coupled to optical integrated device 101 via electrical path 153, which includes solder interconnects from a plurality of solder interconnects 123. Integrated device 103 can be configured to be electrically coupled to optical integrated device 101 via electrical path 155, which includes solder interconnects from a plurality of solder interconnects 123, optical integrated device 101, and another solder interconnect from a plurality of solder interconnects. Integrated device 130 can be configured to be electrically coupled to optical integrated device 101 via electrical path 155, which includes solder interconnects from a plurality of solder interconnects 131, metallized interconnects from metallized portions 104, pillar interconnects from a plurality of pillar interconnects 160, and solder interconnects from a plurality of solder interconnects 123. Electrical path 155 may include an electrical path between integrated device 130 and integrated device 134. The electrical path between integrated device 130 and integrated device 134 may include die interconnects from integrated device 130, through-substrate vias from integrated device 130, solder interconnects from a plurality of solder interconnects 133, die interconnects from integrated device 132, through-substrate vias from integrated device 132, solder interconnects from a plurality of solder interconnects 135, and die interconnects from integrated device 134. In some implementations, pillar interconnects may exist between (i) integrated device 130 and integrated device 132, and / or (ii) integrated device 132 and integrated device 134. In such cases, the electrical path between integrated device 130 and integrated device 134 may also include the aforementioned pillar interconnects.

[0034] Integrated device 130 can be configured to be electrically coupled to integrated device 103 via electrical path 157, which includes solder interconnects from a plurality of solder interconnects 131, metallization interconnects from metallization portions 104, pillar interconnects from a plurality of pillar interconnects 160, solder interconnects from a plurality of solder interconnects 123, interconnects from a package substrate 102, and another solder interconnect from the plurality of solder interconnects 123. Electrical path 157 may include an electrical path between integrated device 130 and integrated device 134. The electrical path between integrated device 130 and integrated device 134 may include die interconnects from integrated device 130, through-substrate vias from integrated device 130, solder interconnects from a plurality of solder interconnects 133, die interconnects from integrated device 132, through-substrate vias from integrated device 132, solder interconnects from a plurality of solder interconnects 135, and die interconnects from integrated device 134. In some implementations, a pillar interconnect may exist between: (i) integrated device 130 and integrated device 132, and / or (ii) integrated device 132 and integrated device 134. In such a case, the electrical path between integrated device 130 and integrated device 134 may also include the aforementioned pillar interconnect.

[0035] Integrated device 130 can be configured to be electrically coupled to integrated device 105 via electrical path 157, which includes solder interconnects from a plurality of solder interconnects 131, metallization interconnects from metallization portion 104, pillar interconnects from a plurality of pillar interconnects 160, solder interconnects from a plurality of solder interconnects 123, interconnects from package substrate 102, and another solder interconnect from the plurality of solder interconnects 123. Electrical path 159 may include an electrical path between integrated device 130 and integrated device 134. The electrical path between integrated device 130 and integrated device 134 may include die interconnects from integrated device 130, through-substrate vias from integrated device 130, solder interconnects from a plurality of solder interconnects 133, die interconnects from integrated device 132, through-substrate vias from integrated device 132, solder interconnects from a plurality of solder interconnects 135, and die interconnects from integrated device 134. In some implementations, a pillar interconnect may exist between: (i) integrated device 130 and integrated device 132, and / or (ii) integrated device 132 and integrated device 134. In such a case, the electrical path between integrated device 130 and integrated device 134 may also include the aforementioned pillar interconnect.

[0036] In some implementations, optical signals can be received by optical integrated device 101 via optical fiber 110. Optical integrated device 101 can convert optical signals into electrical signals, and the electrical signals can be transmitted to integrated device 103, integrated device 105 and / or integrated device 130 using one or more of the electrical paths described above.

[0037] In some implementations, the optical integrated device 101 can receive electrical signals through one or more of the aforementioned electrical paths. The optical integrated device 101 can convert the electrical signals into optical signals, and the optical signals can be transmitted through the optical fiber 110.

[0038] Integrated device 103 may be a system-on-a-chip (SoC). Integrated device 109 may include a power management integrated circuit (PMIC). Passive device 111 may include a capacitor. Integrated devices 130, 132, and / or 134 may include memory. The electrical path between integrated device 109 and integrated device 130 may include solder interconnects from a plurality of solder interconnects 190, metallized interconnects from a plurality of metallized interconnects 142, and solder interconnects from a plurality of solder interconnects 131. The electrical path between integrated device 109 and integrated device 134 may include the electrical path between integrated device 130 and integrated device 134, as described above.

[0039] In some implementations, optical integrated device 101 can be configured to operate as a bridge. Integrated device 103 can be configured to be electrically coupled to integrated device 105 via optical integrated device 101. For example, the electrical path between integrated device 103 and integrated device 105 may include optical integrated device 101. The electrical path between integrated device 103 and integrated device 105 may include electrical path 151 (as described above), interconnections from optical integrated device 101, and electrical path 153 (as described above).

[0040] Figure 2 A cross-sectional view of a package 200 including optical integrated devices is shown. The package 200 includes an optical integrated device 101, a package substrate 102, an integrated device 103, a metallized portion 104, an integrated device 105, an integrated device 109, a connector socket 107, a passive device 111, an integrated device 130, an integrated device 132, an integrated device 134, a plurality of pillar interconnects 160, an encapsulation layer 106, at least one rear power rail interconnect 203, and at least one rear power rail interconnect 205.

[0041] At least one back power rail interconnect 203 can be considered part of the integrated device 103. For example, at least one back power rail interconnect 203 can be located in the die substrate of the integrated device 103. The back power rail interconnect 203 may include trace interconnects and / or through-substrate vias. The back power rail interconnect 203 can be considered part of the back side of the integrated device 103. At least one back power rail interconnect 205 can be considered part of the integrated device 105. For example, at least one back power rail interconnect 205 can be located in the die substrate of the integrated device 105. The back power rail interconnect 205 may include trace interconnects and / or through-substrate vias. The back power rail interconnect 205 can be considered part of the back side of the integrated device 105.

[0042] Package 200 is similar to package 100. However, some components of package 200 are positioned and / or coupled in a different manner than some components of package 100.

[0043] Integrated device 103 is coupled to the bottom surface of metallized portion 104 via multiple solder interconnects 223. The front side of integrated device 103 may face metallized portion 104. For example, the surface of the front side of integrated device 103 may be oriented toward metallized portion 104. Integrated device 105 is coupled to the bottom surface of metallized portion 104 via multiple solder interconnects 225. The front side of integrated device 105 may face metallized portion 104. For example, the surface of the front side of integrated device 105 may be oriented toward metallized portion 104. Integrated device 109 is coupled to the bottom surface of metallized portion 104 via multiple solder interconnects 190. Passive device 111 is coupled to the bottom surface of metallized portion 104 via multiple solder interconnects 112. Encapsulation layer 106 may at least partially encapsulate integrated device 103, integrated device 105, integrated device 109, passive device 111, back power rail interconnect 203, back power rail interconnect 205, and multiple pillar interconnects 160. The encapsulation layer 106 may include a molding compound, resin, and / or epoxy resin. The encapsulation layer 106 may be formed using compression molding, transfer molding, or liquid molding processes.

[0044] Package 200 is coupled to board 108 via multiple solder interconnects 183. Connector socket 113 is coupled to board 108 via multiple solder interconnects 114.

[0045] Integrated device 130 can be configured to be electrically coupled to integrated device 103 via electrical path 257, which includes solder interconnects from a plurality of solder interconnects 131, metallized interconnects from metallized portions 104, and solder interconnects from a plurality of solder interconnects 223. Integrated device 130 can be configured to be electrically coupled to integrated device 105 via electrical path 259, which includes solder interconnects from a plurality of solder interconnects 131, metallized interconnects from metallized portions 104, and solder interconnects from a plurality of solder interconnects 225. Electrical path 257 may include an electrical path between integrated device 130 and integrated device 134. The electrical path between integrated device 130 and integrated device 134 may include die interconnects from integrated device 130, through-substrate vias from integrated device 130, solder interconnects from a plurality of solder interconnects 133, die interconnects from integrated device 132, through-substrate vias from integrated device 132, solder interconnects from a plurality of solder interconnects 135, and die interconnects from integrated device 134. In some implementations, pillar interconnects may exist between (i) integrated device 130 and integrated device 132, and / or (ii) integrated device 132 and integrated device 134. In such cases, the electrical path between integrated device 130 and integrated device 134 may also include the aforementioned pillar interconnects. Electrical path 259 may include the electrical path between integrated device 130 and integrated device 134. The electrical path between integrated device 130 and integrated device 134 may include die interconnects from integrated device 130, through-substrate vias from integrated device 130, solder interconnects from a plurality of solder interconnects 133, die interconnects from integrated device 132, through-substrate vias from integrated device 132, solder interconnects from a plurality of solder interconnects 135, and die interconnects from integrated device 134. In some implementations, pillar interconnects may exist between (i) integrated device 130 and integrated device 132, and / or (ii) integrated device 132 and integrated device 134. In such cases, the electrical path between integrated device 130 and integrated device 134 may also include the aforementioned pillar interconnects.

[0046] Integrated device 130 can be configured to be electrically coupled to optical integrated device 101 via electrical path 255, which includes solder interconnects from a plurality of solder interconnects 131, metallization interconnects from metallization portions 104, pillar interconnects from a plurality of pillar interconnects 160, and solder interconnects from a plurality of solder interconnects 123. Electrical path 255 may include an electrical path between integrated device 130 and integrated device 134. The electrical path between integrated device 130 and integrated device 134 may include die interconnects from integrated device 130, through-substrate vias from integrated device 130, solder interconnects from a plurality of solder interconnects 133, die interconnects from integrated device 132, through-substrate vias from integrated device 132, solder interconnects from a plurality of solder interconnects 135, and die interconnects from integrated device 134. In some implementations, a pillar interconnect may exist between: (i) integrated device 130 and integrated device 132, and / or (ii) integrated device 132 and integrated device 134. In such a case, the electrical path between integrated device 130 and integrated device 134 may also include the aforementioned pillar interconnect.

[0047] In some implementations, the integrated device 103 may be configured to be electrically coupled to the integrated device 105 via a plurality of solder interconnects 223, metallized interconnects from a plurality of metallized interconnects 142, and a plurality of solder interconnects 225.

[0048] In some implementations, integrated device 103 may be configured to be electrically coupled to integrated device 105 via solder interconnects from a plurality of solder interconnects 123, optical integrated device 101, and other solder interconnects from the plurality of solder interconnects 123. In some implementations, optical integrated device 101 may be configured as a bridge. In some implementations, optical integrated device 101, integrated device 103, and / or integrated device 105 may be one or more chiplets. In some implementations, integrated device 103 may be manufactured using a first technology node, and integrated device 105 may be manufactured using a second technology node that is less advanced than the first technology node. Optical integrated device 101 may be manufactured using a third technology node different from the first and / or second technology nodes.

[0049] In some implementations, optical signal can be received by optical integrated device 101 via optical fiber 110. Optical integrated device 101 can convert optical signal into electrical signal, and the electrical signal can be sent to integrated device 103, integrated device 105 and / or integrated device 130 using one or more of the above-mentioned electrical paths.

[0050] In some implementations, the optical integrated device 101 can receive electrical signals through one or more of the aforementioned electrical paths. The optical integrated device 101 can convert the electrical signals into optical signals, and the optical signals can be transmitted through the optical fiber 110.

[0051] Optical integrated device 101 is coupled to packaging substrate 102. For example, optical integrated device 101 may be embedded in packaging substrate 102. In some implementations, optical integrated device 101 may be located in a cavity of packaging substrate 102. Optical integrated device 101 may be coupled to packaging substrate 102 by an adhesive (not shown). Optical fiber 110 is coupled to optical integrated device 101. Optical fiber 110 may be considered as part of package 200.

[0052] Power can be supplied to integrated device 103 via the back side. For example, the electrical path for supplying power to integrated device 103 may include interconnects from a plurality of interconnects 122, at least one solder interconnect from a plurality of solder interconnects 123, and at least one back power rail interconnect 203. Similarly, power can be supplied to integrated device 105 via the back side. For example, the electrical path for supplying power to integrated device 105 may include interconnects from a plurality of interconnects 122, at least one solder interconnect from a plurality of solder interconnects 123, and at least one back power rail interconnect 205.

[0053] Figure 3 A cross-sectional view of a package 300 including optical integrated devices is shown. The package 300 includes an optical integrated device 101, a package substrate 102, an integrated device 103, a metallized portion 104, an integrated device 105, an integrated device 109, a connector socket 107, a passive device 111, an integrated device 130, an integrated device 132, an integrated device 134, a plurality of pillar interconnects 160, an encapsulation layer 106, at least one rear power rail interconnect 203, and at least one rear power rail interconnect 205.

[0054] Package 300 is similar to package 200. However, some components of package 300 are positioned and / or coupled in a different manner than some components of package 200.

[0055] For example, the optical integrated device 101 is coupled to the top surface of the metallized portion 104 via multiple solder interconnects 310. Below... Figure 8 An example of optical integrated device 101 is shown and described. Optical integrated device 101 is coupled to optical integrated device 301 via optical fiber 110. Optical integrated device 301 is coupled to board 108. Optical integrated device 301 can be coupled to board 108 via multiple solder interconnects.

[0056] Integrated device 130 can be configured to be electrically coupled to integrated device 103 via electrical path 257, which includes solder interconnects from a plurality of solder interconnects 131, metallized interconnects from metallized portion 104, and solder interconnects from a plurality of solder interconnects 223. Integrated device 130 can be configured to be electrically coupled to integrated device 105 via electrical path, which includes solder interconnects from a plurality of solder interconnects 131, metallized interconnects from metallized portion 104, and solder interconnects from a plurality of solder interconnects 225.

[0057] Integrated device 130 can be configured to be electrically coupled to optical integrated device 101 via electrical path 355, which includes solder interconnects from a plurality of solder interconnects 131, metallization interconnects from metallization portion 104, and solder interconnects from a plurality of solder interconnects 310. Electrical path 355 may include an electrical path between integrated device 130 and integrated device 134. The electrical path between integrated device 130 and integrated device 134 may include die interconnects from integrated device 130, through-substrate vias from integrated device 130, solder interconnects from a plurality of solder interconnects 133, die interconnects from integrated device 132, through-substrate vias from integrated device 132, solder interconnects from a plurality of solder interconnects 135, and die interconnects from integrated device 134. In some implementations, pillar interconnects may exist between: (i) integrated device 130 and integrated device 132, and / or (ii) integrated device 132 and integrated device 134. In such a case, the electrical path between integrated device 130 and integrated device 134 may also include the aforementioned pillar interconnect.

[0058] The integrated device 103 can be configured to be electrically coupled to the optical integrated device 101 via an electrical path 353, which includes solder interconnects from a plurality of solder interconnects 223, metallization interconnects from a metallization portion 104, and solder interconnects from a plurality of solder interconnects 310.

[0059] The integrated device 105 can be configured to be electrically coupled to the optical integrated device 101 via an electrical path 357, which includes solder interconnects from a plurality of solder interconnects 225, metallization interconnects from a metallization portion 104, and solder interconnects from a plurality of solder interconnects 310.

[0060] In some implementations, optical signal can be received by optical integrated device 101 via optical fiber 110. Optical integrated device 101 can convert optical signal into electrical signal, and the electrical signal can be sent to integrated device 103, integrated device 105 and / or integrated device 130 using one or more of the above-mentioned electrical paths.

[0061] In some implementations, the optical integrated device 101 can receive electrical signals through one or more of the aforementioned electrical paths. The optical integrated device 101 can convert the electrical signals into optical signals, and the optical signals can be transmitted through the optical fiber 110.

[0062] Figure 4 A cross-sectional view of a package 400 including optical integrated devices is shown. The package 400 includes an optical integrated device 101, a package substrate 102, an integrated device 103, a metallized portion 104, an integrated device 105, an integrated device 109, a connector socket 107, a passive device 111, an integrated device 130, an integrated device 132, an integrated device 134, a plurality of pillar interconnects 160, an encapsulation layer 106, at least one rear power rail interconnect 203, and at least one rear power rail interconnect 205.

[0063] Package 400 is similar to package 300. However, some components of package 400 are positioned and / or coupled in a different manner than some components of package 300. For example, package substrate 102 includes interconnects 122a and 122b. Interconnects 122a and 122b are configured as heat dissipation devices in package substrate 102. Board 108 includes board interconnects 182a and 182b. Heat sink 403 is coupled to board 108. Thermal interface material may be used to couple heat sink 403 to board 108. Heat sink 405 is coupled to board 108. Thermal interface material may be used to couple heat sink 405 to board 108. Heat generated by integrated device 103 and / or back power rail interconnect 203 can be dissipated by solder interconnects from multiple solder interconnects 123, interconnect 122a, solder interconnects from multiple solder interconnects 183, board interconnect 182a, and heat sink 403. The heat generated by the integrated device 105 and / or the rear power rail interconnect 205 can be dissipated by the following: solder interconnects from the plurality of solder interconnects 123, interconnect 122b, solder interconnects from the plurality of solder interconnects 183, board interconnect 182b, and heat sink 405.

[0064] In some implementations, integrated device 103 may be a first chip, and integrated device 105 may be a second chip. Integrated device 103 may be configured to perform a first plurality of functions and / or operations. Integrated device 105 may be configured to perform a second plurality of functions and / or operations. The second plurality of functions and / or operations includes at least one function and / or operation that is different from the first plurality of functions and / or operations. In some implementations, integrated device 103 may be manufactured using a first technology node, and integrated device 105 may be manufactured using a second technology node that is less advanced than the first technology node.

[0065] Figure 5 A cross-sectional view of a package 500 including optical integrated devices is shown. The package 500 includes an optical integrated device 101, a package substrate 102, an integrated device 103, a metallized portion 104, an integrated device 105, an integrated device 109, a connector socket 107, a passive device 111, an integrated device 130, an integrated device 132, an integrated device 134, a plurality of pillar interconnects 160, an encapsulation layer 106, at least one rear power rail interconnect 203, and at least one rear power rail interconnect 205.

[0066] Package 500 is similar to package 300 and / or package 400. However, some components of package 500 are positioned and / or coupled in a different manner than some components of package 300 and / or package 400.

[0067] like Figure 5 As shown, optical integrated device 101 is coupled to the top surface of metallized portion 104 (e.g., a second integrated device) via multiple solder interconnects 310. Integrated device 109 is coupled to the top surface of metallized portion 104 via multiple solder interconnects 190. Passive device 111 is coupled to the top surface of metallized portion 104 via multiple solder interconnects 112.

[0068] In some implementations, the optical integrated device 101 can receive the optical signal via the optical fiber 110. The optical integrated device 101 can convert the optical signal into an electrical signal, and can use the above-mentioned at least Figure 3 One or more of the electrical paths described herein send electrical signals to integrated device 103, integrated device 105 and / or integrated device 130.

[0069] In some implementations, the optical integrated device 101 can be used via the above at least Figure 3 One or more electrical paths described herein receive electrical signals. The electrical signals can be converted into optical signals by the optical integrated device 101, and the optical signals can be transmitted via the optical fiber 110.

[0070] Figure 6 A cross-sectional view of a package 600 including optical integrated devices is shown. The package 600 includes an optical integrated device 101, a package substrate 102, an integrated device 103, a metallized portion 104, an integrated device 105, an integrated device 109, a connector socket 107, a passive device 111, an integrated device 130, an integrated device 132, an integrated device 134, a plurality of pillar interconnects 160, an encapsulation layer 106, at least one rear power rail interconnect 203, and at least one rear power rail interconnect 205.

[0071] Package 600 is similar to package 300 and / or package 400. However, some components of package 600 are positioned and / or coupled in a different manner than some components of package 300 and / or package 400.

[0072] Package substrate 102 includes interconnects 122a and 122b. Interconnects 122a and 122b are configured as heat dissipation devices in package substrate 102. Board 108 includes board interconnects 182a and 182b. Heat sink 403 is coupled to board 108. Thermal interface material may be used to couple heat sink 403 to board 108. Heat sink 405 is coupled to board 108. Thermal interface material may be used to couple heat sink 405 to board 108. Heat generated by integrated device 103 and / or back power rail interconnect 203 can be dissipated by solder interconnects from multiple solder interconnects 123, interconnect 122a, solder interconnects from multiple solder interconnects 183, board interconnect 182a, and heat sink 403. The heat generated by the integrated device 105 and / or the rear power rail interconnect 205 can be dissipated by the following: solder interconnects from the plurality of solder interconnects 123, interconnect 122b, solder interconnects from the plurality of solder interconnects 183, board interconnect 182b, and heat sink 405.

[0073] In some implementations, the optical integrated device 101 can receive the optical signal via the optical fiber 110. The optical integrated device 101 can convert the optical signal into an electrical signal, and can use the above-mentioned at least Figure 3 One or more of the electrical paths described herein send electrical signals to integrated device 103, integrated device 105 and / or integrated device 130.

[0074] In some implementations, the optical integrated device 101 can be used via the above at least Figure 3 One or more electrical paths described herein receive electrical signals. The electrical signals can be converted into optical signals by the optical integrated device 101, and the optical signals can be transmitted via the optical fiber 110.

[0075] It should be noted that any of the packages may include additional components and / or other components. For example, integrated devices may be replaced by integrated device stacks. For example, integrated device 103 and / or integrated device 105 may each be replaced by an integrated device stack (e.g., similar to integrated device 130, integrated device 132, and integrated device 134). Integrated device stacks may include front-to-front integrated devices, front-to-back integrated devices, and / or back-to-back integrated devices. In another example, a substrate and / or interposer may be located between package substrate 102 and integrated device 103 and / or integrated device 105.

[0076] It should be noted that any of the plurality of solder interconnects described in this disclosure can be implemented as a plurality of bump interconnects. Bump interconnects can include pillar interconnects and solder interconnects. In some implementations, the plurality of bump interconnects can include a plurality of microbump interconnects. Microbump interconnects can be similar to bump interconnects. However, microbump interconnects can have a smaller size than bump interconnects to accommodate finer interconnect pitches. For example, in some implementations, the plurality of solder interconnects 123 can be implemented as a plurality of microbump interconnects, while the plurality of solder interconnects 183 can be implemented as a plurality of bump interconnects. In some implementations, one or more bump interconnects can have a pitch in the range of approximately 80-120 micrometers (e.g., minimum pitch). In some implementations, one or more microbump interconnects can have a pitch in the range of approximately 25-50 micrometers (e.g., minimum pitch).

[0077] Exemplary optical integrated device

[0078] Figure 7 An exemplary optical integrated device 700 is shown. The optical integrated device 700 can be... Figures 1-6 The optical integrated device 101 is described. The optical integrated device 700 includes a substrate 702 (e.g., a silicon substrate), an optics 704, waveguides 706, 708, and 709, an oxide layer 710, multiple interconnects 730, and an optical fiber ferrule 720. An optical fiber 110 is coupled to waveguide 706 and the optical fiber ferrule 720. Optical signals from the optical fiber 110 can travel through waveguides 706, 709, and 708. The optical signals can be processed by the optics 704, whereby the optical signals can be converted into electrical signals. The electrical signals can be transmitted through the multiple interconnects 730. The oxide layer 710 can surround waveguides 709 and 708. Waveguide 709 can include silicon (S) or silicon nitride. Waveguide 709 can extend through the thickness of the substrate 702, like a through-silicon via (TSV). Waveguide 708 can include silicon (S), germanium (Ge), or silicon nitride.

[0079] Figure 8 An exemplary optical integrated device 800 is shown. The optical integrated device 800 may be... Figures 1-6 The optical integrated device 101 is described. The optical integrated device 800 includes a substrate 702 (e.g., a silicon substrate), an optics 704, a waveguide 706, multiple interconnects 830, multiple interconnects 840, and an optical fiber ferrule 720. An optical fiber 110 is coupled to the waveguide 706 and the optical fiber ferrule 720. An optical signal from the optical fiber 110 can travel through the waveguide 706. The optical signal can be processed by the optics 704, wherein the optical signal can be converted into an electrical signal. The electrical signal can be transmitted through the multiple interconnects 830 and / or the multiple interconnects 840.

[0080] Although not shown, the fiber ferrule 720 can be coupled to a carrier (e.g., a silicon carrier), and the carrier serves to help couple the fiber ferrule 720 to the waveguide 706. In some implementations, more than one fiber may be present.

[0081] Different implementations can use different waveguide designs. In some implementations, the waveguide may include silicon ridge waveguides, silicon rib waveguides, silicon trench waveguides, and / or silicon nitride ridge waveguides. However, other implementations can use other waveguide designs. For example, some implementations may combine germanium with silicon.

[0082] Integrated devices (e.g., 103) may include dies (e.g., bare semiconductor dies). Integrated devices may include power management integrated circuits (PMICs). Integrated devices may include application processors. Integrated devices may include modems. Integrated devices may include radio frequency (RF) devices, passive devices, filters, capacitors, inductors, antennas, transmitters, receivers, gallium arsenide (GaAs) based integrated devices, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated devices, silicon (Si) based integrated devices, silicon carbide (SiC) based integrated devices, memories, power management processors, and / or combinations thereof. Integrated devices (e.g., 103, 105) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). Integrated devices may include transistors. Integrated devices may be examples of electrical components and / or electrical devices. In some implementations, integrated devices may be chips. In some implementations, optical integrated devices (e.g., 101) may be chips. Compared to other processes used to manufacture other types of integrated devices, dies can be manufactured using processes that provide better yields, which can reduce the overall cost of manufacturing dies. Different dies can have different sizes and / or shapes. Different dies can be configured to provide different functions. Different dies can have different interconnect densities (e.g., interconnects with different widths and / or spacings). In some implementations, several dies can be used to perform the functions of one or more chips (e.g., one or more integrated devices). Thus, for example, a single integrated device can be divided into several dies. As described above, using several dies that perform several functions can reduce the overall cost of the package compared to using a single chip to perform all the functions of the package. In some implementations, one or more dies and / or one or more integrated devices (e.g., 103) in the dies described in this disclosure can be manufactured using the same technology node or two or more different technology nodes. For example, an integrated device can be manufactured using a first technology node, and dies can be manufactured using a second technology node that is less advanced than the first technology node. In such an example, the integrated device may include components (e.g., interconnects, transistors) having a first minimum size, and the die may include components (e.g., interconnects, transistors) having a second minimum size, wherein the second minimum size is larger than the first minimum size. In some implementations, the integrated device of the package and another integrated device may be manufactured using the same technology node or different technology nodes. In some implementations, the die of the package and another die may be manufactured using the same technology node or different technology nodes.

[0083] A technology node can refer to a specific manufacturing process and / or technology used to manufacture integrated devices and / or dies. A technology node can specify the minimum possible size that can be manufactured (e.g., minimum size) (e.g., transistor size, trace width, gap between two transistors). Different technology nodes may have different yield losses. Different technology nodes may have different costs. Technology nodes that produce components with fine details (e.g., traces, transistors) are more expensive and may have higher yield losses compared to technology nodes that produce components with less fine detail (e.g., traces, transistors). Therefore, more advanced technology nodes may be more expensive and may have higher yield losses compared to less advanced technology nodes. When all the functions of a package are implemented in a single integrated device, the same technology node is used to manufacture the entire integrated device, even if some functions of the integrated device do not require manufacturing using that specific technology node. Therefore, the integrated device is locked into a technology node. To optimize the cost of the package, some functions can be implemented in different integrated devices and / or dies, where the different integrated devices and / or dies can be manufactured using different technology nodes to reduce the overall cost. For example, functionality requiring state-of-the-art technology nodes may be implemented in the integrated device, while functionality achievable with less advanced technology nodes may be implemented in another integrated device and / or one or more dies. An example would be an integrated device manufactured using a first technology node (e.g., the state-of-the-art technology node) configured to provide computing applications, and at least one die manufactured using a second technology node configured to provide other functionality, wherein the second technology node is less expensive than the first technology node, and wherein the second technology node manufactures a component with a minimum size larger than the minimum size of a component manufactured using the first technology node. Examples of computing applications could include high-performance computing and / or high-performance processing, which can be achieved by manufacturing and packaging as many transistors as possible in the integrated device. This is why the state-of-the-art technology node can be used to manufacture the integrated device configured for computing applications, while less advanced technology nodes can be used to manufacture other dies, as these dies may not require manufacturing as many transistors as possible. Therefore, using a combination of different technology nodes (which may have different associated yield losses) for different integrated devices and / or dies can reduce the total cost of the package compared to using a single integrated device to perform all the functions of the package.

[0084] Another advantage of dividing functionality into several integrated devices and / or dies is that it allows for improvements in package performance without having to redesign each individual integrated device and / or die. For example, if a package configuration uses a first integrated device and a first die, it is possible to improve package performance by changing the design of the first integrated device while keeping the design of the first die the same. Therefore, the first die can be reused with improved and / or differently configured first integrated devices. This saves costs when manufacturing packages with improved integrated devices by eliminating the need to redesign the first die.

[0085] Exemplary sequence for manufacturing packages including optically integrated devices

[0086] In some implementations, manufacturing the package involves several processes. Figures 9A-9D Exemplary sequences for providing or manufacturing packages are shown. In some implementations, Figures 9A-9D The sequence can be used to provide or manufacture Figure 3 The package is 300. However, Figures 9A-9D The process can be used to manufacture any of the packages described in this disclosure (e.g., 100, 200, 400, 500, 600).

[0087] It should be noted that Figures 9A-9D The sequence can combine one or more stages to simplify and / or clarify the sequence used to provide or manufacture the package. In some implementations, the order of these processes can be changed or modified. In some implementations, one or more processes can be replaced or substituted without departing from the spirit of this disclosure.

[0088] like Figure 9A As shown, stage 1 illustrates the state after the metallized portion 104 on the carrier 900 is provided. The metallized portion 104 includes at least one dielectric layer 140 and a plurality of metallized interconnects 142. The metallized portion 104 can be formed on the carrier 900. The metallized portion 104 can be formed using deposition processes, masking processes, exposure processes, etching processes, plating processes, and / or stripping processes. At least one dielectric layer can be formed and patterned using deposition, lamination, exposure, development, and / or etching processes. Metallized interconnects can be formed using plating processes and / or patterning processes.

[0089] Phase 2 illustrates the state after multiple pillar interconnects 160 have been formed on and coupled to the metallization portion 104. The multiple pillar interconnects 160 are coupled to multiple metallization interconnects 142. A plating process can be used to form the multiple pillar interconnects 160.

[0090] Phase 3 illustrates the state after multiple integrated devices and / or at least one passive device are coupled to the surface of the metallized portion 104. For example, integrated device 103 is coupled to the surface of the metallized portion 104 via multiple solder interconnects 223. For example, the front side of integrated device 103 is coupled to the surface of the metallized portion 104. Integrated device 103 may include a back power rail interconnect 203. Integrated device 105 is coupled to the surface of the metallized portion 104 via multiple solder interconnects 225. For example, the front side of integrated device 105 is coupled to the surface of the metallized portion 104. Integrated device 105 may include a back power rail interconnect 205. Integrated device 109 is coupled to the surface of the metallized portion 104 via multiple solder interconnects 190. Passive device 111 is coupled to the surface of the metallized portion 104 via multiple solder interconnects 112. One or more solder reflow processes can be used to couple multiple integrated devices and / or passive devices to the metallized portion 104.

[0091] like Figure 9B As shown, stage 4 illustrates the state after the encapsulation layer 106 is formed over and coupled to the metallization portion 104. The encapsulation layer 106 may comprise a molding compound, resin, and / or epoxy resin. The encapsulation layer 106 may be formed using compression molding, transfer molding, or liquid molding processes. The encapsulation may be performed on the integrated device 103 / backside power rail interconnect 203, the integrated device 105 / backside power rail interconnect 205, the integrated device 109, the passive device 111, and the plurality of pillar interconnects 160 (e.g., partially encapsulated).

[0092] Phase 5 shows the state after the carrier 900 is decoupled from the metallized portion 104.

[0093] Phase 6 illustrates the state after the package substrate 102 is coupled to the back power rail interconnects (e.g., 203, 205) and multiple pillar interconnects 160 of the integrated devices (e.g., 103, 105) via multiple solder interconnects 123. The power rail interconnects and multiple pillar interconnects 160 can be coupled via the multiple solder interconnects 123 using a solder reflow process. The package substrate 102 can be coupled to the back side of integrated devices 103 and 105. The package substrate 102 includes at least one dielectric layer 120 and multiple interconnects 122. In some implementations, the package substrate 102 may include an optical integrated device 101, and / or the optical integrated device 101 may be coupled to the package substrate 102. Figure 1 and Figure 2 As shown and described, in some implementations, the optical integrated device 101 may be part of the packaging substrate 102. The optical integrated device 101 may be located within a cavity of the packaging substrate 102. The optical integrated device 101 may be coupled to the packaging substrate 102 via an adhesive.

[0094] Phase 7 illustrates the state after an underfill 125 is provided between the package substrate 102 and the encapsulation layer 106. The underfill 125 may be formed such that it laterally surrounds a plurality of solder interconnects 123. The underfill 125 may be coupled to and contact the package substrate 102, the plurality of solder interconnects 123, the encapsulation layer 106, the integrated device 103, and / or the integrated device 105.

[0095] like Figure 9C As shown, stage 8 illustrates the state after one or more integrated devices are coupled to the surface of the metallization portion 104. For example, an integrated device stack can be coupled to the metallization portion 104. In one example, an integrated device stack including integrated devices 130, 132, and 134 can be coupled to the metallization portion 104 via a solder reflow process.

[0096] Phase 9 illustrates the state after the package substrate 102 is coupled to the board 108 via multiple solder interconnects 183. The package substrate 102 can be coupled to the board 108 using a solder reflow process.

[0097] like Figure 9D As shown, stage 10 illustrates the state after optical integrated device 101 is coupled to metallized portion 104 via multiple solder interconnects 310. Optical integrated device 301 is coupled to board 108. Optical integrated device 301 may be similar to optical integrated device 101. Optical integrated device 301 may be coupled to board 108 via multiple solder interconnects. Optical fiber 110 may be coupled to optical integrated device 101 and optical integrated device 301.

[0098] Phase 10 also illustrates the state after connector receptacle 107 is coupled to metallized portion 104 via multiple solder interconnects 170 and connector receptacle 113 is coupled to board 108 via multiple solder interconnects 114. A solder reflow process can be used to connect connector receptacle 107 to metallized portion 104 and connector receptacle 113 to board 108. Connector receptacle 107 can be coupled to connector receptacle 113 via one or more wires.

[0099] An exemplary flowchart of a method for manufacturing a package including optical integrated devices.

[0100] In some implementations, manufacturing the package involves several processes. Figure 10 An exemplary flowchart of a method 1000 for providing or manufacturing a package is shown. In some implementations, Figure 10 Method 1000 can be used to provide or manufacture at least Figures 1-6 The packaging component.

[0101] It should be noted that Figure 10 Method 1000 may combine one or more processes to simplify and / or clarify the methods used to provide or manufacture packages. In some implementations, the order of these processes may be changed or modified.

[0102] This method provides a metallized portion (at 1005) and multiple post interconnects. The metallized portion may be provided on a carrier. In some implementations, providing the metallized portion and multiple post interconnects includes fabricating the metallized portion and multiple post interconnects. Figure 9A Phases 1 and 2 show and describe examples of providing metallized portions 104 and multiple post interconnects 160. Figure 9A Phase 1 illustrates and describes an example of providing a metallized portion. The metallized portion 104 includes at least one dielectric layer 140 and a plurality of metallized interconnects 142. The metallized portion 104 can be formed on a carrier 900. At least one dielectric layer can be formed and patterned using deposition, lamination, exposure, development, and / or etching processes. The metallized interconnects can be formed using plating processes and / or patterning processes.

[0103] Figure 9A Phase 2 shows and describes an example of a plurality of pillar interconnects 160 formed on and coupled to the metallized portion 104. The plurality of pillar interconnects 160 are coupled to a plurality of metallized interconnects 142. The plurality of pillar interconnects 160 can be formed using a plating process.

[0104] This method couples multiple integrated devices and / or at least one passive device (at 1010) to the metallized portion. Figure 9A Phase 3 illustrates and describes examples of multiple integrated devices and / or at least one passive device coupled to the surface of the metallized portion 104. For example, integrated device 103 is coupled to the surface of the metallized portion 104 via multiple solder interconnects 223. Integrated device 105 is coupled to the surface of the metallized portion 104 via multiple solder interconnects 225. Integrated device 109 is coupled to the surface of the metallized portion 104 via multiple solder interconnects 190. Passive device 111 is coupled to the surface of the metallized portion 104 via multiple solder interconnects 112. Multiple integrated devices and / or passive devices can be coupled to the metallized portion 104 using one or more solder reflow processes.

[0105] This method forms an encapsulation layer (at position 1015). The encapsulation layer can at least partially encapsulate multiple pillar interconnects, integrated devices, and / or passive devices. Figure 9BPhase 4 shows and describes an example of an encapsulation layer 106 formed on and coupled to the metallization portion 104. The encapsulation layer 106 may include molding compound, resin, and / or epoxy resin. The encapsulation layer 106 may be formed using compression molding, transfer molding, or liquid molding processes. Encapsulation may be performed on integrated device 103 / backside power rail interconnect 203, integrated device 105 / backside power rail interconnect 205, integrated device 109, passive device 111, and multiple pillar interconnects 160.

[0106] This method can also remove the carrier coupled to the metallized portion (at 1015). Figure 9B Phase 5 shows and describes an example of a carrier 900 decoupled from the metallized portion 104.

[0107] This method can couple the package substrate (at 1020) to multiple pillar interconnects via multiple solder interconnects. Figure 9B Phase 6 illustrates and describes an example of a package substrate 102 coupled to power rail interconnects (e.g., 203, 205) and multiple pillar interconnects 160 via multiple solder interconnects 123 to integrated devices (e.g., 103, 105). A solder reflow process can be used to couple the power rail interconnects and the multiple pillar interconnects 160 via the multiple solder interconnects 123. The package substrate 102 includes at least one dielectric layer 120 and multiple interconnects 122.

[0108] In some implementations, the packaging substrate 102 may include an optical integrated device 101, and / or the optical integrated device 101 may be coupled to the packaging substrate 102. For example... Figure 1 and Figure 2 As shown and described, in some implementations, the optical integrated device 101 may be part of the packaging substrate 102. The optical integrated device 101 may be located within a cavity of the packaging substrate 102. The optical integrated device 101 may be coupled to the packaging substrate 102 via an adhesive.

[0109] In some implementations, once the package substrate 102 is coupled to multiple pillar interconnects via multiple solder interconnects, an underfill 125 can be provided between the package substrate 102 and the encapsulation layer 106. Figure 9B Phase 7 shows and describes an example of providing an underfill. The underfill 125 may be formed such that the underfill 125 laterally surrounds a plurality of solder interconnects 123. The underfill 125 may be coupled to and contact the package substrate 102, the plurality of solder interconnects 123, the encapsulation layer 106, the integrated device 103 and / or the integrated device 105.

[0110] This method can also couple integrated devices and / or passive devices (at 1020) to the package. For example, this method can couple integrated devices and / or passive devices to the surface of a metallized portion. Figure 9C Phase 8 shows and describes examples of one or more integrated devices coupled to the surface of the metallization portion 104. For example, an integrated device stack may be coupled to the metallization portion 104. In one example, an integrated device stack including integrated device 130, integrated device 132, and integrated device 134 may be coupled to the metallization portion 104 via a solder reflow process.

[0111] This method can couple the package substrate (at 1025) to the board via multiple solder interconnects. Figure 9C Phase 9 shows and describes an example of a package substrate 102 coupled to a board 108 via multiple solder interconnects 183. A solder reflow process can be used to couple the package substrate 102 to the board 108 via multiple solder interconnects 183.

[0112] This method can couple a connector socket (at 1030) to the package and the board. The method can also (at 1030) couple an optical integrated device to the package and another optical integrated device to the board. Figure 9D Phase 10 shows and describes an example of an optical integrated device 101 coupled to a metallized portion 104 via multiple solder interconnects 310. Optical integrated device 301 is coupled to a board 108. Optical integrated device 301 may be similar to optical integrated device 101. Optical integrated device 301 may be coupled to board 108 via multiple solder interconnects. Optical fiber 110 may be coupled to both optical integrated device 101 and optical integrated device 301.

[0113] Figure 9D Phase 10 also shows and describes an example of a connector receptacle 107 coupled to a metallized portion 104 via multiple solder interconnects 170, and a connector receptacle 113 coupled to a board 108 via multiple solder interconnects 114. A solder reflow process can be used to connect the connector receptacle 107 to the metallized portion 104 and the connector receptacle 113 to the board 108. The connector receptacle 107 can be coupled to the connector receptacle 113 via one or more wires.

[0114] Exemplary electronic devices

[0115] Figure 11Various electronic devices are shown that can be integrated with any of the following: the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, stacked packages (PoP), system-in-package (SiP), or system-on-a-chip (SoC). For example, mobile phone device 1102, laptop computer device 1104, fixed-location terminal device 1106, wearable device 1108, or motor vehicle 1110 may include device 1100 as described herein. Device 1100 may be any of the devices and / or integrated circuit (IC) packages described herein, for example. Figure 11 The devices 1102, 1104, 1106, and 1108 shown, as well as vehicle 1110, are merely exemplary. Other electronic devices may also feature device 1100, including, but not limited to, a group of devices (e.g., electronic devices) including mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as instrument reading devices), communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other devices that store or retrieve data or computer instructions, or any combination thereof.

[0116] Can be used in Figures 1-8 , Figures 9A-9D and / or Figures 10-11 The components, processes, features, and / or functions shown may be rearranged and / or combined into a single component, process, feature, or function, or embodied in several components, processes, or functions. Additional elements, components, processes, and / or functions may be added without departing from the scope of this disclosure. It should also be noted that... Figures 1-8 , Figures 9A-9D and / or Figures 10-11 And its corresponding description in this disclosure is not limited to dies and / or ICs. In some implementations, Figures 1-8 , Figures 9A-9D and / or Figures 10-11 The corresponding descriptions can be used to manufacture, create, provide, and / or produce devices and / or integrated devices. In some implementations, devices may include dies, integrated devices, integrated passive devices (IPDs), die packages, integrated circuit (IC) devices, device packages, integrated circuit (IC) packages, wafers, semiconductor devices, stacked package (PoP) devices, thermal devices, and / or interposers.

[0117] It should be noted that the figures in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, the figures may not be to scale. In some cases, not all components and / or parts are shown for clarity. In some cases, the position, orientation, size, and / or shape of the various parts and / or components in the figures may be exemplary. In some implementations, the various components and / or parts in the figures may be optional.

[0118] The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects of this disclosure. Similarly, the term “aspect” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term “coupling” is used herein to refer to direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A is physically in contact with object B, and object B is in contact with object C, objects A and C can still be considered coupled to each other—even if they are not in direct physical contact with each other. The term “electrical coupling” can mean that two objects are directly or indirectly coupled together such that current (e.g., signal, power, ground) can travel between the two objects. Electrically coupled objects may or may not have current traveling between them. The use of the terms “first,” “second,” “third,” and “fourth” (and / or any item above the fourth) is arbitrary. Any component described can be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component can be a first component, a second component, a third component, or a fourth component. The term "encapsulation" means that an object can partially or completely encapsulate another object. A first component "located" within a second component can mean that the first component is "partially located" within or "completely located" within the second component. A first component "embedded" within a second component can mean that the first component is "partially embedded" within or "completely embedded" within the second component. The terms "top" and "bottom" are arbitrary. A component located at the top can be located above a component that is located at the bottom. A top component can be considered a bottom component, and vice versa. As described in this disclosure, a first component located "above" a second component can mean that the first component is located above or below the second component, depending on how bottom or top is arbitrarily defined. In another example, a first component can be located above (e.g., above) a first surface of a second component, and a third component can be located above (e.g., below) a second surface of a second component, where the second surface is opposite to the first surface. It should also be noted that the term "above," as used in this application in the context of a component situated above another component, can be used to mean a component that is on and / or in another component (e.g., on the surface of the component or embedded in the component). Thus, for example, a first component above a second component can mean: (1) the first component is above the second component but does not directly contact the second component, (2) the first component is on the second component (e.g., on the surface of the second component), and / or (3) the first component is in the second component (e.g., embedded in the second component). The value of approximately X-XX can mean a value between X and XX, including both X and XX. Values ​​between X and XX can be discrete or continuous.As used in this disclosure, the terms “approximately 'value X'” or “approximately value X” mean within 10% of “value X”. For example, a value of approximately 1 or approximately 1 would mean a value in the range of 0.9–1.1. “Multiple” components may include all possible components or only some components from all possible components. For example, if the device comprises ten components, the use of the term “multiple components” may refer to all ten components or only some of the ten components.

[0119] In some implementations, an interconnect is a element or component in a device or package that allows or facilitates an electrical connection between two points, elements, and / or assemblies. In some implementations, an interconnect may include traces, vias, pads, pillars, redistributed metal layers, and / or under-bump metallization (UBM) layers. An interconnect may include one or more metal components (e.g., a seed layer + metal layer). In some implementations, an interconnect is a conductive material that can be configured to provide an electrical path for current (e.g., data signals, ground, or power). An interconnect may be part of a circuit. An interconnect may include more than one element or component. An interconnect may be defined by one or more interconnects. Different implementations may use similar or different processes to form interconnects. In some implementations, chemical vapor deposition (CVD) processes and / or physical vapor deposition (PVD) processes are used to form interconnects. For example, sputtering, spraying, and / or electroplating processes or electroless plating processes may be used to form interconnects.

[0120] Furthermore, it should be noted that the various disclosures contained herein can be described as processes, depicted as flowcharts, schematic diagrams, structural diagrams, or block diagrams. Although a flowchart may describe operations as a sequential process, many of these operations can be performed in parallel or concurrently. Additionally, the order of these operations can be rearranged. A process terminates when its operations are completed.

[0121] Further examples are described below to facilitate understanding of the invention.

[0122] Aspect 1: A package comprising: a package substrate; a first integrated device coupled to the package substrate via a first plurality of solder interconnects; an encapsulation layer encapsulating at least partially the first integrated device; a plurality of pillar interconnects located within the encapsulation layer; a metallized portion coupled to the plurality of pillar interconnects; a second integrated device coupled to the metallized portion via a second plurality of solder interconnects; an optical integrated device coupled to the package substrate; and an optical fiber coupled to the optical integrated device.

[0123] Aspect 2: The package according to aspect 1, wherein the front side of the first integrated device is oriented toward the package substrate.

[0124] Aspect 3: The package according to aspects 1 to 2, wherein the second integrated device is configured to be electrically coupled to the optical integrated device via an electrical path, the electrical path including solder interconnects from the second plurality of solder interconnects, metallization interconnects from the metallization portion, pillar interconnects from the plurality of pillar interconnects, and solder interconnects from the first plurality of solder interconnects.

[0125] Aspect 4: The package according to aspects 1 to 3, wherein the first integrated device is configured to be electrically coupled to the optical integrated device via an electrical path, the electrical path including solder interconnects from the first plurality of solder interconnects.

[0126] Aspect 5: The package according to aspects 1 to 4, wherein the second integrated device is configured to be electrically coupled to the first integrated device via an electrical path, the electrical path including solder interconnects from the second plurality of solder interconnects, metallization interconnects from the metallization portion, pillar interconnects from the plurality of pillar interconnects, solder interconnects from the first plurality of solder interconnects, interconnects from the package substrate, and another solder interconnect from the first plurality of solder interconnects.

[0127] Aspect 6: The package according to aspects 1 to 5, wherein the second integrated device is configured to be electrically coupled to the first integrated device via an electrical path, the electrical path including solder interconnects from the second plurality of solder interconnects, metallization interconnects from the metallization portion, pillar interconnects from the plurality of pillar interconnects and solder interconnects from the first plurality of solder interconnects, the optical integrated device, and another solder interconnect from the first plurality of solder interconnects.

[0128] Aspect 7: The package according to aspects 1 to 6 further includes: a connector socket coupled to the metallized portion, wherein the connector socket is configured to provide an electrical path for power.

[0129] Aspect 8: The package according to aspects 1 to 7, wherein the optical integrated device includes a waveguide and circuitry for processing optical signals and / or electrical signals.

[0130] Aspect 9: The package according to aspects 1 to 8, wherein the optical fiber extends through the package substrate.

[0131] Aspect 10: The package according to aspects 1 to 9, wherein the second integrated device includes a memory.

[0132] Aspect 11: A package comprising: a metallized portion; a first integrated device coupled to the metallized portion via a first plurality of solder interconnects, wherein the front side of the first integrated device is oriented toward the metallized portion; an encapsulation layer encapsulating the first integrated device; a plurality of pillar interconnects located within the encapsulation layer; a second integrated device coupled to the metallized portion via a second plurality of solder interconnects; an optical integrated device coupled to the metallized portion via a third plurality of solder interconnects; an optical fiber coupled to the optical integrated device; and a package substrate coupled to the plurality of pillar interconnects via a fourth plurality of solder interconnects.

[0133] Aspect 12: The package according to aspect 11, wherein the second integrated device is coupled to the optical integrated device via an electrical path, the electrical path including solder interconnects from the second plurality of solder interconnects, metallization interconnects from the metallization portion, and solder interconnects from the third plurality of solder interconnects.

[0134] Aspect 13: The package according to aspects 11 to 12, wherein the first integrated device is coupled to the optical integrated device via an electrical path, the electrical path including solder interconnects from the first plurality of solder interconnects, metallization interconnects from the metallization portion, and solder interconnects from the third plurality of solder interconnects.

[0135] Aspect 14: The package according to aspects 11 to 13, wherein the second integrated device is coupled to the first integrated device via an electrical path, the electrical path including solder interconnects from the second plurality of solder interconnects, metallization interconnects from the metallization portion, and solder interconnects from the first plurality of solder interconnects.

[0136] Aspect 15: The package according to aspects 11 to 14 further includes: a passive device coupled to the metallized portion.

[0137] Aspect 16: The package according to aspect 15, wherein the passive device is at least partially encapsulated by the encapsulation layer.

[0138] Aspect 17: The package according to aspects 11 to 16 further includes: a plurality of power rail interconnects located in the encapsulation layer.

[0139] Aspect 18: The package according to aspect 17, wherein the plurality of power rail interconnects are located between the back side of the first integrated device and the package substrate.

[0140] Aspect 19: The package according to aspects 11 to 18, wherein the second integrated device includes a memory.

[0141] Aspect 20: The package according to aspects 11 to 19 further includes: a connector socket coupled to the metallized portion, wherein the connector socket is configured to provide an electrical path for power.

[0142] Aspect 21: The package according to aspects 11 to 20, wherein the package is implemented in a device selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in motor vehicles.

[0143] Aspect 22: The package according to aspects 1 to 10, wherein the package is implemented in a device selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in motor vehicles.

[0144] The various features of this disclosure described herein can be implemented in different systems without departing from this disclosure. It should be noted that the foregoing aspects of this disclosure are merely illustrative and should not be construed as limiting the scope of this disclosure. The descriptions of various aspects of this disclosure are intended to be illustrative and not to limit the scope of the aspects. Therefore, the teachings herein can be readily applied to other types of devices, and many changes, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A package comprising: Packaging substrate; A first integrated device is coupled to the package substrate via a first plurality of solder interconnects; An encapsulation layer that at least partially encapsulates the first integrated device; Multiple pillars are interconnected and located within the encapsulation layer; The metallized portion is coupled to the plurality of pillar interconnects; A second integrated device is coupled to the metallized portion via a second plurality of solder interconnects; An optical integrated device coupled to the packaging substrate; as well as An optical fiber, which is coupled to the optical integrated device.

2. The packaging component according to claim 1, wherein, The front side of the first integrated device is oriented toward the packaging substrate.

3. The packaging component according to claim 1, wherein, The second integrated device is configured to be electrically coupled to the optical integrated device via an electrical path including solder interconnects from the second plurality of solder interconnects, metallization interconnects from the metallization portion, pillar interconnects from the plurality of pillar interconnects, and solder interconnects from the first plurality of solder interconnects.

4. The package according to claim 1, wherein, The first integrated device is configured to be electrically coupled to the optical integrated device via an electrical path, the electrical path including solder interconnects from the first plurality of solder interconnects.

5. The package according to claim 1, wherein, The second integrated device is configured to be electrically coupled to the first integrated device via an electrical path, the electrical path including solder interconnects from the second plurality of solder interconnects, metallization interconnects from the metallization portion, pillar interconnects from the plurality of pillar interconnects, solder interconnects from the first plurality of solder interconnects, interconnects from the package substrate, and another solder interconnect from the first plurality of solder interconnects.

6. The package according to claim 1, wherein, The second integrated device is configured to be electrically coupled to the first integrated device via an electrical path including solder interconnects from the second plurality of solder interconnects, metallization interconnects from the metallization portion, pillar interconnects from the plurality of pillar interconnects, solder interconnects from the first plurality of solder interconnects, the optical integrated device, and another solder interconnect from the first plurality of solder interconnects.

7. The package according to claim 1, further comprising: A connector socket coupled to the metallized portion, wherein the connector socket is configured to provide an electrical path for power.

8. The package according to claim 1, wherein, The optical integrated device includes a waveguide and circuitry for processing optical and / or electrical signals.

9. The package according to claim 1, wherein, The optical fiber extends through the packaging substrate.

10. The package according to claim 1, wherein, The second integrated device includes a memory.

11. A package comprising: Metallized portion; A first integrated device is coupled to the metallized portion via a first plurality of solder interconnects, wherein the front side of the first integrated device is oriented toward the metallized portion; An encapsulation layer that at least partially encapsulates the first integrated device; Multiple pillars are interconnected and located within the encapsulation layer; A second integrated device is coupled to the metallized portion via a second plurality of solder interconnects; An optical integrated device coupled to the metallized portion via a third plurality of solder interconnects; Optical fiber, which is coupled to the optical integrated device; and The packaging substrate is coupled to the plurality of pillar interconnects via a fourth plurality of solder interconnects.

12. The package according to claim 11, wherein, The second integrated device is coupled to the optical integrated device via an electrical path, the electrical path including solder interconnects from the second plurality of solder interconnects, metallization interconnects from the metallization portion, and solder interconnects from the third plurality of solder interconnects.

13. The package according to claim 11, wherein, The first integrated device is coupled to the optical integrated device via an electrical path, the electrical path including solder interconnects from the first plurality of solder interconnects, metallization interconnects from the metallization portion, and solder interconnects from the third plurality of solder interconnects.

14. The package according to claim 11, wherein, The second integrated device is coupled to the first integrated device via an electrical path, the electrical path including solder interconnects from the second plurality of solder interconnects, metallization interconnects from the metallization portion, and solder interconnects from the first plurality of solder interconnects.

15. The package according to claim 11, further comprising: Passive devices coupled to the metallized portion.

16. The package according to claim 15, wherein, The passive device is at least partially encapsulated by the encapsulation layer.

17. The package according to claim 11, further comprising: Multiple power rails located in the encapsulation layer are interconnected.

18. The package according to claim 17, wherein, The plurality of power rail interconnects are located between the back side of the first integrated device and the packaging substrate.

19. The package according to claim 11, wherein, The second integrated device includes a memory.

20. The package according to claim 11, further comprising: A connector socket coupled to the metallized portion, wherein the connector socket is configured to provide an electrical path for power.

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