Notebook computer hard disk destruction trigger circuit and method and notebook computer

Abstract

The invention relates to a notebook computer hard disk destruction trigger circuit and method and a notebook computer. The circuit comprises a notebook computer power supply end, a cover opening state detection module, a power supply control module, an embedded controller power supply end and a destruction signal trigger module. The cover opening state detection module generates a cover opening state signal, and the cover opening state signal is in a low level when the rear cover of the notebook computer is in a closed state and is in a high level when the rear cover of the notebook computer is in an open state. And the power supply control module controls the power supply end of the notebook computer to be conducted with the power supply end of the embedded controller after receiving the high-level cover opening state signal. And the destruction signal triggering module generates a low-level destruction signal after receiving the high-level cover opening state signal. And the embedded controller controls the hard disk to execute hard disk destruction operation after receiving the low-level destruction signal. The circuit has the advantages that when the rear cover of the notebook computer is not opened, the embedded controller is powered off, and the circuit power consumption is low.

Description

Technical Field

[0001] This application relates to the field of electronic circuits and data security, and in particular to a trigger circuit, method, and laptop computer for hard drive destruction. Background Technology

[0002] With the widespread use of laptops, data security issues have become increasingly prominent. Traditional hard drive destruction methods typically require high power consumption and are complex to operate. Currently, there is no low-power hard drive destruction solution specifically designed for laptops when the back cover is opened.

[0003] Current data protection technologies for laptops include traditional software encryption, remote erasure, physical destruction, and mechanical self-destruction. However, traditional software encryption is vulnerable to cracking, remote erasure relies on network connections and suffers from response delays, and mechanical self-destruction mechanisms are bulky, impacting device portability. Therefore, most hard drive destruction solutions employ physical destruction technology. However, existing physical destruction devices often require separate battery power and microcontroller control, resulting in excessive power consumption and making them unsuitable for long-term data protection in laptops.

[0004] Regarding the aforementioned technologies, there are drawbacks such as physical destruction devices requiring separate battery power and separate microcontroller control, resulting in excessive power consumption and an inability to provide long-term protection for laptop data. Summary of the Invention

[0005] In order to reduce the power consumption of physical destruction devices and extend the data protection time of laptops, this application provides a laptop hard drive destruction trigger circuit, method, and laptop.

[0006] On the one hand, this application provides a notebook computer hard drive destruction trigger circuit, which adopts the following technical solution: A laptop hard drive destruction trigger circuit includes: Power supply terminals for laptops and embedded controllers; The lid opening status detection module is used to generate a lid opening status signal. When the back cover of the laptop is closed, the lid opening status signal is low level, and when the back cover of the laptop is open, the lid opening status signal is high level. A power supply control module is disposed between the power supply terminal of the laptop and the power supply terminal of the embedded controller. The power supply control module includes a first N-type field-effect transistor (FET), a P-type field-effect transistor (FET), and a fourth resistor. The gate of the first N-type FET receives the open-cover status signal, the drain of the first N-type FET is connected to the second terminal of the fourth resistor, and the source of the first N-type FET is grounded. The source of the P-type FET is connected to the power supply terminal of the laptop, the drain of the P-type FET is connected to the power supply terminal of the embedded controller, and the gate of the P-type FET is connected to the second terminal of the fourth resistor. The fourth resistor's... One end is connected to the power supply terminal of the laptop computer, and an enable signal is generated between the power supply terminal of the laptop computer and the gate of the P-type field-effect transistor. When the open-lid state signal is low, the drain and source of the first N-type field-effect transistor are cut off, the enable signal is pulled high by the fourth resistor, and the drain and source of the P-type field-effect transistor are cut off. When the open-lid state signal is high, the drain and source of the first N-type field-effect transistor are connected, the enable signal is pulled low, the source and drain of the P-type field-effect transistor are connected, and the power supply terminal of the laptop computer is connected to the power supply terminal of the embedded controller. The destruction signal trigger module includes a second N-type field-effect transistor (FET) and a ninth resistor. The gate of the second N-type FET receives the open-cover status signal, the drain of the second N-type FET is connected to the second terminal of the ninth resistor, and the source of the second N-type FET is grounded. The first terminal of the ninth resistor is connected to the power supply terminal of the embedded controller, and the second terminal of the ninth resistor is also connected to the embedded controller, generating a destruction signal between the second terminal of the ninth resistor and the embedded controller. When the open-cover status signal is low, the source and drain of the second N-type FET are cut off; when the open-cover status signal is high, the drain and source of the second N-type FET are connected, and the destruction signal is pulled low. An embedded controller is used to perform a hard disk destruction operation upon receiving a low-level destruction signal.

[0007] By adopting the above technical solution, the power supply control module uses a specific combination of the field-effect transistor and the resistor, which can accurately control the conduction and cutoff between the power supply terminal of the laptop and the power supply terminal of the embedded controller under different open cover state signals. This ensures that the power supply terminal of the laptop only supplies power to the embedded controller when the hard drive needs to be destroyed (i.e., when the back cover of the laptop is opened), which greatly reduces the power consumption of the circuit and extends the time when the laptop's data is protected.

[0008] Optionally, the open-lid state detection module includes a micro switch and a first resistor. The power supply terminal of the laptop is connected to the first end of the first resistor, and the open-lid state signal is generated through the first resistor. The second end of the first resistor is also connected to the micro switch. When the back cover of the laptop is closed, the micro switch is closed to ground the power supply terminal of the laptop, and the open-lid state signal is pulled low. When the back cover of the laptop is open, the micro switch is open, and the open-lid state signal is pulled high by the first resistor.

[0009] By adopting the above technical solution, when the back cover of the laptop is in an open or closed state, the micro switch can work with the first resistor to conveniently and stably generate a high-level or low-level open state signal, accurately reflecting the state of the back cover of the laptop, and providing a reliable input signal for the subsequent power supply control module and the destruction signal trigger module.

[0010] Optionally, the open-cover state detection module further includes a transient voltage suppression diode and a second resistor for protection. The second end of the first resistor is connected to the first end of the transient voltage suppression diode, and the second end of the transient voltage suppression diode is grounded. The second end of the first resistor is also connected to the first end of the second resistor, and the second end of the second resistor is grounded. The open-cover state detection module further includes a third resistor for buffering current. The second end of the first resistor is connected to the first end of the third resistor, and the second end of the third resistor is connected to the gate of the first N-type field-effect transistor and the gate of the second N-type field-effect transistor.

[0011] By adopting the above technical solution, the transient voltage suppression diode and the second resistor can effectively absorb transient high voltages in the circuit, protect the components in the circuit, and improve the stability and reliability of the circuit. The third resistor can act as a signal buffer, further stabilizing the open-cover status signal and preventing signal jitter and false triggering.

[0012] Optionally, the power supply control module further includes a first common anode dual diode, the cathode of which is connected to the gate of the first N-type field-effect transistor, the first anode of which receives the cover-opening status signal, and the second anode of which receives the power-on signal.

[0013] By adopting the above technical solution and introducing the first common anode dual diode, the power supply control module can not only receive the open cover status signal, but also the power-on signal, thus being compatible with the power-on circuit of the laptop.

[0014] Optionally, the embedded controller generates a high-level latching signal after receiving a low-level destroy signal; wherein, after the gate of the first N-type field-effect transistor receives the high-level latching signal, the drain and source of the first N-type field-effect transistor continue to conduct, and the power supply terminal of the laptop computer and the power supply terminal of the embedded controller continue to conduct; the power supply control module further includes a second common-anode dual diode, the cathode of the second common-anode dual diode is connected to the gate of the first N-type field-effect transistor, the first anode of the second common-anode dual diode receives the latching signal, and the second anode of the second common-anode dual diode receives an AC status signal.

[0015] By adopting the above technical solution, the embedded controller generates a high-level power-lock signal after receiving the low-level destruction signal. The high-level power-lock signal replaces the function of the high-level open-lid status signal, so that the power supply terminal of the laptop and the power supply terminal of the embedded controller can be continuously connected, ensuring that the hard drive destruction operation can be completed completely.

[0016] Optionally, the power supply control module further includes a seventh resistor, a first capacitor, and a second capacitor for protection. The first end of the seventh resistor is connected to the gate of the first N-type field-effect transistor, and the second end of the seventh resistor is grounded. The first end of the first capacitor is connected to the gate of the first N-type field-effect transistor, and the second end of the first capacitor is grounded. The first end of the second capacitor is connected to the power supply terminal of the laptop computer, and the second end of the second capacitor is connected to the gate of the P-type field-effect transistor. The power supply control module further includes a fifth resistor, a sixth resistor, and an eighth resistor for buffering. The fourth resistor is connected to the gate of the P-type field-effect transistor through the fifth resistor. The fourth resistor is connected to the drain of the first N-type field-effect transistor through the sixth resistor. The cathode of the first common-anode dual diode is connected to the gate of the first N-type field-effect transistor through the eighth resistor.

[0017] By adopting the above technical solution, the seventh resistor can effectively absorb transient high voltages in the circuit, improving circuit stability. The first and second capacitors can filter the circuit, reducing the impact of noise and interference signals on the first N-type field-effect transistor and the P-type field-effect transistor. The fifth, sixth, and eighth resistors act as signal buffers, further optimizing circuit performance, ensuring that all circuit components function normally, and ensuring accurate signal transmission.

[0018] Optionally, the gate of the first N-type field-effect transistor also receives a temperature status signal, wherein when the temperature of the laptop exceeds a preset temperature, the temperature status signal is at a low level, and the power supply terminal of the laptop is cut off from the power supply terminal of the embedded controller.

[0019] By adopting the above technical solution, the gate of the first N-type field-effect transistor receives the temperature status signal, and when the temperature of the laptop exceeds the preset temperature, it automatically cuts off the connection between the power supply terminal of the laptop and the power supply terminal of the embedded controller, preventing high temperature from causing damage to circuit components or failure of hard drive destruction function, thereby improving the safety and stability of the entire system.

[0020] Optionally, the destruction signal triggering module further includes a third capacitor for protection, the first end of which is connected to the second end of the ninth resistor, and the second end of the third capacitor is grounded.

[0021] By adopting the above technical solution, the third capacitor can effectively filter out high-frequency interference signals and voltage spikes in the circuit, prevent these interference signals from affecting the state of the destruction signal, and improve the stability and reliability of the destruction signal.

[0022] On the other hand, this application also provides a notebook computer, which adopts the following technical solution: A laptop computer having a hard drive destruction trigger circuit.

[0023] By adopting the above technical solution, the hard drive destruction trigger circuit for the laptop computer is applied to the laptop, providing an efficient, reliable, and low-power data destruction method. Once the laptop is opened abnormally or other situations require the destruction of data on the hard drive, this circuit can quickly trigger the hard drive destruction operation, promptly erasing sensitive data on the hard drive. This is particularly suitable for situations with high data security requirements, such as enterprise offices and government departments.

[0024] On the other hand, this application also provides a method for destroying a laptop hard drive, which adopts the following technical solution: A method for destroying a laptop hard drive, implemented according to a laptop hard drive destruction trigger circuit, the method comprising: The state of the back cover of the laptop is detected by a micro switch and an open state signal is generated. When the back cover of the laptop is in the open state, the open state signal is pulled high by a first resistor. When the open state signal is high, the power supply control module controls the connection between the power supply terminal of the laptop and the power supply terminal of the embedded controller, and the destruction signal trigger module controls the destruction signal to be low. After the embedded controller receives the low-level destruction signal, it turns on the hard disk power supply, performs the hard disk destruction operation, and pulls the power-on signal high. After the power supply control module receives the high-level power-lock signal, the power supply control module executes the power-lock action. After the hard drive completes the hard drive destruction operation, the embedded controller pulls the power-lock signal low and performs a power-down action.

[0025] By adopting the above technical solution, the laptop hard drive destruction triggering method clarifies the specific steps from detecting the open state of the laptop's back cover to the completion of hard drive destruction. Through the orderly operation of the open cover detection module, the power supply control module, and the destruction signal triggering module, the standardization and accuracy of the hard drive destruction process are ensured, avoiding incomplete data destruction due to human error or improper operation. After the hard drive completes the destruction operation, the embedded controller promptly pulls down the power-lock signal and performs a power-off action, further ensuring that the data on the hard drive is completely erased and unrecoverable, providing reliable protection for user data security and reducing the risk of data leakage.

[0026] In summary, this application includes at least one of the following beneficial technical effects: 1. The power supply control module uses a specific combination of the field-effect transistor and the resistor, which can accurately control the conduction and cutoff between the power supply terminal of the laptop and the power supply terminal of the embedded controller under different open cover state signals. This ensures that the power supply terminal of the laptop only supplies power to the embedded controller when the hard drive needs to be destroyed (i.e., when the back cover of the laptop is opened), which greatly reduces the power consumption of the circuit and extends the data protection time of the laptop. 2. When the back cover of the laptop is in an open or closed state, the micro switch can work with the first resistor to conveniently and stably generate a high-level or low-level open state signal, accurately reflecting the state of the back cover of the laptop, and providing a reliable input signal for the subsequent power supply control module and the destruction signal trigger module. 3. The transient voltage suppression diode and the second resistor can effectively absorb transient high voltages in the circuit, protect the components in the circuit, and improve the stability and reliability of the circuit. The third resistor can act as a signal buffer, further stabilizing the open-cover status signal and preventing signal jitter and false triggering; 4. Applying the aforementioned laptop hard drive destruction trigger circuit to the laptop provides an efficient, reliable, and low-power data destruction method. Once the laptop is opened abnormally or other situations require the destruction of data on the hard drive, this circuit can quickly trigger the hard drive destruction operation, promptly erasing sensitive data from the hard drive. This is particularly suitable for situations with high data security requirements, such as enterprise offices and government departments. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of a laptop hard drive destruction trigger circuit; Figure 2 yes Figure 1 A schematic diagram of the lid opening status detection module; Figure 3 yes Figure 1 A schematic diagram of the power supply control module; Figure 4 yes Figure 1 A schematic diagram of the destruction signal triggering module; Figure 5 This is a flowchart of a method for triggering the destruction of a laptop hard drive.

[0028] Figure labeling: 10, Laptop power supply; 20, Open lid detection module; 21, Micro switch; 21a, Micro switch ground pin; 21b, Micro switch ungrounded pin; 22, Transient voltage suppression diode; 30, Power supply control module; 31, First N-type MOSFET; 32, P-type MOSFET; 40, Embedded controller power supply; 50, Destroy signal trigger module; 51, Second N-type MOSFET; 60, Embedded controller. Detailed Implementation

[0029] The following is in conjunction with the appendix Figure 1-5 This application will be described in further detail.

[0030] This application discloses a trigger circuit for the destruction of a laptop hard drive.

[0031] Reference Figure 1 A laptop hard drive destruction trigger circuit includes a laptop power supply terminal 10, a lid opening status detection module 20, a power supply control module 30, an embedded controller power supply terminal 40, a destruction signal trigger module 50, and an embedded controller 60.

[0032] The laptop computer power supply terminal 10 is connected to the open / closed state detection module 20, and is used to supply power to the open / closed state detection module 20 and generate an open / closed state signal. When the laptop computer's back cover is closed, the open / closed state signal is low; when the laptop computer's back cover is open, the open / closed state signal is high.

[0033] The laptop computer power supply terminal 10 is connected to the embedded controller power supply terminal 40 via the power supply control module 30, and the power supply control module 30 receives the lid-opening status signal. Specifically, when the lid-opening status signal is high, the laptop computer power supply terminal 10 is connected to the embedded controller power supply terminal 40 via the power supply control module 30. When the lid-opening status signal is low, the connection between the laptop computer power supply terminal 10 and the embedded controller power supply terminal 40 is cut off.

[0034] The embedded controller power supply terminal 40 is connected to the destruction signal triggering module 50. The destruction signal triggering module 50 can receive the lid opening status signal and can also generate a destruction signal. When the lid opening status signal is high, the destruction signal is low.

[0035] The destruction signal triggering module 50 is connected to the embedded controller 60, and the embedded controller 60 can receive destruction signals. After the embedded controller 60 receives the low-level destruction signal, the embedded controller 60 controls the hard disk to perform a destruction operation.

[0036] The embedded controller 60 generates a high-level power-lock signal while controlling the hard drive to perform a destruction operation. The power supply control module 30 can receive the power-lock signal, and after receiving the high-level power-lock signal, controls the power supply terminal 10 of the laptop computer and the power supply terminal 40 of the embedded controller to remain connected.

[0037] The power supply control module 30 can also receive a power-on signal, which is used to connect the power supply terminal 10 of the laptop and the power supply terminal 40 of the embedded controller when the laptop is normally powered on and powered by the laptop's battery. The power supply control module 30 can also receive an AC power status signal, which is used to connect the power supply terminal 10 of the laptop and the power supply terminal 40 of the embedded controller when the laptop is normally powered on and powered by an external AC power source. The power supply control module 30 can also receive a temperature status signal, which is used to disconnect the power supply terminal 10 of the laptop and the power supply terminal 40 of the embedded controller when the temperature of the laptop exceeds a preset temperature.

[0038] Reference Figure 2The cover opening state detection module 20 includes a micro switch 21, a transient voltage suppression diode 22, a first resistor R1, a second resistor R2, and a second resistor R3.

[0039] The micro switch 21 has multiple micro switch ground pins 21a and micro switch ungrounded pins 21b. The laptop power supply terminal 10 is connected to the first terminal of the first resistor R1, and the open / closed state signal is generated through the first resistor R1. The second terminal of the first resistor R1 is connected to the ungrounded pin 21b of the micro switch. When the laptop's back cover is closed, the micro switch 21 is closed, the micro switch ground pin 21a is grounded, and the open / closed state signal is pulled low; when the laptop's back cover is open, the micro switch 21 is open, the micro switch ground pin 21a is not grounded, and the open / closed state signal is pulled high by the first resistor R1.

[0040] The second terminal of the first resistor R1 is also connected to the first terminal of the transient voltage suppression diode 22, the second terminal of which is grounded. The transient voltage suppression diode 22 is used to protect the circuit from damage caused by transient high voltage. The second terminal of the first resistor R1 is also connected to the first terminal of the second resistor R2, the second terminal of which is grounded. The second resistor R2 is used to provide overvoltage protection. The second terminal of the first resistor R1 is also connected to the first terminal of the third resistor R3, the second terminal of which generates the open-cover status signal. The third resistor R3 is used to buffer current.

[0041] Reference Figure 3 The power supply control module 30 includes a first N-type field-effect transistor 31, a P-type field-effect transistor 32, a fourth resistor R4, a first common anode dual diode PD1, and a second common anode dual diode PD2.

[0042] The laptop computer power supply terminal 10 is connected to the source of the P-type field-effect transistor 32 via three branches, which serve to distribute the current. The drain of the P-type field-effect transistor 32 is connected to the embedded controller power supply terminal 40.

[0043] The laptop power supply terminal 10 is connected to the first end of the fourth resistor R4, and the second end of the fourth resistor R4 is connected to the gate of the P-type field-effect transistor 32. The laptop power supply terminal 10 generates an enable signal between the second end of the fourth resistor R4 and the gate of the P-type field-effect transistor through the fourth resistor R4.

[0044] The second terminal of the fourth resistor R4 is also connected to the drain of the first N-type field-effect transistor 31. The source of the first N-type field-effect transistor 31 is grounded, and the gate of the first N-type field-effect transistor 31 is connected to the cathodes of the first common-anode dual diode PD1 and the second common-anode dual diode PD1. The first anode of the first common-anode dual diode PD1 receives the cover-opening status signal, and the second anode receives the power-on signal. The first anode of the second common-anode dual diode PD2 receives the power-lock signal, and the second anode receives the AC power status signal. The gate of the first N-type field-effect transistor 31 can also receive the temperature status signal, and when the temperature of the laptop exceeds a preset temperature, the temperature status signal is low, and the drain and source of the first N-type field-effect transistor 31 are cut off.

[0045] The power supply control module 30 also includes a first capacitor C1, a second capacitor C2, and a seventh resistor R7 for circuit protection. The first terminal of the first capacitor C1 and the first terminal of the seventh resistor R7 are both connected to the gate of the first N-type field-effect transistor 31, and the second terminals of both the first capacitor C1 and the seventh resistor R7 are grounded. The first terminal of the second capacitor C2 is connected to the laptop power supply terminal 10, and the second terminal of the second capacitor C2 is connected to the gate of the P-type field-effect transistor.

[0046] The power supply control module 30 further includes a fifth resistor R5, a sixth resistor R6, and an eighth resistor R8 for buffering current. The fifth resistor R5 is located between the fourth resistor R4 and the P-type field-effect transistor 32. The first end of the fifth resistor R5 is connected to the second end of the fourth resistor R4, and the second end of the fifth resistor R5 is connected to the gate of the P-type field-effect transistor 32. The sixth resistor R6 is located between the fourth resistor R4 and the first N-type field-effect transistor 31. The first end of the sixth resistor R6 is connected to the second end of the fourth resistor R4, and the second end of the sixth resistor R6 is connected to the drain of the first N-type field-effect transistor 31. The eighth resistor R8 is located between the first N-type field-effect transistor 31 and the first common-anode dual diode PD1 and the second common-anode dual diode PD1. The first end of the eighth resistor R8 is connected to the gate of the first N-type field-effect transistor 31, and the second end of the eighth resistor R8 is connected to the cathodes of the first and second common-anode dual diodes PD1.

[0047] Reference Figure 4The destruction signal trigger module 50 includes a ninth resistor R9 and a second N-type field-effect transistor 51. The embedded controller power supply terminal 40 is connected to the first terminal of the ninth resistor R9, and the destruction signal is generated through the ninth resistor R9. The second terminal of the ninth resistor R9 is also connected to the drain of the second N-type field-effect transistor 51, the source of the second N-type field-effect transistor 51 is grounded, and the gate of the second N-type field-effect transistor 51 receives the cover-up status signal.

[0048] The destruction signal trigger module 50 also includes a third capacitor C3 for protecting the circuit. The first end of the third capacitor C3 is connected to the second end of the ninth resistor R9, and the second end of the third capacitor C3 is grounded.

[0049] When the laptop is powered off, most existing technologies require an additional battery and a microcontroller unit to detect the open / closed state signal. This additional microcontroller unit increases circuit power consumption and reduces the data protection time of the laptop's hard drive. In this solution, when the laptop's back cover is closed, the microswitch 21 is closed, the open / closed state signal is low, and the connection between the laptop's power supply terminal 10 and the embedded controller's power supply terminal 40 is cut off. Therefore, the embedded controller 60 does not consume power, and the power consumption of the laptop's hard drive destruction trigger circuit is in the microampere range, significantly increasing the data protection time of the laptop's hard drive.

[0050] In this solution, when the back cover of the laptop is opened, the microswitch 21 is disconnected, the open state signal is high, and the power supply terminal 10 of the laptop is connected to the power supply terminal 40 of the embedded controller, thus powering on the embedded controller 60. Simultaneously, upon receiving the high-level open state signal, the destruction signal trigger module 50 sends a low-level destruction signal to the embedded controller 60. Upon receiving the low-level destruction signal, the embedded controller 60 controls the hard drive to perform a hard drive destruction operation and sends a power-lock signal to the power supply control module 30 to ensure continuous power supply to the hard drive.

[0051] This application also discloses a laptop computer.

[0052] The laptop computer has a laptop hard drive destruction trigger circuit.

[0053] This application also discloses a method for triggering the destruction of a laptop hard drive.

[0054] Reference Figure 5 The method for triggering hard drive destruction in a laptop computer includes: S1. Determine whether the back cover of the laptop is open. If the back cover of the laptop is open, proceed to the next step. If the back cover of the laptop is not open, do not perform the hard drive destruction operation.

[0055] S2, micro switch 21 is opened, and the cover opening status signal is pulled high.

[0056] S3, the destroy signal is low level, the embedded controller 60 is powered on and the lock signal is pulled high level.

[0057] S4. Determine whether the BIOS (Basic Input / Output Module) has the destroy function enabled. If the destroy function is enabled, proceed to the next step. If the destroy function is not enabled, do not perform the hard drive destroy operation.

[0058] S5. The embedded controller 60 turns on the power supply to the hard disk and performs the hard disk destruction operation.

[0059] S6. After the hard disk destruction operation is completed, the embedded controller pulls the latch signal low to a low level and performs a power-down action.

[0060] The implementation principle of a laptop hard drive destruction trigger circuit in this application embodiment is as follows: when the laptop is turned off, the micro switch 21 is closed, the embedded controller 60 is de-energized, and the power consumption of the laptop hard drive destruction trigger circuit is in the microampere level, which greatly increases the time when the data of the laptop hard drive is protected.

[0061] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. A trigger circuit for hard drive destruction in a laptop computer, characterized in that, include: Laptop power supply terminal (10) and embedded controller power supply terminal (40); The open cover detection module (20) is used to generate an open cover status signal. When the back cover of the laptop is closed, the open cover status signal is at a low level, and when the back cover of the laptop is open, the open cover status signal is at a high level. A power supply control module (30) is disposed between the power supply terminal (10) of the laptop computer and the power supply terminal (40) of the embedded controller. The power supply control module (30) includes a first N-type field-effect transistor (31), a P-type field-effect transistor (32), and a fourth resistor (R4). The gate of the first N-type field-effect transistor (31) receives the cover opening status signal, the drain of the first N-type field-effect transistor (31) is connected to the second terminal of the fourth resistor (R4), and the source of the first N-type field-effect transistor (31) is grounded. The source of the P-type field-effect transistor (32) is connected to the power supply terminal (10) of the laptop computer, the drain of the P-type field-effect transistor (32) is connected to the power supply terminal (40) of the embedded controller, and the gate of the P-type field-effect transistor (32) is connected to the first terminal of the fourth resistor (R4). Two terminals; the first terminal of the fourth resistor (R4) is connected to the power supply terminal (10) of the laptop computer and generates an enable signal between the power supply terminal (10) of the laptop computer and the gate of the P-type field-effect transistor (32); wherein, when the open-lid state signal is low, the drain and source of the first N-type field-effect transistor (31) are cut off, the enable signal is pulled high by the fourth resistor (R4), and the drain and source of the P-type field-effect transistor (32) are cut off; when the open-lid state signal is high, the drain and source of the first N-type field-effect transistor (31) are connected, the enable signal is pulled low, the source and drain of the P-type field-effect transistor (32) are connected, and the power supply terminal (10) of the laptop computer and the power supply terminal (40) of the embedded controller are connected; The destruction signal trigger module (50) includes a second N-type field-effect transistor (51) and a ninth resistor (R9). The gate of the second N-type field-effect transistor (51) receives the opening state signal. The drain of the second N-type field-effect transistor (51) is connected to the second terminal of the ninth resistor (R9), and the source of the second N-type field-effect transistor (51) is grounded. The first terminal of the ninth resistor (R9) is connected to the power supply terminal (40) of the embedded controller, and the second terminal of the ninth resistor (R9) is also connected to the embedded controller (60). A destruction signal is generated between the second terminal of the ninth resistor (R9) and the embedded controller (60). When the opening state signal is low, the source and drain of the second N-type field-effect transistor (51) are cut off. When the opening state signal is high, the drain and source of the second N-type field-effect transistor (51) are connected, and the destruction signal is pulled low. An embedded controller (60) is configured to perform a hard disk destruction operation upon receiving a low-level destruction signal.

2. The laptop hard drive destruction trigger circuit according to claim 1, characterized in that, The open cover detection module (20) includes a micro switch (21) and a first resistor (R1). The power supply terminal (10) of the laptop is connected to the first end of the first resistor (R1), and the open cover status signal is generated through the first resistor (R1). The second end of the first resistor (R1) is also connected to the micro switch (21). When the back cover of the laptop is in the closed state, the micro switch (21) is closed to ground the power supply terminal (10) of the laptop, and the open cover status signal is pulled low to a low level. When the back cover of the laptop is in the open state, the micro switch (21) is open, and the open cover status signal is pulled high to a high level by the first resistor (R1).

3. The laptop hard drive destruction trigger circuit according to claim 2, characterized in that, The open-cover state detection module (20) further includes a transient voltage suppression diode (22) and a second resistor (R2) for protection. The second end of the first resistor (R1) is connected to the first end of the transient voltage suppression diode (22), and the second end of the transient voltage suppression diode (22) is grounded. The second end of the first resistor (R1) is also connected to the first end of the second resistor (R2), and the second end of the second resistor (R2) is grounded. The open-cover state detection module (20) further includes a third resistor (R3) for buffering current. The second end of the first resistor (R1) is connected to the first end of the third resistor (R3), and the second end of the third resistor (R3) is connected to the gate of the first N-type field-effect transistor (31) and the gate of the second N-type field-effect transistor (51).

4. The laptop hard drive destruction trigger circuit according to claim 1, characterized in that, The power supply control module (30) further includes a first common anode dual diode (PD1), the cathode of the first common anode dual diode (PD1) is connected to the gate of the first N-type field-effect transistor (31), the first anode of the first common anode dual diode (PD1) receives the cover opening status signal, and the second anode of the first common anode diode (PD1) receives the power-on signal.

5. The laptop hard drive destruction trigger circuit according to claim 4, characterized in that, The embedded controller (60) generates a high-level power-lock signal after receiving the low-level destruction signal; wherein, after the gate of the first N-type field-effect transistor (31) receives the high-level power-lock signal, the drain and source of the first N-type field-effect transistor (31) continue to conduct, and the power supply terminal (10) of the laptop computer and the power supply terminal (40) of the embedded controller continue to conduct; the power supply control module (30) also includes a second common anode dual diode (PD2), the cathode of the second common anode dual diode (PD2) is connected to the gate of the first N-type field-effect transistor (31), the first anode of the second common anode dual diode (PD2) receives the power-lock signal, and the second anode of the second common anode dual diode (PD2) receives the AC power status signal.

6. The laptop hard drive destruction trigger circuit according to claim 5, characterized in that, The power supply control module (30) also includes a seventh resistor (R7), a first capacitor (C1), and a second capacitor (C2) for protection. The first end of the seventh resistor (R7) is connected to the gate of the first N-type field-effect transistor (31), and the second end of the seventh resistor (R7) is grounded. The first end of the first capacitor (C1) is connected to the gate of the first N-type field-effect transistor (31), and the second end of the first capacitor (C1) is grounded. The first end of the second capacitor (C2) is connected to the power supply terminal (10) of the laptop computer, and the second end of the second capacitor (C2) is connected to... The power supply control module (30) further includes a fifth resistor (R5), a sixth resistor (R6), and an eighth resistor (R8) for buffering; the fourth resistor (R4) is connected to the gate of the P-type field-effect transistor (32) through the fifth resistor (R5); the fourth resistor (R4) is connected to the drain of the first N-type field-effect transistor (31) through the sixth resistor (R6); the cathode of the first common anode dual diode (PD1) is connected to the gate of the first N-type field-effect transistor (31) through the eighth resistor (R8).

7. The laptop hard drive destruction trigger circuit according to claim 6, characterized in that, The gate of the first N-type field-effect transistor (31) also receives a temperature status signal, wherein when the temperature of the laptop exceeds a preset temperature, the temperature status signal is low, and the power supply terminal (10) of the laptop is cut off from the power supply terminal of the embedded controller (60).

8. The laptop hard drive destruction trigger circuit according to claim 1, characterized in that, The destruction signal trigger module (50) also includes a third capacitor (C3) for protection, the first end of the third capacitor (C3) being connected to the second end of the ninth resistor (R9), and the second end of the third capacitor (C3) being grounded.

9. A laptop computer, characterized in that, It has a notebook computer hard drive destruction trigger circuit as described in any one of claims 1-8.

10. A method for triggering the destruction of a laptop hard drive, characterized in that, Implemented according to the notebook computer hard drive destruction trigger circuit as described in any one of claims 1-8, the method includes: The state of the back cover of the laptop is detected by the micro switch (21) and an open state signal is generated. When the back cover of the laptop is in the open state, the open state signal is pulled high by the first resistor R1. When the open state signal is high, the power supply control module (30) controls the connection between the power supply terminal (10) of the laptop computer and the power supply terminal (40) of the embedded controller, and the destruction signal trigger module (50) controls the destruction signal to be low. After the embedded controller (60) receives the low-level destruction signal, the embedded controller (60) turns on the hard disk power supply, performs the hard disk destruction operation, and pulls the power-on signal high. After the power supply control module (30) receives the high-level power-lock signal, the power supply control module (30) performs the power-lock action. After the hard disk completes the hard disk destruction operation, the embedded controller (60) pulls the power-lock signal low to a low level and performs a power-down action.

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