A multi-pvt corner setup time and hold time characterization method and related apparatus

Abstract

The present application belongs to the field of integrated circuit design automation, and discloses a multi-PVT corner setup hold time characterization method and related device. The method first uses a logic effort analysis method to estimate an initial search interval, and quickly locks the key area. Secondly, a bias term is introduced in the test points generated based on binary interpolation by assuming an interpolation error distribution to form a biased test point, and the optimal bias is solved by minimizing the expected interval length, thereby obtaining the optimal test point. Finally, the simulation output characterization result is executed. The method significantly improves the characterization efficiency, realizes faster convergence speed in the steep transition and multi-PVT corner scene, effectively overcomes the interpolation stagnation and binary slow speed problem, ensures the sign level precision, greatly reduces the simulation iteration number and CPU time consumption, and provides an efficient and reliable solution for chip timing bottleneck.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design automation technology, and particularly relates to a method and related apparatus for characterizing the setup and hold times of multiple PVT corners. Background Technology

[0002] In modern integrated circuit design, setup time and hold time are core parameters for the reliable operation of sequential circuits, and their accurate characterization has a decisive impact on chip timing convergence. Setup time refers to the minimum duration for which data must remain stable before the clock edge arrives, while hold time refers to the minimum duration for which data must remain stable after the clock edge arrives. Together, they ensure the normal operation of the chip under various operating conditions. As process nodes advance to the sub-10 nanometer level, chip verification needs to cover 20-30 process, voltage, and temperature (PVT) corners, and errors at the level of 5 picoseconds can cause timing failures in multi-GHz circuits. Taking a typical library containing 100 timing cells as an example, considering multiple pin combinations and operating conditions, the timing characterization stage accounts for 80% of the total design time, accumulating to thousands of days in a single-core computing environment, becoming a major bottleneck restricting chip design efficiency. Although existing tools have improved the capacity and speed of timing analysis through multi-threaded architectures, the demand for high-precision simulation in complex PVT scenarios has not been fundamentally solved.

[0003] Existing methods for representing setup and hold times have significant limitations: In traditional search algorithms, the bisection method, while robust, has a linear convergence speed, requiring 15-20 simulations for single-point representation; interpolation methods theoretically converge faster, but stagnate during steep metastable transitions because test points are concentrated at the interval endpoints. Commercial tools use hybrid methods, such as the improved Brent method, but their abrupt switching mechanism fails to completely eliminate the interpolation stagnation problem, reducing the number of simulations by only 10-15% compared to the pure bisection method. Analytical methods attempt to derive closed-form expressions, but modeling state transitions in complex structures such as transmission gate registers is difficult, and the accuracy is insufficient for approval-level requirements. While machine learning methods have reduced statistical sampling in recent years, their reliance on prediction results instead of actual simulations leads to insufficient accuracy, and they do not address the core source of CPU time consumption: the iterative search process.

[0004] It is evident that existing technologies suffer from slow search convergence and low exploration efficiency in multi-PVT corner scenarios, making it difficult to develop novel methods that can significantly improve characterization efficiency while ensuring accuracy, and thus hindering the breakthrough of timing characterization bottlenecks in chip design processes. Summary of the Invention

[0005] This invention provides a method and related apparatus for characterizing the establishment and holding times of multiple PVT corners. This method can effectively solve the problems of slow search convergence and low exploration efficiency in multi-PVT corner scenarios. It is a novel method that can significantly improve characterization efficiency while ensuring accuracy, thereby breaking through the timing characterization bottleneck in chip design process.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] In a first aspect, the present invention provides a method for characterizing the establishment and holding time of multiple PVT corner points, comprising:

[0008] The initial search interval corresponding to the establishment and holding times of the multi-corner points is estimated based on the logical effort analysis method.

[0009] Based on the estimated multi-corner establishment time and holding time corresponding to the initial search interval, a bias term is added to the test points to obtain multiple bias test points; with the goal of minimizing the expected interval length, the optimal bias amount is solved to obtain the optimal test point; the test points are generated based on the binary interpolation method.

[0010] The simulation is performed at the optimal test point, and the simulation results corresponding to the establishment time and holding time of the multi-corner point are output to characterize the establishment time and holding time of the multi-corner point.

[0011] A further improvement of the present invention is that, after performing simulation at the optimal test point and outputting the simulation results corresponding to the establishment and holding times of the multi-corner points, the following steps are included:

[0012] The initial search interval corresponding to the representative corner points, their establishment time, and holding time, along with the simulation structure of the representative corner points, are used as training samples to train the pre-constructed initial search interval prediction model, outputting the trained initial search interval prediction model; the representative corner points are selected based on the amount of information.

[0013] The trained initial search interval prediction model is used to predict the initial search intervals corresponding to the establishment time and holding time of each unsimulated corner point, thus obtaining the initial search intervals corresponding to the establishment time and holding time of each unsimulated corner point.

[0014] For unsimulated corner point samples, based on the initial search interval corresponding to the establishment time and holding time of the unsimulated corner point samples, a bias term is added to the test points to obtain multiple bias test points; the test points are generated based on the binary interpolation method.

[0015] With the goal of minimizing the expected interval length, the optimal bias is obtained by solving the problem, thereby obtaining the optimal test point;

[0016] The simulation is performed at the optimal test point, and the simulation results corresponding to the establishment and holding times of the unsimulated corner points are output.

[0017] A further improvement of the present invention is that the basic model of the initial search interval prediction model adopts a Gaussian regression model.

[0018] A further improvement of the present invention is that the initial search interval corresponding to the representative corner point, the establishment time and holding time of the representative corner point, and the simulation structure of the representative corner point are used as training samples to train the pre-constructed initial search interval prediction model, and the trained initial search interval prediction model is output, including:

[0019] Initialize the total number of samples, hyperparameters, and initial iteration count of the initial search interval prediction model;

[0020] The acquired representative corner points, the initial search interval corresponding to the establishment and holding times of the representative corner points, and the simulation structure of the representative corner points are used as training samples and input into the initial search interval prediction model, and the trained initial search interval prediction model is output.

[0021] A further improvement of the present invention is that the method of using a trained initial search interval prediction model to predict the initial search intervals corresponding to the establishment and holding times of unsimulated corner points, thereby obtaining the initial search intervals corresponding to the establishment and holding times of each unsimulated corner point, includes:

[0022] The expected value and variance of the establishment time and holding time corresponding to the unsimulated corner points are predicted using the trained initial search interval prediction model.

[0023] Using the expected value as the initial test position and the variance as the initial step size, the initial search interval for the setup and hold times corresponding to the unsimulated corner points is generated.

[0024] A further improvement of the present invention is that the initial search interval corresponding to the establishment time and holding time of the multi-corner points is estimated based on the logical effort analysis method, including:

[0025] Based on the logical effort analysis method, the initial search interval is estimated by utilizing the delay time and the relationship between the delay and the setup and hold times. The specific formula is as follows:

[0026]

[0027] In the formula, D represents the gate circuit delay time; g represents logic effort; h represents the fan-out number; p represents parasitic delay; γ represents parasitic parameter; wherein, the corresponding parameter values ​​are set according to different types of electrical units, and the electrical units include latches and flip-flops.

[0028] A further improvement of the present invention is that, based on the estimated multi-corner point establishment time and holding time corresponding to the initial search interval, a bias term is added to the test points to obtain multiple biased test points; with the goal of minimizing the desired interval length, the optimal bias amount is solved to obtain the optimal test point, including:

[0029] The initial search intervals corresponding to the estimated multi-corner establishment time and holding time are normalized.

[0030] In the initial search interval after normalization, the position of the actual root is modeled as a random variable:

[0031]

[0032] In the formula, Here, σ is the current interpolation estimation point, and σ is the uncertainty parameter. By adding a bias term ε at the test point location, the biased test point is obtained as x'0+ε.

[0033] The process of finding the optimal bias with the objective of minimizing the desired interval length includes:

[0034] Case 1: The actual root lies in the interval Within, the new interval length is now ;

[0035] The second scenario: The actual root is located at... Within, the new interval length is now ;

[0036] The specific formula is as follows:

[0037]

[0038]

[0039] in, Let P1 be the cumulative distribution function of the standard normal distribution; P2 be the probability of the first case; P3 be the probability of the second case.

[0040] Expected new interval length for:

[0041]

[0042] Minimize the expected new interval length as :

[0043]

[0044] Its first-order condition for:

[0045]

[0046] After simplification:

[0047]

[0048] in, is the probability density function of the standard normal distribution;

[0049] Then the optimal bias for:

[0050] ;

[0051] When the test point repeatedly falls on the same side of the interval, a corresponding uncertainty parameter will be added, and the specific formula is as follows:

[0052]

[0053] For initial uncertainty, As a growth factor, This represents the number of consecutive iterations that remain on the same side.

[0054] Secondly, the present invention provides a multi-PVT corner establishment time and hold time characterization system, comprising:

[0055] The interval estimation module is used to estimate the initial search interval corresponding to the establishment time and holding time of the multi-corner points based on the logical effort analysis method.

[0056] The calculation module is used to add bias terms to test points based on the estimated multi-corner point establishment time and holding time corresponding to the initial search interval, so as to obtain multiple bias test points; with the goal of minimizing the expected interval length, the optimal bias amount is solved to obtain the optimal test point; the test points are generated based on the binary interpolation method.

[0057] The simulation module is used to perform simulations on the optimal test points and output simulation results corresponding to the establishment and holding times of the multi-corner points, so as to characterize the establishment and holding times of the multi-corner points.

[0058] Thirdly, the present invention provides a device for characterizing the establishment and holding time of multiple PVT corner points, comprising:

[0059] Memory, used to store computer programs;

[0060] A processor is used to implement the steps of the above-described method for characterizing the establishment and holding times of multiple PVT corners when executing the computer program.

[0061] Fourthly, the present invention provides a computer-readable storage medium storing a computer program, which, when executed by a processor, is used to implement the steps of the above-described method for characterizing the establishment and holding times of multiple PVT corners.

[0062] Compared with the prior art, the present invention has the following beneficial effects:

[0063] This invention provides a method for characterizing the establishment and holding times of multiple PVT corners. First, the method utilizes logical effort analysis to pre-estimate the initial search interval, quickly locating key regions. Second, a bias term is introduced into the test points generated based on binary interpolation by assuming an interpolation error distribution, forming biased test points. The optimal bias is then solved with the goal of minimizing the expected interval length, thus obtaining the optimal test points. Finally, simulation is performed to output the characterization results. Logical effort analysis provides efficient initial interval localization, reducing blind searching. The bias mechanism dynamically adjusts the distribution of test points, avoiding the stagnation of traditional interpolation methods in the interval endpoint regions due to point concentration. Simultaneously, mathematical optimization ensures that test points focus on highly sensitive regions, improving global convergence. This method significantly improves characterization efficiency, achieving faster convergence speeds in steep transitions and multiple PVT corner scenarios. It effectively overcomes the interpolation stagnation and slow bisection problem, ensuring signature-level accuracy while significantly reducing simulation iterations and CPU time consumption, providing an efficient and reliable solution to chip timing bottlenecks. Attached Figure Description

[0064] Figure 1 This is a schematic diagram illustrating the quadratic interpolation method and the solution of the bias term provided in an embodiment of the present invention;

[0065] Figure 2 This is a schematic diagram of the smooth transition of the BEIRA method provided in an embodiment of the present invention;

[0066] Figure 3 The following is a typical latch and flip-flop schematic diagram provided for an embodiment of the present invention; wherein, (a) is a latch and (b) is a flip-flop;

[0067] Figure 4 A flowchart for estimating the initial search interval using active learning regression provided in an embodiment of the present invention;

[0068] Figure 5 The diagram illustrates the establishment time and delay relationship of latches and triggers, as well as the convergence trajectory of all search methods, provided in the embodiments of the present invention. (a) is a diagram illustrating the establishment time and delay relationship of triggers; (b) is a diagram illustrating the establishment time and delay relationship of latches; (c) is a diagram illustrating the convergence trajectory of all search methods for triggers; and (d) is a diagram illustrating the convergence trajectory of all search methods for latches.

[0069] Figure 6 The states established during the iteration process provided in this embodiment of the invention are: (a) the selection of candidate samples, (b) the trajectory of the search simulation, and (c) the initial search interval of the regression during the BEERA active learning iteration process.

[0070] Figure 7 A comparison chart of the final number of local iterations (simulations) provided for embodiments of the present invention;

[0071] Figure 8 A flowchart illustrating a method for characterizing the establishment and holding time of multiple PVT corners, as provided in an embodiment of the present invention;

[0072] Figure 9 This is a schematic diagram of a multi-PVT corner establishment time and hold time characterization system provided in an embodiment of the present invention. Detailed Implementation

[0073] To further understand the content of this invention, the invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments are merely illustrative and not limiting of the invention.

[0074] To facilitate a better understanding of this technical solution, the technical terms involved in this invention are explained as follows:

[0075] PVT is a key term in semiconductor design and manufacturing, short for Process, Voltage, and Temperature. It represents three main variable factors that a chip may encounter during actual operation, which significantly affect the circuit's performance, timing, and reliability.

[0076] Corner: refers to multiple process-voltage-temperature (PVT) corners, that is, various combinations of different process conditions, voltage levels and temperature conditions that need to be considered in chip design and simulation.

[0077] Test point: refers to the simulation input point under a specific process-voltage-temperature (PVT) combination selected during the iterative search process to determine the time boundary required for the chip timing unit to meet the setup or hold conditions during the setup and hold time characterization process.

[0078] BEIRA method: short for Bias-Enhanced Interpolation with Redundancy Adjustment, emphasizes improving the convergence speed of interpolation methods through redundant adjustments.

[0079] The Brent method is a numerical optimization algorithm that combines the advantages of bisection, secant, and inverse quadratic interpolation. It is mainly used to solve simple roots of nonlinear equations.

[0080] EQ delay: refers to the time interval from when a signal is triggered by the clock edge (such as rising or falling edge) of a flip-flop until its output (Q) stably outputs a valid signal.

[0081] Nominal estimate: Preliminary delay calculation based on idealized conditions (such as typical process, nominal voltage, ambient temperature), without considering actual factors such as process fluctuations, voltage changes, temperature drift, etc. (i.e., PVT changes).

[0082] CPU: The CPU (Central Processing Unit) is the core component of a computer system, responsible for executing program instructions, processing data, and coordinating the work of various hardware components.

[0083] CK-Q delay refers to the time interval from when a signal is triggered by the clock edge (such as rising or falling edge) of a flip-flop until its output (Q) stably outputs a valid signal.

[0084] SPICE (Simulation Program with Integrated Circuit Emphasis) is a general term for transistor-level circuit simulation simulators, which are widely used in the design and verification stages of integrated circuits (ICs), electronic systems, and analog / digital mixed circuits.

[0085] AL: short for Active Learning; refers to active learning.

[0086] like Figure 8 As shown, this embodiment provides a method for characterizing the establishment and holding time of multiple PVT corners, including:

[0087] The initial search interval corresponding to the establishment and holding times of the multi-corner points is estimated based on the logical effort analysis method.

[0088] Based on the estimated multi-corner establishment time and holding time corresponding to the initial search interval, a bias term is added to the test points to obtain multiple bias test points; with the goal of minimizing the expected interval length, the optimal bias amount is solved to obtain the optimal test point; the test points are generated based on the binary interpolation method.

[0089] The simulation is performed at the optimal test point, and the simulation results corresponding to the establishment time and holding time of the multi-corner point are output to characterize the establishment time and holding time of the multi-corner point.

[0090] The following is a more detailed explanation of the multi-PVT corner establishment time and holding time characterization method provided in this embodiment, with reference to the accompanying drawings:

[0091] As described in the background section, traditional root-finding methods have a key trade-off between convergence and efficiency: the bisection method guarantees linear convergence but ignores information about the function values; therefore, in order to solve the above problems, this embodiment provides a method for characterizing the establishment and holding times of multiple PVT corners, and uses interpolation to achieve a faster convergence speed.

[0092] For example, this embodiment provides a method for characterizing the establishment and holding times of multiple PVT corners, specifically applying the BEERA method, including:

[0093] Step 1: Statistical modeling of interpolation error:

[0094] like Figure 1 As shown, Figure 1 The top figure shows a schematic diagram of quadratic interpolation, and the bottom figure shows the results under the assumption that the estimation error follows a Gaussian distribution, based on... The process of obtaining the bias ε from the distribution; the core idea of ​​the BEERA method is to treat the uncertainty in the interpolation process as a probabilistic problem. In this embodiment, the initial search interval is normalized so that the coordinates of endpoints P1 and P2 are respectively and .

[0095] When quadratic interpolation provides a test point (Especially when it is near the endpoint of the interval), this point may not be the optimal choice for achieving efficient interval contraction.

[0096] The BEERA method is used to model the location of the actual root as a random variable:

[0097]

[0098] In the formula, For the current interpolation estimation point, This is an uncertain parameter. An offset term is added at the test point location. That is, the test point is This allows for strategic optimization of the search process.

[0099] Step 2: Solving for the optimal bias:

[0100] In this embodiment, when When testing is conducted at the location, (wherein) There are two possible scenarios:

[0101] Case 1: The actual root lies in the interval Within, the new interval length is now .

[0102] The second scenario: The actual root is located at... Within, the new interval length is now .

[0103] The probability of each scenario depends on the uncertainty model, as shown in the following formula:

[0104]

[0105]

[0106] in, Let P1 be the cumulative distribution function of the standard normal distribution; P2 be the probability of the first case; P3 be the probability of the second case.

[0107] Expected new interval length for:

[0108]

[0109] Minimize the expected new interval length as :

[0110]

[0111] Its first-order condition for:

[0112]

[0113] After simplification:

[0114]

[0115] in, is the probability density function of the standard normal distribution;

[0116] In practical implementation, when When the value is small, the optimal bias is... The following approximation can be used:

[0117]

[0118] This bias, unlike methods that rely solely on interpolation estimation results, aims to maximize the desired convergence speed by strategically adjusting the test point locations.

[0119] like Figure 2 As shown, with uncertainty ( As the value increases from 0.001 to 100, the BIERA method smoothly transitions from interpolation-based test points to bisection-like behavior (where...). ).

[0120] In this embodiment, an adaptive mechanism is also introduced, as follows:

[0121] Unlike methods such as Brent's algorithm, which abruptly switch between different strategies, BEERA gradually and adaptively adjusts itself when it detects potential stagnation. When test points repeatedly fall on the same side of an interval, BEERA increases its uncertainty parameter.

[0122]

[0123] in, This represents the initial uncertainty (typically 0.001). The growth factor is typically 5. This represents the number of consecutive iterations that remain on the same side.

[0124] For example Figure 2 As shown, this method also introduces an adaptive mechanism: increasing... This causes the test points to gradually approach the midpoint of the interval (0.5 in normalized coordinates). This mechanism enables a smooth transition from aggressive interpolation search to conservative bisection behavior without relying on manual switching rules. This adaptive method effectively handles complex situations that conventional interpolation methods struggle with, such as when the root is close to the interval boundary, while maintaining high efficiency under favorable conditions.

[0125] For example, the BEERA method requires determining the initial search interval corresponding to the establishment and holding times of the multi-corner points. The initial search interval can be formalized as the initial test position. and initial step size ,in, It is set as the first test point, and then successively taken along the other side of the threshold. or ,in This indicates the number of attempts until the other end of the interval is reached.

[0126] The relationship between setup time offset and CK-Q delay is not smooth, and for larger setup time offsets it may even be non-monotonic, making interpolation methods difficult to use for obtaining the initial interval.

[0127] Traditional representation implementations typically employ fixed and overly conservative initial intervals, using large initial test locations. and initial step size To ensure interval closure, the number of search iterations inevitably increases in practice.

[0128] In this embodiment, two complementary methods are used to solve the inefficiency problem: First, a circuit analysis method for general representation scenarios that does not require any simulation is provided, and an active learning (AL) framework for multi-corner scenarios that utilizes cross-corner correlations is provided.

[0129] Both strategies significantly reduce the number of iterations required to determine the enclosing interval that includes the actual setup and hold times.

[0130] For example, in this embodiment, a circuit analysis method is used to estimate the initial search interval, that is, a circuit analysis-based initial search interval estimation is provided:

[0131] In this embodiment, the initial search interval for setup and hold times is estimated by analyzing logical effort. Unlike the path difference method, which directly estimates setup and hold times, this method only uses this estimate to determine the initial search interval. For all setup and hold time representations, simulation of the nominal CK-Q delay is an unavoidable first step; this delay and the relationship between the delay and setup and hold times are used to estimate the initial search interval.

[0132] In this embodiment, the following logical effort analysis formula is used:

[0133]

[0134] Where D represents the gate circuit delay time; Indicates logical effort. For the number of fans, For parasitic delay. In this embodiment, parasitic parameters are assumed. ,and Figure 3 The pull-up and pull-down ratios (NMOS:PMOS width 1:2) of all CMOS gates are consistent. The NMOS:PMOS width of the transmission gate is 1:1. In this embodiment, the following parameters are set:

[0135]

[0136] Latch: Figure 3 In the middle, Figure (a) shows a typical example. Latch schematic diagram.

[0137] In this embodiment, logical effort analysis can be used to estimate the nominal ED delay, setup time, and hold time (in inverter delay units).

[0138] Nominal ED delay:

[0139] The delay can be approximated by the critical path: ;

[0140] Approximate EQ delay is unit.

[0141] Setup Time:

[0142] The path is: ;

[0143] Approximate establishment time is unit.

[0144] Hold Time:

[0145] The path is: ;

[0146] Approximate holding time is unit.

[0147] In this embodiment, the initial search interval is set to the latch establishment characteristic. The initial interval for holding time is set to .

[0148] Trigger (DFF): Figure 3 In the middle, Figure (b) shows a typical example. Schematic diagram of transmission gate flip-flop.

[0149] In this embodiment, logical effort analysis is also used to estimate the nominal CK-D delay, setup time, and hold time (in inverter delay).

[0150] Nominal CK-D delay:

[0151] The delay can be approximated by the critical path: ;

[0152] Approximate delay is unit.

[0153] Setup Time:

[0154] The path is: ;

[0155] Approximate establishment time is unit.

[0156] Hold Time:

[0157] The path is: ;

[0158] Approximate holding time is unit.

[0159] For the establishment time representation of DFF, the initial search interval can be set to The initial holding time interval is: .

[0160] Based on the above analysis, this embodiment assumes an ideal conversion of the gate input signal. However, in actual circuits, the rising / falling edge (slew) of the input signal significantly affects the gate delay. Especially when the clock and data inputs D convert simultaneously, but with different slew rates, the nominal CK-Q delay may even be negative. This phenomenon is even more pronounced in deep submicron processes where parasitic capacitance and resistance are non-negligible. In this embodiment, by providing... Minimum constraints are added to avoid negative searches. Utilizing the initial interval estimation provided by this circuit analysis method, this characterization approach can quickly obtain a narrow search interval without additional SPICE simulations, significantly improving practical efficiency.

[0161] For example, in order to further improve the representation efficiency and overall accuracy of the entire simulation process, this embodiment also provides an initial search interval estimation method based on active learning (AL), as follows:

[0162] For characterization tasks with sufficient PVT samples, regression methods can be used to mine the setup time of previously simulated data. With corresponding PVT information The correlation between them is used to estimate the PVT information of the new sample. The initial interval below .

[0163] like Figure 4 As shown, in this embodiment, the proposed AL component includes a high-level iterative framework, with a total number of samples. The hyperparameter batch size is The maximum number of iterations is .

[0164] To ensure universality, both global and local process variations are considered. The AL framework progressively selects samples expected to have a large initial range and a high impact on the regression model. Each AL iteration includes the following three main steps: sample selection, establishing a time-search simulation, and interval regression estimation. The specific steps are as follows:

[0165] 1) Initial sample selection (let) ):

[0166] Given a PVT sample .

[0167] Uniform selection 1 sample, forming the initial sample set .

[0168] For each sample, the initial search interval is estimated using circuit analysis methods.

[0169] Proceed to step 3).

[0170] 2) Sample selection (let) ):

[0171] For each process corner ,definition ,in It is the total uncertainty of all samples. This represents the total uncertainty under this process angle.

[0172] For each Select uncertainty The largest front One sample.

[0173] Merge the selected samples under each PVT into .

[0174] Proceed to step 3).

[0175] 3) Simulation:

[0176] Within the estimated initial search interval, for the sample set Perform setup time search simulation (using SPICE), and obtain setup time results using BIERA or the bisection method. .

[0177] Proceed to step 4).

[0178] 4) Regression:

[0179] Using the simulated sample set and Train a Gaussian process (GP) model.

[0180] For unsimulated samples, GP regression is used to predict their setup time, obtaining the expected and variance of the setup time for each sample. .

[0181] For each sample To establish time expectations As the initial test location, with uncertainty Use this as the initial step size to estimate the initial search interval.

[0182] Proceed to step 5).

[0183] 5) Termination of criterion check:

[0184] like Then for all remaining samples Simulation was performed using the estimated initial search interval to obtain... (Same as step 3).

[0185] Otherwise, return to step 2).

[0186] For step 2), there is a higher uncertainty. This usually helps improve regression accuracy.

[0187] The AL framework introduced in this method possesses inherent parallelism for the following reasons:

[0188] First, each iteration involves The setup-time search can be executed in parallel. Secondly, AL typically only needs to represent a small portion of the total samples, with the remainder... Each sample can be searched in parallel within the estimated initial interval.

[0189] By strategically directing expensive simulations toward the most informative process corners, this method employs the AL approach to minimize redundancy in multi-corner representations while ensuring that all represented values ​​have SPICE-level accuracy.

[0190] In this embodiment, experiments have shown that under appropriate hyperparameter settings (such as...), Typical characteristics (Points), using this characterization method, the average number of iterations was reduced from 14.16 to 6.69, achieving The simulation cost is reduced and the additional overhead is minimal. The specific PVT corner points of the experiment are shown in Table 1.

[0191] Table 1 shows the PVT angles in the experiment, where the units for voltage and temperature are volts (V) and degrees Celsius (°C), respectively.

[0192]

[0193] For example, this embodiment also provides the SetupKit framework, which is a learning-driven framework for characterizing setup and hold times for multiple process corners, used to implement all the steps involved in the characterization method provided in this embodiment, thereby realizing the characteristic functions of the method.

[0194] In this embodiment, the experiments were based on the 16 global PVT angles listed in Table 1, using a standard TSMC 22nm cell, and all local process variations were enabled. All transient simulations were performed on a Linux machine equipped with an Intel Xeon 6348 processor using HSPICE (a circuit simulation tool). The proposed active learning (AL) strategy was driven by a Gaussian process (GP).

[0195] This experiment compared five search methods: BEERA, bisection, quadratic interpolation, Brent's method, and the improved Brent's method implemented in Liberate (a cell library representation tool from Cadence).

[0196] BEIRA uses typical parameter settings, namely and All methods aim to achieve the target accuracy. Terminates at ns (emulator precision). and The establishment time of the nominal cell is used as a representative example, corresponding to register and latch scenarios respectively. The proposed method is also applicable to other timing metrics such as hold time, removal time, and recovery time.

[0197] First, we will give a general characterization of latches and flip-flops:

[0198] This experiment verifies that SetupKit... The effectiveness of characterizing the single setup time of DFF and latch under PVT angle and nominal local process variations.

[0199] For the BEIRA method and other methods, SetupKit estimates the initial search interval through circuit analysis, while Liberate relies on a fixed initial interval.

[0200] like Figure 5 As shown, (a) and (c) respectively demonstrate the setup offset and delay relationship between the trigger and the latch.

[0201] In both cases, the setup time is extremely close to the fault boundary. Notably, for latches, the fault region even overlaps with the effective delay point, often leading to frequent backtracking to the binary search method due to ambiguity in the pass / fail criterion. Simultaneously, the steep curvature of the delay jump also increases the risk of convergence failure for interpolation-based methods.

[0202] For example Figure 5 As shown, (b) and (d) present the convergence trajectories for all methods. Typically, three simulations are sufficient to determine an effective search interval. Compared to a fixed interval, estimation based on circuit analysis can achieve approximately 10 times higher initial accuracy.

[0203] During the iteration process, all interpolation-based methods stagnate in the initial stage and then rapidly shrink the search interval, while the bisection method maintains linear convergence throughout the process. The BEIRA method typically converges in less than 10 steps, significantly outperforming other methods by escaping stagnation early and achieving the fastest convergence speed. Among all methods, the Liberate method, representing the industry's leading commercial tool, requires almost twice as many steps to achieve the same accuracy as BEIRA.

[0204] Therefore, the experimental results demonstrate the effectiveness of the circuit analysis-based interval initialization method and the robustness of the BIERA method, especially in scenarios near the failure boundary with large delay curvature. The proposed characterization method is well-suited for general setup and hold time characterization tasks.

[0205] The specific analysis of the characterization of the cross-PVT angle and process variations is as follows:

[0206] This experiment, through the... The unit (168-dimensional) is characterized under various PVT angles and process variation samples to evaluate the SetupKit's capabilities. Using a quasi-Monte Carlo method with quasi-random sequences, 10,000 sets of 168-dimensional local process variation samples are generated for each global PVT angle, totaling... A 171-dimensional PVT sample. Quantified separately and SetupKit uses BIERA to search for setup time and uses AL (batch size) to determine the setup time. Maximum iteration Estimate the initial search interval.

[0207] like Figure 6 The diagram illustrates the various states established during the AL iteration process, including sample selection, simulation, and regression. First, uniform selection is performed, specifically as follows: Figure 6 As shown in (a), in this embodiment, the selection strategy can successfully identify the sample with the largest initial search step size (uncertainty) at each corner point and achieve a balanced distribution. As iterations proceed, the regression uncertainty gradually decreases. Figure 6 Figure (b) shows all the precision trajectories in the BEERA search, demonstrating that the trajectories rapidly compress to the left after fewer iterations. These trajectories are statistically steeper than the reference line of the bisection method, indicating that BEERA has a faster statistical convergence speed. Figure 6 In (c), the Pred. vs Real discrete points demonstrate a rapid improvement in the accuracy of the initial interval estimation, verifying the efficiency of SetupKit's AL strategy.

[0208] In this embodiment, the initial interval predicted in the fourth iteration was used, and the setup time of the remaining 159,000 samples was obtained using BEERA, with an average of 6.67 simulations per sample. The average number of simulations for the entire 160,000 samples was 6.69, significantly better than the 14.16 of the initial iteration. The results show that SetupKit can accurately estimate the initial interval and intelligently learn PVT-temporal correlation, actively guiding expensive simulations to the corner points with the most information, thereby greatly reducing the redundancy of multi-corner representations.

[0209] The overall running time comparison analysis is as follows:

[0210] This embodiment provides a comprehensive analysis of the advantages of SetupKit. First, the experiment is extended to... unit Delay-delay table. Next, assuming two iterative methods (bisection and BEIRA) and two initial interval settings (fixed and AL prediction), their combined performance is evaluated.

[0211] like Figure 7 As shown, the number of simulations required for each scheme is compared, and the listed values ​​represent 16 PVT angles. 10,000 MC samples The average of 160,000 samples. It should be noted that... Figure 7 The data in Figure (d) (D Slew1, CLK Slew2) are from previous experimental data. The table shows that the AL method can save an average of 7 simulations, while the BIERA method can save an additional 4, indicating that the improvement of SetupKit is statistically significant.

[0212] To ensure a fair comparison, Table 2 summarizes the detailed breakdown of CPU time, including the runtime of AL and BIERA searches. Although BIERA is more complex to implement and slightly slower than the bisection method, its overhead is negligible compared to the simulation cost; the same applies to the amortized CPU time of AL. SetupKit reduces the total CPU time for a single representation from 15.5 seconds for the bisection method to 6.4 seconds, achieving a 2.4x speedup. Given that this result is based on 25 entries... 16 PVT corners 10,000 MC samples On average, with 4 million samples, SetupKit's total CPU time was reduced from 720 days to 290 days. Furthermore, SetupKit is easily accelerated through parallel computing because the dependencies between its algorithm components are minimal.

[0213] Table 2 is a comparison table of CPU time characteristics of single setup time and hold time.

[0214]

[0215] This embodiment provides a learning-driven framework—SetupKit—for representing setup and hold times across multiple process corners. The embedded BEERA algorithm, by introducing an optimal bias, statistically balances the advantages and disadvantages of interpolation and bisection methods. Combining circuit analysis-based accurate interval estimation with proactive learning-driven PVT-aware initialization, SetupKit reduces the overall runtime for 4 million samples from 720 days to 290 days (a 2.4x speedup in a single-core environment).

[0216] In summary, this embodiment provides a method for representing the establishment and holding times of multiple PVT corner points, fundamentally reshaping the establishment / holding representation process from a learning-driven and adaptive perspective. Unlike previous methods that uniformly employ a fixed search algorithm for all points, this representation method dynamically optimizes the search path for each point through statistical intelligence, integrating circuit analysis and cross-corner learning. Its innovations include:

[0217] First, Bias Enhanced Interpolation and Redundancy Adjustment (BEIRA): A root search algorithm based on statistical error modeling, which introduces an optimal bias term to overcome interpolation stagnation and achieves a convergence speed 1.3 times faster than the bisection method.

[0218] Second, initial interval estimation based on circuit analysis: using logic effort analysis to predict the upper and lower bounds of setup and hold time intervals with zero simulation cost, the conservative interval can be reduced by 10 times compared to commercial tools.

[0219] Third, multi-corner active learning representation: driven by uncertainty, it gradually learns the relationship between PVT parameters and setup and hold times, strategically selects the most informative corner points for simulation and predicts other corner points, reducing the amount of multi-corner simulation by 40% overall, without any loss of accuracy.

[0220] Fourth, comprehensive experimental verification: On an industrial 22nm standard cell library with 16 PVT corner points and full statistical process fluctuations, this characterization method reduced the total CPU time of 4 million characterization points from 720 days to 290 days, a speedup of 2.4 times.

[0221] like Figure 9As shown, this embodiment also provides a characterization system for the establishment and holding times of multiple PVT corner points, including: an interval estimation module, used to estimate the initial search interval corresponding to the establishment and holding times of multiple corner points based on the logical effort analysis method; a calculation module, used to add bias terms to test points based on the estimated initial search interval corresponding to the establishment and holding times of multiple corner points to obtain multiple biased test points; and to solve for the optimal bias amount with the goal of minimizing the expected interval length to obtain the optimal test point; the test points are generated based on the binary interpolation method; and a simulation module, used to perform simulation on the optimal test point and output the simulation results corresponding to the establishment and holding times of multiple corner points to achieve the characterization of the establishment and holding times of multiple corner points.

[0222] The present invention also provides a multi-PVT corner establishment time and hold time characterization device, comprising: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of the multi-PVT corner establishment time and hold time characterization method.

[0223] The present invention also provides a computer program product, including a computer program / instruction that, when executed by a processor, implements the steps of the multi-PVT corner establishment time and hold time characterization method.

[0224] When the processor executes the computer program, it implements the steps for characterizing the establishment and holding times of the multiple PVT corners, for example: estimating the initial search interval corresponding to the establishment and holding times of the multiple corners based on logical effort analysis; adding bias terms to the test points based on the estimated initial search interval corresponding to the establishment and holding times of the multiple corners to obtain multiple biased test points; solving for the optimal bias amount with the goal of minimizing the expected interval length to obtain the optimal test point; the test point is generated based on binary interpolation; the optimal test point is used for simulation, and the simulation results corresponding to the establishment and holding times of the multiple corners are output to characterize the establishment and holding times of the multiple corners.

[0225] For example, the computer program can be divided into one or more modules / units, which are stored in the memory and executed by the processor to complete the present invention. The one or more modules / units can be a series of computer program instruction segments capable of performing preset functions, the instruction segments describing the execution process of the computer program in the multi-PVT corner establishment and holding time characterization device. For example, the computer program can be divided into an interval estimation module, a calculation module, and a simulation module; the specific functions of each module are as follows: the interval estimation module is used to estimate the initial search interval corresponding to the multi-corner establishment and holding times based on the logical effort analysis method; the calculation module is used to add bias terms to test points based on the estimated initial search interval corresponding to the multi-corner establishment and holding times to obtain multiple biased test points; with the goal of minimizing the desired interval length, the optimal bias amount is solved to obtain the optimal test point; the test point is generated based on the binary interpolation method; the simulation module is used to perform simulation on the optimal test point and output the simulation results corresponding to the multi-corner establishment and holding times to achieve the characterization of the multi-corner establishment and holding times.

[0226] The multi-PVT corner establishment and hold time characterization device can be a computing device such as a desktop computer, laptop, handheld computer, or cloud server. The multi-PVT corner establishment and hold time characterization device may include, but is not limited to, processors and memory. Those skilled in the art will understand that the above are examples of multi-PVT corner establishment and hold time characterization devices and do not constitute a limitation on multi-PVT corner establishment and hold time characterization devices. It may include more components than described above, or combine certain components, or different components. For example, the multi-PVT corner establishment and hold time characterization device may also include input / output devices, network access devices, buses, etc.

[0227] The processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor, or any conventional processor. The processor is the control center for the multi-PVT corner setup and hold time characterization, connecting various parts of the multi-PVT corner setup and hold time characterization device via various interfaces and lines.

[0228] The memory can be used to store the computer program and / or modules. The processor implements various functions of the multi-PVT corner establishment time and hold time characterization device by running or executing the computer program and / or modules stored in the memory and calling the data stored in the memory.

[0229] The memory may primarily include a program storage area and a data storage area. The program storage area may store the operating system and at least one application program required for a function (such as sound playback, image playback, etc.). The data storage area may store data created based on the use of the mobile phone (such as audio data, phonebook, etc.). Furthermore, the memory may include high-speed random access memory and non-volatile memory, such as hard disks, RAM, plug-in hard disks, smart media cards (SMC), secure digital cards (SD cards), flash cards, at least one disk storage device, flash memory device, or other volatile solid-state storage devices.

[0230] The present invention also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the method for characterizing the establishment and holding times of multiple PVT corners.

[0231] The multi-PVT corner establishment time and holding time characterize the system integration module / unit. If the module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium.

[0232] Based on this understanding, the present invention can implement all or part of the processes in the above-mentioned multi-PVT corner establishment and holding time characterization method, or it can be accomplished by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium. When executed by a processor, the computer program can implement the steps of the above-mentioned multi-PVT corner establishment and holding time characterization method. The computer program includes computer program code, which can be in the form of source code, object code, executable file, or a preset intermediate form, etc.

[0233] The computer-readable storage medium may include: any entity or device capable of carrying the computer program code, recording media, USB flash drive, portable hard drive, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal, and software distribution medium, etc.

[0234] It should be noted that the content contained in the computer-readable storage medium may be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, the computer-readable storage medium does not include electrical carrier signals and telecommunication signals.

[0235] The above embodiments are merely one of the implementation methods for achieving the technical solution of the present invention. The scope of protection claimed by the present invention is not limited to this embodiment, but also includes any variations, substitutions and other implementation methods that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention.

[0236] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A method for characterizing the establishment and holding time of multiple PVT corner points, characterized in that, include: The initial search interval corresponding to the establishment and holding times of the multi-corner points is estimated based on the logical effort analysis method. Based on the estimated multi-corner establishment time and holding time corresponding to the initial search interval, bias terms are added to the test points to obtain multiple bias test points; The optimal bias is obtained by minimizing the desired interval length, thereby obtaining the optimal test point; the test point is generated based on the binary interpolation method. The simulation is performed at the optimal test point, and the simulation results corresponding to the establishment time and holding time of the multi-corner point are output to characterize the establishment time and holding time of the multi-corner point. Specifically, based on the estimated multi-corner point establishment time and holding time corresponding to the initial search interval, a bias term is added to the test points to obtain multiple biased test points; with the objective of minimizing the desired interval length, the optimal bias amount is solved to obtain the optimal test point, including: The initial search intervals corresponding to the estimated multi-corner establishment time and holding time are normalized. In the initial search interval after normalization, the position of the actual root is modeled as a random variable: In the formula, Here, σ is the current interpolation estimation point, and σ is the uncertainty parameter. By adding a bias term ε at the test point location, the biased test point is obtained as x'0+ε. The process of finding the optimal bias with the objective of minimizing the desired interval length includes: Case 1: The actual root lies in the interval Within, the new interval length is now ; The second scenario: The actual root is located at... Within, the new interval length is now ; The specific formula is as follows: in, Let P1 be the cumulative distribution function of the standard normal distribution; P2 be the probability of the first case; P3 be the probability of the second case. Expected new interval length for: Minimize the expected new interval length as : Its first-order condition for: After simplification: in, is the probability density function of the standard normal distribution; Then the optimal bias for: ； When the test point repeatedly falls on the same side of the interval, a corresponding uncertainty parameter will be added, and the specific formula is as follows: For initial uncertainty, As a growth factor, This represents the number of consecutive iterations that remain on the same side.

2. The method for characterizing the establishment and holding time of multiple PVT corners according to claim 1, characterized in that, After performing simulation at the optimal test point and outputting the simulation results corresponding to the establishment and holding times of the multi-corner points, the process includes: The initial search interval corresponding to the representative corner points, their establishment time, and holding time, along with the simulation structure of the representative corner points, are used as training samples to train the pre-constructed initial search interval prediction model, outputting the trained initial search interval prediction model; the representative corner points are selected based on the amount of information. The trained initial search interval prediction model is used to predict the initial search intervals corresponding to the establishment time and holding time of each unsimulated corner point, thus obtaining the initial search intervals corresponding to the establishment time and holding time of each unsimulated corner point. For unsimulated corner point samples, based on the initial search interval corresponding to the establishment time and holding time of the unsimulated corner point samples, a bias term is added to the test points to obtain multiple bias test points; the test points are generated based on the binary interpolation method. With the goal of minimizing the expected interval length, the optimal bias is obtained by solving the problem, thereby obtaining the optimal test point; The simulation is performed at the optimal test point, and the simulation results corresponding to the establishment and holding times of the unsimulated corner points are output.

3. The method for characterizing the establishment and holding time of multiple PVT corners according to claim 2, characterized in that, The basic model of the initial search interval prediction model is a Gaussian regression model.

4. The method for characterizing the establishment and holding time of multiple PVT corner points according to claim 3, characterized in that, The method uses representative corner points, the initial search interval corresponding to the establishment and holding times of representative corner points, and the simulation structure of representative corner points as training samples to train a pre-constructed initial search interval prediction model, and outputs the trained initial search interval prediction model, including: Initialize the total number of samples, hyperparameters, and initial iteration count of the initial search interval prediction model; The acquired representative corner points, the initial search interval corresponding to the establishment and holding times of the representative corner points, and the simulation structure of the representative corner points are used as training samples and input into the initial search interval prediction model, and the trained initial search interval prediction model is output.

5. The method for characterizing the establishment and holding time of multiple PVT corners according to claim 4, characterized in that, The trained initial search interval prediction model is used to predict the initial search intervals corresponding to the establishment and holding times of the unsimulated corner points, resulting in the initial search intervals corresponding to the establishment and holding times of each unsimulated corner point, including: The expected value and variance of the establishment time and holding time corresponding to the unsimulated corner points are predicted using the trained initial search interval prediction model. Using the expected value as the initial test position and the variance as the initial step size, the initial search interval for the setup and hold times corresponding to the unsimulated corner points is generated.

6. The method for characterizing the establishment and holding time of multiple PVT corners according to claim 1, characterized in that, The initial search intervals corresponding to the establishment and holding times of the multi-corner points, estimated using the logical effort analysis method, include: Based on the logical effort analysis method, the initial search interval is estimated by utilizing the delay time and the relationship between the delay and the setup and hold times. The specific formula is as follows: In the formula, D represents the gate circuit delay time; g represents logic effort; h represents the fan-out number; p represents parasitic delay; γ represents parasitic parameter; wherein, the corresponding parameter values ​​are set according to different types of electrical units, and the electrical units include latches and flip-flops.

7. A multi-PVT corner setup time and hold time characterization system, used to implement the steps of the multi-PVT corner setup time and hold time characterization method according to any one of claims 1-6, characterized in that, include: The interval estimation module is used to estimate the initial search interval corresponding to the establishment time and holding time of the multi-corner points based on the logical effort analysis method. The calculation module is used to add bias terms to the test points based on the estimated multi-corner point establishment time and holding time corresponding to the initial search interval, so as to obtain multiple bias test points; The optimal bias is obtained by minimizing the desired interval length, thereby obtaining the optimal test point; the test point is generated based on the binary interpolation method. The simulation module is used to perform simulations on the optimal test points and output simulation results corresponding to the establishment and holding times of the multi-corner points, so as to characterize the establishment and holding times of the multi-corner points.

8. A device for characterizing the establishment and holding time of multiple PVT corner points, characterized in that, include: Memory, used to store computer programs; A processor, configured to execute the computer program to implement the steps of the multi-PVT corner establishment time and hold time characterization method according to any one of claims 1-6.

9. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it is used to implement the steps of the multi-PVT corner establishment time and holding time characterization method according to any one of claims 1-6.

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